JP3606275B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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Publication number
JP3606275B2
JP3606275B2 JP2002313069A JP2002313069A JP3606275B2 JP 3606275 B2 JP3606275 B2 JP 3606275B2 JP 2002313069 A JP2002313069 A JP 2002313069A JP 2002313069 A JP2002313069 A JP 2002313069A JP 3606275 B2 JP3606275 B2 JP 3606275B2
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Japan
Prior art keywords
wiring
semiconductor
semiconductor element
resin
sealing
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Expired - Fee Related
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JP2002313069A
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Japanese (ja)
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JP2003133479A (en
Inventor
直樹 福富
良明 坪松
文男 井上
聡夫 山崎
洋人 大畑
伸介 萩原
矩之 田口
宏 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
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Priority to JP2002313069A priority Critical patent/JP3606275B2/en
Publication of JP2003133479A publication Critical patent/JP2003133479A/en
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Publication of JP3606275B2 publication Critical patent/JP3606275B2/en
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor package substrate which can deal with high integration of semiconductor. SOLUTION: An insulating support is removed from a part for forming the external connection terminal of wiring, a through hole for external connection terminal is provided, a plurality of sets of wiring are formed on one side of the insulating support, a semiconductor element is mounted on the insulating support arranged with a plurality of sets of wiring through a die bonding tape, the semiconductor element and the wiring are conducted, the semiconductor element is resin sealed, an external connection terminal conducting with the wiring is formed in the through hole for external connection terminal and then individual semiconductor packages are separated.

Description

【０００１】
（技術分野）
本発明は、半導体パッケ−ジの製造法及び半導体パッケ−ジに関する。
【０００２】
（背景技術）
半導体の集積度が向上するに従い、入出力端子数が増加している。従って、多くの入出力端子数を有する半導体パッケージが必要になった。一般に、入出力端子はパッケージの周辺に一列配置するタイプと、周辺だけでなく内部まで多列に配置するタイプがある。前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）が代表的である。これを多端子化する場合は、端子ピッチを縮小することが必要であるが、０．５ｍｍピッチ以下の領域では、配線板との接続に高度な技術が必要になる。後者のアレイタイプは比較的大きなピッチで端子配列が可能なため、多ピン化に適している。
【０００３】
従来、アレイタイプは接続ピンを有するＰＧＡ （Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は挿入型となり、表面実装には適していない。このため、表面実装可能なＢＧＡ （Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と称するパッケージが開発されている。ＢＧＡの分類としては、（１）セラミックタイプ、（２）プリント配線板タイプ及び（３）ＴＡＢ（ｔａｐｅ ａｕｔｏｍａｔｅｄ ｂｏｎｄｉｎｇ）を使ったテープタイプなどがある。このうち、セラミックタイプについては、従来のＰＧＡに比べるとマザーボードとパッケージ間の距離が短くなるために、マザーボードとパッケージ間の熱応力差に起因するパッケージ反りが深刻な問題である。また、プリント配線板タイプについても、基板の反り、耐湿性、信頼性などに加えて基板厚さが厚いなどの問題があり、ＴＡＢ技術を適用したテープＢＧＡが提案されている。
【０００４】
パッケージサイズの更なる小型化に対応するものとして、半導体チップとほぼ同等サイズの、いわゆるチップサイズパッケージ（ＣＳＰ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案されている。これは、半導体チップの周辺部でなく、実装領域内に外部配線基板との接続部を有するパッケージである。
【０００５】
具体例としては、バンプ付きポリイミドフィルムを半導体チップの表面に接着し、チップと金リード線により電気的接続を図った後、エポキシ樹脂などをポッティングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４． ４， Ｎｏ．１４０， ｐ１８−１９）や、仮基板上に半導体チップ及び外部配線基板との接続部に相当する位置に金属バンプを形成し、半導体チップをフェースダウンボンディング後、仮基板上でトランスファーモールドしたもの（Ｓｍａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃｋａｇｅ ＣＳＰ； Ｔｈｅ Ｓｅｃｏｎｄ ＶＬＳＩ Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐａｎ， ｐ４６−５０， １９９４）などである。
【０００６】
一方、前述のように、ＢＧＡやＣＳＰ分野でポリイミドテープをベースフィルムとして利用したパッケージが検討されている。この場合、ポリイミドテープとしては、ポリイミドフィルム上に接着材層を介して銅箔をラミネートしたものが一般的であるが、耐熱性や耐湿性などの観点から銅箔上に直接ポリイミド層を形成した、いわゆる２層フレキ基材が好ましい。２層フレキ基材の製造方法としては、▲１▼銅箔上にポリイミドの前駆体であるポリアミック酸を塗布し後熱硬化させる方法、▲２▼硬化したポリイミドフィルム上に真空成膜法や無電解めっき法などにより金属薄膜を形成する方法に大別されるが、例えば、レーザ加工を適用して所望する部分（第２の接続機能部に相当）のポリイミドを除去して銅箔に達する凹部を設ける場合には、ポリイミドフィルムはできる限り薄いことが好ましい。反面、２層フレキ基材をリードフレーム状に加工してハンドリングする場合、ベースフィルム厚さが薄いとハンドリング性やフレームとしての剛直性に欠けるなどの問題がある。
【０００７】
以上のように小型化高集積度化に対応できる半導体パッケージとして、種々の提案がされているが、性能、特性、生産性等全てにわたって満足するよう一層の改善が望まれている。
【０００８】
本発明は、小型化、高集積度化に対応できる半導体パッケージを、生産性良くかつ安定的に製造するを可能とする半導体パッケージの製造法及び半導体パッケージを提供するものである。
【０００９】
（発明の開示）
本願の第一の発明は、
１Ａ．導電性仮支持体の片面に配線を形成する工程、
１Ｂ．配線が形成された導電性仮支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
１Ｃ．半導体素子を樹脂封止する工程、
１Ｄ．導電性仮支持体を除去し配線を露出する工程、
１Ｅ．露出された配線の外部接続端子が形成される箇所以外に絶縁層を形成する工程、
１Ｆ．配線の絶縁層が形成されていない箇所に外部接続端子を形成する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００１０】
本願の第二の発明は、
２Ａ．導電性仮支持体の片面に配線を形成する工程、
２Ｂ．配線が形成された導電性仮支持体の配線が形成された面に絶縁性支持体を形成する工程、
２Ｃ．導電性仮支持体を除去し配線を絶縁性支持体に転写する工程、
２Ｄ．配線の外部接続端子が形成される箇所の絶縁性支持体を除去し外部接続端子用透孔を設ける工程、
２Ｅ．配線が転写された絶縁性支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
２Ｇ．半導体素子を樹脂封止する工程、
２Ｈ．外部接続端子用透孔に配線と導通する外部接続端子を形成する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００１１】
第二の発明に於いて、２Ａ〜２Ｈの順に進めるのが好ましいが、２Ｄの工程を２Ｂの前に行うようにしても良い。例えば２Ｂの工程を外部接続端子用透孔を予め設けた絶縁フィルム絶縁性支持体を配線が形成された導電性仮支持体の配線が形成された面に貼り合わすことにより行っても良い。
【００１２】
本願の第三の発明は、
３Ａ．導電性仮支持体の片面に配線を形成する工程、
３Ｂ．配線が形成された導電性仮支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
３Ｃ．半導体素子を樹脂封止する工程、
３Ｄ．配線の外部接続端子が形成される箇所以外の導電性仮支持体を除去し導電性仮支持体よりなる外部接続端子を形成する工程、
３Ｅ．外部接続端子の箇所以外に絶縁層を形成する工程、を含むことを特徴とする半導体パッケージの製造法である。
【００１３】
本願の第四の発明は、
４Ａ．導電性仮支持体の片面に配線を形成する工程、
４Ｂ．配線が形成された導電性仮支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
４Ｃ．半導体素子を樹脂封止する工程、
４Ｄ．導電性仮支持体の半導体素子搭載面と反対側の配線の外部接続端子が形成される箇所に、導電性仮支持体と除去条件が異なる金属パターンを形成する工程、
４Ｅ．金属パターンが形成された箇所以外の導電性仮支持体を除去する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００１４】
金属パターンとしてははんだが好ましく、又ニッケル続いて金の層を積ねたものでも良い。
【００１５】
本願の第五の発明は、
５Ａ．絶縁性支持体の片面に複数組の配線を形成する工程、
５Ｂ．配線の外部接続端子となる箇所の絶縁性支持体を除去し外部接続端子用透孔を設ける工程
５Ｃ．複数組の配線が形成された絶縁性支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
５Ｄ．半導体素子を樹脂封止する工程、
５Ｅ．外部接続端子用透孔に配線と導通する外部接続端子を形成する工程、
５Ｆ．個々の半導体パッケ−ジに分離する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００１６】
第五の発明に於いて、製造工程は、５Ａ〜５Ｆの順に進めるのが好ましいが、５Ａ、５Ｂを逆にしても良い。すなわち外部接続端子用透孔を設けた絶縁性支持体に、複数組の配線を形成するようにしても良い。
【００１７】
本願の第六の発明は、
６Ａ．導電性仮支持体の片面に複数組の配線を形成する工程、
６Ｂ．導電性仮支持体に形成された複数組の配線を所定の単位個数になるように導電性仮支持体を切断分離し、配線が形成された分離導電性仮支持体をフレ−ムに固着する工程、
６Ｃ．配線が形成された導電性仮支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
６Ｄ．半導体素子を樹脂封止する工程、
６Ｅ．導電性仮支持体を除去し配線を露出する工程、
６Ｆ．露出された配線の外部接続端子が形成される箇所以外に絶縁層を形成する工程、
６Ｇ．配線の絶縁層が形成されていない箇所に外部接続端子を形成する工程
６Ｈ．個々の半導体パッケ−ジに分離する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００１８】
６Ｂの所定の単位個数は１個が好ましいが、生産性を上げるため複数個であっても良い。
【００１９】
本願の第七の発明は、
７Ａ．絶縁性支持体の片面に複数組の配線を形成する工程、
７Ｂ．配線の外部接続端子となる箇所の絶縁性支持体を除去し外部接続端子用透孔を設ける工程
７Ｃ．絶縁性支持体に形成された複数組の配線を所定の単位個数になるように絶縁性支持体を切断分離し、配線が形成された分離絶縁性支持体をフレ−ムに固着する工程、
７Ｄ．配線が形成された絶縁性支持体に半導体素子を搭載し、半導体素子端子と配線を導通する工程、
７Ｅ．半導体素子を樹脂封止する工程、
７Ｆ．外部接続端子用透孔に配線と導通する外部接続端子を形成する工程、
７Ｇ．個々の半導体パッケ−ジに分離する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００２０】
製造工程は、７Ａ〜７Ｇの順に進めるのが好ましいが、第五の発明と同様７Ａ、７Ｂを逆にしても良い。
【００２１】
本願の第八の発明は、１層の配線においてその配線の片面が半導体素子と接続する第１の接続機能を持ち、その配線の反対側が外部の配線と接続する第２の接続機能をもつように構成された配線を備えた半導体パッケージの製造法であって、下記８Ａ、８Ｂ、８Ｃ、８Ｄの工程を含むことを特徴とする半導体パッケージの製造法。
８Ａ．耐熱性を有する金属箔付き絶縁基材の金属箔を複数組の配線パターンに加工する工程。
８Ｂ．後工程で第２の接続機能部となる位置に、絶縁基材側から配線パターンに達する凹部を設ける工程。
８Ｃ．配線パターン面及び配線パターンと隣接する絶縁基材面上の所望する位置に、所定の部分を開孔させたフレーム基材を貼り合わせる工程。
８Ｄ．半導体素子を搭載し半導体素子端子と配線を導通し半導体素子を樹脂封止する工程。
【００２２】
第八の発明に於いて、工程は８Ａ〜８Ｄの順に進めるのが好ましいが、８Ａと８Ｂを逆にしても良い。すなわち、絶縁基板に金属箔に達する凹を設けた後金属箔を配線パターンに加工するようにしても良い。
【００２３】
本願の第九の発明は、１層の配線においてその配線の片面が半導体素子と接続する第１の接続機能を持ち、その配線の反対側が外部の配線と接続する第２の接続機能をもつように構成された配線を備えた半導体パッケージの製造法であって、下記９Ａ、９Ｂ、９Ｃ、９Ｄの工程を含むことを特徴とする半導体パッケージの製造法。
９Ａ．耐熱性を有する金属箔付き絶縁基材の金属箔を複数組の配線パターンに加工する工程。
９Ｂ．後工程で第２の接続機能部となる位置に、絶縁基材側から配線パターンに達する凹部を設ける工程。
９Ｃ．配線パターン面及び配線パターンと隣接する絶縁基材面上の所望する位置に、所定の部分を開孔させた第２絶縁基材を貼り合わせ絶縁支持体を構成する工程。
９Ｄ．絶縁支持体に形成された複数組の配線を所定の単位個数になるように絶縁支持体を切断分離し、配線が形成された分離絶縁支持体をフレームに固着する工程。
９Ｅ．半導体素子を搭載し半導体素子端子と配線を導通し半導体素子樹脂封止する工程。
【００２４】
第九の発明に於いて、工程は９Ａ〜９Ｅの順に進めるのが好ましいが、第八の発明と同様９Ａと９Ｂを逆にしても良い。
【００２５】
本願の第十の発明は、
１０Ａ．支持体の片面に複数組の配線を形成する工程、
１０Ｂ．配線が形成された支持体に複数個の半導体素子を搭載し、半導体素子端子と配線とを導通させる工程、
１０Ｃ．導通された複数組の半導体素子と配線とを一括して樹脂封止する工程、
１０Ｄ．支持体の所望する部分を除去して配線の所定部分を露出させ、露出した配線と電気的に接続した外部接続端子を形成する工程、
１０Ｅ．個々の半導体パッケ−ジに分離する工程
を含むことを特徴とする半導体パッケージの製造法である。
【００２６】
支持体として金属箔を使用し樹脂封止後に支持体を除去することにより配線パターンを露出させるようにしても良い。
【００２７】
又、支持体が絶縁基材で、樹脂封止後に絶縁基材の所定部分を除去して配線パターンに達する非貫通凹部を形成するようにすることもできる。
【００２８】
本願の第十一の発明は、複数個の半導体素子実装基板部を備え、複数個の半導体素子実装基板部を連結するための連結部を備え、位置合わせマーク部を備えている半導体素子実装用フレームの製造法であって、
（ａ）導電性仮基板上に半導体素子実装部の配線を作製する工程、
（ｂ）樹脂基材上に配線を転写する工程、
（ｃ）導電性仮基板をエッチング除去する工程、
を含み、（ｃ）の導電性仮基板の除去に際して、導電性仮基板に一部を残し連結部の一部を構成するようにすることを特徴とする半導体素子実装用フレームの製造法である。
【００２９】
本発明では、半導体素子はＬＳＩチップ、ＩＣチップ等通常の素子が使用できる。
【００３０】
半導体素子端子と配線とを同通する方法には、ワイヤボンディングだけでなく、バンプ、異方導電性フィルム等通常の手段を用いることができる。
【００３１】
本発明においては、半導体素子を樹脂封止した後、封止樹脂硬化物を加熱処理することにより、そり、変形のない半導体パッケージを製造することができる。
【００３２】
加熱処理は、封止樹脂硬化物のガラス転移温度±２０℃の温度が好ましい。この理由は、ガラス転移温度±２０℃の範囲で樹脂硬化物は最も塑性的な性質が強く、残留歪みを解消し易いためである。加熱処理の温度が、ガラス転移温度−２０℃未満では樹脂硬化物はガラス状態の弾性体となり緩和の効果が少なくなる傾向があり、ガラス転移温度＋２０℃を超えれば樹脂硬化物はゴム弾性体となり同様に歪みを解消する効果がすきなくなる傾向にある。
【００３３】
封止樹脂硬化物のガラス転移温度±２０℃の温度で加熱処理をした後、５℃／分以下の降温速度で室温まで冷却することにより、半導体パッケ−ジのそり、変形をより確実に防止することができる。
【００３４】
加熱処理及び／又は冷却の工程は、封止樹脂硬化物の上下面を剛性平板で、封止樹脂硬化物のそり、変形を押さえる力で押圧した状態で行うのが好ましい。
【００３５】
本発明の半導体パッケージにおいては、配線は１層の配線においてその配線の片面が半導体チップと接続する第１の接続機能を持ち、その配線の反対面が外部の配線と接続する第２の接続機能をもつように構成されている。
【００３６】
外部の配線と接続する外部接続端子は、例えばはんだバンプ、金バンプ等が好的に使用できる。
【００３７】
外部接続端子は、半導体素子端子が配線とワイヤボンディング等で導通される位置より内側に設けるようにするのが高密度化の上で好ましい（ファンインタイプ）。このように外部接続端子の位置は、半導体素子が搭載された下面に格子状に配置するのが高密度化の上で好ましい。
【００３８】
（発明を実施するための最良の形態）
図１により、本発明の第一の実施例について説明する。
【００３９】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図１では省略）をめっきする。次に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて、硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次に、めっきレジストを剥離し、配線２を形成する（図１ａ）。このようにして、配線２を形成した銅箔１にＬＳＩチップ３を搭載する（図１ｂ）。ＬＳＩチップの接着には、半導体用銀ペースト４を用いた。次にＬＳＩ端子部と配線２とをワイヤボンド１００により接続する（図１ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図１ｄ）。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させた。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して、配線部を露出させた（図１ｅ）。続いて、ソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。この配線露出部に、はんだボール７を配置し溶融させた（図１ｆ）。このはんだボール７を介して外部の配線と接続する。
【００４０】
図２により、本発明の第二の実施例について説明する。
【００４１】
図１の場合と同様の方法で、配線２を有する銅箔１を作成した（図２ａ）。ＬＳＩチップ３を搭載する。ＬＳＩチップには、端子部に金バンプ８を形成し、この金バンプ８と配線２の端子部とを加熱加圧して接続する（図２ｂ）。次に、ＬＳＩチップ下部に液状エポキシ樹脂を充填し硬化９させる（図２ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止１０した（図２ｄ）。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させた。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して、配線部を露出させた（図２ｅ）。続いて、ソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。この配線露出部に、はんだボール７を配置し溶融させた（図２ｆ）。このはんだボール７を介して外部の配線と接続する。
【００４２】
図３により、本発明の第三の実施例について説明する。
【００４３】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図３では省略）をめっきする。次に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像しめっきレジストを形成する。続いて、硫酸銅浴にて電解銅めっきを行い、第一の配線１３を形成する。次にめっきレジストを剥離し、第一の配線１３の表面を酸化処理、還元処理を行う。新たな銅箔と接着樹脂としてポリイミド系接着フィルム（日立化成工業（株）製、商品名：ＡＳ２２１０）１２を用いて配線１３が内側となるように積層接着する。（銅箔１１に直径０．１ｍｍの穴を通常のフォトエッチング法により形成する。パネルめっき法により、穴内と銅箔表面全体を銅めっきする。）銅箔をフォトエッチング法で第二の配線１１を形成する。ＬＳＩ搭載部の樹脂（ポリイミド系接着フィルム１２）をエキシマレーザにより除去し端子部を露出させる。該端子部に、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする（図３ａ）。このようにして、２層配線を形成した銅箔１にＬＳＩチップを搭載する。ＬＳＩチップの接着には、半導体用銀ペーストを用いた（図３ｂ）。次にＬＳＩ端子部と配線１３とをワイヤボンド１００により接続する（図３ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させた。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して、配線部を露出させた（図３ｅ）。続いて、ソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。該露出部に、はんだボール７を配置し溶融させた（図３ｆ）。このはんだボール７を介して外部の配線と接続する。
【００４４】
図４により、本発明の第四の実施例について説明する。
【００４５】
厚さ０．１ｍｍのＳＵＳ（ステンレス鋼）板１４に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて、硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次に、めっきレジストを剥離し、配線２を形成する（図４ａ）。このようにして配線２を形成したＳＵＳ板１４に半導体チップ１０３を搭載する（図４ｂ）。半導体チップの接着には半導体用銀ベースト４を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図４ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図４ｄ）。その後、ＳＵＳ板１４を機械的に剥離除去し、配線部を露出させた（図４ｅ）。続いてソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。この配線露出部にはんだボール７を配置し溶融させた（図４ｆ）。このはんだボール７を介して外部の配線と接続する。
【００４６】
図５により、本発明の第五の実施例について説明する。
【００４７】
厚さ０．０３５ｍｍの電解銅箔１に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いてニッケルのパターンめっき１５を行った後、硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次に、めっきレジストを剥離し、配線２を形成する（図５ａ）。このようにして配線２を形成した銅箔１に半導体チップ１０３を搭載する（図５ｂ）。半導体チップの接着には、半導体用銀ベースト４を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図５ｃ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図５ｄ）。その後、銅箔１をアルカリエッチャンで溶解除去し、ニッケルの配線部を露出させた（図５ｅ）。続いてソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。この配線露出部にはんだボール７を配置し溶融させた（図５ｆ）。このはんだボール７を介して外部の配線と接続する。
【００４８】
図６により、本発明の第六の実施例について説明する。
【００４９】
厚さ０．０３５ｍｍの電解銅箔１に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて純度９９．９％以上の金めっきを０．０００３ｍｍ、ニッケルめっきを０．００３ｍｍ以上の厚さでめっきする。さらに、硫酸銅浴にて電解銅めっきを行い、めっきレジストを剥離し、配線２を形成する（図６ａ）。このようにして配線２を形成した銅箔１の配線面にポリイミドフィルム１６を接着し、レーザを用いて配線２の接続用端子部を露出させ（図６ｂ）、銅箔１をエッチングで除去する（図６ｃ）。また、ポリイミドの代わりに、感光性フィルムを用いることで、レーザを使用しないで接続用端子部を露出させることができる。続いて、ポリイミドフィルム１６の配線パターン面にＬＳＩチップ３を搭載する。ＬＳＩチップの接着には半導体用銀ペースト４を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図６ｄ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５する（図６ｅ）。その後、接続用端子部にはんだボール７を配置し溶融させる（図６ｆ）。このはんだボール７を介して外部の配線と接続する。
【００５０】
図７により、本発明の第七の実施例について説明する。
【００５１】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図７では省略）をめっきする。次に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次にめっきレジストを剥離し、配線２を形成する（図７ａ）。このようにして配線２を形成した銅箔１にＬＳＩチップ３を搭載する。ＬＳＩチップの接着には半導体用銀ペースト４を用いた。次に、半導体端子部と配線２とをワイヤボンド１００により接続する（図７ｂ）。このようにして形成したものをトランスファモールド金型に装填し半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５する（図７ｃ）。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させる。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して配線部を露出させる（図７ｄ）。続いて、接続用端子部を開口させたポリイミドフィルム１６を接着し（図７ｅ）、この配線露出部にはんだボール７を配置し溶融させる（図７ｆ）。このはんだボール７を介して外部の配線と接続する。
【００５２】
図８により、本発明の第八の実施例について説明する。
【００５３】
厚さ０．０３５ｍｍの電解銅箔１に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて純度９９．９％以上の金めっきを０．０００３ｍｍ、ニッケルめっきを０．００３ｍｍ以上の厚さでめっきする。さらに、硫酸銅浴にて電解銅めっきを行い、めっきレジストを剥離し配線２を形成する（図８ａ）。このようにして配線２を形成した銅箔１の配線面に液状封止樹脂１７をスクリーン印刷により塗布し、配線２の接続用端子部を露出させるようにして絶縁層を形成する（図８ｂ）。液状封止樹脂を硬化させた後、銅箔１をエッチングで除去する（図８ｃ）。続いて、硬化させた液状封止樹脂３の配線パターン面にＬＳＩチップ３を搭載する。ＬＳＩチップの接着には半導体用銀ペースト４を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図８ｄ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５する（図８ｅ）。その後、配線２の接続用端子部にはんだボール７を配置し溶融させる（図８ｆ）。このはんだボール７を介して外部の配線と接続する。
【００５４】
図９により、本発明の第九の実施例について説明する。
【００５５】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図９では省略）をめっきする。次に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターンを露光、現像し、めっきレジストを形成する。続いて硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次にめっきレジストを剥離し、配線２を形成する（図９ａ）。このようにして配線２を形成した銅箔１にＬＳＩチップ３を搭載する。ＬＳＩチップ３の接着には半導体用銀ペースト４を用いた。次に、半導体端子部と配線２とをワイヤボンド１００により接続する（図９ｂ）。このようにして形成したものをトランスファモールド金型に装填し半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５する（図９ｃ）。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させる。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して配線部を露出させる（図９ｄ）。続いて、液状封止樹脂１７をスクリーン印刷により塗布し、配線２の接続用端子部を露出させるようにして、液状封止樹脂１７の絶縁層を形成する（図９ｅ）。この配線２の接続用端子部にはんだボール７を配置し溶融させる（図９ｆ）。このはんだボール７を介して外部の配線と接続する。
【００５６】
図１０により、本発明の第十の実施例について説明する。
【００５７】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図１０では省略）をめっきする。次に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、配線パターン及び位置合わせマークのめっきレジストを露光、現像により形成する。続いて、硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきする。次に、めっきレジストを剥離し、配線２及び位置合わせマーク１８を形成した後（図１０ａ）、位置合わせマーク１８の部分だけをＳＵＳ板で挟みプレスすることで銅箔１の裏面に位置合わせマークを浮かび上がらせる（図１０ｂ）。このようにして配線２及び位置合わせマーク１８を形成した銅箔１にＬＳＩチップ３を搭載する（図１０ｃ）。ＬＳＩチップ３の接着には半導体用銀ペースト４を用いた。次に、半導体端子部と配線２とをワイヤボンド１００により接続する（図１０ｄ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図１０ｅ）。銅箔裏側に再び感光性ドライフィルムをラミネートし、位置合わせマーク１８を利用してエッチングパターン形成する。その後、銅箔１及びニッケル層をエッチングして、銅箔１によるバンプ７の形成及び配線部の露出を行う（図１０ｆ）。続いて、ソルダレジスト８を塗布し、バンプ７が露出するように絶縁層を形成した（図１０ｇ）。このバンプ７を介して外部の配線と接続する。
【００５８】
図１１により、本発明の第十一の実施例について説明する。
【００５９】
厚さ０．０３５ｍｍの電解銅箔１に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、複数組の配線パターンを露光、現像し、めっきレジストを形成する。続いて、純度９９．９％以上の金めっきを０．０００３ｍｍ、ニッケルめっきを０．００３ｍｍ以上の厚さでめっきする。さらに、硫酸銅浴にて電解銅めっきを行い、レジストを剥離し、複数組の配線２を形成する（図１１ａ）。このようにして、複数組の配線２を形成した銅箔１の配線面にポリイミドフィルム１９を接着し、レーザを用いて配線２の接続端子部を露出させ（図１１ｂ）、銅箔１をエッチングで除去する（図１１ｃ）。以上のように、１枚のポリイミドフィルム上に複数組の配線２を形成した後、ＬＳＩチップ３を搭載する。ＬＳＩチップの接着には、半導体用ダイボンディングテープ４’を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図１１ｄ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて各々封止５する（図１１ｅ）。その後、配線２の接続端子部にはんだボール７を配置し溶融させる（図１１ｆ）。このはんだボール７を介して外部の配線と接続する。最後にポリイミドフィルムで連結されたパッケージを、金型で打ち抜く（図１１ｇ）。
【００６０】
図１２により、本発明の第十二の実施例について説明する。
【００６１】
厚さ０．０７ｍｍの接着剤付きポリイミドフィルム２０を、金型で打ち抜き接続端子部となる部分を開口させる（図１２ａ）。次に、厚さ０．０３５ｍｍの銅箔２１を接着後（図１２ｂ）、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、複数組の配線パターンを露光、現像し、エッチングレジストを形成する。続いて銅箔をエッチングし、レジストを剥離し、複数組の配線２を形成する（図１２ｃ）。以上のように、１枚のポリイミドフィルム上に複数組の配線パターンを形成した後、ＬＳＩチップ３を搭載する。ＬＳＩチップ３の接着には、半導体用ダイボンディングテープ４’を用いた。次に半導体端子部と配線２とをワイヤボンド１００により接続する（図１２ｄ）。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて各々封止５する（図１２ｅ）。その後、配線の接続端子部にはんだボール７を配置し溶融させる（図１２ｆ）。このはんだボール７を介して外部の配線と接続する。最後にポリイミドフィルムで連結されたパッケージを、金型で打ち抜く（図１２ｇ）。
【００６２】
図１３〜１５により、本発明の第十三の実施例について説明する。
【００６３】
厚さ０．０３５ｍｍの電解銅箔１の片面に厚さ０．００１ｍｍのニッケル層（図１３では省略）をめっきする。感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、複数組の配線パターンのめっきレジストを露光、現像により形成する。続いて、硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめっきを０．００３ｍｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ以上の厚さでめっきし、めっきレジストを剥離し、配線２を形成した（図１３ａ）。次に、配線２を形成した銅箔１を単位個数に分けた後、ポリイミド接着フィルムを介して別に用意したステンレス製フレーム２２（厚さ；０．１３５ｍｍ）にはりつけた（図１３ｂ）。フレームとしては、りん青銅等の銅合金、銅箔、ニッケル箔、ニッケル合金箔等が使用できる。接着の方法としては他に金属間の共晶を利用した接合、超音波を利用した接合等を用いることも可能である。また、図１４に示したように銅箔１上の配線をあらかじめ検査し、配線良品２３だけを撰択し、フレーム２２にはりつけると良い。図１４において、１は電解銅箔、２２はフレ−ム、２４は配線不良品、２５は位置合わせ用穴である。また、この実施例では、切り分けた銅箔上には配線１個となるようにしたが、切り分けた銅箔上に複数組の配線があるようにしても良い。フレーム２２と配線付き銅箔との張り合わせの位置関係として、例えば図１５（ａ）、（ｂ）に示したものなど種々可能である。図１５はフレ−ム２２の平面図であり、２６はフレ−ム開口部、２７は配線付き銅箔の搭載位置、２８は箔固定用接着剤である。次に、ＬＳＩチップ３を搭載し、半導体端子部と配線２とをワイヤボンド１００により接続する（図１３ｃ）。ＬＳＩチップの搭載には半導体用ダイボンディングテープ４’を用いた。ここで、ボンディングテープ４’の代わりにダイボンド用銀ペースト等を用いてもよい。また、半導体チップの実装には、通常のワイヤーボンディング接続を用いたが、フィリップチップ等、他の方法を用いてもよい。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図１３ｄ）。その後、銅箔１のみをアルカリエッチャントで溶解除去し、ニッケルを露出させた。ニッケル層を銅の溶解性の少ないニッケル剥離液にて除去して、配線部を露出させた。続いて、ソルダレジスト６を塗布し、接続用端子部を露出するようにパターンを形成した。この配線露出部に、はんだボール７を配置し溶融させた（図１３ｅ）。この後で、切断機を用いて切断し、フレーム２２の不要な切片１０１を除いて、個々の半導体パッケージに分割した（図１３ｆ）。このはんだボール７を介して外部の配線と接続する。この例では、板取りを上げて効率よく半導体パッケ−ジを製造することができる。
【００６４】
図１６により、本発明の第十四の実施例について説明する。
【００６５】
厚さ０．０７ｍｍの接着剤付きポリイミドフィルム２９を、金型で打ち抜き接続端子部となる部分を開口させる。次に、厚さ０．０３５ｍｍの銅箔を接着後、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、複数組の配線パターンを露光、現像し、エッチングレジストを形成た。続いて銅箔をエッチングし、レジストを剥離し、複数組の配線２を形成する（図１６ａ）。ここで、銅箔上にポリイミドを直接コ−ティングした材料（例えば、日立化成工業（株）製、商品名５０００１）を用いて、接続端子部および配線２を形成するようにしても良い。開口部の形成もドリル加工、エキシマレ−ザ等のレ−ザ加工、印刷等の方法を用いたり、ポリイミドに感光性を持たせた材料を使用し、露光・現像により形成しても良い。ポリイミドの代わりに封止樹脂等他の材料を使用しても良い。
【００６６】
以上のように、１枚のポリイミドフィルム上に複数組の配線パターンを形成した後、配線付きフィルムを単位個数に分けた、ポリイミド接着接着剤２８を介して別に用意したステンレス製フレーム２２（厚さ；０．１３５ｍｍ）にはりつけた（図１６ｂ）。次に、ＬＳＩチップ３を搭載し、半導体端子部と配線２とをワイヤボンド１００により接続する（図１６ｃ）。ＬＳＩチップの搭載には半導体用ダイボンディングテープ４´を用いた。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて封止５した（図１６ｄ）。続いて最初に設けた接続端子部となるべき開口部にはんだボール７を配置し溶融させる（図１６ｅ）。このはんだボール７を介して外部の配線と接続する。最後にフレームで連結されたパッケージを金型で打ち抜き、個々のパッケージに分割した（図１６ｆ）。
【００６７】
図１７により本発明の第十五の実施例について説明する。
【００６８】
金属箔３１上に絶縁基材３２を直接形成した２層フレキシブル基材（図１７ａ）の金属箔上に所定のレジスト像を形成し、公知のエッチング法により所望する複数組の配線パターン３３を形成し、レジスト像を剥離する（図１７ｂ）。金属箔としては、電解銅箔や圧延銅箔あるいは銅合金箔などの単一箔の他、後工程で除去可能なキャリヤ箔上に銅薄層を有する複合金属箔なども適用可能である。具体的には、厚さ１８μｍの電解銅箔の片面に厚さ０．２μｍ程度のニッケル−リンめっき層を形成後、続けて厚さ５μｍ程度の銅薄層をめっきしたものなどが適用できる。この場合、銅薄層上にポリイミド層を形成した後、銅箔及びニッケル−リン層をエッチング除去することにより、銅薄層が露出する。すなわち、本願の発明においては銅薄層全てを露出させた後銅薄層を配線加工しても良いし、キャリヤ箔（銅箔／ニッケル薄層）をリードフレーム構造体の一部として利用しても良い。一方、絶縁基材としては、プロセス耐熱性などの観点からポリイミド材が一般的である。この場合、ポリイミドと銅箔の熱膨張係数が異なるとはんだリフロー工程において基材の反りが顕著になるため、ポリイミドとしては（化１）の繰り返し単位を有するポリイミドを７０モル％以上含んだポリイミドを適用することが好ましい。
【００６９】
【化１】

Figure 0003606275
次に、後工程で外部基板との接続部となる位置に銅箔に達する凹部３４を設ける（図１７ｃ）。凹部の加工方法は特に限定するものではなく、エキシマレーザや炭酸ガスレーザ及びＹＡＧレーザなどレーザ加工の他、ウエットエッチング法などが適用可能である。
【００７０】
次に、所定の部分（開孔部３５）をパンチング加工等で打ち抜いた接着材３６付きフレーム基材３７を配線パターン面に接着させる（図１７ｄ）。この場合、フレーム基材は特に限定するものではなく、ポリイミドフィルムや銅箔などの金属箔の適用が可能である。ここで、仮に２層フレキシブル基材のポリイミド層厚さが２５μｍで、かつ、接着するフレーム基材がポリイミドフィルムの場合、フレーム全体としての剛直性を確保するためにはフィルム厚さとして５０〜７０μｍ程度が必要になる。なお、フレーム基材層を形成する領域についても特に限定するものではなく、半導体チップを搭載する部分にフレーム基材層を設けることも可能である。具体的には、チップ実装がワイヤボンディング方式の場合には、最小限ワイヤボンド用端子部３８が露出していれば他の領域全てにフレーム基材層を設けても良い。次に、半導体チップ３９を搭載し、金ワイヤ４０で半導体チップと配線パターン間を電気的に接続させる（図１７ｅ）。一方、半導体チップ実装方式としてフェースダウン方式を採用する場合には、配線パターンの所定位置（半導体チップの外部接続用電極位置に対応）に金属パンプ等を設け、金属バンプを介して半導体チップと波線パターンとを電気的に接続させても良い。次に、トランスファーモールド用の金型にセットし、樹脂封止材４１で封止する（図１７ｆ）。この場合、樹脂封止材は特に限定するものではなく、例えば、直径１０〜２０μｍ程度のシリカを５〜８０ｗｔ％の範囲で含有したエポキシ系樹脂などが適用できる。次に、外部基板との接続部４２を形成する。接続部４２の形成方法としては、図１７ｃの工程後にあらかじめ電解めっき法によりポリイミドフィルム厚さ以上のバンプを形成しておく方法や樹脂封止後にはんだ印刷法によりはんだバンプを形成する方法などが適用可能である。最後に、フレームからパッケージ部を切断して所望するパッケージが得られる（図１７ｇ）。
【００７１】
図１７の第十五の実施例を更に具体的に説明する。
【００７２】
具体例１
厚さ１２μｍの電解銅箔を片面に有する２層フレキシブル基材（日立化成工業（株）製、商品名：ＭＣＦ ５０００Ｉ）の銅箔面上にドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＫ８１５）をラミネートし、露光、現像により所望するレジストパターンを得た。次に、塩化第二鉄溶液で銅箔をエッチング加工後、レジストパターンを水酸化カリウム溶液で剥離することにより所定の配線パターンを得た。次に、エキシマレーザ加工機（住友重機械工業（株）製、装置名：ＩＮＤＥＸ２００）を用いて絶縁基材側から配線パターン裏面に達する凹部（直径３００μｍ）を所定の位置に所定の数だけ形成した。エキシマレーザ加工条件は、エネルギー密度２５０ｍＪ／ｃｍ２、縮小率３．０、発振周波数２００Ｈｚ、照射パルス数３００パルスである。次に５０μｍ厚さのポリイミドフィルム（宇部興産製、商品名：ＵＰＩＬＥＸ Ｓ）の片面に厚さ１０μｍのポリイミド系接着材（日立化成工業（株）製、商品名：ＡＳ ２２５０）を有する接着シートを作製し、後工程でのワイヤボンド端子部に相当する領域を含む所定領域をパンチ加工により除去し、接着材を介してポリイミドフィルムと配線パターン付き２層フレキ基材とを加熱圧着させた。圧着条件は、圧力２０ｋｇｆ／ｃｍ２、温度１８０℃、加熱加圧時間６０分である。次に、無電解ニッケル、金めっき法によりワイヤボンド用端子部にニッケル／金めっきを施した。めっき厚さは、それぞれ、３μｍ、０．３μｍである。次に、半導体チップ搭載用ダイボンド材（日立化成工業（株）製、商品名：ＨＭ−１）を用いて半導体チップを搭載した。搭載条件は、プレス圧力５ｋｇｆ／ｃｍ２、接着温度３８０℃及び圧着時間５秒である。次に、ワイヤボンディングにより半導体チップの外部電極部と配線パターンを電気的に接続した。その後、リードフレーム状に金型加工し、トランスファーモールド用金型にセットし、半導体封止用エポキシ樹脂（日立化成工業（株）製、ＣＬ−７７００）を用いて１８５℃、９０秒で封止した。続いて、前述の凹部に所定量のはんだを印刷塗布し、赤外線リフロー炉によりはんだを溶融させて外部接続用バンプを形成した。最後に、パッケージ部を金型で打ち抜き、所望するパッケージを得た。
【００７３】
図１８により本発明の第十六の実施例について説明する。
【００７４】
金属箔３１上に絶縁基材３２を直接形成した２層フレキシブル基材（図１８ａ）の金属箔上に所定のレジスト像を形成し、公知のエッチング法により所望する複数組の配線パターン３を形成し、レジスト像を剥離する（図１８ｂ）。金属箔としては、電解銅箔や圧延銅箔あるいは銅合金箔などの単一箔の他、後工程で除去可能なキャリヤ箔上に銅薄層を有する複合金属箔なども適用可能である。具体的には、厚さ１８μｍの電解銅箔の片面に厚さ０．２μｍ程度のニッケル−リンめっき層を形成後、続けて厚さ５μｍ程度の銅薄層をめっきしたものなどが適用できる。この場合、銅薄層上にポリイミド層を形成した後、銅箔及びニッケル−リン層をエッチング除去することにより、銅薄層が露出する。すなわち、本願の発明においては銅薄層全てを露出させた後銅薄層を配線加工しても良いし、キャリヤ箔（銅箔／ニッケル薄層）をリードフレーム構造体の一部として利用しても良い。一方、絶縁基材としては、プロセス耐熱性などの観点からポリイミド材が一般的である。この場合、ポリイミドと銅箔の熱膨張係数が異なるとはんだリフロー工程において基材の反りが顕著になるため、ポリイミドとしては（化１）の繰り返し単位を有するポリイミドを７０モル％以上含んだポリイミドを適用することが好ましい。
【００７５】
次に、後工程で外部基板との接続部となる位置に銅箔に達する凹部３４を設ける（図１８ｃ）。凹部の加工方法は特に限定するものではなく、エキシマレーザや炭酸ガスレーザ及びＹＡＧレーザなどレーザ加工の他、ウエットエッチング法などが適用可能である。
【００７６】
次に、第２絶縁基体として所定の部分（開孔部５）をパンチング加工等で打ち抜いた接着材３６付きフレーム基材３７を配線パターン面に接着させる（図１８ｄ）。ここで、仮に２層フレキシブル基材のポリイミド層厚さが２５μｍであれば、後工程でフレームに固着することを考慮すれば接着するポリイミドフィルムの厚さとして５０〜７０μｍ程度が必要になる。なお、ポリイミドを接着する領域についても特に限定するものではなく、半導体チップを搭載する部分に設けることにより、ＣＳＰのように半導体チップ下部に外部接続端子を形成することも可能である。具体的には、チップ実装がワイヤボンディング方式の場合には、最小限ワイヤボンド用端子部３８が露出していれば他の領域全てにポリイミドフィルムを接着しても良い。このようにして得られた絶縁基板を、個々の配線パターンに分離し（図１８ｅ）別に用意した例えばＳＵＳなどのフレーム４３に固着する（図１８ｆ）。次に、半導体チップ３９を搭載し、金ワイヤ４０で半導体チップと配線パターン間を電気的に接続させる（図１８ｇ）。一方、半導体チップ実装方式としてフェースダウン方式を採用する場合には、配線パターンの所定位置（半導体チップの外部接続用電極位置に対応）に金属パンプ等を設け、金属バンプを介して半導体チップと波線パターンとを電気的に接続させても良い。次に、トランスファーモールド用の金型にセットし、樹脂封止材４１で封止する（図１８ｈ）。この場合、樹脂封止材は特に限定するものではなく、例えば、直径１０〜２０μｍ程度のシリカを５〜８０ｗｔ％の範囲で含有したエポキシ系樹脂などが適用できる。次に、外部基板との接続部１２を形成する。接続部１２の形成方法としては、図１８ｃの工程後にあらかじめ電解めっき法によりポリイミドフィルム厚さ以上のバンプを形成しておく方法や樹脂封止後にはんだ印刷法によりはんだバンプを形成する方法などが適用可能である。最後に、フレームからパッケージ部を切断して所望するパッケージが得られる（図１８ｉ）。
【００７７】
図１８の第十六の実施例を更に具体的に説明する。
【００７８】
具体例２
厚さ１２μｍの電解銅箔を片面に有する２層フレキシブル基材（日立化成工業（株）製、商品名：ＭＣＦ ５０００Ｉ）の銅箔面上にドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＫ８１５）をラミネートし、露光、現像により所望するレジストパターンを得た。次に、塩化第二鉄溶液で銅箔をエッチング加工後、レジストパターンを水酸化カリウム溶液で剥離することにより所定の配線パターンを得た。次に、エキシマレーザ加工機（住友重機械工業（株）製、装置名：ＩＮＤＥＸ２００）を用いて絶縁基材側から配線パターン裏面に達する凹部（直径３００μｍ）を所定の位置に所定の数だけ形成した。エキシマレーザ加工条件は、エネルギー密度２５０ｍＪ／ｃｍ２、縮小率３．０、発振周波数２００Ｈｚ、照射パルス数３００パルスである。次に５０μｍ厚さのポリイミドフィルム（宇部興産製、商品名：ＵＰＩＬＥＸ Ｓ）の片面に厚さ１０μｍのポリイミド系接着材（日立化成工業（株）製、商品名：ＡＳ ２２５０）を有する接着シートを作製し、後工程でのワイヤボンド端子部に相当する領域を含む所定領域をパンチ加工により除去し、接着材を介してポリイミドフィルムと配線パターン付き２層フレキ基材とを加熱圧着させた。圧着条件は、圧力２０ｋｇｆ／ｃｍ２、温度１８０℃、加熱加圧時間６０分である。次に、無電解ニッケル、金めっき法によりワイヤボンド用端子部にニッケル／金めっきを施した。めっき厚さは、それぞれ、３μｍ、０．３μｍである。このようにして得られた基板を、個々の配線パターンに分離し、別に用意したＳＵＳフレ−ムに固着した。次に、半導体チップ搭載用ダイボンド材（日立化成工業（株）製、商品名：ＨＭ−１）を用いて半導体チップを搭載した。搭載条件は、プレス圧力５ｋｇｆ／ｃｍ２、接着温度３８０℃及び圧着時間５秒である。次に、ワイヤボンディングにより半導体チップの外部電極部と配線パターンを電気的に接続した。その後、リードフレーム状に金型加工し、トランスファーモールド用金型にセットし、半導体封止用エポキシ樹脂（日立化成工業（株）製、ＣＬ−７７００）を用いて１８５℃、９０秒で封止した。続いて、前述の凹部に所定量のはんだを印刷塗布し、赤外線リフロー炉によりはんだを溶融させて外部接続用バンプを形成した。最後に、パッケージ部を金型で打ち抜き、所望するパッケージを得た。
【００７９】
図１９、２０、２１により本発明の第十七の実施例について説明する。
【００８０】
支持体５１上に複数組の所定の配線パターン５２を形成する（図１９ａ）。支持体としては、電解銅箔などの金属箔の他にポリイミドフィルムなどの絶縁基材を適用できる。絶縁基材を適用する場合には２通りの方法がある。第１の方法は、絶縁基材の所定部分に配線パターンに達する非貫通凹部を形成し、配線パターンの露出部に外部接続端子を形成する方法である。非貫通凹部はエキシマレーザや炭酸ガスレーザなどを適用して形成できる。第２の方法は、接着材付き絶縁基材にドリル加工したものを予め形成しておき、電解銅箔などと積層させた後、銅箔をエッチング加工する方法である。
【００８１】
一方、金属箔を適用する場合には、まずフォトレジストなどによりレジストパターンを形成後、金属箔をカソードとして電気めっき法で配線パターンを形成する。この場合、通常の電解銅箔や電解銅箔上に銅箔と化学エッチング条件の異なる金属（ニッケル、金、はんだ等）の薄層を設けたものなどが適用できる。また、配線パターンとしては銅が好ましいが、前述のように電解銅箔を支持体として適用する場合には、銅箔とエッチング条件の異なる金属自体を配線パターンとして適用したり、あるいは、銅箔エッチング時のバリヤ層となるパターン薄層をパターン銅めっき前に形成したりする必要がある。
【００８２】
次に、ダイボンド材５３で半導体素子５４を搭載後、半導体素子端子と配線パターンとを電気的に接続し（図１９ｂ）、トランスファーモールド法により複数組の半導体素子と配線パターンとを一括して樹脂封止材５６で封止する（図１９ｃ）。樹脂封止材は特に限定するものではなく、例えば、直径１０〜２０μｍ程度のシリカを５〜８０ｗｔ％の範囲で含有したエポキシ樹脂のが適用できる。なお、本発明は半導体素子の実装方式がフェースアップ方式の場合に限定されるものではなく、例えば、フェースダウン方式の場合にも適用可能である。具体的には、配線パターン５２上の所定位置にフェースダウンボンド用のバンプをめっき法などにより形成した後、半導体素子の外部接続部とバンプとを電気的に接続させれば良い。
【００８３】
更に、図２０や図２１に示したように後工程でパッケージを分割しやすいようにしておくことは有効である。このうち、図２０は複数個ある各パッケージ部分の境界部分に溝５９を形成するものである。溝の幅や深さ等は、トランスファーモールド用金型の加工寸法により制御可能である。また、図２１は、あらかじめ各パッケージ部に対応した部分をくり抜いた格子状中間板６０を使用してトランスファーモールドを行なうものである。次に、支持体が金属箔の場合、化学エッチング法などにより支持体を除去し、所定の位置に外部接続用端子５７を形成する（図１９ｄ）。支持体として絶縁基材を適用する場合には、前述したようにレーザ等により所定部分の絶縁基材のみを選択的に除去すれば良い。最後に、一括封止した基板を単位部分５８に切断分離する。なお、配線パターン露出面に配線パターンを保護する目的でソルダーレジスト層を形成しても良い。
【００８４】
第十七の実施例を具体的に説明する。
【００８５】
具体例３
厚さ３５μｍ、外形２５０ｍｍ角の電解銅箔のシャイニー面に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ６４０）をラミネートし、露光、現像により所望するレジストパターン（最少ライン／スペース＝５０μｍ ／５０μｍ ）を形成した。次に、電気めっき法により、厚さ０．２μｍのニッケル、３０μｍの銅、５μｍのニッケル及び１μｍのソフト金で構成される同一の配線パターンを３００個（４ブロック／２５０ｍｍ角、７５個／ブロック）形成した。次に、液温３５℃、濃度３ｗｔ％の水酸化カリウム溶液を用いてレジストパターンを剥離し、８５℃で１５分間乾燥後、各ブロックに切断後、半導体素子実装用ダイボンド材（日立化成工業（株）製、商品名：ＨＭ−１）を用いて半導体素子を接着した。接着条件は、プレス圧力５ｋｇ／ｃｍ２、温度３８０℃及び圧着時間５秒である。次に、半導体素子の外部端子と金めっき端子部（第２の接続部）をワイヤボンドにより電気的に接続した後、トランスファーモールド金型にセットし、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて１８５℃、９０秒で７５個（１ブロックに相当）の配線パターンを一括封止することにより、各配線パターンを封止材中に転写した。次に、アルカリエッチャント（メルテックス（株）製、商品名： Ａ プロセス）を用いて電解銅箔の所望する部分をエッチング除去した。エッチング液の温度は４０℃、スプレー圧力は１．２ｋｇｆ／ ｃｍ２である。次に、印刷法により外部接続端子部にはんだパターンを形成し、赤外線リフロー炉によりはんだを溶融させて外部接続用バンプを形成した。最後に、ダイヤモンドカッターにより、各パッケージ部に分離して所望するパッケージを得た。
【００８６】
具体例４
厚さ３５μｍ、外形２５０ｍｍ角の電解銅箔のシャイニー面に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ６４０）をラミネートし、露光、現像により所望するレジストパターン（最少ライン／スペース＝５０μｍ ／５０μｍ ）を形成した。次に、電気めっき法により、厚さ０．２μｍのニッケル、３０μｍの銅、５μｍのニッケル及び１μｍのソフト金で構成される同一の配線パターンを３００個（４ブロック／２５０ｍｍ角、７５個／ブロック）形成した。次に、液温３５℃、濃度３ｗｔ％の水酸化カリウム溶液を用いてレジストパターンを剥離し、８５℃で１５分間乾燥後、各ブロックに切断後、半導体素子実装用ダイボンド材（日立化成工業（株）製、商品名：ＨＭ−１）を用いて半導体素子を接着した。接着条件は、プレス圧力５ｋｇ／ｃｍ２、温度３８０℃及び圧着時間５秒である。次に、半導体素子の外部端子と金めっき端子部（第２の接続部）をワイヤボンドにより電気的に接続した。次に、パッケージ領域に相当する部分（１５ｍｍ角）をくり抜いた格子状ステンレス板を中間板としてトランスファーモールド金型にセットし、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて１８５℃、９０秒で７５個（１ブロックに相当）の配線パターンを一括封止することにより、各配線パターンを封止材中に転写した。中間板の格子部分は、各パッケージが中間板から分離しやすいように１２°のテーパがついている。次に、アルカリエッチャント（メルテックス（株）製、商品名： Ａ プロセス）を用いて電解銅箔の所望する部分をエッチング除去した。各パッケージ部は、格子状中間板で保持されている。エッチング液の温度は４０℃、スプレー圧力は１．２ｋｇｆ／ ｃｍ２である。最後に、印刷法により外部接続端子部にはんだパターンを形成し、赤外線リフロー炉によりはんだを溶融させて外部接続用バンプを形成し、中間板から各パッケージ部に分離して所望するパッケージを得た。
【００８７】
図２２により本発明の第十八の実施例について説明する。
【００８８】
導電性の仮支持体６１（図２２ａ）上に複数組の所定のレジストパターン６２（図２２ｂ）を形成する。次に、電気めっき法により仮支持体の露出部に配線パターン６３を形成する。この場合、仮支持体は特に限定されるものではなく、例えば、通常の電解銅箔や電解銅箔上に銅箔と化学エッチング条件の異なる金属（ニッケル、金、はんだ等）の薄層を設けたものなどが適用できる。また、配線パターンとしては銅が好ましいが、前述のように電解銅箔を仮支持体として適用する場合には、銅箔とエッチング条件の異なる金属自体を配線パターンとして適用したり、あるいは、銅箔エッチング時のバリヤ層となるパターン薄層をパターン銅めっき前に形成したりする必要がある。仮支持体の厚さは、後工程でのハンドリング性や半導体素子実装時の寸法安定性などの点で支障がなければ特に限定されることはない。次に、仮支持体をカソードとして金ワイヤボンド用のめっき（通常は、ニッケル／金）６４を施した後、レジストパターンを除去する（図２２ｃ）。なお、本発明は半導体素子の実装方式がフェースアップ方式の場合に限定されるものではなく、例えば、フェースダウン方式の場合にも適用可能である。具体的には、配線パターン６３上の所定位置にフェースダウンボンド用のバンプをめっき法などにより形成した後、半導体素子の外部接続部とバンプとを電気的に接続させれば良い。
【００８９】
次に、半導体素子６５をダイボンド材６６などで接着し、半導体素子の外部接続端子と配線パターンとを電気的に接続する（図２２ｄ）。次に、トランスファーモールド用金型にセットし、樹脂封止材６８で封止する（図２２ｅ）。この場合、樹脂封止材は特に限定するものではなく、例えば、直径１０〜２０μｍ程度のシリカを５〜８０ｗｔ％の範囲で含有したエポキシ樹脂が適用できる。
【００９０】
次に、外部接続端子に相当する箇所に所定の金属パターン６９を形成する（図２２ｆ）。この場合、適用する金属としては、導電性仮支持体をエッチング除去する条件下でエッチングされないものであれば良く、例えば、はんだ、金、ニッケル／金などが適用可能である。また、金属パターンの形成法としては、公知の電気めっき法やはんだ印刷法などが適用できる。更に、金属パターン６９をはんだパターンを印刷法で形成する場合、リフローすることによりハンダバンプ７０を形成することができる。この場合、パターン６９の厚さを調節することにより、リフロー後のはんだバンプ７０の高さを制御することができる。次に、金属パターンをエッチングレジストとして仮支持体の所定部分を除去し、配線パターンを露出させる。
【００９１】
最後に、金型加工、あるいは、ダイシング加工など適用して各パッケージ７１を分割する（図２２ｇ）。なお、露出した配線パターンがニッケルなどの耐腐食性金属で保護されていない場合には、外部接続端子部以外の領域を公知のソルダーレジストなどで被覆しても良い。また、はんだを金属パターンとして適用する場合、リフロー工程は特に限定するものではなく、各パッケージに分割する前でも後でも良いし、あるいは、外部配線基板上に各パッケージを実装する際に行なっても良い。
【００９２】
第十八の実施例を具体的に説明する。
【００９３】
具体例５
厚さ７０μｍの電解銅箔のシャイニー面に、感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ６４０）をラミネートし、露光、現像により所望するレジストパターン（最少ライン／スペース＝５０μｍ ／５０μｍ ）を形成した。次に、電気めっき法により、厚さ０．２μｍのニッケル、３０μｍの銅、５μｍのニッケル及び１μｍのソフト金で構成される配線パターンを形成した。次に、液温３５℃、濃度３ｗｔ％の水酸化カリウム溶液を用いてレジストパターンを剥離し、８５℃で１５分間乾燥後、半導体素子実装用ダイボンド材（日立化成工業（株）製、商品名：ＨＭ−１）を用いて半導体素子を接着した。接着条件は、プレス圧力５ｋｇ／ｃｍ２、温度３８０℃及び圧着時間５秒である。次に、半導体素子の外部端子と金めっき端子部（第２の接続部）をワイヤボンドにより電気的に接続した後、トランスファーモールド金型にセットし、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて１８５℃、９０秒で封止することにより、配線パターンを封止材中に転写した。次に、電解銅箔上に感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、露光、現像により所望するレジストパターンを形成後、電気めっき法により厚さ４０μｍのはんだパッド（直径０．３ｍｍφ、配置ピッチ１．０ｍｍ）を形成した。次に、ドライフィルムレジストを剥離した後、アルカリエッチャント（メルテックス（株）製、商品名： Ａ プロセス）を用いて電解銅箔の所望する部分をエッチング除去した。エッチング液の温度は４０℃、スプレー圧力は１．２ｋｇｆ／ｃｍ２である。最後に、赤外線リフロー炉によりはんだを溶融させて外部接続用バンプを形成した。
【００９４】
図２３、２４、２５により本発明の第十九の実施例を説明する。
【００９５】
半導体実装用フレームの構成について図２３を用いて説明する。８９は半導体実装用基板であり絶縁基材と配線によって構成される。基板部と連結部９０を介して、複数個連結されている。連結部９０には、基準位置用ピン穴９１が形成される。ピン穴９１の代わりに画像認識で用いられる認識マーク等でも構わない。後工程では、これらの基準位置をもとに位置が決められる。特に半導体を樹脂でモールドする際はキャビティ内のピンをピン穴９１にさして位置合わせを行うことなどが行われる。
【００９６】
更に図２４及び２５を用いて説明する。導電性仮基板である厚さ約０．０７０ｍｍの電解銅箔８１の片面に厚さ０．００１ｍｍのニッケル層（図２４、２５では省略）を電解めっきで形成した。次に感光性ドライフィルムレジスト（日立化成工業（株）製、商品名：フォテックＨＮ３４０）をラミネートし、露光、現像により複数組の配線パターンのめっきレジストを形成する。この時の露光量は７０ｍＪ／ｃｍ２である。さらに、公知の硫酸銅浴にて電解銅めっきを行い、レジストを剥離し、複数組の配線８２を形成する（図２４ａ、図２５ａ）。ここで、図２５ａに示したように連結部もにめっき銅８２’を形成することも考えられ、これにより出来上がりのフレームの剛性をさらに高めることも可能である。図２４ａ、図２５ａに示した構成は、銅／ニッケル薄層／銅の３層からなる基材をあらかじめ用意し、片方の銅箔を通常のエッチング工程で配線形成しても得られる。また、ここで得られた銅箔８１／ニッケル薄層（図示せず）／銅配線８２（及び８２’）の構成を銅箔／ニッケル配線、ニッケル箔／銅配線等、ニッケル薄層のない２層構造にしてもよい。すなわち、金属種の撰択は本実施例の種類に限られることはないが、後の工程で仮基板の一部をエッチング除去（図２４ｃ、図２５ｃ）したときに、配線が撰択的に残るようにできることが好適な撰択基準となる。また、導電性仮基板はフレームの連結部の構成材となるため厚いほうが好ましいが、後でその一部をエッチング除去する工程があるため、適当な厚さを撰択する必要がある。導電性仮基板の厚みとしては、材質にもよるが、例えば銅箔を用いる場合、約０．０３〜０．３ｍｍ程度が好ましい。次に、複数組の配線８２を形成した銅箔８１の配線面にポリイミド接着剤８３を接着した。ここで、ポリイミド接着剤８３は、この材料に限られることなく、例えば、エポキシ系接着フィルム、ポリイミドフィルムに接着剤を塗布したフィルム等も利用可能である。次に、エキシマレーザを用いて外部接続端子用穴８４を形成した（図２４ｂ、図２５ｂ）。後工程における工程簡略化のためには半導体を実装する前に接続端子を設けておくことが好適である。また、この穴８４の形成法として他に、あらかじめドリルやパンチ加工でフィルムに外部接続端子用穴８４を形成しておき、このフィルムを接着する方法を用いてもかまわない。さらにここで、この穴８４に接続端子として用いる半田等の金属（図２４ｆ、図２５ｆの８８に相当）を充填させておいてもかまわないが、後の半導体実装工程、樹脂封止工程では、金属突起が障害となることもあり、後の工程で形成する方が好ましい。半導体素子実装基板部の外部接続端子用穴（または端子）は半導体素子搭載反対面にアレイ状に配置されるようにしるのが好ましい。
【００９７】
次に、配線パターンが形成されている部分の仮基板である電解銅箔の一部をエッチング除去した。このエッチング液として、この実施例の構成の場合、ニッケルに比べて銅の溶解速度が著しく高いエッチング液、エッチング条件を撰択するのがよい。この実施例では、エッチング液としてアルカリエッチャント（メルテックス（株）製、商品名： Ａ プロセス）が、エッチング条件としては例えば液温度を４０℃、スプレー圧力を１．２ｋｇｆ／ｃｍ２とした。ここで示した液の種類、条件は一例にすぎない。この工程によって基板部分のニッケル薄層が露出される。このニッケル薄層だけをエッチングする際には、銅よりニッケルの溶解速度が著しく高いエッチング液、エッチング条件を撰択するのがよい。この実施例では、ニッケルエッチャント（メルテックス（株）製、商品名：メルストリップ Ｎ９５０）で選択的にエッチング除去した。エッチング液の温度を４０℃、スプレー圧力を１．２ｋｇｆ／ｃｍ２とした。ここで示した液の種類、条件も一例にすぎない。このような工程を経て、連結部の仮基板が残され、剛性のある半導体実装用フレームが得れれる（図２４ｃ、図２５ｃ）。この実施例ではこのフレームの銅配線端子部分には無電解ニッケル−金めっきが施される（図では省略）。これは、後工程でチップをワイヤーボンディングするために必要であり、このような表面処理は必要に応じて施せばよい。
【００９８】
さらに半導体チップ８５を搭載する。半導体チップの接着には、半導体用ダイボンディングテープ８６（例えば、日立化成工業（株）製、商品名：ＨＭ−１）を用いた。ここで、チップの下に配線がない場合には、ダイボンド用銀ペーストを用いて接着してもよい。次に半導体端子部と配線とをワイヤボンド１００により接続する（図２４ｄ、図２５ｄ）。半導体端子との接続は、他の方法、例えば、フェイスダウンによるフィリップチップ接続や異方導電性背着剤による接着でもよい。このようにして形成したものをトランスファモールド金型に装填し、半導体封止用エポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７７００）を用いて各々封止８７する（図２４ｅ、図２５ｅ）。その後、配線８２の接続端子部に設けた接続用穴にはんだボール８８を配置し溶融させて形成する（図２４ｆ、図２５ｆ）。このはんだボール８８はいわゆる外部接続端子となる。連結部１０２によってつながっている複数個の半導体装置を金型で打ち抜いて個々の半導体装置が得られる（図２４ｇ、図２５ｇ）。
【００９９】
この実施例では、半導体実装用フレーム及び半導体装置製造法により、ポリイミドテープ等フィルム基板を用いたＢＧＡ、ＣＳＰ等の半導体装置製造において、十分な剛性を備えたフレームを得ることができ、これを利用することによって半導体装置を精度良く効率良く作製可能になる。
【０１００】
本発明により、半導体チップの高集積度化に対応することができる半導体パッケージを生産性良く、かつ安定的に製造することができる。
【図面の簡単な説明】
【図１】図１は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２】図２は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図３】図３は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図４】図４は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図５】図５は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図６】図６は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図７】図７は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図８】図８は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図９】図９は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１０】図１０は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１１】図１１は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１２】図１２は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１３】図１３は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１４】図１４は、本発明の半導体パッケージの製造法の一例を説明する平面図である。
【図１５】図１５は、本発明の半導体パッケージの製造法の一例を説明する平面図である。
【図１６】図１６は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１７】図１７は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１８】図１８は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図１９】図１９は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２０】図２０は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２１】図２１は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２２】図２２は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２３】図２３は、本発明の半導体パッケージの製造法の一例を説明する平面図である。
【図２４】図２４は、本発明の半導体パッケージの製造法の一例を説明する断面図である。
【図２５】図２５は、本発明の半導体パッケージの製造法の一例を説明する断面図である。[0001]
(Technical field)
The present invention relates to a method of manufacturing a semiconductor package and a semiconductor package.
[0002]
(Background technology)
As the degree of integration of semiconductors has improved, the number of input / output terminals has increased. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, there are a type in which input / output terminals are arranged in a row around the package and a type in which the input / output terminals are arranged in multiple rows not only in the periphery but also in the interior. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in a region having a pitch of 0.5 mm or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch.
[0003]
Conventionally, the array type is generally a PGA (Pin Grid Array) having connection pins, but the connection to the wiring board is an insertion type and is not suitable for surface mounting. Therefore, a package called BGA (Ball Grid Array) that can be mounted on the surface has been developed. The BGA classification includes (1) ceramic type, (2) printed wiring board type, and (3) tape type using TAB (tape automated bonding). Among these, the ceramic type has a serious problem of package warpage due to the difference in thermal stress between the mother board and the package because the distance between the mother board and the package is shorter than the conventional PGA. Also, the printed wiring board type has a problem that the substrate thickness is large in addition to the warp, moisture resistance, reliability, etc. of the substrate, and a tape BGA to which the TAB technology is applied has been proposed.
[0004]
As a countermeasure for further downsizing of the package size, a so-called chip size package (CSP) having a size almost equal to that of a semiconductor chip has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip.
[0005]
As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, and after electrical connection is made between the chip and a gold lead wire, epoxy resin or the like is potted and sealed (NIKKEI MATERIALS & TECHNOLOGY 94. 4, No. 140, p.18-19) or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions between the semiconductor chip and the external wiring substrate, and the semiconductor chip is transferred on the temporary substrate after face-down bonding. Molded (Smallest Flip-Chip-Like Package CSP; The Second VLSI Packaging Workshop of Japan, p46-50, 1994).
[0006]
On the other hand, as described above, packages using a polyimide tape as a base film have been studied in the BGA and CSP fields. In this case, the polyimide tape is generally laminated with a copper foil via an adhesive layer on a polyimide film, but a polyimide layer is formed directly on the copper foil from the viewpoint of heat resistance and moisture resistance. A so-called two-layer flexible substrate is preferred. The production method of the two-layer flexible substrate is as follows: (1) a method of applying a polyamic acid, which is a polyimide precursor, on a copper foil and then heat-curing; (2) a vacuum film-forming method on a cured polyimide film; A method of forming a metal thin film by electrolytic plating or the like is roughly divided. For example, laser processing is applied to remove polyimide at a desired portion (corresponding to the second connection function portion) and reach the copper foil. Is preferably as thin as possible. On the other hand, when the two-layer flexible base material is processed into a lead frame and handled, there are problems such as lack of handling properties and rigidity as a frame if the base film thickness is thin.
[0007]
As described above, various proposals have been made as semiconductor packages that can cope with downsizing and high integration, but further improvements are desired to satisfy all of the performance, characteristics, productivity, and the like.
[0008]
The present invention provides a method for manufacturing a semiconductor package and a semiconductor package that enable a semiconductor package that can be reduced in size and highly integrated to be manufactured with high productivity and stability.
[0009]
(Disclosure of the Invention)
The first invention of the present application is
1A. Forming a wiring on one side of the conductive temporary support,
1B. A step of mounting a semiconductor element on a conductive temporary support on which wiring is formed, and conducting the semiconductor element terminal and the wiring;
1C. A step of resin-sealing a semiconductor element;
1D. Removing the conductive temporary support to expose the wiring;
1E. Forming an insulating layer other than where the external connection terminals of the exposed wiring are formed;
1F. A process of forming external connection terminals at locations where the wiring insulation layer is not formed
A method for manufacturing a semiconductor package, comprising:
[0010]
The second invention of the present application is:
2A. Forming a wiring on one side of the conductive temporary support,
2B. Forming an insulating support on the surface of the conductive temporary support on which the wiring is formed;
2C. Removing the conductive temporary support and transferring the wiring to the insulating support;
2D. Removing the insulating support at the location where the external connection terminal of the wiring is formed and providing a through hole for the external connection terminal;
2E. A process of mounting a semiconductor element on an insulating support to which wiring is transferred, and conducting the semiconductor element terminal and the wiring;
2G. A step of resin-sealing a semiconductor element;
2H. Forming external connection terminals that are electrically connected to the wiring in the through holes for external connection terminals
A method for manufacturing a semiconductor package, comprising:
[0011]
In the second invention, it is preferable to proceed in the order of 2A to 2H, but the 2D process may be performed before 2B. For example, the process of 2B may be performed by bonding an insulating film insulating support provided with a through hole for an external connection terminal in advance to the surface of the conductive temporary support on which the wiring is formed.
[0012]
The third invention of the present application is:
3A. Forming a wiring on one side of the conductive temporary support,
3B. A step of mounting a semiconductor element on a conductive temporary support on which wiring is formed, and conducting the semiconductor element terminal and the wiring;
3C. A step of resin-sealing a semiconductor element;
3D. Removing the conductive temporary support other than the portion where the external connection terminal of the wiring is formed to form an external connection terminal made of the conductive temporary support;
3E. And a step of forming an insulating layer in addition to the location of the external connection terminal.
[0013]
The fourth invention of the present application is:
4A. Forming a wiring on one side of the conductive temporary support,
4B. A step of mounting a semiconductor element on a conductive temporary support on which wiring is formed, and conducting the semiconductor element terminal and the wiring;
4C. A step of resin-sealing a semiconductor element;
4D. A step of forming a metal pattern having a different removal condition from the conductive temporary support at a position where the external connection terminal of the wiring on the opposite side to the semiconductor element mounting surface of the conductive temporary support is formed
4E. The step of removing the conductive temporary support other than the portion where the metal pattern is formed
A method for manufacturing a semiconductor package, comprising:
[0014]
The metal pattern is preferably a solder, or may be a nickel layer followed by a gold layer.
[0015]
The fifth invention of the present application is:
5A. Forming a plurality of sets of wirings on one side of the insulating support;
5B. The process of removing the insulating support at the location to be the external connection terminal of the wiring and providing the through hole for the external connection terminal
5C. A step of mounting a semiconductor element on an insulating support formed with a plurality of sets of wirings, and electrically connecting the semiconductor element terminals and the wiring;
5D. A step of resin-sealing a semiconductor element;
5E. Forming an external connection terminal that is electrically connected to the wiring in the through hole for the external connection terminal;
5F. Separating into individual semiconductor packages
A method for manufacturing a semiconductor package, comprising:
[0016]
In the fifth invention, it is preferable that the manufacturing process proceeds in the order of 5A to 5F, but 5A and 5B may be reversed. That is, a plurality of sets of wirings may be formed on the insulating support provided with the through holes for external connection terminals.
[0017]
The sixth invention of the present application is:
6A. Forming a plurality of sets of wirings on one side of the conductive temporary support;
6B. The plurality of sets of wirings formed on the conductive temporary support are cut and separated so that a predetermined unit number is obtained, and the separated conductive temporary support on which the wiring is formed is fixed to the frame. Process,
6C. A step of mounting a semiconductor element on a conductive temporary support on which wiring is formed, and conducting the semiconductor element terminal and the wiring;
6D. A step of resin-sealing a semiconductor element;
6E. Removing the conductive temporary support to expose the wiring;
6F. Forming an insulating layer other than where the external connection terminals of the exposed wiring are formed;
6G. A process of forming external connection terminals at locations where the wiring insulation layer is not formed
6H. Separating into individual semiconductor packages
A method for manufacturing a semiconductor package, comprising:
[0018]
The predetermined unit number of 6B is preferably one, but may be plural in order to increase productivity.
[0019]
The seventh invention of the present application is
7A. Forming a plurality of sets of wirings on one side of the insulating support;
7B. The process of removing the insulating support at the location to be the external connection terminal of the wiring and providing the through hole for the external connection terminal
7C. Cutting and separating the insulating support so that a plurality of sets of wires formed on the insulating support have a predetermined unit number, and fixing the separated insulating support on which the wires are formed to the frame;
7D. Mounting a semiconductor element on an insulating support on which wiring is formed, and conducting the semiconductor element terminal and the wiring;
7E. A step of resin-sealing a semiconductor element;
7F. Forming an external connection terminal that is electrically connected to the wiring in the through hole for the external connection terminal;
7G. Separating into individual semiconductor packages
A method for manufacturing a semiconductor package, comprising:
[0020]
The manufacturing process preferably proceeds in the order of 7A to 7G, but 7A and 7B may be reversed as in the fifth invention.
[0021]
The eighth invention of the present application has a first connection function in which one side of the wiring in one layer wiring connects to the semiconductor element, and a second connection function in which the opposite side of the wiring connects to an external wiring. A method for manufacturing a semiconductor package comprising wiring configured as described above, comprising the following steps 8A, 8B, 8C, and 8D.
8A. The process which processes the metal foil of the insulation base material with a metal foil which has heat resistance into several sets of wiring patterns.
8B. The process of providing the recessed part which reaches a wiring pattern from the insulating base material side in the position used as a 2nd connection function part in a post process.
8C. A step of bonding a frame substrate having a predetermined portion opened to a desired position on the wiring pattern surface and the insulating substrate surface adjacent to the wiring pattern.
8D. A step of mounting a semiconductor element, conducting the semiconductor element terminal and wiring, and sealing the semiconductor element with resin.
[0022]
In the eighth invention, the steps are preferably carried out in the order of 8A to 8D, but 8A and 8B may be reversed. That is, the metal foil may be processed into a wiring pattern after providing a recess reaching the metal foil on the insulating substrate.
[0023]
According to a ninth aspect of the present application, in one layer of wiring, one side of the wiring has a first connection function of connecting to a semiconductor element, and the opposite side of the wiring has a second connection function of connecting to an external wiring. A method of manufacturing a semiconductor package comprising wiring configured as described above, comprising the following steps 9A, 9B, 9C, and 9D.
9A. The process which processes the metal foil of the insulation base material with a metal foil which has heat resistance into several sets of wiring patterns.
9B. The process of providing the recessed part which reaches a wiring pattern from the insulating base material side in the position used as a 2nd connection function part in a post process.
9C. A step of forming an insulating support by bonding a wiring pattern surface and a second insulating substrate having a predetermined portion opened at a desired position on an insulating substrate surface adjacent to the wiring pattern.
9D. A step of cutting and separating the insulating support so that a plurality of sets of wirings formed on the insulating support have a predetermined unit number, and fixing the separated insulating support formed with the wires to the frame.
9E. A step of mounting a semiconductor element, conducting the semiconductor element terminal and wiring, and encapsulating the semiconductor element with resin.
[0024]
In the ninth invention, the steps are preferably carried out in the order of 9A to 9E, but 9A and 9B may be reversed as in the eighth invention.
[0025]
The tenth invention of the present application is:
10A. Forming a plurality of sets of wirings on one side of the support,
10B. Mounting a plurality of semiconductor elements on a support on which wiring is formed, and conducting the semiconductor element terminals and the wiring;
10C. A process of resin-sealing a plurality of conductive semiconductor elements and wirings collectively;
10D. Removing a desired portion of the support to expose a predetermined portion of the wiring, and forming an external connection terminal electrically connected to the exposed wiring;
10E. Separating into individual semiconductor packages
A method for manufacturing a semiconductor package, comprising:
[0026]
A metal foil may be used as the support, and the wiring pattern may be exposed by removing the support after resin sealing.
[0027]
Alternatively, the support may be an insulating base material, and a predetermined portion of the insulating base material may be removed after resin sealing to form a non-penetrating recess that reaches the wiring pattern.
[0028]
An eleventh invention of the present application includes a plurality of semiconductor element mounting substrate portions, a connecting portion for connecting the plurality of semiconductor element mounting substrate portions, and an alignment mark portion. A method of manufacturing a frame,
(A) producing a wiring for a semiconductor element mounting portion on a conductive temporary substrate;
(B) a step of transferring the wiring onto the resin substrate;
(C) a step of removing the conductive temporary substrate by etching;
And (c) a method of manufacturing a frame for mounting a semiconductor element, wherein a part of the connecting portion is formed by leaving a part of the conductive temporary substrate when the conductive temporary substrate is removed. .
[0029]
In the present invention, a normal element such as an LSI chip or an IC chip can be used as the semiconductor element.
[0030]
As a method for allowing the semiconductor element terminal and the wiring to communicate with each other, not only wire bonding but also normal means such as a bump and an anisotropic conductive film can be used.
[0031]
In the present invention, a semiconductor package free from warpage and deformation can be produced by heat-treating the cured resin product after resin-sealing the semiconductor element.
[0032]
The heat treatment is preferably performed at a glass transition temperature ± 20 ° C. of the cured encapsulated resin. This is because the cured resin has the strongest plastic property within the range of the glass transition temperature ± 20 ° C., and it is easy to eliminate the residual strain. When the temperature of the heat treatment is less than the glass transition temperature of −20 ° C., the cured resin tends to be an elastic body in a glass state, and the effect of relaxation tends to decrease. When the temperature of the heat treatment exceeds + 20 ° C., the cured resin becomes a rubber elastic. Similarly, the effect of eliminating distortion tends to be lost.
[0033]
Heat treatment at a glass transition temperature of ± 20 ° C of the cured encapsulated resin and then cooling to room temperature at a rate of 5 ° C / min or less can prevent the semiconductor package from warping and deformation more reliably. can do.
[0034]
The heat treatment and / or cooling step is preferably carried out in a state where the upper and lower surfaces of the cured encapsulated resin are pressed by a rigid flat plate with a force that suppresses warpage and deformation of the encapsulated cured resin.
[0035]
In the semiconductor package of the present invention, the wiring has a first connection function in which one side of the wiring is connected to the semiconductor chip in a single layer wiring, and the second connection function is connected to the external wiring on the opposite side of the wiring. It is comprised so that it may have.
[0036]
For example, solder bumps and gold bumps can be preferably used as the external connection terminals connected to the external wiring.
[0037]
It is preferable to provide the external connection terminals on the inner side from the position where the semiconductor element terminals are electrically connected to the wiring by wire bonding or the like (fan-in type). As described above, the external connection terminals are preferably arranged in a grid pattern on the lower surface on which the semiconductor element is mounted in terms of increasing the density.
[0038]
(Best Mode for Carrying Out the Invention)
The first embodiment of the present invention will be described with reference to FIG.
[0039]
A nickel layer (not shown in FIG. 1) having a thickness of 0.001 mm is plated on one surface of an electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 1a). In this way, the LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is formed (FIG. 1b). For bonding the LSI chip, a silver paste 4 for semiconductor was used. Next, the LSI terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 1c). What was formed in this way was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 1d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having low copper solubility to expose the wiring portion (FIG. 1e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed and melted in the wiring exposed portions (FIG. 1f). The solder balls 7 are connected to external wiring.
[0040]
The second embodiment of the present invention will be described with reference to FIG.
[0041]
A copper foil 1 having wirings 2 was created in the same manner as in FIG. 1 (FIG. 2a). The LSI chip 3 is mounted. In the LSI chip, gold bumps 8 are formed on the terminal portions, and the gold bumps 8 and the terminal portions of the wiring 2 are connected by heating and pressing (FIG. 2b). Next, the lower part of the LSI chip is filled with a liquid epoxy resin and cured 9 (FIG. 2c). What was formed in this way was loaded into a transfer mold, and sealed 10 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 2d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having a low copper solubility to expose the wiring portion (FIG. 2e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portions and melted (FIG. 2f). The solder balls 7 are connected to external wiring.
[0042]
A third embodiment of the present invention will be described with reference to FIG.
[0043]
A nickel layer (not shown in FIG. 3) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath to form the first wiring 13. Next, the plating resist is peeled off, and the surface of the first wiring 13 is subjected to oxidation treatment and reduction treatment. Using a polyimide adhesive film (manufactured by Hitachi Chemical Co., Ltd., trade name: AS2210) 12 as a new copper foil and adhesive resin, lamination bonding is performed so that the wiring 13 is on the inside. (A hole having a diameter of 0.1 mm is formed in the copper foil 11 by a normal photoetching method. The inside of the hole and the entire surface of the copper foil are copper-plated by a panel plating method.) Form. The resin (polyimide adhesive film 12) on the LSI mounting portion is removed by an excimer laser to expose the terminal portion. The terminal part is plated with 0.003 mm of nickel plating and gold plating with a purity of 99.9% or more with a thickness of 0.0003 mm or more (FIG. 3a). In this manner, the LSI chip is mounted on the copper foil 1 on which the two-layer wiring is formed. For bonding the LSI chip, a silver paste for semiconductor was used (FIG. 3b). Next, the LSI terminal portion and the wiring 13 are connected by a wire bond 100 (FIG. 3c). What was formed in this way was loaded in a transfer mold die, and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having a low copper solubility to expose the wiring portion (FIG. 3e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed portions and melted (FIG. 3f). The solder balls 7 are connected to external wiring.
[0044]
A fourth embodiment of the present invention will be described with reference to FIG.
[0045]
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on a SUS (stainless steel) plate 14 having a thickness of 0.1 mm, and the wiring pattern is exposed and developed, and the plating resist is applied. Form. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 4a). The semiconductor chip 103 is mounted on the SUS plate 14 on which the wiring 2 is formed in this way (FIG. 4b). A semiconductor-based silver base 4 was used for bonding the semiconductor chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 4c). What was formed in this way was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 4d). Thereafter, the SUS plate 14 was mechanically peeled and removed to expose the wiring portion (FIG. 4e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portion and melted (FIG. 4f). The solder balls 7 are connected to external wiring.
[0046]
The fifth embodiment of the present invention will be described with reference to FIG.
[0047]
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, after nickel pattern plating 15 is performed, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 5a). The semiconductor chip 103 is mounted on the copper foil 1 on which the wiring 2 is thus formed (FIG. 5b). For bonding the semiconductor chip, a silver base 4 for semiconductor was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 5c). What was formed in this way was loaded into a transfer mold die, and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 5d). Thereafter, the copper foil 1 was dissolved and removed with an alkaline etchant to expose the nickel wiring portion (FIG. 5e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portions and melted (FIG. 5f). The solder balls 7 are connected to external wiring.
[0048]
The sixth embodiment of the present invention will be described with reference to FIG.
[0049]
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the plating resist is peeled off, and the wiring 2 is formed (FIG. 6a). The polyimide film 16 is bonded to the wiring surface of the copper foil 1 on which the wiring 2 is formed in this way, the connection terminal portion of the wiring 2 is exposed using a laser (FIG. 6b), and the copper foil 1 is removed by etching. (Figure 6c). Further, by using a photosensitive film instead of polyimide, the connection terminal portion can be exposed without using a laser. Subsequently, the LSI chip 3 is mounted on the wiring pattern surface of the polyimide film 16. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 6d). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 6e). Thereafter, the solder balls 7 are placed on the connecting terminal portions and melted (FIG. 6f). The solder balls 7 are connected to external wiring.
[0050]
The seventh embodiment of the present invention will be described with reference to FIG.
[0051]
A nickel layer (not shown in FIG. 7) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 7a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is thus formed. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 7b). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 7c). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel. The wiring layer is exposed by removing the nickel layer with a nickel stripping solution having low copper solubility (FIG. 7d). Subsequently, the polyimide film 16 having the connection terminal portion opened is adhered (FIG. 7e), and the solder balls 7 are disposed on the wiring exposed portion and melted (FIG. 7f). The solder balls 7 are connected to external wiring.
[0052]
An eighth embodiment of the present invention will be described with reference to FIG.
[0053]
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, and the plating resist is peeled off to form the wiring 2 (FIG. 8a). The liquid sealing resin 17 is applied by screen printing to the wiring surface of the copper foil 1 on which the wiring 2 is formed in this way, and an insulating layer is formed so as to expose the connection terminal portion of the wiring 2 (FIG. 8b). . After the liquid sealing resin is cured, the copper foil 1 is removed by etching (FIG. 8c). Subsequently, the LSI chip 3 is mounted on the wiring pattern surface of the cured liquid sealing resin 3. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 8d). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 8e). Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring 2 and melted (FIG. 8f). The solder balls 7 are connected to external wiring.
[0054]
A ninth embodiment of the present invention will be described with reference to FIG.
[0055]
A nickel layer (not shown in FIG. 9) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 9a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is thus formed. A semiconductor silver paste 4 was used for bonding the LSI chip 3. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 9b). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 9c). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel. The nickel layer is removed with a nickel stripping solution with low copper solubility to expose the wiring portion (FIG. 9d). Subsequently, the liquid sealing resin 17 is applied by screen printing, and an insulating layer of the liquid sealing resin 17 is formed so as to expose the connection terminal portion of the wiring 2 (FIG. 9e). Solder balls 7 are placed on the connection terminals of the wires 2 and melted (FIG. 9f). The solder balls 7 are connected to external wiring.
[0056]
A tenth embodiment of the present invention will be described with reference to FIG.
[0057]
A nickel layer (not shown in FIG. 10) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plating resist for wiring patterns and alignment marks is formed by exposure and development. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, after the plating resist is peeled off and the wiring 2 and the alignment mark 18 are formed (FIG. 10a), only the position of the alignment mark 18 is sandwiched between the SUS plates and pressed, so that the alignment mark is formed on the back surface of the copper foil 1. Is raised (FIG. 10b). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 and the alignment mark 18 are thus formed (FIG. 10c). A semiconductor silver paste 4 was used for bonding the LSI chip 3. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 10d). What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 10e). A photosensitive dry film is again laminated on the back side of the copper foil, and an etching pattern is formed using the alignment mark 18. Thereafter, the copper foil 1 and the nickel layer are etched to form the bumps 7 by the copper foil 1 and expose the wiring portion (FIG. 10f). Subsequently, a solder resist 8 was applied, and an insulating layer was formed so that the bumps 7 were exposed (FIG. 10g). The bumps 7 are connected to external wiring.
[0058]
An eleventh embodiment of the present invention will be described with reference to FIG.
[0059]
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and a plurality of sets of wiring patterns are exposed and developed to form a plating resist. Form. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 11a). In this way, the polyimide film 19 is adhered to the wiring surface of the copper foil 1 on which a plurality of sets of wirings 2 are formed, the connection terminal portions of the wirings 2 are exposed using a laser (FIG. 11b), and the copper foil 1 is etched. (Fig. 11c). As described above, after a plurality of sets of wirings 2 are formed on one polyimide film, the LSI chip 3 is mounted. For bonding the LSI chip, a semiconductor die bonding tape 4 'was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 11d). What was formed in this way was loaded into a transfer mold die, and each was sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 11e). . Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring 2 and melted (FIG. 11f). The solder balls 7 are connected to external wiring. Finally, the package connected with the polyimide film is punched out with a mold (FIG. 11g).
[0060]
A twelfth embodiment of the present invention will be described with reference to FIG.
[0061]
A polyimide film 20 with an adhesive having a thickness of 0.07 mm is punched out with a mold and a portion to be a connection terminal portion is opened (FIG. 12a). Next, after bonding a copper foil 21 having a thickness of 0.035 mm (FIG. 12b), a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring patterns are formed. Exposure and development are performed to form an etching resist. Subsequently, the copper foil is etched, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 12c). As described above, after a plurality of sets of wiring patterns are formed on one polyimide film, the LSI chip 3 is mounted. For bonding the LSI chip 3, a semiconductor die bonding tape 4 ′ was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 12d). What was formed in this way was loaded into a transfer mold die, and each was sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 12e). . Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring and melted (FIG. 12f). The solder balls 7 are connected to external wiring. Finally, the package connected with the polyimide film is punched out with a mold (FIG. 12g).
[0062]
A thirteenth embodiment of the present invention will be described with reference to FIGS.
[0063]
A nickel layer (not shown in FIG. 13) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Furthermore, nickel plating was plated at a thickness of 0.003 mm and a purity of 99.9% or more at a thickness of 0.0003 mm or more, the plating resist was peeled off, and wiring 2 was formed (FIG. 13a). Next, the copper foil 1 on which the wiring 2 was formed was divided into unit numbers, and then attached to a separately prepared stainless steel frame 22 (thickness: 0.135 mm) via a polyimide adhesive film (FIG. 13b). As the frame, a copper alloy such as phosphor bronze, copper foil, nickel foil, nickel alloy foil or the like can be used. As other bonding methods, bonding using a eutectic between metals, bonding using ultrasonic waves, or the like can be used. Further, as shown in FIG. 14, the wiring on the copper foil 1 may be inspected in advance, and only the non-defective wiring 23 may be selected and attached to the frame 22. In FIG. 14, 1 is an electrolytic copper foil, 22 is a frame, 24 is a defective wiring product, and 25 is an alignment hole. In this embodiment, one wire is provided on the cut copper foil, but a plurality of sets of wires may be provided on the cut copper foil. As the positional relationship of bonding between the frame 22 and the copper foil with wiring, various ones such as those shown in FIGS. 15A and 15B are possible. FIG. 15 is a plan view of the frame 22, wherein 26 is a frame opening, 27 is a mounting position of a copper foil with wiring, and 28 is an adhesive for fixing the foil. Next, the LSI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 13c). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. Here, a silver paste for die bonding or the like may be used instead of the bonding tape 4 ′. Moreover, although the normal wire bonding connection was used for mounting the semiconductor chip, other methods such as a Philip chip may be used. What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 13d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having a low copper solubility to expose the wiring portion. Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the wiring exposed portions and melted (FIG. 13e). After that, it was cut using a cutting machine, and unnecessary sections 101 of the frame 22 were removed and divided into individual semiconductor packages (FIG. 13f). The solder balls 7 are connected to external wiring. In this example, the semiconductor package can be efficiently manufactured by raising the plate.
[0064]
A fourteenth embodiment of the present invention will be described with reference to FIG.
[0065]
A polyimide film 29 with an adhesive having a thickness of 0.07 mm is punched out with a mold and a portion to be a connection terminal portion is opened. Next, after bonding a copper foil having a thickness of 0.035 mm, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photech HN340) is laminated, and a plurality of wiring patterns are exposed and developed. An etching resist was formed. Subsequently, the copper foil is etched, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 16a). Here, the connection terminal portion and the wiring 2 may be formed using a material obtained by directly coating polyimide on the copper foil (for example, Hitachi Chemical Co., Ltd., trade name 50001). The opening may also be formed by exposure / development using a method such as drilling, laser processing such as excimer laser, printing, etc., or using a material that is sensitive to polyimide. Other materials such as a sealing resin may be used instead of polyimide.
[0066]
As described above, after forming a plurality of sets of wiring patterns on a single polyimide film, the stainless steel frame 22 (thickness) prepared separately via the polyimide adhesive adhesive 28 is obtained by dividing the film with wiring into unit numbers. ; 0.135 mm) (Fig. 16b). Next, the LSI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 16c). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 16d). Subsequently, the solder ball 7 is disposed and melted in the opening portion to be the connection terminal portion provided first (FIG. 16e). The solder balls 7 are connected to external wiring. Finally, the packages connected by the frame were punched out with a mold and divided into individual packages (FIG. 16f).
[0067]
A fifteenth embodiment of the present invention will be described with reference to FIG.
[0068]
A predetermined resist image is formed on the metal foil of a two-layer flexible base material (FIG. 17a) in which the insulating base material 32 is directly formed on the metal foil 31, and a plurality of desired wiring patterns 33 are formed by a known etching method. Then, the resist image is peeled off (FIG. 17b). As the metal foil, in addition to a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorous plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is subsequently applied. In this case, after forming a polyimide layer on the copper thin layer, the copper thin layer is exposed by etching away the copper foil and the nickel-phosphorus layer. That is, in the present invention, the copper thin layer may be processed after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) is used as a part of the lead frame structure. Also good. On the other hand, a polyimide material is generally used as an insulating base material from the viewpoint of process heat resistance. In this case, if the thermal expansion coefficients of the polyimide and the copper foil are different, the warpage of the substrate becomes remarkable in the solder reflow process. Therefore, as the polyimide, a polyimide containing 70 mol% or more of a polyimide having a repeating unit of It is preferable to apply.
[0069]
[Chemical 1]
Figure 0003606275
Next, a recess 34 reaching the copper foil is provided at a position to be a connection portion with the external substrate in a later process (FIG. 17c). The method for processing the recess is not particularly limited, and wet etching or the like can be applied in addition to laser processing such as excimer laser, carbon dioxide laser, and YAG laser.
[0070]
Next, a frame base material 37 with an adhesive 36 obtained by punching a predetermined portion (opening portion 35) by punching or the like is adhered to the wiring pattern surface (FIG. 17d). In this case, the frame base material is not particularly limited, and a metal foil such as a polyimide film or a copper foil can be applied. Here, if the thickness of the polyimide layer of the two-layer flexible base material is 25 μm and the frame base material to be bonded is a polyimide film, the film thickness is 50 to 70 μm to ensure the rigidity of the entire frame. A degree is required. The region for forming the frame base material layer is not particularly limited, and the frame base material layer can be provided in a portion where the semiconductor chip is mounted. Specifically, when the chip mounting is a wire bonding method, the frame base material layer may be provided in all other regions as long as the wire bonding terminal portions 38 are exposed. Next, the semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 17e). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal bump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line through the metal bump. The pattern may be electrically connected. Next, it sets to the metal mold | die for transfer molding, and seals with the resin sealing material 41 (FIG. 17f). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Next, the connection part 42 with the external substrate is formed. As a method for forming the connection portion 42, a method of forming a bump having a thickness of a polyimide film or more in advance by electrolytic plating after the step of FIG. 17c or a method of forming a solder bump by solder printing after resin sealing is applied. Is possible. Finally, the package is cut from the frame to obtain the desired package (FIG. 17g).
[0071]
The fifteenth embodiment of FIG. 17 will be described more specifically.
[0072]
Example 1
A dry film resist (manufactured by Hitachi Chemical Co., Ltd.) on a copper foil surface of a two-layer flexible substrate (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having an electrolytic copper foil having a thickness of 12 μm on one side. Name: Photec HK815) was laminated, and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with a ferric chloride solution, a predetermined wiring pattern was obtained by peeling the resist pattern with a potassium hydroxide solution. Next, by using an excimer laser processing machine (manufactured by Sumitomo Heavy Industries, Ltd., device name: INDEX200), a predetermined number of recesses (diameter 300 μm) reaching the back surface of the wiring pattern from the insulating substrate side are formed at a predetermined position. did. Excimer laser processing conditions are an energy density of 250 mJ / cm 2, a reduction ratio of 3.0, an oscillation frequency of 200 Hz, and an irradiation pulse number of 300 pulses. Next, an adhesive sheet having a polyimide adhesive material (product name: AS 2250, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 μm on one side of a polyimide film (product name: UPILEX S, manufactured by Ube Industries, Ltd.) having a thickness of 50 μm is provided. The predetermined region including the region corresponding to the wire bond terminal portion in the subsequent process was removed by punching, and the polyimide film and the two-layer flexible substrate with a wiring pattern were heat-pressed through an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm 2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thickness is 3 μm and 0.3 μm, respectively. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). The mounting conditions are a press pressure of 5 kgf / cm 2, an adhesion temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. Thereafter, the die is processed into a lead frame shape, set in a transfer mold die, and sealed at 185 ° C. for 90 seconds using a semiconductor sealing epoxy resin (CL-7700, manufactured by Hitachi Chemical Co., Ltd.). did. Subsequently, a predetermined amount of solder was printed and applied to the recesses described above, and the solder was melted in an infrared reflow furnace to form external connection bumps. Finally, the package part was punched with a mold to obtain a desired package.
[0073]
A sixteenth embodiment of the present invention will be described with reference to FIG.
[0074]
A predetermined resist image is formed on the metal foil of a two-layer flexible substrate (FIG. 18a) in which an insulating substrate 32 is directly formed on the metal foil 31, and a desired plurality of sets of wiring patterns 3 are formed by a known etching method. Then, the resist image is peeled off (FIG. 18b). As the metal foil, in addition to a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorous plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is subsequently applied. In this case, after forming a polyimide layer on the copper thin layer, the copper thin layer is exposed by etching away the copper foil and the nickel-phosphorus layer. That is, in the present invention, the copper thin layer may be processed after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) is used as a part of the lead frame structure. Also good. On the other hand, a polyimide material is generally used as an insulating base material from the viewpoint of process heat resistance. In this case, if the thermal expansion coefficients of the polyimide and the copper foil are different, the warpage of the base material becomes remarkable in the solder reflow process. Therefore, as the polyimide, a polyimide containing 70 mol% or more of a polyimide having a repeating unit of (Chemical Formula 1) is used. It is preferable to apply.
[0075]
Next, a recess 34 reaching the copper foil is provided at a position to be a connection portion with the external substrate in a later process (FIG. 18c). The method for processing the recess is not particularly limited, and wet etching or the like can be applied in addition to laser processing such as excimer laser, carbon dioxide laser, and YAG laser.
[0076]
Next, a frame base material 37 with an adhesive 36 obtained by punching a predetermined portion (opening portion 5) as a second insulating base by punching or the like is bonded to the wiring pattern surface (FIG. 18d). Here, if the thickness of the polyimide layer of the two-layer flexible base material is 25 μm, the thickness of the polyimide film to be bonded needs to be about 50 to 70 μm in consideration of fixing to the frame in a later step. Note that the region to which the polyimide is bonded is not particularly limited, and an external connection terminal can be formed below the semiconductor chip like a CSP by providing the region where the semiconductor chip is mounted. Specifically, when the chip mounting is a wire bonding method, a polyimide film may be bonded to all other regions as long as the wire bonding terminal portion 38 is exposed. The insulating substrate thus obtained is separated into individual wiring patterns (FIG. 18e) and fixed to a separately prepared frame 43 such as SUS (FIG. 18f). Next, the semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 18g). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal bump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line through the metal bump. The pattern may be electrically connected. Next, it is set in a mold for transfer molding and sealed with a resin sealing material 41 (FIG. 18h). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Next, the connection part 12 with an external substrate is formed. As a method for forming the connecting portion 12, a method of forming a bump of a polyimide film thickness or more in advance by an electrolytic plating method after the step of FIG. 18c or a method of forming a solder bump by a solder printing method after resin sealing is applied. Is possible. Finally, the package is cut from the frame to obtain the desired package (FIG. 18i).
[0077]
The sixteenth embodiment of FIG. 18 will be described more specifically.
[0078]
Example 2
A dry film resist (manufactured by Hitachi Chemical Co., Ltd.) on a copper foil surface of a two-layer flexible substrate (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having an electrolytic copper foil having a thickness of 12 μm on one side. Name: Photec HK815) was laminated, and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with a ferric chloride solution, a predetermined wiring pattern was obtained by peeling the resist pattern with a potassium hydroxide solution. Next, by using an excimer laser processing machine (manufactured by Sumitomo Heavy Industries, Ltd., device name: INDEX200), a predetermined number of recesses (diameter 300 μm) reaching the back surface of the wiring pattern from the insulating substrate side are formed at a predetermined position. did. Excimer laser processing conditions are an energy density of 250 mJ / cm 2, a reduction ratio of 3.0, an oscillation frequency of 200 Hz, and an irradiation pulse number of 300 pulses. Next, an adhesive sheet having a polyimide adhesive material (product name: AS 2250, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 μm on one side of a polyimide film (product name: UPILEX S, manufactured by Ube Industries, Ltd.) having a thickness of 50 μm is provided. The predetermined region including the region corresponding to the wire bond terminal portion in the subsequent process was removed by punching, and the polyimide film and the two-layer flexible substrate with a wiring pattern were heat-pressed through an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm 2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thickness is 3 μm and 0.3 μm, respectively. The substrate thus obtained was separated into individual wiring patterns and fixed to a separately prepared SUS frame. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). The mounting conditions are a press pressure of 5 kgf / cm 2, an adhesion temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. Thereafter, the die is processed into a lead frame shape, set in a transfer mold die, and sealed at 185 ° C. for 90 seconds using a semiconductor sealing epoxy resin (CL-7700, manufactured by Hitachi Chemical Co., Ltd.). did. Subsequently, a predetermined amount of solder was printed and applied to the recesses described above, and the solder was melted in an infrared reflow furnace to form external connection bumps. Finally, the package part was punched with a mold to obtain a desired package.
[0079]
The seventeenth embodiment of the present invention will be described with reference to FIGS.
[0080]
A plurality of sets of predetermined wiring patterns 52 are formed on the support 51 (FIG. 19a). As the support, in addition to a metal foil such as an electrolytic copper foil, an insulating substrate such as a polyimide film can be applied. There are two methods for applying an insulating substrate. The first method is a method in which a non-penetrating recess reaching the wiring pattern is formed in a predetermined portion of the insulating substrate, and an external connection terminal is formed in an exposed portion of the wiring pattern. The non-penetrating recess can be formed by applying an excimer laser, a carbon dioxide gas laser, or the like. The second method is a method in which a drilled material is formed in advance on an insulating base material with an adhesive, and after being laminated with an electrolytic copper foil or the like, the copper foil is etched.
[0081]
On the other hand, when applying a metal foil, a resist pattern is first formed using a photoresist or the like, and then a wiring pattern is formed by electroplating using the metal foil as a cathode. In this case, a normal electrolytic copper foil or a thin layer of metal (nickel, gold, solder, etc.) having different chemical etching conditions from the copper foil can be applied. Also, copper is preferable as the wiring pattern. However, when the electrolytic copper foil is applied as a support as described above, a metal itself having a different etching condition from the copper foil can be applied as the wiring pattern, or copper foil etching can be performed. It is necessary to form a pattern thin layer to be a barrier layer at the time before pattern copper plating.
[0082]
Next, after mounting the semiconductor element 54 with the die bond material 53, the semiconductor element terminal and the wiring pattern are electrically connected (FIG. 19b), and a plurality of sets of semiconductor elements and the wiring pattern are collectively collected by a transfer molding method. It seals with the sealing material 56 (FIG. 19c). The resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. The present invention is not limited to the case where the semiconductor element mounting method is the face-up method, and can be applied to, for example, the face-down method. Specifically, after forming a bump for face down bonding at a predetermined position on the wiring pattern 52 by plating or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.
[0083]
Furthermore, it is effective to make it easy to divide the package in a later process as shown in FIGS. Of these, FIG. 20 shows a case in which a groove 59 is formed at a boundary portion between a plurality of package portions. The width and depth of the grooves can be controlled by the processing dimensions of the transfer mold. In FIG. 21, transfer molding is performed using a lattice-shaped intermediate plate 60 in which portions corresponding to the respective package portions are cut out in advance. Next, when the support is a metal foil, the support is removed by a chemical etching method or the like, and external connection terminals 57 are formed at predetermined positions (FIG. 19d). When an insulating base material is applied as the support, only a predetermined portion of the insulating base material may be selectively removed with a laser or the like as described above. Finally, the collectively sealed substrate is cut and separated into unit portions 58. A solder resist layer may be formed on the exposed surface of the wiring pattern for the purpose of protecting the wiring pattern.
[0084]
The seventeenth embodiment will be specifically described.
[0085]
Example 3
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil having a thickness of 35 μm and an outer shape of 250 mm square, and a desired resist pattern (minimum) by exposure and development. Line / space = 50 μm / 50 μm). Next, by electroplating, 300 identical wiring patterns composed of nickel having a thickness of 0.2 μm, copper of 30 μm, nickel of 5 μm and soft gold of 1 μm (4 blocks / 250 mm square, 75 pieces / block) ) Formed. Next, the resist pattern is peeled off using a potassium hydroxide solution having a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and then die-bonding material for mounting semiconductor elements (Hitachi Chemical Industries ( The semiconductor element was bonded using a product name, HM-1). The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressure bonding time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal portion (second connection portion) are electrically connected by wire bonding, and then set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry ( Co., Ltd., trade name: CL-7700), 75 wiring patterns (corresponding to 1 block) were collectively sealed at 185 ° C. for 90 seconds to transfer each wiring pattern into the sealing material. . Next, a desired portion of the electrolytic copper foil was removed by etching using an alkali etchant (Meltex Co., Ltd., trade name: A process). The temperature of the etching solution is 40 ° C., and the spray pressure is 1.2 kgf / cm 2. Next, a solder pattern was formed on the external connection terminal portion by a printing method, and the solder was melted by an infrared reflow furnace to form an external connection bump. Finally, the desired package was obtained by separating into each package part with a diamond cutter.
[0086]
Example 4
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil having a thickness of 35 μm and an outer shape of 250 mm square, and a desired resist pattern (minimum) by exposure and development. Line / space = 50 μm / 50 μm). Next, by electroplating, 300 identical wiring patterns composed of nickel having a thickness of 0.2 μm, copper of 30 μm, nickel of 5 μm and soft gold of 1 μm (4 blocks / 250 mm square, 75 pieces / block) ) Formed. Next, the resist pattern is peeled off using a potassium hydroxide solution having a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and then die-bonding material for mounting semiconductor elements (Hitachi Chemical Industries ( The semiconductor element was bonded using a product name, HM-1). The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressure bonding time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal part (second connection part) were electrically connected by wire bonding. Next, a lattice-shaped stainless steel plate in which a portion corresponding to the package region (15 mm square) is hollowed is set as an intermediate plate in a transfer mold, and an epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) was used to collectively seal 75 wiring patterns (corresponding to 1 block) at 185 ° C. for 90 seconds, thereby transferring each wiring pattern into the sealing material. The lattice portion of the intermediate plate has a 12 ° taper so that each package can be easily separated from the intermediate plate. Next, a desired portion of the electrolytic copper foil was removed by etching using an alkali etchant (Meltex Co., Ltd., trade name: A process). Each package part is held by a grid-like intermediate plate. The temperature of the etching solution is 40 ° C., and the spray pressure is 1.2 kgf / cm 2. Finally, a solder pattern was formed on the external connection terminal portion by a printing method, solder was melted by an infrared reflow furnace to form external connection bumps, and the desired package was obtained by separating from the intermediate plate into each package portion. .
[0087]
The eighteenth embodiment of the present invention will be described with reference to FIG.
[0088]
A plurality of sets of predetermined resist patterns 62 (FIG. 22b) are formed on the conductive temporary support 61 (FIG. 22a). Next, a wiring pattern 63 is formed on the exposed portion of the temporary support by electroplating. In this case, the temporary support is not particularly limited. For example, a thin layer of a metal (nickel, gold, solder, etc.) having different chemical etching conditions from a copper foil is provided on a normal electrolytic copper foil or electrolytic copper foil. Can be applied. Moreover, although copper is preferable as the wiring pattern, when the electrolytic copper foil is applied as a temporary support as described above, a metal itself having a different etching condition from the copper foil may be applied as the wiring pattern, or the copper foil. It is necessary to form a pattern thin layer to be a barrier layer during etching before pattern copper plating. The thickness of the temporary support is not particularly limited as long as there is no problem in terms of handling properties in a later process and dimensional stability when mounting a semiconductor element. Next, after plating with a gold wire bond (usually nickel / gold) 64 using the temporary support as a cathode, the resist pattern is removed (FIG. 22c). The present invention is not limited to the case where the semiconductor element mounting method is the face-up method, and can be applied to, for example, the face-down method. Specifically, after forming a bump for face down bonding at a predetermined position on the wiring pattern 63 by plating or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.
[0089]
Next, the semiconductor element 65 is bonded with a die bond material 66 or the like, and the external connection terminal of the semiconductor element and the wiring pattern are electrically connected (FIG. 22d). Next, it is set in a transfer mold and sealed with a resin sealing material 68 (FIG. 22e). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied.
[0090]
Next, a predetermined metal pattern 69 is formed at a location corresponding to the external connection terminal (FIG. 22f). In this case, the metal to be applied may be any metal that is not etched under the condition of removing the conductive temporary support by etching. For example, solder, gold, nickel / gold, or the like is applicable. Moreover, as a formation method of a metal pattern, a well-known electroplating method, a solder printing method, etc. are applicable. Furthermore, when the metal pattern 69 is formed by a solder pattern, the solder bump 70 can be formed by reflowing. In this case, the height of the solder bump 70 after reflow can be controlled by adjusting the thickness of the pattern 69. Next, a predetermined portion of the temporary support is removed using the metal pattern as an etching resist to expose the wiring pattern.
[0091]
Finally, each package 71 is divided by applying die processing or dicing processing (FIG. 22g). If the exposed wiring pattern is not protected by a corrosion-resistant metal such as nickel, the region other than the external connection terminal portion may be covered with a known solder resist or the like. In addition, when solder is applied as a metal pattern, the reflow process is not particularly limited, and may be performed before or after being divided into packages, or may be performed when each package is mounted on an external wiring board. good.
[0092]
The eighteenth embodiment will be specifically described.
[0093]
Example 5
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil having a thickness of 70 μm, and a desired resist pattern (minimum line / space =) by exposure and development. 50 μm / 50 μm). Next, a wiring pattern composed of nickel having a thickness of 0.2 μm, copper of 30 μm, nickel of 5 μm, and soft gold of 1 μm was formed by electroplating. Next, the resist pattern is peeled off using a potassium hydroxide solution having a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, and then bonded to a semiconductor device die bond material (trade name, manufactured by Hitachi Chemical Co., Ltd.) : HM-1) was used to bond the semiconductor elements. The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressure bonding time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal portion (second connection portion) are electrically connected by wire bonding, and then set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry ( The wiring pattern was transcribe | transferred in the sealing material by sealing at 185 degreeC and 90 second using the product made from Corporation | KK, a brand name: CL-7700. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil, and after forming a desired resist pattern by exposure and development, the thickness is obtained by electroplating. A 40 μm solder pad (diameter 0.3 mmφ, arrangement pitch 1.0 mm) was formed. Next, after peeling off the dry film resist, a desired portion of the electrolytic copper foil was removed by etching using an alkaline etchant (trade name: A process manufactured by Meltex Co., Ltd.). The temperature of the etching solution is 40 ° C. and the spray pressure is 1.2 kgf / cm 2. Finally, solder was melted in an infrared reflow furnace to form external connection bumps.
[0094]
The nineteenth embodiment of the present invention will be described with reference to FIGS.
[0095]
The configuration of the semiconductor mounting frame will be described with reference to FIG. Reference numeral 89 denotes a semiconductor mounting substrate, which is composed of an insulating base material and wiring. A plurality of substrates are connected via the substrate portion and the connecting portion 90. A reference position pin hole 91 is formed in the connecting portion 90. Instead of the pin hole 91, a recognition mark or the like used for image recognition may be used. In the post-process, the position is determined based on these reference positions. In particular, when a semiconductor is molded with a resin, alignment is performed by placing a pin in the cavity into the pin hole 91.
[0096]
Further description will be made with reference to FIGS. A nickel layer (not shown in FIGS. 24 and 25) having a thickness of 0.001 mm was formed by electrolytic plating on one surface of an electrolytic copper foil 81 having a thickness of about 0.070 mm, which was a conductive temporary substrate. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. The exposure amount at this time is 70 mJ / cm 2. Further, electrolytic copper plating is performed in a known copper sulfate bath, the resist is peeled off, and a plurality of sets of wirings 82 are formed (FIGS. 24a and 25a). Here, as shown in FIG. 25a, it is also conceivable to form plated copper 82 'in the connecting portion, which can further increase the rigidity of the completed frame. The configurations shown in FIGS. 24a and 25a can also be obtained by preparing a base material composed of three layers of copper / nickel thin layer / copper in advance and forming a wiring on one copper foil by a normal etching process. Further, the copper foil 81 / nickel thin layer (not shown) / copper wiring 82 (and 82 ') obtained here is composed of copper foil / nickel wiring, nickel foil / copper wiring, etc., which has no nickel thin layer. A layer structure may be used. That is, the selection of the metal type is not limited to the type of this embodiment, but when the part of the temporary substrate is removed by etching (FIGS. 24C and 25C) in the subsequent process, the wiring is selectively selected. Being able to remain is a suitable selection criterion. Further, the conductive temporary substrate is preferably a thick material because it becomes a constituent material of the connecting portion of the frame. However, since there is a step of removing a part of the conductive temporary substrate later, it is necessary to select an appropriate thickness. Although the thickness of the conductive temporary substrate depends on the material, for example, when using copper foil, about 0.03 to 0.3 mm is preferable. Next, a polyimide adhesive 83 was bonded to the wiring surface of the copper foil 81 on which a plurality of sets of wirings 82 were formed. Here, the polyimide adhesive 83 is not limited to this material. For example, an epoxy adhesive film, a film obtained by applying an adhesive to a polyimide film, or the like can be used. Next, an external connection terminal hole 84 was formed using an excimer laser (FIGS. 24b and 25b). In order to simplify the process in the subsequent process, it is preferable to provide the connection terminal before mounting the semiconductor. As another method for forming the holes 84, a method may be used in which the holes 84 for external connection terminals are formed in advance in a film by drilling or punching, and the film is adhered. Further, the hole 84 may be filled with a metal such as solder (corresponding to 88 in FIGS. 24f and 25f) used as a connection terminal. However, in the subsequent semiconductor mounting process and resin sealing process, The metal protrusion may become an obstacle, and it is preferable to form in a later step. The external connection terminal holes (or terminals) of the semiconductor element mounting substrate are preferably arranged in an array on the opposite side of the semiconductor element mounting.
[0097]
Next, a part of the electrolytic copper foil, which is a temporary substrate where the wiring pattern is formed, was removed by etching. As the etching solution, in the case of the configuration of this embodiment, it is preferable to select an etching solution and etching conditions in which the dissolution rate of copper is significantly higher than that of nickel. In this example, an alkali etchant (manufactured by Meltex Co., Ltd., trade name: A process) was used as an etching solution, and the etching conditions were, for example, a liquid temperature of 40 ° C. and a spray pressure of 1.2 kgf / cm 2. The types and conditions of the liquids shown here are only examples. This step exposes the nickel thin layer of the substrate portion. When etching only this thin nickel layer, it is preferable to select an etching solution and etching conditions in which the dissolution rate of nickel is significantly higher than that of copper. In this example, the etching was selectively removed with a nickel etchant (Meltex Co., Ltd., trade name: Melstrip N950). The temperature of the etching solution was 40 ° C., and the spray pressure was 1.2 kgf / cm 2. The types and conditions of the liquid shown here are only examples. Through these steps, the temporary substrate of the connecting portion is left, and a rigid semiconductor mounting frame can be obtained (FIGS. 24c and 25c). In this embodiment, the copper wiring terminal portion of this frame is subjected to electroless nickel-gold plating (not shown in the figure). This is necessary for wire bonding of the chip in a later process, and such surface treatment may be performed as necessary.
[0098]
Further, a semiconductor chip 85 is mounted. For bonding the semiconductor chip, a semiconductor die bonding tape 86 (for example, trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.) was used. Here, when there is no wiring under the chip, it may be bonded using a silver paste for die bonding. Next, the semiconductor terminal portion and the wiring are connected by a wire bond 100 (FIGS. 24d and 25d). The connection with the semiconductor terminal may be another method, for example, a Philip chip connection by face-down or an adhesion with an anisotropic conductive back agent. What was formed in this way was loaded into a transfer mold die, and sealed 87 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 24e, FIG. 25e). Thereafter, solder balls 88 are disposed in the connection holes provided in the connection terminal portions of the wiring 82 and melted (FIGS. 24f and 25f). The solder balls 88 serve as so-called external connection terminals. A plurality of semiconductor devices connected by the connecting portion 102 are punched out with a mold to obtain individual semiconductor devices (FIGS. 24g and 25g).
[0099]
In this embodiment, the semiconductor mounting frame and the semiconductor device manufacturing method can provide a frame having sufficient rigidity in the manufacture of semiconductor devices such as BGA and CSP using a film substrate such as polyimide tape. This makes it possible to manufacture a semiconductor device with high accuracy and efficiency.
[0100]
According to the present invention, it is possible to stably and stably manufacture a semiconductor package that can cope with high integration of semiconductor chips.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 2 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 5 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 6 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 8 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 9 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 11 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 12 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 13 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 14 is a plan view for explaining an example of a method for producing a semiconductor package of the present invention.
FIG. 15 is a plan view for explaining an example of a method for producing a semiconductor package of the present invention.
FIG. 16 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 17 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 18 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 19 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 20 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 21 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 22 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 23 is a plan view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 24 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.
FIG. 25 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package of the present invention.

Claims (6)

（Ａ）半導体素子搭載領域と、該半導体素子搭載領域の外側の樹脂封止用半導体パッケージ領域とを有する絶縁性支持体の片面に、複数組の配線を形成する工程、
（Ｂ）上記複数組の配線が形成された上記絶縁性支持体に複数個の半導体素子を搭載し、半導体素子端子と配線に設けられたワイヤボンディング端子とをボンディングワイヤにより導通する工程、
（Ｃ）上記導通された複数組の半導体素子と配線とを封止樹脂により一括して樹脂封止する工程、
（Ｅ）上記絶縁性支持体の所望する部分を除去して配線を露出させ、露出した配線に電気的に接続した外部接続端子を形成する工程、及び、
（Ｆ）上記封止樹脂と上記絶縁性支持体とを切断し、上記絶縁性支持体と上記半導体素子と上記配線とを含む個々の半導体パッケージに分離する工程
を含み、
上記ワイヤボンディング端子は上記樹脂封止用半導体パッケージ領域に設けられ、
上記外部接続端子は上記半導体素子搭載領域に設けられることを特徴とする半導体パッケージの製造方法。(A) forming a plurality of sets of wirings on one surface of an insulating support having a semiconductor element mounting region and a resin sealing semiconductor package region outside the semiconductor element mounting region;
(B) a step of mounting a plurality of semiconductor elements on the insulating support on which the plurality of sets of wirings are formed, and electrically connecting the semiconductor element terminals and the wire bonding terminals provided on the wirings by bonding wires;
(C) a step of resin-sealing the plurality of conductive semiconductor elements and wirings collectively with a sealing resin;
(E) removing a desired portion of the insulating support to expose the wiring, and forming an external connection terminal electrically connected to the exposed wiring; and
(F) cutting the sealing resin and the insulating support and separating them into individual semiconductor packages including the insulating support, the semiconductor element, and the wiring;
The wire bonding terminal is provided in the semiconductor package region for resin sealing,
The method of manufacturing a semiconductor package, wherein the external connection terminal is provided in the semiconductor element mounting region. （Ｅ）半導体素子搭載領域と、該半導体素子搭載領域の外側の樹脂封止用半導体パッケージ領域とを有する絶縁性支持体の所望する部分を除去する工程、
（Ａ）上記絶縁性支持体の片面に複数組の配線を形成する工程、
（Ｂ）上記複数組の配線が形成された上記絶縁性支持体に複数個の半導体素子を搭載し、半導体素子端子と配線に設けられたワイヤボンディング端子とをボンディングワイヤにより導通する工程、
（Ｃ）上記導通された複数組の半導体素子と配線とを封止樹脂により一括して樹脂封止する工程、及び、
（Ｆ）上記封止樹脂と上記絶縁性支持体とを切断し、上記絶縁性支持体と上記半導体素子と上記配線とを含む個々の半導体パッケージに分離する工程
を含み、
上記ワイヤボンディング端子は上記樹脂封止用半導体パッケージ領域に設けられ、
上記配線の外部接続端子部は上記半導体素子搭載領域に設けられることを特徴とする半導体パッケージの製造方法。(E) a step of removing a desired portion of an insulating support having a semiconductor element mounting region and a resin sealing semiconductor package region outside the semiconductor element mounting region;
(A) forming a plurality of sets of wiring on one surface of the insulating support,
(B) a step of mounting a plurality of semiconductor elements on the insulating support on which the plurality of sets of wirings are formed, and electrically connecting the semiconductor element terminals and the wire bonding terminals provided on the wirings by bonding wires;
(C) a step of resin-sealing the plurality of conductive semiconductor elements and wirings collectively with a sealing resin; and
(F) cutting the sealing resin and the insulating support and separating them into individual semiconductor packages including the insulating support, the semiconductor element, and the wiring;
The wire bonding terminal is provided in the semiconductor package region for resin sealing,
A method of manufacturing a semiconductor package, wherein the external connection terminal portion of the wiring is provided in the semiconductor element mounting region. （Ａ）半導体素子搭載領域と、該半導体素子搭載領域の外側の樹脂封止用半導体パッケージ領域とを有する絶縁性支持体の表面に、複数組の配線を形成する工程、
（Ｂ）上記複数組の配線が形成された上記絶縁性支持体に複数個の半導体素子を搭載し、半導体素子端子と配線に設けられたワイヤボンディング端子とをボンディングワイヤにより導通する工程、
（Ｃ）上記導通された複数組の半導体素子と配線とを封止樹脂により一括して樹脂封止する工程、
（Ｅ）上記配線の外部接続端子部に電気的に接続した外部接続端子を形成する工程、及び、
（Ｆ）上記封止樹脂と上記絶縁性支持体とを切断し、上記絶縁性支持体と上記半導体素子と上記配線とを含む個々の半導体パッケージに分離する工程
を含み、
上記ワイヤボンディング端子は上記樹脂封止用半導体パッケージ領域に設けられ、
上記外部接続端子は上記半導体素子搭載領域に設けられることを特徴とする半導体パッケージの製造方法。(A) and the semiconductor element mounting area, on the surface of an insulating support having an outer resin sealing semiconductor package region of said semiconductor element mounting area, forming a plurality of sets of wiring,
(B) a step of mounting a plurality of semiconductor elements on the insulating support on which the plurality of sets of wirings are formed, and electrically connecting the semiconductor element terminals and the wire bonding terminals provided on the wirings by bonding wires;
(C) a step of resin-sealing the plurality of conductive semiconductor elements and wirings collectively with a sealing resin;
(E) forming an external connection terminal electrically connected to the external connection terminal portion of the wiring ; and
(F) cutting the sealing resin and the insulating support and separating them into individual semiconductor packages including the insulating support, the semiconductor element, and the wiring;
The wire bonding terminal is provided in the semiconductor package region for resin sealing,
The method of manufacturing a semiconductor package, wherein the external connection terminal is provided in the semiconductor element mounting region. 上記半導体パッケージの分離をダイヤモンドカッターにより行うことを特徴とする請求項１〜３のいずれかに記載の半導体パッケージの製造方法。4. The method of manufacturing a semiconductor package according to claim 1, wherein the semiconductor package is separated by a diamond cutter. 半導体素子を樹脂封止した後、封止樹脂硬化物を加熱処理する請求項１〜４のいずれかに記載の半導体パッケージの製造方法。The manufacturing method of the semiconductor package in any one of Claims 1-4 which heat-process the sealing resin hardened | cured material after resin-sealing a semiconductor element. 請求項１〜５のいずれかに記載の方法で製造された半導体パッケージ。A semiconductor package manufactured by the method according to claim 1.
JP2002313069A 1994-03-18 2002-10-28 Semiconductor package and manufacturing method thereof Expired - Fee Related JP3606275B2 (en)

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