JP3586972B2 - Semiconductor integrated circuit and test method therefor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog or mixed analog / digital semiconductor integrated circuit and a test method therefor.
[0002]
[Prior art]
In recent years, as electronic devices have become more sophisticated and smaller, the size of mounting packages and the area of printed circuit boards have been reduced. Therefore, the pin pitch width of semiconductor devices such as ICs and LSIs mounted on a printed circuit board has become narrower, and the distance between semiconductor devices mounted on the printed circuit board has become extremely small.
[0003]
For the above reasons, it is very difficult to fix an inspection electrode (hereinafter, referred to as a probe) to a pin of a semiconductor device, and it is necessary to fix a large number of probes to the pins of the semiconductor device, such as in-circuit inspection or function inspection. It is becoming very difficult to inspect the mounting board.
[0004]
In order to solve the above-mentioned problem, a boundary scan test technology capable of performing in-circuit inspection with a smaller number of inspection probes has been devised, and this technology was defined in a standard (IEEE Standard 1149.1-1990) in 1990. I have.
[0005]
However, a test technique (hereinafter, referred to as a digital boundary scan test technique) defined by the above standard (IEEE Standard 1149.1-1990) is effective for digital circuits, but tests analog circuits. I couldn't. Therefore, in many cases, a semiconductor device on which analog circuits and digital circuits are mixed is mounted on a printed circuit board of an actual electronic device, and the digital boundary scan test technology stipulated by the above standard is not always required. Did not cover all the tests on the printed circuit board.
[0006]
Therefore, in order to inspect an analog circuit or a mixed digital / analog circuit, a boundary scan test technique (hereinafter, referred to as an analog boundary scan test technique) has been proposed (ITC 1993 Paper 15.2). Structure and Metrology for an Analog Testability Bus, Kenneth P. Parker et al., And JP-A-6-347517).
[0007]
With this analog boundary scan test technology, even in the case of digital and analog mixed semiconductor devices, a large number of test probes can be used simultaneously for the interconnection of devices and the inspection of analog discrete components existing between devices. You do not have to use it.
[0008]
Next, a conventional analog boundary scan test will be briefly described with reference to FIGS.
[0009]
FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit in which boundary scan cell units 100 and 101 are configured to perform a boundary scan test.
[0010]
As shown in FIG. 4, reference numeral 50 denotes an integrated circuit device having a main analog circuit 120 therein. 59 and 157 are device terminals for inputting or outputting analog signals of the integrated circuit device 50. The device terminal 157 is connected to the device terminal 59 via the switch 121, the main analog circuit 120, and the switch 82 in this order.
[0011]
A first analog bus 155 is connected to the device terminal 157 via the switch 112 and to the device terminal 59 via the switch 152. A second analog bus 156 is connected to the device terminal 157 via the switch 113 and to the device terminal 59 via the switch 153. The device terminal 157 is connected to VDD (power supply) via the switch 110, and is connected (grounded) to VSS via the switch 111. The device terminal 59 is connected to VDD (power supply) via a switch 150, and is connected (grounded) to VSS via a switch 151.
[0012]
A boundary scan cell unit 100 is connected to a wiring connecting the device terminal 157 and the switch 121, and includes a digital converter, a boundary scan cell, and a logic circuit (not shown). The output from the boundary scan cell unit 100 controls on / off of the switches 110 to 113. Reference numeral 101 denotes a boundary scan cell unit, which is connected to a wiring connecting the device terminal 59 and the switch 82. Similarly to the boundary scan cell unit 100, a digital converter, a boundary scan cell, and a logic circuit ( (Not shown), and the output from the boundary scan cell unit 101 controls on / off of the switches 150 to 153.
[0013]
Next, the configuration of the boundary scan cell unit 100 will be described in more detail with reference to FIG. 5 showing the configuration of the boundary scan cell unit.
[0014]
Note that the same components as those of the semiconductor integrated circuit shown in FIG. 4 are denoted by the same reference numerals and description thereof is omitted.
[0015]
As shown in FIG. 5, reference numerals 106, 107, 108, and 109 denote boundary scan cells, each of which is a flip-flop for capturing data (hereinafter, referred to as a capture flip-flop, and FIG. 5). C) and a data update flip-flop (hereinafter, referred to as an update flip-flop, and denoted by U in FIG. 5). The boundary scan cells 106, 107, 108, and 109 have a scan chain structure in which scan inputs and scan outputs of the respective capture flip-flops are connected in a chain. Further, each capture flip-flop is connected to a corresponding update flip-flop by a scan chain, and finally, a serial test data input terminal TDI of the integrated circuit device 50 (not shown in FIG. 5). The flip flops of all the boundary scan cells 106 to 109 are connected by a scan chain to the test data output terminal TDO. Reference numeral 105 denotes a digital converter, which compares the signal voltage level of the analog device terminal 157 with a reference voltage (threshold voltage) VT to convert the signal voltage to an “H” level or “L” level digital signal, and converts the conversion result to a boundary signal. The potential of the node connected to the analog flip-flop terminal 157 can be supplied to the capture flip-flop of the scan cell 106 and the potential of the node connected to the analog device terminal 157 can be output as a digital signal from the TDO to the outside of the integrated circuit device 50.
[0016]
Reference numerals 74 and 75 denote logic gates for controlling the opening and closing of the switches 110 and 111 based on the output of the update flip-flop of the boundary scan cells 106 and 107. Also, the outputs of the update flip-flops of the boundary scan cells 108 and 109 control the switches 112 and 113, respectively.
[0017]
The configuration of the boundary scan cells 106 to 109 is defined by IEEE1149.1.
[0018]
Next, the operation of the integrated circuit device 50 will be described with reference to FIGS.
[0019]
First, a normal operation in which the main analog circuit 120 performs an original operation will be described.
[0020]
During normal operation, only the switches 82 and 121 are closed, and the other switches 110 to 113 and 150 to 153 are in the open state. At this time, when an analog signal is input from the device terminal 157, the analog signal is input to the main analog circuit 120 via the switch 121, and an output signal from the main analog circuit 120 is output from the device terminal 59 through the switch 82.
[0021]
Next, an operation at the time of performing a boundary scan test will be described.
[0022]
First, control signals for controlling on / off of the switches 110 to 113 are serially input from the TDI to the boundary scan cells 106 to 109, and the respective capture flip-flops of the boundary scan cells 106 to 109 are input. Data is sequentially loaded into the flop. Thereafter, switch control data is delivered to the update flip-flop, and the switch is kept in the same state until the data of the update flip-flop is updated. By this series of operations, necessary switches among the switches 110 to 113 can be turned on.
[0023]
Subsequently, the potential of the node connected to the analog device terminal 157 is converted into a digital signal by the digital converter 105, and the result is output from the capture flip-flop of the boundary scan cell 106 to the outside of the integrated circuit device via the TDO. You can do it.
[0024]
As is clear from the above description, by using the analog boundary scan test technique, a device which is converted into a digital signal from TDO, which is a dedicated test terminal of an integrated circuit device, without fixing a probe to the device terminal 157. The state of the terminal 157 can be output, and an analog boundary scan test can be executed.
[0025]
Note that the operation of the boundary scan cell unit 101 is the same as that of the boundary scan cell unit 100, and a description thereof will be omitted. However, while the boundary scan cell unit 100 can convert the voltage of the node of the device terminal 157 into a digital signal and output the digital signal from the TDO, the boundary scan cell unit 101 converts the voltage of the node of the device terminal 59 into a digital signal. , TDO.
[0026]
Next, a configuration in which two integrated circuit devices are connected will be described with reference to FIG.
[0027]
FIG. 6 shows an example in which an integrated circuit device 40 and an integrated circuit device 60 similar to the integrated circuit device described with reference to FIGS. 4 and 5 are connected on a printed circuit board via analog discrete components.
[0028]
First, a first example of a conventional semiconductor integrated circuit to which two integrated circuit devices are connected will be described with reference to FIG.
[0029]
As shown in FIG. 6, the integrated circuit devices 40 and 60 are connected via an analog discrete component 18, and an example of the analog discrete component 18 is a resistor.
[0030]
The integrated circuit devices 40 and 60 are the same as the integrated circuit device 50 described with reference to FIGS. 4 and 5, and the same components are denoted by the same reference numerals and description thereof will be omitted.
[0031]
Although not shown in FIG. 4, as shown in FIG. 6, surge protection diodes 116a and 117a are provided on the device terminal 157a of the integrated circuit device 40 to provide surge protection. Specifically, the surge protection diode 116a is connected between the device terminal 157a and the power supply terminal VDD, and the surge protection diode 117a is connected between the device terminal 157a and the ground terminal VSS. The main analog circuit 120a, the boundary scan cells 106a to 109a, and the digital converter 105a are connected to the VDD terminal and the VSS terminal and are supplied with power.
[0032]
Surge protection diodes 123 and 124 are provided at the serial test data input terminal TDI of the integrated circuit device 60 to provide surge protection.
[0033]
It should be noted that, although device terminals other than the device terminals 157a and 157b and the serial test data input terminal TDI of the integrated circuit device 60 are generally provided with surge protection as a set of two surge protection diodes, In FIG. 6, the disclosure of the surge protection diodes of the other device terminals is omitted.
[0034]
The difference between the integrated circuit device 40 and the integrated circuit device 60 is that while 5 V power is supplied from the power supply terminal VDD of the integrated circuit device 40, 3 V power is supplied from the power supply terminal VDD of the integrated circuit device 60. That is the point.
[0035]
Next, the operation of the semiconductor integrated circuit configured as described above will be described.
[0036]
During normal operation, as in the case of the integrated circuit device 50 described above with reference to FIG. 4, only the switch 121a is on, and the other switches 110a to 113a are off.
[0037]
The switch state of the integrated circuit device will be described only for the integrated circuit device 40, and the integrated circuit device 60 will not be described because it is the same as the switch state of the integrated circuit device 40.
[0038]
On the other hand, when testing the interconnection of the two integrated circuit devices 40 and 60, the standard boundary scan test method of IEEE1149.1 is followed.
[0039]
More specifically, first, serial test data for switch control is input from the TDI of the integrated circuit device 40, and capture of the boundary scan cells 109a, 108a, 107a, 106a, 109b, 108b, 107b, and 106b is performed. The test data sequentially applied to the flip-flops and subsequently input to the capture flip-flops are sent to the corresponding update flip-flops, and only necessary switches are turned on (here, assuming that only the switch 110a is turned on). It will be described below.). Then, the voltage of the power supply potential VDD of the integrated circuit device 40 is input to the integrated circuit device 60 via the switch 110a, the device terminal 157a, the discrete component 18, and the device terminal 157b. Then, the voltage of the device terminal 157b is compared with the reference voltage VT fixed to the device by the digital converter 105b, and the converted digital data is taken into the update flip-flop of the boundary scan cell 106b. The data is finally output as the test result data from the TDO of the integrated circuit device 60 by the data shift operation of the boundary scan cell. Then, by using a digital automatic inspection device (digital tester) or the like to compare and determine (GO / NOGO determination) the expected value data prepared in advance and the test data output from the TDO, an interconnection test can be performed.
[0040]
[Problems to be solved by the invention]
However, in the conventional semiconductor integrated circuit described with reference to FIG. 6, since the power supply potential VDD differs between the integrated circuit device 40 and the integrated circuit device 60 between 5 V and 3 V, the following problem occurs. I do. For example, when only the switch 110a is turned on and a mutual test is performed, as shown by a dotted line in FIG. 6, when the switch 110a is closed and the power supply VDD (5V) of the integrated circuit device 40 is applied to the device terminal 157a, the analog discrete component 18 A voltage of 5 V is applied to the power supply VDD (3 V) of the integrated circuit device 60 via the device terminal 157b and the surge protection diode 116b. However, since the integrated circuit device 60 operates with the 3V power supply, an abnormal current flows from the integrated circuit device 40 to the integrated circuit device 60.
[0041]
Further, the following problem also occurs when transmitting the boundary scan test signal from the TDO of the integrated circuit device 40 to the TDI of the integrated circuit device 60. Since the “H” level of the digital signal output from the TDO of the integrated circuit device 40 is based on the supply from the power supply VDD (5 V), an “H” level signal is output from the TDO of the integrated circuit device 40. Similarly, as described above, the power supply VDD (5 V) of the integrated circuit device 40 is applied to the power supply VDD (3 V) of the integrated circuit device 60 via the TDI terminal of the integrated circuit device 60 and the surge protection diode 123, and an abnormal current flows. become.
[0042]
As another example, as shown in FIG. 7, there is a problem that a malfunction occurs when a configuration in which a voltage drop occurs on a wiring connecting an integrated circuit device occurs.
[0043]
In the configuration of the conventional semiconductor integrated circuit of the second example shown in FIG. 7, the discrete component 28 is arranged between the device terminal 157a and the device terminal 157b, one end is grounded, and the other end is grounded. Discrete components 28 and device terminals 157b And a discrete component 29 connected to the wiring connecting the Other configurations are the same as those of the semiconductor integrated circuit shown in FIG. In the semiconductor integrated circuit shown in FIG. 7, when a signal is output from the device terminal 157a to the device terminal 157b, the output signal is divided by the discrete components 28 and 29, so that the signal output from the device terminal 157a is directly used as the device terminal. 157b, and a voltage drop occurs.
[0044]
At the time of the interconnection test of the semiconductor integrated circuit shown in FIG. 7, the switch 110a of the integrated circuit device 40 is closed and the power supply voltage VDD of the integrated circuit device 40 is connected to the device terminal 157a in the same manner as the semiconductor integrated circuit described with reference to FIG. 5V) is applied. However, since a voltage drop occurs between the device terminal 157a and the device terminal 157b, a potential lower than the actual potential (5 V) is input to the device terminal 157b. The potential supplied to the integrated circuit device 60 via the device terminal 157b is compared with the reference voltage VT by the digital converter 105b and is converted to a digital value of “H” or “L”. Since the voltage input to the terminal 105b is lower, the result of the digital converter 105b becomes “L” level even if an analog signal corresponding to “H” level is output from the device terminal 157a. Malfunction has occurred.
[0045]
The present invention solves the above-mentioned conventional problems, and uses a boundary scan, an integrated circuit device including an analog circuit, and a semiconductor integrated circuit capable of obtaining an accurate test result in a test between devices. , To provide a test method.
[0046]
[Means for Solving the Problems]
In order to solve this problem, a semiconductor integrated circuit according to the present invention includes a high voltage applying means capable of lowering a power supply voltage of an integrated circuit device to perform an interconnection test between the integrated circuit devices; There is a low voltage applying means that can make the voltage higher than the ground voltage. Further, in order to perform an interconnection test between the integrated circuit devices, a means for changing a reference voltage to be supplied to a digital converter for comparing and determining a terminal voltage with a reference voltage is provided.
[0047]
In order to solve this problem, the method for testing a semiconductor integrated circuit according to the present invention includes, when performing an interconnection test between integrated circuit devices, a step of applying a high voltage to a voltage lower than a power supply voltage of the integrated circuit device; And a step of applying a low voltage that can be made higher than the ground voltage of the integrated circuit device. The method further includes a step of performing a test by changing the reference voltage.
[0048]
According to the present invention, when performing an interconnection test between integrated circuit devices, even if the main power supply voltage and the main ground voltage of each integrated circuit device are different, the integrated circuit device to which the voltage is applied is abnormal. It is possible to realize a safe test in which no current flows and no problem such as device destruction due to prolonged abnormal current occurs. Further, according to the present invention, when performing an interconnection test between integrated circuit devices, a device to which a voltage is applied is changed by a digital converter corresponding to a voltage change due to a configuration of an analog discrete component between device terminals. Judgment becomes possible, and the application range of the test can be extended to various configurations.
[0049]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention A boundary scan cell unit, an analog circuit, a first terminal for supplying a first power supply to the analog circuit, and a second terminal for supplying a second power supply to the boundary scan cell unit. It is provided.
[0050]
Thereby, in the semiconductor integrated circuit in which the first power supply supplied to the main analog circuit is different, at least the second power supply supplied to the boundary scan cell unit is the same as the first power supply of all the semiconductor integrated circuits, or Has the effect that it can be lower.
[0051]
The invention also provides Composed on a substrate, and Ground potential In a plurality of different semiconductor integrated circuits, each semiconductor integrated circuit is a boundary scan cell section, an analog circuit, and a first Ground potential And a second terminal connected to the boundary scan cell unit. Ground potential And a second terminal for supplying the main analog circuit. Ground potential In semiconductor integrated circuits with different contacts, the second supply to the boundary scan cell Ground potential Has at least the same or higher value as the first ground potential of all the semiconductor integrated circuits.
[0052]
The present invention A boundary scan cell unit, an analog circuit, a terminal for supplying a first power supply to the analog circuit, and means for generating a second power supply from the first power supply, Same as above Has an action.
[0053]
The present invention The reference voltage supplied to the digital converter constituting the boundary scan cell unit is variable, and the reference voltage can be changed to a more appropriate value during an interconnection test.
[0054]
The present invention In an interconnect test of a plurality of semiconductor integrated circuits each having a boundary scan cell unit, an analog circuit, and device terminals, the analog circuit is operated by a first power supply during normal operation. In the interconnection test, the boundary scan cell section is operated by a second power supply, and the second ground potential supplied to the boundary scan cell section is at least all of The semiconductor integrated circuit can be tested in a state equal to or higher than the first ground potential of the semiconductor integrated circuit. Also, the semiconductor integrated circuit can be tested in a state where the second power supply potential supplied to the boundary scan cell unit is at least the same as or lower than the first power supply potential of all the semiconductor integrated circuits. Have.
[0055]
The present invention In an interconnect test of a plurality of semiconductor integrated circuits each having a boundary scan cell unit, an analog circuit, and device terminals, the analog circuit is operated by a first power supply during normal operation. During the interconnection test, the boundary scan cell section is operated by a second power supply, and the digital converter of the boundary scan cell section is referenced to the digital converter via an analog bus external to the semiconductor integrated circuit. It is characterized by applying a voltage, and has an effect that a semiconductor integrated circuit can be tested in a state where a reference voltage is changed to a more appropriate value during an interconnection test.
[0056]
The present invention In an interconnection test of a plurality of semiconductor integrated circuits each formed on a substrate and each including a boundary scan cell unit, an analog circuit, and a device terminal, an analog test of the boundary scan cell unit is performed during the interconnection test. A reference voltage of the converter is set to about a half of an "H" level potential input to an input terminal of the semiconductor integrated circuit; Same as above It has the action of
[0057]
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0058]
(Embodiment 1)
A first embodiment of the present invention will be described with reference to FIG.
[0059]
Hereinafter, the configuration of the semiconductor integrated circuit shown in FIG. 1 will be described.
[0060]
The difference between the semiconductor integrated circuit shown in FIG. 1 and the conventional semiconductor integrated circuit described above with reference to FIG. 6 is that each of the integrated circuit devices 1 and 30 has two power supply terminals VDD1 ( Hereinafter, the main power supply terminal), VDD2 (hereinafter, referred to as a sub power supply terminal), two ground terminals VSS1 (hereinafter, referred to as a first ground terminal), and a ground terminal VSS2 (hereinafter, referred to as a second ground terminal). And the reference voltage VT applied to the digital converters 105a and 105b is connected to the first analog bus 155 and the second analog bus 156. The same components as those of the conventional semiconductor integrated circuit shown in FIG. 6 are denoted by the same reference numerals and description thereof is omitted.
[0061]
As shown in FIG. 1, with respect to the integrated circuit device 1, the main analog circuit 120a is supplied with a drive voltage of 5 V from the main power supply terminal VDD1, and the digital converter 105a and the boundary scan cells 106a to 109a are provided with sub power supply terminals. Power of 3 V is supplied from VDD2. The reference voltage VT is applied to the digital converter 105a via the switch 14a, and the first analog bus 155 is connected to the digital converter 105a via the switch 15a.
[0062]
In the integrated circuit device 30, a driving voltage of 3 V is supplied from the main power supply terminal VDD1 to the main analog circuit 120b, and a voltage of 3 V is supplied from the sub power supply terminal VDD2 to the digital converter 105b and the boundary scan cells 106b to 109b. Have been. The reference voltage VT is applied to the digital converter 105b via the switch 14b, and the first analog bus 155 is connected to the digital converter 105a via the switch 15b. Further, the scan output TDO of the integrated circuit device 1 and the scan input TDI of the integrated circuit device 30 are connected.
[0063]
The operation of the semiconductor integrated circuit configured as described above will be described below.
[0064]
When the device interconnection test is performed according to the standard boundary scan test method of IEEE1149.1, first, serial test data for switch control is captured from the TDI of the integrated circuit device 1 by the capture flip-flops of the boundary scan cells 106a to 109a. To the capture flip-flops of the boundary scan cells 106b to 109b via the TDO of the integrated circuit device 1 and the TDI of the integrated circuit device 30. Then, each capture flip-flop sends test data to the corresponding update flip-flop, and turns on the switches 110a and 15b.
[0065]
The first analog bus 155 supplies the lower power supply voltage (here, the main analog circuit 120b) of the main power supply voltages VDD1 supplied to the main analog circuits 120a or 120b of the two integrated circuit devices. A reference voltage of about 1/2 of the main power supply voltage (3 V) is supplied. Then, in the integrated circuit device 1, a high level voltage (3V) lower than the main power supply terminal VDD1 (5V) is transmitted from the sub power supply terminal VDD2 to the device terminal 157a via the switch 110a, and the analog discrete component 18 (resistor ) To the device terminal 157b of the integrated circuit device 30. This voltage is supplied from the first analog bus 155 via the switch 15b and compared with the reference voltage in the digital converter 105b, and is set to the “H” level to capture the flip-flop of the boundary scan cell 106b as digital data. Captured on the flop. The fetched data is transmitted as a 3V / 0V digital signal from TDO of the integrated circuit device 1 to TDI of the integrated circuit device 30 by the data shift operation of the boundary scan cell of the power supply 3V of VDD2 of the integrated circuit device 30 by the data shift operation. , And finally output from the TDO of the integrated circuit device 30 as test result data. The TDO output data is subjected to an interconnection test by performing a comparison judgment (GO / NOGO judgment) with expected value data prepared in advance by a digital automatic inspection device (digital tester) or the like.
[0066]
In the above embodiment, the main power supply voltage VDD1 (3 V) of the integrated circuit device 30 and the sub power supply terminal VDD2 of the integrated circuit device 1 are the same. If it is equal to or less than and is higher than the reference voltage VT supplied to the digital converter of each integrated circuit device, there is no problem.
[0067]
As is apparent from the above description, in the semiconductor integrated circuit of the present invention, even if the interconnection test of the integrated circuit devices is performed between the integrated circuit devices 1 and 30 having different main power supply voltages (VDD1), Since the voltage supplied from the terminal VDD2 is lower than the main power supply voltage, it is possible to prevent an abnormal current from flowing from an integrated circuit device having a high main power supply to an integrated circuit device having a low main power supply.
[0068]
In the above-described embodiment, a terminal different from the main power supply is provided as means for supplying a voltage lower than the main power supply voltage to the boundary scan cell unit; however, the present invention is not limited to this. For example, means for generating a sub power supply from a main power supply may be provided inside the integrated circuit device.
[0069]
In the above embodiment, only the power supply voltage has been described. However, when an interconnection test is performed between two integrated circuit devices, even if the ground power supply VSS is different, the abnormal current is the same as when the power supply voltage VDD is different. As shown in FIG. 1, by providing each of the integrated circuit devices with two ground power supply terminals VSS (VSS1 and VSS2), the same effect as in the case of the power supply voltage can be obtained.
[0070]
Note that the operation between the integrated circuit devices having different ground power supplies VSS is the same as the case where the main power supply voltage is different, and therefore the description is omitted here.
[0071]
Further, by adopting a configuration in which the reference potential VT of the digital converter is supplied from the analog bus and the reference voltage is made variable, the versatility of the potential of the sub-power supply VDD2 can be further provided.
[0072]
For example, referring to FIG. 1, when the integrated circuit device 1 is operated normally, the main power supply VDD1 is 5V, so that the reference voltage VH of the digital converter 105a is set to about 2.5V.
[0073]
However, when performing the interconnection test, a power of 3 V is supplied to the integrated circuit device 1 from the sub power supply VDD2. However, since the potential of the reference voltage (2.5 V) is very close to the potential of the power supply (3 V), a malfunction easily occurs. Therefore, when performing an interconnection test, the switch 14a is turned off, the switch 15a is turned on, and a reference voltage supplied to the digital converter 105a is turned on, and a voltage of 1.5 V is supplied from the first analog bus, thereby causing a malfunction. Can be reduced.
[0074]
Note that it is not always necessary to adopt a configuration that can change the reference potential of the digital converter.
[0075]
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIG.
[0076]
Hereinafter, the configuration of the semiconductor integrated circuit shown in FIG. 2 will be described.
[0077]
The semiconductor integrated circuit shown in FIG. 2 is different from the semiconductor integrated circuit of the first embodiment described above with reference to FIG. 1 in that VDD2 and VDD1 are all 5V power supplies, The point is that discrete components 28 and 29 are interposed between the device 1 and the integrated circuit device 30. The configuration of the discrete components 28 and 29 is the same as that of the semiconductor integrated circuit shown in FIG. 1 and 6 are denoted by the same reference numerals, and description thereof is omitted. Since the operation is also the same as that of the semiconductor integrated circuit of the first embodiment, only the differences from the operation of the first embodiment will be described below, and the description of the other operations will be omitted.
[0078]
Hereinafter, the operation of the semiconductor integrated circuit according to the second embodiment shown in FIG. 2 will be described.
[0079]
The analog discrete components 28 and 29 of the semiconductor integrated circuit shown in FIG. 2 are resistors having the same size. When a signal of 5V is output from the device terminal 157a, the signal input to the device terminal 157b is It is assumed that the voltage drops to about 2.5V. In addition, a reference voltage of about の of the voltage (2.5 V) after the voltage drop of the power supply voltage VDD2, that is, about 1.25 V, is supplied from the first analog bus 155 to the digital converter 105 b.
[0080]
In the second embodiment, the voltage applied from the integrated circuit device 1 to the device terminal 157b drops to about 2.5 V through the analog discrete components 28 and 29. converter 105b In First Analog bus 155 Supplies a reference voltage of about 1.25 V via the switch 15b, so that even if a voltage drop occurs between the integrated circuit devices 1 and 30, it can be converted into a correct digital signal.
[0081]
As is apparent from the above description, in the semiconductor integrated circuit according to the second embodiment of the present invention, when performing an interconnection test between a plurality of integrated circuit devices, even if a voltage drop occurs between the integrated circuit devices, In other words, even when the signal amplitude differs depending on the integrated circuit device, the conversion reference voltage of the digital converter can be arbitrarily changed from the outside via the first or second analog bus. And a correct conversion result can be obtained from the digital converter.
[0082]
1 and 2, each integrated circuit device has a configuration having one device terminal 157a or 157b. However, an actual integrated circuit device has a plurality of device terminals as shown in FIG. It is common.
[0083]
Next, an embodiment in which the present invention is applied to an integrated circuit device having a plurality of device terminals will be briefly described with reference to FIG.
[0084]
As shown in FIG. 3, the main analog circuit block 2 is composed of a main analog circuit 120a, a switch 121a, and switches 22 to 24, and a digital converter 105a, boundary scan cells 106a to 109a, and a boundary scan cell unit 3. , The surge protection circuit 4 is configured by the surge protection diodes 116a and 117a, and the switch section 6 is configured by the switches 110a to 113a.
[0085]
The integrated circuit device 1 has four device terminals 157a, 7, 8, and 9. Between the device terminal 157a and the main analog circuit block 2, a surge protection circuit 4, a switch unit 6, a boundary scan Through the cell 3. Similarly, the other device terminals 7, 8, 9 are connected between the device terminals 7, 8, 9 and the main analog circuit block 2 by the surge protection circuits 41, 42, 43, the switch units 61, 62, 63, and the boundary. Via scan cells 31, 32, 33; Reference numeral 25 denotes a test access port (TAP) controller for controlling boundary scan according to IEEE1149.1. When a boundary scan test is performed, a test clock TCK and a test mode switching signal TMS are input to the TAP controller from outside the integrated circuit device 1. The TDO is connected by one line via the TDI and the boundary scan cells 33, 32, 3, and 31. The device terminal 157a is connected to the device terminal 157b of the adjacent integrated circuit device 30, and the device terminal 7 is connected to the device terminal 11.
[0086]
Since the configuration of the integrated circuit device 30 is the same as that of the integrated circuit device 1, the description is omitted.
[0087]
Although only four device terminals are disclosed in the integrated circuit device 1 in FIG. 3, actually, the integrated circuit device 1 has more device terminals.
[0088]
For example, there are a number of device terminals between the device terminal 157a and the device terminal 7, and each device terminal is connected to the main analog circuit block via a surge protection circuit, a switch unit, and a boundary scan cell unit. It is connected.
[0089]
In the above embodiment, a surge protection diode is used as a surge protection element as the most general example, but the surge protection element is not limited to this.
[0090]
In the above embodiment, when integrated circuit devices having different drive voltages of the main analog circuit of the integrated circuit device are connected, a voltage lower than the power supply voltage of the integrated circuit device is applied to the signal terminals TDI and TDO of the boundary scan chain. As the supplying means, another power supply voltage lower than the main power supply voltage of the integrated circuit device is supplied to all the boundary scan cells of the integrated circuit device, but the power supply voltage is supplied to all the boundary scan cells of the integrated circuit device. Instead, only the TDO and TDI of the integrated circuit device may be provided as separate power supplies.
[0091]
Further, a buffer or the like having a small voltage amplitude may be used for the final output supplied to the TDO terminal inside the integrated circuit device, and a gate or the like having a low input voltage level may be used as the first logic element connected to the TDI terminal. .
[0092]
Further, in the above-described embodiment, when the interconnection test of the integrated circuit device is described, the case where the voltage lower than the power supply voltage of the integrated circuit device is supplied to the device terminal is mainly described. Similar effects can be obtained when a voltage higher than the power supply voltage is supplied to the device.
[0093]
【The invention's effect】
As described above, according to the present invention, in an interconnect test of an integrated circuit device including analog circuits having different power supply voltages and ground voltages, it is possible to prevent adverse effects caused by an abnormal current flowing through the integrated circuit device, and An interconnect test between integrated circuit devices can be performed. A system for mounting an electronic element such as an integrated circuit device including an analog circuit on a substrate can be easily tested by a unified test method, and the applicable range can be greatly expanded. In addition, the accuracy and stability of the test can be improved by arbitrarily varying the voltage judgment level using the analog bus due to the configuration of analog discrete components between integrated circuit devices including analog circuits and the difference in device power supply voltage. Can be improved. Further, since the analog bus is shared to supply the reference voltage from outside the integrated circuit device, an advantageous effect that a new terminal need not be added to the device can be obtained. In addition, the conversion reference voltage of the digital converter can be arbitrarily changed from the outside by using the analog bus, and the digital conversion can be correctly performed even when the signal voltage of the device under test terminal is changed. The application range of boundary scan test is expanded.
[0094]
That is, there is obtained an effect that the application range of the integrated circuit device mounted on the printed circuit board is expanded, and the applicable range of the boundary scan test for various analog terminals is greatly expanded.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a semiconductor integrated circuit according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention;
FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit of the present invention.
FIG. 4 is a diagram showing a configuration of a conventional semiconductor integrated circuit.
FIG. 5 is a diagram showing a configuration of a boundary scan cell section of a conventional semiconductor integrated circuit.
FIG. 6 is a diagram showing a configuration of a first example of a conventional semiconductor integrated circuit.
FIG. 7 is a diagram showing a configuration of a second example of a conventional semiconductor integrated circuit.
[Explanation of symbols]
1 Integrated circuit device
2 Main analog circuit block
3 Boundary scan cell section
4 Surge protection circuit
6 Switch section
7, 8, 9, 11, 12, 13 device terminals
14, 15 switch
18 Discrete parts
22, 23, 24 switches
25 TAP controller
26 Main analog circuit block
27 TAP controller
28, 29 Discrete parts
30 Integrated circuit devices
31, 32, 33, 34, 35, 36, 37 Boundary scan cell section
40, 50, 60 integrated circuit devices
41, 42, 43, 44, 45, 46, 47 surge protection circuit
55, 56, 59, 157 Device terminals
61, 62, 63, 64, 65, 66, 67 switch section
82, 110, 111, 112, 113 switch
100, 101 Boundary scan cell section
105 Digital Converter
106, 107, 108, 109 Boundary scan cell
116, 117, 123, 124 Surge protection diode
120 Main analog circuit
121 switch
150, 151, 152, 153 switch
155 first analog bus
156 second analog bus
157 Device terminal

Claims (9)

In a semiconductor integrated circuit in which a plurality of integrated circuit devices having different main power supplies are formed on a printed circuit board,
Each of the plurality of integrated circuit devices has a boundary scan cell unit, an analog circuit, a first terminal for supplying a first power supply to the analog circuit, and a second power supply for the boundary scan cell unit. comprises a second and a terminal for supplying a,
A semiconductor integrated circuit, wherein all of the second power supplies of the plurality of integrated circuit devices are equal to or lower than the lowest potential of the first power supplies of the plurality of integrated circuit devices . In a semiconductor integrated circuit in which a plurality of integrated circuit devices having different ground-side potentials are formed on a printed circuit board ,
Each of the plurality of integrated circuit devices includes a boundary scan cell unit, an analog circuit, a first terminal for supplying a first ground potential to the analog circuit, and a second terminal connected to the boundary scan cell unit . A second terminal for supplying a second ground potential ,
A semiconductor wherein all of the second ground potentials of the plurality of integrated circuit devices are equal to or higher than the highest potential among the first ground potentials of the plurality of integrated circuit devices. Integrated circuit. In a semiconductor integrated circuit in which a plurality of integrated circuit devices having different main power supplies are formed on a printed circuit board ,
Each of the plurality of integrated circuit devices has a boundary scan cell unit, an analog circuit, a first terminal for supplying a first power supply to the analog circuit, and a second power supply for the boundary scan cell unit . Means for supplying
A semiconductor integrated circuit, wherein all of the second power supplies of the plurality of integrated circuit devices are equal to or lower than the lowest potential of the first power supply of the plurality of integrated circuit devices . In a semiconductor integrated circuit in which a plurality of integrated circuit devices having different ground-side potentials are formed on a printed circuit board ,
Each of the plurality of integrated circuit devices includes a boundary scan cell unit, an analog circuit, a first terminal for supplying a first ground potential to the analog circuit, and a second terminal connected to the boundary scan cell unit. Means for supplying a second ground potential,
A semiconductor wherein all of the second ground potentials of the plurality of integrated circuit devices are equal to or higher than the highest potential among the first ground potentials of the plurality of integrated circuit devices. Integrated circuit. 3. The semiconductor integrated circuit according to claim 1 , wherein a reference voltage supplied to a digital converter forming the boundary scan cell unit is variable. 6. The semiconductor device according to claim 5, wherein a terminal for supplying a reference voltage of a digital converter constituting the boundary scan cell unit and an analog bus external to the semiconductor integrated circuit are connected via a switch. Semiconductor integrated circuit. An interconnect test of a plurality of integrated circuit devices configured on a printed circuit board , each including a boundary scan cell unit, an analog circuit, and device terminals. Operating the circuit, and at the time of the interconnection test, operating the boundary scan cell unit with the second power supply;
A method of testing an integrated circuit, wherein all of the second power supplies of the plurality of integrated circuit devices are at the lowest potential or lower than the first power supply of the plurality of integrated circuit devices . An interconnect test of a plurality of integrated circuit devices configured on a printed circuit board , each including a boundary scan cell unit, an analog circuit, and device terminals. A circuit is operated, and at the time of an interconnection test, the boundary scan cell section is operated by a second power supply, and an analog bus external to the integrated circuit device is connected to a digital converter of the boundary scan cell section. A test method for a semiconductor integrated circuit, wherein a reference voltage is applied via the semiconductor integrated circuit. An interconnect test for a plurality of integrated circuit devices configured on a printed circuit board and each including a boundary scan cell unit, an analog circuit, and a device terminal, wherein during the interconnect test, the boundary scan cell is used. A reference voltage of an analog converter of the unit is set to about one half of an "H" level potential input to an input terminal of the integrated circuit device .

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