JP3308496B2 - Manufacturing method of dielectric isolation wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric isolation wafer, and more particularly, to a method in which a negative resist applied to the back surface of a silicon wafer is applied to the front side of the outer peripheral portion of the wafer during a photolithography process for forming a dielectric isolation groove. When the front negative resist film is developed after the back negative resist is applied, it is prevented from squeezing and crushing the window for the dielectric separation groove formed in the negative resist on the front surface of the wafer existing in this region. Also, the present invention relates to a method for manufacturing a dielectrically separated wafer in which the vicinity of the outer peripheral portion of the backside negative resist film is less likely to be melted down even if the developing solution flows around the wafer backside.

[0002]

2. Description of the Related Art In a general dielectric isolation wafer, a dielectric isolation groove is formed on the surface of a silicon wafer, and then a dielectric isolation oxide film is laminated thereon.
(Chemical Vapor Deposition
n: chemical vapor deposition), a polysilicon layer is grown on the dielectric isolation oxide film to approximately the thickness of a wafer, and then the silicon single crystal of the dielectric isolation silicon island is ground and polished from the silicon wafer side. It is manufactured by manufacturing. However, in the case of a dielectric isolation wafer manufactured by such a method, only a wafer having a diameter of up to 4 inches can be manufactured due to the entire thickness and the warpage. In order to solve the problem of increasing the diameter of the wafer, a bonded dielectric manufactured by bonding a wafer for an active layer, which is a dielectric separation wafer, and a wafer for a supporting substrate that supports the wafer has recently been developed. Separate wafers have been developed.

[0003] This bonded dielectric separation wafer is manufactured through the steps shown in the explanatory view showing the manufacturing process of the general bonded dielectric separation wafer in FIG. Less than,
The bonded dielectric separation wafer will be described with reference to FIG. First, a silicon wafer 10 whose surface is mirror-finished is prepared as an active layer wafer (FIG. 2).
(A)). Next, a mask oxide film 11 is formed on the front and back surfaces of the silicon wafer 10 (see FIG. 2B).
Then, a negative resist film 12 with a window 12a is formed by photolithography. Next, the silicon wafer 10 is immersed in an etchant (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window 12a on the wafer surface (see FIG. 2C). As a result, a dielectric separation groove 13 having a V-shaped cross section is formed on the wafer surface.
In addition, the anisotropic etching referred to here is etching in which the etching speed in the depth direction is higher than that in the horizontal direction due to the crystal plane orientation of the silicon wafer 10 and the etching speed has direction dependency. is there.

Next, the negative resist film 12 is removed, and the exposed mask oxide film 11 is washed and removed (see FIG. 2D). Thereafter, if necessary, dopants (Sb, As, etc.) are thermally diffused and ion-implanted into the silicon wafer 10, and then a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 2E). reference). As a result, the dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13.
Is formed. Next, the wafer surface is cleaned.

Subsequently, a seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by low-temperature CVD at about 600.degree. After cleaning, this kind of polysilicon layer 1
A high-temperature polysilicon layer 16 is grown thicker on the substrate 5 by a high-temperature CVD method at about 1250 ° C. (see FIG. 2F). Then, the outer peripheral portion of the wafer is chamfered, and if necessary, the back surface of the wafer is flattened. Then, the high temperature polysilicon layer 16 on the wafer surface is ground to a thickness of about 20 to 50 μm.
Polishing (see FIG. 2 (g)). Thereafter, a low-temperature polysilicon layer 17 having a thickness of about 2 to 3 μm is formed on the wafer surface by a low-temperature CVD method at 600 ° C., and then the surface of the low-temperature polysilicon layer 17 is polished in order to mirror-bond the bonding surface. .

On the other hand, a silicon wafer 20 (here, covered with a silicon oxide film 21) to be a support substrate wafer is prepared (see FIG. 2 (h)). This is a mirror-finished wafer surface. Next, the silicon wafer 10 for the active layer wafer is bonded onto the silicon wafer 20 by bringing the mirror surfaces into contact with each other (see FIG. 2 (i)). Then, heat treatment is performed to increase the bonding strength of the bonded wafer. Next, FIG.
As shown in (j), the outer periphery of the silicon wafer 10 for the active layer is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is removed by HF cleaning. Is ground and polished. The amount of grinding of the silicon wafer 10 is such that the dielectric isolation oxide film 14 is exposed to the outside and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 on the surface of the high-temperature polysilicon layer 16. Appearance, the amount is such that adjacent silicon islands are completely separated. In this way, a bonded dielectric separation wafer is manufactured.

As described above, a photolithographic method is used to form a window 12a for anisotropically etching the dielectric isolation groove 13 in the negative resist film 12 of the silicon wafer 10. The photolithography method writes a pattern on the surface of a negative resist film 12 applied to a silicon wafer 10 by exposure,
Thereafter, this is a method of developing. Hereinafter, the flow of the photolithographic process will be described with reference to the explanatory diagram of the general photolithographic process in FIG.

First, a negative resist 12 is applied to the surface of a silicon wafer 10 (see FIG. 3A) on which a mask oxide film 11 is formed, and then the solvent in the applied negative resist film 12 is effectively removed by pre-baking. Remove. Next, the negative resist film 12 is exposed, developed and rinsed (see FIG. 3B). As a result, windows 12a for anisotropic etching are formed in the negative resist film 12 on the wafer surface. After that, the silicon wafer 10 may be put into a baking furnace, and post-baking may be performed to promote the cross-linking reaction of the surface negative resist film 12 to make it stronger. Then, a negative resist 12A is applied to the back surface of the wafer in order to prevent the back surface side of the mask oxide film 11 covering the silicon wafer 10 from being melted and damaged by the etchant during anisotropic etching in a later step. More specifically, the silicon wafer 10 is turned over, and a negative resist film 12A is applied to the back surface of the wafer (see FIG. 3C). Then, the negative resist film 12A is put into a baking furnace, and the front and back negative resist films 12, 12A are post-baked. Thus, the crosslinking reaction of the negative resist films 12 and 12A is promoted (see FIG. 3D).

In this general method, when the negative resist 12A is applied to the back surface of the silicon wafer 10,
The back negative resist 12A wraps around the front side of the outer peripheral portion of the wafer, and this is the window 12 for the dielectric isolation groove 13 formed in the front negative resist film 12 existing in this region.
There was a risk of crushing a (see FIGS. 3C and 3D).
Therefore, conventional means for solving this problem have been developed. That is, after the negative resist 12A is applied to the back surface of the silicon wafer 10, the silicon wafer 10 is rotated forward again as shown in FIG. 4 (c1) of the photolithography process according to the conventional means of FIG. This is a method of performing development and rinsing processing from the side to wash and remove a part of the back negative resist 12A adhered in the window 12a. Note that other steps in FIG. 4 (FIG. 4A)
4 (d) perform the same working steps as the corresponding steps in FIGS. 3 (a) to 3 (d).

[0010]

However, according to such a conventional method of manufacturing a dielectric isolation wafer, a part of the back negative resist 12
In order to eliminate the collapse of the window portion 12a due to A, FIG.
When performing the second development and rinsing process of the wafer surface shown in 1), the second developer is applied in reverse to the reverse of the back negative resist 12A to the front side shown in FIG.
It goes around to the back side of the silicon wafer 10. As a result, the peripheral portion of the unexposed back negative resist 12A is melted and damaged by the second developing solution, and during the anisotropic etching,
There has been a problem that saw-like irregularities are formed in the peripheral portion of the silicon wafer 10 through the eroded portion. The unevenness causes a crack in the wafer at the time of handling the wafer, and causes a crack and a chip in a high-temperature polysilicon forming process in a later process.

Therefore, the inventor of the present invention applies a back negative resist to a silicon wafer, exposes the entire surface of the silicon resist in advance, and causes the entire back negative resist film to undergo a cross-linking reaction. Even if the developer wrapped around the back surface of the wafer, it was found that the vicinity of the outer peripheral portion of the back negative resist film was not melted,
The present invention has been completed.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent the vicinity of the outer periphery of a negative resist film applied on the back surface of a wafer from being melted and damaged by the developing solution during the front negative resist development process after the application of the back negative resist in a photolithographic process. It is an object of the present invention to provide a method for manufacturing a dielectric isolation wafer that can be prevented. Another object of the present invention is to prevent a backside negative resist film from being partially damaged in a method for manufacturing a bonded dielectric separation wafer.

[0013]

According to the first aspect of the present invention, the front and back surfaces of a silicon wafer are covered with a mask oxide film,
A resist film with a window is provided on the surface of the mask oxide film,
Using the resist film as a mask, a window of a predetermined pattern is formed in the mask oxide film, thereby exposing a part of the silicon wafer surface from the window, and anisotropically etching the exposed silicon wafer part to obtain a dielectric material. A separation groove is formed, a dielectric isolation oxide film is formed on the surface of the silicon wafer, a polysilicon layer is grown on the dielectric isolation oxide film, and the silicon wafer is ground and polished from the back side. In the method of manufacturing a dielectric isolation wafer for exposing silicon islands separated by the dielectric isolation oxide film on the polished surface, the step of providing the resist film with the window,
Applying a negative resist to the surface of the mask oxide film, and exposing and developing the negative resist film .
Forming a window of a predetermined pattern, applying a negative resist to the mask oxide film on the back side, exposing the entire surface of the negative resist film on the back side, Removing the adhered back negative resist.

As a method for growing the polysilicon layer, a high-temperature CVD method can be adopted. In this method, a source gas containing silicon is introduced into a reaction furnace together with a carrier gas (such as H ₂ gas), and silicon generated by thermal decomposition or reduction of the source gas is deposited on a silicon wafer heated to a high temperature. Is the way. As the compound containing silicon, SiCl ₄ , SiHCl _{3 and the} like are usually used. As a reactor, in a dome-shaped quartz bell jar,
There is also a vertical (pancake) furnace in which a gas is introduced while rotating a susceptor on which a silicon wafer is mounted and heated by high-frequency induction. In addition, a cylinder (barrel) furnace in which a silicon wafer is attached to each surface of a hexagonal column-shaped susceptor contained in a quartz container, and then the susceptor is rotated while being heated by gas introduction and an infrared lamp. Etc. can also be adopted.

[0015] The growth temperature of polysilicon depends on the heating method of the furnace. In the most common vertical furnace used for this application, 1200 to 1290 ° C, particularly 1230 to 1280 ° C
Is preferred. If the temperature is lower than 1200 ° C., there is a disadvantage that the silicon wafer is easily broken. On the other hand, if the temperature exceeds 1290 ° C., a slip occurs, which causes a disadvantage that the silicon wafer is liable to crack. The thickness of the polysilicon layer is
The thickness is obtained by adding the thickness of the polysilicon layer to be left to the thickness of two to three times the depth at which the anisotropic etching is performed. If the thickness of the polysilicon layer is not more than twice the depth at which the anisotropic etching is performed, the grooves of the anisotropic etching may not be sufficiently filled. On the other hand, if it is three times or more, it will be unnecessarily thick, and it is uneconomical. In addition, when a diffusion layer is formed on an active layer wafer, it is not appropriate to unnecessarily lengthen the thermal history because the diffusion profile greatly changes.

As an anisotropic etching solution, KOH (I
PA / KOH / H ₂ O), KOH (KOH / H ₂ O),
An alkaline etching solution such as KOH (hydrazine / KOH / H ₂ O) can be used. Normal conditions can be applied as the conditions for the anisotropic etching. In addition, the negative resist film on the wafer surface side,
General conditions can be adopted as the conditions of each step for forming the window for anisotropic etching. Further, as the condition for exposing the entire surface of the back negative resist film, which is a feature of the present invention, ordinary exposure conditions can be adopted.

According to a second aspect of the present invention, there is provided a bonded dielectric, wherein the dielectric isolation wafer is formed by laminating an active layer wafer having the dielectric isolation silicon island formed thereon and a supporting substrate wafer. The method for producing a dielectric isolation wafer according to claim 1, wherein the dielectric isolation wafer is a separation wafer.

[0018]

According to the present invention, a mask oxide film is formed on the front and back surfaces of a silicon wafer. Next, a windowed negative resist film is formed on the surface of the silicon wafer. That is, a negative resist is applied to the surface of the silicon wafer, and a predetermined pattern is exposed on the mask oxide film using the negative resist film as a mask. After this exposure, development and rinsing are performed. In some cases, post-baking is performed. Thereafter, the silicon wafer is inverted, and a negative resist is applied to the back side of the wafer of the mask oxide film. Spin coating.

Next, by exposing the entire surface of the negative resist film on the rear surface, a crosslinking reaction proceeds in the entire negative resist film. As a result, the back negative resist film is provided with chemical resistance to a developing solution. Next, the silicon wafer is rotated forward and the exposed surface negative resist film is developed. This development is for the surface negative resist film.
Since the surface negative resist film is developed immediately after exposure,
Window with negative resist on back side wrapped around wafer front side
This is the second development processing for avoiding crushing. At this time, even if the developer wraps around the back surface of the silicon wafer and adheres to the peripheral portion of the back negative resist film, there is almost no possibility that this portion will be melted. This is because the chemical resistance of the back negative resist film is increased in advance by the entire surface exposure.

Thereafter, the silicon wafer covered with the front and back negative resist films is immersed in an etching solution to pass through a window on the wafer surface to form a mask oxide film and a part of the silicon wafer inside the film in an anisotropic manner. Etching. As a result, a dielectric isolation groove is formed. Next, the negative resist film and the mask oxide film on the front and back surfaces are removed. Then, a dielectric isolation oxide film is formed on the wafer surface by oxidizing heat treatment. Subsequently, polysilicon is grown on the dielectric isolation oxide film, and thereafter, the silicon wafer is ground and polished from the back surface side of the wafer to reveal dielectric isolation silicon islands. Thus, a dielectric isolation wafer is manufactured.

In particular, according to the second aspect of the present invention, the effect of the present invention can be obtained by laminating a wafer for an active layer having a dielectrically isolated silicon island made of silicon and a wafer for a supporting substrate thereof. A bonded dielectric separation wafer having the same is manufactured. As a result, the present invention can be applied to a bonded dielectric-isolated wafer that is less likely to cause deterioration in the quality of the dielectric-isolated silicon island due to thermal degradation due to the high-temperature CVD method.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a dielectric isolation wafer according to an embodiment of the present invention will be described below. Here, the bonded dielectric separation wafer described as the above-described conventional technique will be described as an example. Therefore, FIG.
The same components as those shown in FIG. 4 are described with the same reference numerals. FIG. 1 is an explanatory view of a photolithographic process of a method for manufacturing a dielectric isolation wafer according to a first embodiment of the present invention. The basic steps of the method for manufacturing a dielectric isolation wafer according to the first embodiment of the present invention are described in FIG.
This is the same as the manufacturing process of the general bonded dielectric isolation wafer shown in FIG. However, the present invention differs from the prior art in part of the basic photolithographic steps during the manufacture of the dielectric isolation wafer shown in FIG.

First, a silicon wafer 10 whose front and back surfaces are mirror-finished is prepared as an active layer wafer (FIG. 2).
(A)). Next, a mask oxide film 11 is formed on the front and back surfaces of the silicon wafer 10 (see FIG. 2B). Next, a negative resist film 12 with a window 12a is formed by photolithography. Next, the silicon wafer 10 is etched with an etching solution (IPA / KOH / H ₂ O).
And anisotropically etch the wafer surface (see FIG. 2 (c)). As a result, a dielectric separation groove 13 having a V-shaped cross section is formed on the wafer surface.

Next, the negative resist film 12 is removed, and the exposed mask oxide film 11 is removed (see FIG. 2D). Thereafter, if necessary, a dopant is implanted into the silicon, and then a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (see FIG. 2E). As a result, a dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13. Next, the wafer surface is cleaned.

Subsequently, a seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by low-temperature CVD at about 600.degree. After cleaning, this kind of polysilicon layer 1
A high-temperature polysilicon layer 16 is grown thicker on the substrate 5 by a high-temperature CVD method at about 1250 ° C. (see FIG. 2F). Then, the outer peripheral portion of the wafer is chamfered, and if necessary, the back surface of the wafer is flattened. Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 30 μm (see FIG. 2G). After that, 600
After a low-temperature polysilicon layer 17 having a thickness of about 3.0 μm is formed by a low-temperature CVD method at a temperature of about 40 ° C., the surface of the low-temperature polysilicon layer 17 is polished in order to mirror the bonding surface.

On the other hand, a silicon wafer 20 (here, covered with a silicon oxide film 21) to be a support substrate wafer is prepared (see FIG. 2 (h)). The wafer surface is mirror-finished. Next, the silicon wafer 10 for the active layer wafer is bonded onto the silicon wafer 20 by bringing the mirror surfaces into contact with each other (FIG. 2).
(See (i)). Then, heat treatment is performed to increase the bonding strength of the bonded wafer. Next, FIG.
As shown in (j), the outer peripheral portion of the silicon wafer 10 for the active layer is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is removed by HF cleaning. The silicon wafer 10 is ground and polished. The amount of grinding of the silicon wafer 10 is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. The amount is such that adjacent silicon islands are completely separated. In this way, a bonded dielectric separation wafer is manufactured.

Hereinafter, the photolithography process in the first embodiment will be described. First, a negative resist 12 is spin-coated on the surface of a silicon wafer 10 (see FIG. 1A) on which a mask oxide film 11 is formed, the surface of which is held horizontally. Next, in the photolithographic process, a window 12a having a predetermined pattern is provided in the negative resist film 12 through pre-baking, exposure, development, and rinsing which are usually performed (see FIG. 1B). After this,
The silicon wafer 10 may be placed in a baking furnace (not shown), and post-baking of the negative resist film 12 on the wafer surface may be performed. Thereafter, the silicon wafer 10 with the window 12a is inverted, and a negative resist 12A is spin-coated on the back surface of the wafer. At this time, the back negative resist 12A wraps around to the front side of the outer peripheral portion of the wafer, and crushes the windows 12a formed in the front negative resist film 12 existing in this region (see FIG. 1C).

Next, the entire surface of the back negative resist film 12A is exposed to cause a cross-linking reaction of the back negative resist film 12A (see FIG. 1 (c2)). This step is a feature of the present invention. By performing a crosslinking reaction, the back negative resist film 12 is formed.
Chemical resistance to the etching solution of A is increased. afterwards,
The entire surface of the exposed silicon wafer 10 is rotated forward, and a second development and rinsing process is performed from the wafer surface side. Thereby, the back negative resist 12A that has crushed the inside of the window 12a is removed by washing. At this time, the second developing solution goes around the back side of the outer peripheral portion of the wafer, and tries to dissolve a part of the outer peripheral portion of the back negative resist film 12 (FIG. 1).
(See (c1)).

However, the back negative resist film 1
As shown in FIG. 1 (c2), 2A has undergone a cross-linking reaction by exposure to the entire surface in advance, and has increased chemical resistance. As a result, even if the second developing solution is applied to the vicinity of the outer peripheral portion of the back negative resist film 12A, it is hard to be melted. Thereafter, the silicon wafer 10 is placed in a baking furnace, and the front and back negative resists 12 and 12A are post-baked. In this embodiment, a bonded dielectric separation wafer in which the active layer wafer 10 having the dielectric separation silicon island 10A and the support substrate wafer 20 are bonded to each other is employed. And not.

[0030]

According to the present invention, since the backside negative resist is applied to the silicon wafer and then the entire surface is exposed, the silicon wafer is coated on the backside of the wafer during the frontside negative resist development process after the backside negative resist is applied. The vicinity of the outer peripheral portion of the negative resist film can be prevented from being melted and damaged by the developer.

In particular, according to the second aspect of the present invention, the present invention can be applied to a bonded dielectric separation wafer. In this case, thick polysilicon layer growth by high-temperature CVD is not required.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a photolithographic process of a method for manufacturing a dielectrically separated wafer according to a first embodiment of the present invention.

FIG. 2 is an explanatory view showing a manufacturing process of a general bonded dielectric separation wafer.

FIG. 3 is an explanatory diagram of a general photolithographic process.

FIG. 4 is an explanatory diagram of a photolithographic process according to a conventional means.

[Explanation of symbols]

10 Silicon wafer for active layer wafer, 10A
Dielectric isolation silicon island, 11 mask oxide film, 12
Negative resist film, 12a window, 13 dielectric isolation groove, 14 dielectric isolation oxide film, 16 polysilicon, 2
0 Silicon wafer for supporting substrate wafer.

Claims (2)

(57) [Claims] 1. A method according to claim 1, wherein the front and back surfaces of the silicon wafer are covered with a mask oxide film, a resist film with a window is provided on the surface of the mask oxide film, and windows of a predetermined pattern are formed in the mask oxide film using the resist film as a mask. A part of the surface of the silicon wafer is exposed from the window, a part of the exposed surface of the silicon wafer is anisotropically etched to form a groove for dielectric isolation, and a dielectric isolation oxide film is formed on the surface of the silicon wafer. A polysilicon layer is grown on the dielectric isolation oxide film, and a silicon wafer is ground and polished from the back side to reveal silicon islands separated by the dielectric isolation oxide film on the polished surface. In the method for manufacturing a dielectric isolation wafer, the step of providing the resist film with a window includes a step of applying a negative resist to the surface of the mask oxide film. Exposure to the negative resist film, by performing a development, and forming a window portion of the predetermined pattern, a step of applying a negative resist on the back side of the mask oxide film, the overall exposure to negative resist film in the back surface side A method for producing a dielectrically separated wafer, comprising: a step of applying; and a step of removing a back negative resist adhered in the window of the front negative resist. 2. The bonded dielectric separation wafer produced by bonding an active layer wafer on which the dielectric isolated silicon island is formed and a supporting substrate wafer to each other. 3. The method for producing a dielectrically separated wafer according to 1.