JP3951568B2 - Manufacturing method of bonded dielectric isolation wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a bonded dielectric isolation wafer, and more particularly, to a method for manufacturing a bonded dielectric isolation wafer that eliminates voids at the wafer bonding interface generated by polysilicon that wraps around the back surface of an active layer wafer.
[0002]
[Prior art]
Conventional bonded dielectric isolation wafers have been manufactured through the steps shown in FIGS.
First, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared (FIG. 3A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 3B). Further, a photoresist film 12 is deposited on the mask oxide film 11, and an opening is formed at a predetermined position by photolithography. Subsequently, the oxide film 11 exposed through the opening is removed, and a window having a predetermined pattern is formed in the oxide film 11. As a result, a part of the surface of the silicon wafer 10 is exposed. Next, after removing the photoresist film 12, the silicon wafer 10 is immersed in an alkaline etching solution (IPA / KOH / H ₂ O) to anisotropically etch the inside of the window on the wafer surface (FIG. 3C). ). Thus, the dielectric separating groove 13 having a V-shaped cross section is formed on the wafer surface.
[0003]
Next, the mask oxide film 11 is removed by washing with dilute HF solution (diluted hydrofluoric acid solution) or buffer hydrofluoric acid solution (FIG. 3D). Then, a dielectric isolation oxide film 14 is formed on the wafer surface by an oxidation heat treatment (FIG. 3E). As a result, a dielectric isolation oxide film 14 having a predetermined thickness is formed on the surface of the silicon wafer including the surface on which the dielectric isolation trench 13 is formed.
Subsequently, a seed polysilicon layer 15 is deposited to a predetermined thickness on the surface of the silicon wafer 10, that is, on the dielectric isolation oxide film 14, and then the high temperature polysilicon is formed by a high temperature CVD method at about 1200 to 1300 ° C. The layer 16 is grown to a thickness of about 150 μm (FIG. 3F). Then, the outer peripheral portion of the wafer is mechanically chamfered with a chamfering grindstone, and the back surface of the wafer is polished to remove unnecessary polysilicon portions that have wrap around the back surface of the wafer and flatten it. Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 10 to 80 μm, and then the silicon wafer 10 is peeled off from the wafer holding plate of the surface polishing apparatus and cleaned (FIG. 4A). .
Thereafter, a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is grown on the wafer surface by a low-temperature CVD method at 550 to 700 ° C. Then, the surface of the low-temperature polysilicon layer 17 is polished for the purpose of flattening the bonding surface (also in FIG. 4A).
[0004]
On the other hand, a silicon wafer 20 covered with a silicon oxide film 21 serving as a support substrate wafer, which is different from the silicon wafer 10, is prepared (FIG. 4B). The wafer surface is mirror-finished. Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 with the mirror surfaces in contact with each other (FIG. 4C).
Thereafter, heat treatment for increasing the bonding strength of the bonded wafer is performed.
Next, as shown in FIG. 4D, the outer peripheral portion of the bonded wafer on the active layer wafer side is chamfered. That is, it is ground obliquely from the surface of the silicon wafer 10 and chamfered until it passes through the bonding interface and reaches the surface layer portion of the silicon wafer 20.
Then, the surface of the bonded wafer on the active layer wafer side is ground and polished (FIG. 4E). The amount of grinding of the active layer wafer is such that a part of the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 on the surface of the high temperature polysilicon layer 16 is used. Until appears. The silicon oxide film 21 is removed at an appropriate time by HF cleaning.
[0005]
[Problems to be solved by the invention]
By the way, in this prior art, as described above, after the high temperature polysilicon layer 16 is grown on the surface of the silicon wafer 10, the polysilicon protrusions 16a that wrap around from the wafer surface side to the wafer back surface are removed by polishing. This is to prevent dimples from being generated by transferring the polysilicon protrusions 16a on the back surface of the wafer to the wafer surface when the subsequent high-temperature polysilicon layer 16 is ground and polished. As a result, voids generated at the bonding interface by dimples during the wafer bonding heat treatment can be eliminated.
However, if the polysilicon protrusions 16a on the back surface of the wafer are removed by polishing in this way, the silicon wafer 10 is damaged when the silicon wafer 10 is adhered to the wafer holding plate of the polishing apparatus and the back surface of the wafer is polished with a polishing cloth. There was a risk of receiving. Further, when the polysilicon protrusion 16a is firmly adhered, the polysilicon protrusion 16a is not removed, and there is a possibility that the periphery thereof is excessively polished.
[0006]
OBJECT OF THE INVENTION
Therefore, an object of the present invention is to provide a method for manufacturing a bonded dielectric isolation wafer that hardly damages the active layer wafer during the removal of the polysilicon adhering to the back surface of the active layer wafer.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, a polysilicon layer is grown on the surface of the active layer wafer via a dielectric isolation oxide film, and after polishing and polishing the surface of the polysilicon layer, the polished surface is bonded to the bonded surface. Then, the active layer wafer is bonded to the surface of the support substrate wafer, the outer periphery of the bonded wafer is chamfered, and then the active layer wafer is ground and polished from the back side, and the dielectric separation oxidation is performed on the polished surface. In a method of manufacturing a laminated dielectric isolation wafer that reveals a plurality of dielectric isolation silicon islands separated by a film, the polysilicon adhered to the back surface of the active layer wafer before grinding and polishing the polysilicon layer and while contacting an alkaline etching liquid only on the back surface of the wafer for the active layer to rotate the wafer for the active layer in 10~60rpm by a A method for producing a laminated dielectric isolated wafer to Cali etching.
[0008]
The polysilicon layer may be grown under any conditions. For example, a high-temperature polysilicon layer obtained by a high-temperature CVD method or a low-temperature polysilicon layer obtained by a low-temperature CVD method may be used. The high-temperature CVD method here refers to a material gas containing silicon introduced into a reaction furnace together with a carrier gas (such as H ₂ gas) and generated by thermal decomposition or reduction of the material gas on a silicon wafer heated to a high temperature. This is a method for precipitating silicon. As the compound containing silicon, SiCl ₂ H ₂ , SiHCl ₃ , SiCl _{4 and the} like are usually used.
As a reaction furnace used for the high temperature CVD method, for example, a pancake furnace, a cylinder furnace, or the like can be employed. In that case, the growth temperature of polysilicon differs depending on the heating method of the furnace. In the vertical furnace used for this purpose, 1200 to 1290 ° C, particularly 1320 to 1280 ° C is preferable. If it is less than 1200 degreeC, the problem that a silicon wafer tends to break will arise. Further, when the temperature exceeds 1290 ° C., slip occurs, and the silicon wafer is abnormally warped or easily broken.
[0009]
The thickness of the polysilicon layer is not limited. However, a thickness obtained by adding the thickness of the polysilicon layer to be left to the thickness of 2 to 3 times the depth of anisotropic etching for forming the dielectric separation groove on the wafer surface is preferable. If the thickness of the polysilicon layer is less than twice the depth of anisotropic etching, the etching groove may not be sufficiently filled. On the other hand, if it is 3 times or more, it will grow unnecessarily thick, which is uneconomical.
As the anisotropic etching solution, KOH (IPA / KOH / H ₂ O), KOH (KOH / H ₂ O), or KOH (hydrazine / KOH / H ₂ O) can be used. Normal conditions can be applied to the anisotropic etching conditions.
Moreover, general conditions can be adopted as the conditions of each step for forming the window portion for anisotropic etching in the resist film on the wafer surface side.
[0010]
Etching for removing polysilicon adhering to the back surface of the active layer wafer is alkaline etching .
For example, KOH or NaOH can be used as the alkaline etching solution. KOH is preferably 5 to 20% by weight. Moreover, the temperature of alkaline etching liquid is 60-100 degreeC.
This KOH has a high etch rate with respect to polysilicon among alkaline etchants. Thereby, the polysilicon on the back surface of the wafer can be removed in a short time. On the other hand, NaOH has a low etch rate. Therefore, it is suitable when high-precision etching is required, for example, when the high-temperature polysilicon layer is thin.
At the time of alkaline etching, a condition in which the ratio of the etch rate of polysilicon and silicon oxide is extremely different from about 100: 1 can be selected. If this is used to etch the dielectric isolation oxide film instead of the stopper, the etching control can be simplified. Further, the alkali etching is less likely to have an etching surface than the acid etching when the dielectric isolation oxide film surface is concerned.
An etching apparatus used for removing polysilicon on the back surface of the wafer is not limited. For example, the apparatus etc. which contact the back surface of the wafer for active layers with the liquid level of an etching tank are mentioned.
[0011]
[Action]
According to the present invention, after the polysilicon is grown, the back surface of the active layer wafer is alkali- etched before the polysilicon layer is ground and polished . Specifically, the active layer wafer is rotated at 10 to 60 rpm while contacting the alkaline etching solution only on the back surface of the active layer wafer to remove the polysilicon that has wrapped around the back surface of the active layer wafer. Since the removal is performed by etching, processing damage is less likely to occur in the active layer wafer than in the conventional removal by polishing. In addition, in the removal by polishing, the flatness of the back surface is impaired in the case of polysilicon that is firmly adhered. However, the etching can avoid the deterioration of the flatness.
In addition, since the polysilicon adhering to the back surface of the active layer wafer is removed by alkali etching, the flatness of the etched surface is increased.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
A method for manufacturing a bonded dielectric isolation wafer according to an embodiment of the present invention will be described below. Here, a method for manufacturing a bonded dielectric isolation wafer described in the prior art section will be described as an example. Accordingly, the same parts are denoted by the same reference numerals.
First, a silicon wafer 10 having a diameter of 4 to 6 inches in which the surface to be the active layer wafer is mirror-finished is prepared and prepared (FIG. 1A). The plane orientation is (100).
Next, the silicon wafer 10 is cleaned. Then, a mask oxide film 11 having a thickness of 1 μm, for example, is formed on the surface of the silicon wafer (FIG. 1B).
Instead of the mask oxide film 11, a nitride film (SiNx) may be grown by CVD.
[0013]
Next, a photoresist film 12 is deposited on the mask oxide film 11 by a known photolithography process. Then, a window having a predetermined pattern is formed in the photoresist film 12 as usual (FIG. 1C).
Subsequently, a window having the same pattern is formed in the oxide film 11 by etching through this window, and a part of the surface of the silicon wafer 10 is exposed. Thereafter, the photoresist film 12 is removed (also in FIG. 1C). Then, the wafer surface is cleaned.
Further, using the oxide film 11 as a mask, the silicon wafer 10 is immersed in an anisotropic etching solution (IPA / KOH / H ₂ O) for a predetermined time. As a result, concave portions (dents) having a predetermined pattern are formed on the surface of the silicon wafer.
That is, anisotropic etching is performed on the wafer surface to form a dielectric separating groove 13 having a V-shaped cross section (also in FIG. 1C).
[0014]
Next, the mask oxide film 11 is removed by cleaning with, for example, dilute HF liquid (FIG. 1D).
Thereafter, if necessary, a dopant is implanted into the silicon, and then a dielectric isolation oxide film 14 having a predetermined thickness is formed on the wafer surface (also the back surface) by an oxidation heat treatment (FIG. 1E). At this time, the dielectric isolation oxide film 14 is also formed on the surface where the dielectric isolation groove 13 is formed. Then, the wafer surface is cleaned.
Subsequently, a seed polysilicon layer 15 is deposited to a predetermined thickness on the surface of the silicon wafer 10, that is, on the dielectric isolation oxide film 14 on the surface side (FIG. 1 (f)). Clean the surface after deposition.
[0015]
Next, the high-temperature polysilicon layer 16 is grown on the surface of the seed polysilicon layer 15 to a thickness of about 150 μm by the high-temperature CVD method at about 1200 to 1300 ° C. (also FIG. 1F).
Thereafter, the outer peripheral portion of the silicon wafer 10 is chamfered using a metal bond grindstone 22 of # 800 (abrasive grain size 15 to 25 μm) (FIG. 1 (g)).
Subsequently, a photoresist film 23 is deposited on the surface and the outer periphery of the high-temperature polysilicon layer 16 by a known photolithography process. Thereafter, the back surface of the silicon wafer 10 is brought into contact with the alkaline etching solution in the etching tank 25 for a predetermined time to remove polysilicon remaining on the back surface of the wafer (FIG. 1 (h)).
[0016]
As the alkaline etching solution, a 10% by weight KOH solution at 80 ° C. is used. During this etching, the silicon wafer 10 is rotated by the motor M at a low speed of 10 to 60 rpm. Since alkali etching is employed, the flatness of the back surface of the silicon wafer 10, specifically, the exposed surface of the dielectric isolation oxide film 14, is higher than that of acid etching in which the etching surface is likely to be formed. This etching is terminated when the dielectric isolation oxide film 14 having an extremely low etching rate is reached.
Also, this etching can be efficiently performed using two types of etching solutions, acid and alkali. That is, first, acid etching is performed at room temperature with a mixed acid of hydrofluoric acid / nitric acid (volume ratio 1: 1 to 1: 5). As a result, most of the polysilicon around the back surface of the outer periphery of the wafer is removed. Thereafter, the remaining polysilicon is removed by the alkaline etching solution.
[0017]
Next, the photoresist film 23 is removed from the high-temperature polysilicon layer 16 by a known method (FIG. 2A).
Subsequently, the back surface of the silicon wafer 10 is sucked and installed on a wafer holding plate of a grinding apparatus (not shown), and the wafer surface is ground. Next, the wafer 10 is peeled off from the wafer holding plate, and then the wafer back surface is adhered to a wafer holding plate of a polishing apparatus (not shown) and then polished. In this manner, the high-temperature polysilicon layer 16 is ground and polished to a thickness of about 10 to 80 μm. Thereafter, the silicon wafer 10 is peeled off from the wafer holding plate of the polishing apparatus and cleaned (FIG. 2B).
[0018]
As described above, after the growth of the high-temperature polysilicon layer 16, the polysilicon protrusions 16a on the back surface of the silicon wafer 10 are removed by etching. It is possible to increase the flatness of the back surface of the silicon wafer 10 adhered to the substrate. As a result, it is possible to eliminate the occurrence of dimples caused by the transfer of polysilicon on the wafer back surface to the wafer surface during grinding / polishing of the wafer surface. As a result, it is possible to eliminate voids at the wafer bonding interface caused by the generation of dimples during the wafer bonding heat treatment described later.
[0019]
In addition, since the removal is performed by etching, processing damage is less likely to occur in the silicon wafer 10 compared to the removal by conventional polishing. Further, in order to remove the strongly adhered polysilicon protrusion 16a, the flatness of the surrounding surface can be maintained. Further, the heat generated during polishing often depends on a part of the silicon wafer 10. Even in such a case, the produced bonded dielectric isolation wafer is a defective product. According to the etching, the silicon wafer 10 is not partially heated.
Thereafter, a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is grown on the wafer surface by a low-temperature CVD method at 550 to 700 ° C. Then, the surface of the low-temperature polysilicon layer 17 is polished for the purpose of flattening the bonded surface (also in FIG. 2B).
[0020]
On the other hand, a mirror-finished silicon wafer 20 having a diameter of 4 to 6 inches coated with a silicon oxide film 21 to be a support substrate wafer is prepared (FIG. 2C).
Next, the mirror surfaces are opposed to each other and positioning of the silicon wafer 20 and the silicon wafer 10 for the active layer wafer is positioned (FIG. 2D).
This positioning is performed by a positioning device using infrared absorption spectroscopy. Subsequently, after the wafers 10 and 20 are moved and bonded together, a normal bonding heat treatment is performed to increase the bonding strength (also in FIG. 2D).
Subsequently, as shown in FIG. 2E, the outer peripheral portion of the bonded wafer on the active layer wafer side is chamfered.
Then, the surface of the bonded wafer on the active layer wafer side is ground and polished (FIG. 2F). The amount of grinding of the active layer wafer is such that a part of the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 on the surface of the high-temperature polysilicon layer 16 is used. Until it appears. The silicon oxide film 21 is removed at an appropriate time by HF cleaning. In this way, a bonded dielectric isolation wafer is produced.
[0021]
【The invention's effect】
According to the present invention, while rotating the sex layer wafer at 10 to 60 rpm, the alkaline etchant is brought into contact only with the back surface of the active layer wafer, and the polysilicon adhering to the back surface of the wafer is removed by alkali etching. Therefore, processing damage is less likely to occur in the active layer wafer as compared with the conventional removal by polishing. In addition, since the firmly adhered polysilicon is removed, the surrounding surface does not lose flatness.
In particular, since the polysilicon adhering to the back surface of the active layer wafer is removed by alkali etching, the flatness of the etched surface is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a method for manufacturing a bonded dielectric isolation wafer according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view continued from FIG. 1 for explaining the method for manufacturing the bonded dielectric isolation wafer according to one embodiment of the present invention;
FIG. 3 is a cross-sectional view for explaining a manufacturing process of a conventional bonded dielectric isolation wafer.
4 is a cross-sectional view continued from FIG. 3 for illustrating a manufacturing process of a conventional bonded dielectric isolation wafer.
[Explanation of symbols]
10 Silicon wafer (wafer for active layer),
10A dielectric isolation silicon island,
13 Dielectric separation groove,
14 Dielectric isolation oxide film,
16 polysilicon layer,
16a polysilicon protrusion (polysilicon),
20 Silicon wafer (wafer for supporting substrate).

Claims (1)

A polysilicon layer is grown on the surface of the active layer wafer through a dielectric isolation oxide film,
After grinding and polishing the surface of the polysilicon layer, the polishing surface is used as a bonding surface, and the active layer wafer is bonded to the surface of the support substrate wafer.
Chamfer the outer periphery of this bonded wafer,
Thereafter, the active layer wafer is ground and polished from the back surface side, and a plurality of dielectric isolation silicon islands separated by the dielectric isolation oxide film appear on the polished surface.
Before grinding and polishing the polysilicon layer, the polysilicon deposited on the back surface of the active layer wafer is contacted with an alkaline etching solution only on the back surface of the active layer wafer, and the active layer wafer is 10 A method for producing a bonded dielectric isolation wafer in which alkali etching is performed by rotating at ~ 60 rpm .

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