JP3263875B2 - Method for manufacturing surface-mounted electronic component and surface-mounted electronic component - Google Patents
Method for manufacturing surface-mounted electronic component and surface-mounted electronic componentInfo
- Publication number
- JP3263875B2 JP3263875B2 JP20976793A JP20976793A JP3263875B2 JP 3263875 B2 JP3263875 B2 JP 3263875B2 JP 20976793 A JP20976793 A JP 20976793A JP 20976793 A JP20976793 A JP 20976793A JP 3263875 B2 JP3263875 B2 JP 3263875B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- solder
- mounted electronic
- flip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、例えば、フリップチ
ップ型半導体集積回路装置（以下、単に「フリップチッ
プ型ＩＣ」と記す）、或いは小型スイッチや狭ピッチの
コネクターなどの表面実装型電子部品の電極に形成され
た半田バンプの構造及びその製造方法並びに半田付け方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type semiconductor integrated circuit device (hereinafter simply referred to as "flip-chip type IC") or a surface mount type electronic component such as a small switch or a narrow pitch connector. The present invention relates to a structure of a solder bump formed on an electrode, a manufacturing method thereof, and a soldering method.
【０００２】[0002]
【従来の技術】従来技術の表面実装型電子部品、例え
ば、フリップチップ型ＩＣの電極の構造及びそのような
フリップチップ型ＩＣを電気回路配線基板（以下、単に
「基板」と記す）に表面実装した場合の様子を図７を用
いて説明する。図７は従来技術のフリップチップ型ＩＣ
の電極の構造及びそのフリップチップ型ＩＣを基板に表
面実装した場合の状態を示した側面図である。2. Description of the Related Art Prior art surface-mounted electronic components, for example, the structure of electrodes of a flip-chip type IC and the surface mounting of such a flip-chip type IC on an electric circuit wiring board (hereinafter simply referred to as "substrate"). The situation in which this is done will be described with reference to FIG. FIG. 7 shows a conventional flip-chip type IC.
FIG. 2 is a side view showing the structure of the electrode and its state when the flip-chip type IC is surface-mounted on a substrate.
【０００３】従来技術のこの種基板１は、ガラスエポキ
シ樹脂などの有機材やアルミナなどのセラミック材な
ど、電気絶縁材で形成されており、その表面にやや突出
して複数の導電性配線部とそれらの端部に形成された導
電性ランド２とで電気回路が構成されている。This type of substrate 1 of the prior art is formed of an electrically insulating material such as an organic material such as glass epoxy resin or a ceramic material such as alumina. And an electrically conductive land 2 formed at the end of the electric circuit.
【０００４】[0004]
【発明が解決しようとする課題】所が、最近、フリップ
チップ型ＩＣなどの表面実装型電子部品は高密度集積
化、小型化されるようになり、それにつれ電極が多くな
り、そしてそれらの電極が狭ピッチ化されるようになっ
ている。また、このような表面実装型電子部品を実装す
る基板の前記導電性ランドも狭ピッチ化されるようにな
った。However, recently, surface-mounted electronic components such as flip-chip type ICs have been highly integrated and miniaturized, and the number of electrodes has increased accordingly. Are narrowed. In addition, the pitch of the conductive lands of the substrate on which such a surface-mounted electronic component is mounted has also been reduced.
【０００５】狭ピッチ化されたフリップチップ型ＩＣ１
０を基板１に実装する場合は、導電性ランド２に被着し
た半田３の表面にフラックスを塗布し、その表面にフリ
ップチップ型ＩＣ１０を搭載するようにしているが、フ
ラックスの流動により、図７に示したように、そのフリ
ップチップ型ＩＣ１０の半田バンプ１１が導電性ランド
２間にずり落ちてしまい、実装不良を起こすことがしば
しば見受けられる。これらの原因は、前記フリップチッ
プ型ＩＣ１０の半田バンプ１１が凸状の構造をしてお
り、また前記導電性ランド２上の半田３も凸状の構造に
なっており、この凸状の半田３の上に前記凸状の半田バ
ンプ１１を載せ、接続させようとすることに起因するも
のであった。この発明は、このような実装不良を解決す
ることを課題とするものである。[0005] Flip chip type IC 1 with narrow pitch
In the case where 0 is mounted on the substrate 1, a flux is applied to the surface of the solder 3 attached to the conductive land 2, and the flip-chip type IC 10 is mounted on the surface. As shown in FIG. 7, it is often observed that the solder bumps 11 of the flip-chip type IC 10 slip down between the conductive lands 2 to cause a mounting failure. The cause is that the solder bump 11 of the flip-chip type IC 10 has a convex structure, and the solder 3 on the conductive land 2 also has a convex structure. This is caused by placing the convex solder bumps 11 on the top and trying to connect them. An object of the present invention is to solve such a mounting defect.
【０００６】[0006]
【課題を解決するための手段】本発明では、表面実装型
電子部品の電極の中央部表面を絶縁樹脂で被覆した後、
この電極を半田にディップし、絶縁樹脂で被覆されてい
ない電極の表面上に半田を付着させることにより半田バ
ンプを形成して表面実装型電子部品を製造する方法を採
った。 According to the present invention, a surface-mount type is provided.
After coating the surface of the center part of the electrode of the electronic component with insulating resin,
This electrode is dipped in solder and covered with insulating resin.
Solder is deposited on the surface of the electrode without solder
A method of manufacturing a surface-mounted electronic component by forming a pump.
Was.
【０００７】また、このような表面実装型電子部品の半
田バンプは、表面実装型電子部品の電極表面上に半田バ
ンプを形成し、その断面形状を凹状とし、中央部に絶縁
樹脂が充填されている構造とした。以上のような表面実
装型電子部品の製造方法及び表面実装型電子部品におけ
る半田バンプの構造を採ることにより、前記課題を解決
した。 Further, a half of such a surface mount type electronic component is used.
Solder bumps are placed on the surface of the electrodes of surface-mounted electronic components.
The pump is formed, the cross section is concave, and the center is insulated.
The structure was filled with resin. The method for manufacturing the surface-mounted electronic component and the surface-mounted electronic component as described above
Solving the above problems by adopting a solder bump structure
did.
【０００８】[0008]
【作用】従って、この表面実装型電子部品の凹状の半田
バンプが基板の凸状の導電性ランドに座り易くなるの
で、この表面実装型電子部品の半田バンプが基板の導電
性ランド間にずり落ちることがない。Therefore, the concave solder bumps of the surface mount electronic component can easily sit on the convex conductive lands of the substrate, and the solder bumps of the surface mount electronic component slip between the conductive lands of the substrate. There is no.
【０００９】[0009]
【実施例】先ず、この発明の表面実装型電子部品の構造
及びその製造方法並びに半田付け方法の実施例を図１乃
至図６を用いて説明する。図１はこの発明の表面実装型
電子部品の半田バンプの構造の実施例を示していて、同
図Ａはその平面図、同図Ｂは同図ＡのＡーＡ線上の断面
側面図であり、図２はこの発明の表面実装型電子部品の
半田バンプのその他の実施例の構造を示した平面図であ
り、図３は図１に示したこの発明の表面実装型電子部品
の半田バンプの製造方法を説明するための工程図あり、
図４はこの発明の表面実装型電子部品を基板に表面実装
する半田付け方法を示していて、同図Ａは基板にこの発
明の表面実装型電子部品を載置した状態を示した断面側
面図であり、同図Ｂは表面実装型電子部品が基板に半田
付けされた状態を示した断面側面図あり、図５はこの発
明の表面実装型スイッチを示していて、同図Ａはその斜
視図、同図Ｂはその導電性端子の構造の平面図、同図Ｃ
は同図ＢのＡーＡ線上の断面側面図であり、そして図６
は図５に示した表面実装型スイッチを基板に表面実装す
る半田付け方法を示していて、同図Ａは基板にこの発明
の表面実装型スイッチを載置する状態を示した斜視図で
あり、同図Ｂは表面実装型スイッチが基板に半田付けさ
れた状態を示した断面側面図ある。なお、従来技術の表
面実装型電子部品などと同一の部分には同一の符号を付
して、それらの部分の説明を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of a structure of a surface mount type electronic component, a method of manufacturing the same, and a method of soldering according to the present invention will be described with reference to FIGS. FIG. 1 shows an embodiment of the structure of a solder bump of a surface-mounted electronic component according to the present invention. FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional side view taken along line AA of FIG. FIG. 2 is a plan view showing the structure of another embodiment of the solder bump of the surface-mounted electronic component of the present invention, and FIG. 3 is a plan view of the solder bump of the surface-mounted electronic component of the present invention shown in FIG. There is a process diagram for explaining the manufacturing method,
FIG. 4 shows a soldering method for surface-mounting the surface-mounted electronic component of the present invention on a substrate, and FIG. 4A is a cross-sectional side view showing a state where the surface-mounted electronic component of the present invention is mounted on the substrate. FIG. B is a cross-sectional side view showing a state in which the surface-mounted electronic component is soldered to the substrate. FIG. 5 shows a surface-mounted switch of the present invention, and FIG. B is a plan view of the structure of the conductive terminal, and FIG.
6 is a sectional side view taken along the line AA in FIG.
Shows a soldering method for surface mounting the surface mount switch shown in FIG. 5 on a substrate, and FIG. FIG. 2B is a cross-sectional side view showing a state where the surface mount switch is soldered to the substrate. The same parts as those of the surface-mounted electronic component of the related art are denoted by the same reference numerals, and description of those parts will be omitted.
【００１０】図１に示した実施例のこの発明の表面実装
型電子部品の半田バンプ２１は、その表面実装型電子部
品の電極パッドＴの表面に、その中央部２１Ａが凹状に
なるよう半田を環状に盛り上げた構造に形成されてい
る。In the embodiment shown in FIG. 1, the solder bump 21 of the surface-mounted electronic component of the present invention is formed by applying solder to the surface of the electrode pad T of the surface-mounted electronic component so that the central portion 21A is concave. It is formed in a ring-shaped structure.
【００１１】図２に、図１に示した実施例の半田バンプ
２１の構造と同一、またはほぼ同一の効果が得られる半
田バンプの構造を挙げた。同図Ａの半田バンプ２２は電
極パッドＴの表面の四隅で、半田２２ａを半球状に盛り
上げ、それら４個の半田２２ａの中央部２２Ａで窪みを
形成した実施例である。同図Ｂの半田バンプ２３は電極
パッドＴの表面の四隅で、半田２３ａを角錐状に盛り上
げ、それら４個の半田２３ａの中央部２３Ａで窪みを形
成した実施例である。 同図Ｃの半田バンプ２４は電極
パッドＴの表面の四辺に沿って、半田２４ａを盛り上
げ、それら四辺の半田２４ａの中央部２４Ａで窪みを形
成した実施例である。そして、同図Ｄの半田バンプ２５
は電極パッドＴの表面の二辺に沿って平行に、半田２５
ａを盛り上げ、それら二辺の半田２５ａが相対する中間
部２５Ａで窪みを形成した実施例である。FIG. 2 shows a structure of a solder bump which can achieve the same or substantially the same effect as the structure of the solder bump 21 of the embodiment shown in FIG. The solder bumps 22 in FIG. 5A are examples in which the solder 22a is raised in a hemispherical shape at the four corners of the surface of the electrode pad T, and a depression is formed at the central portion 22A of the four solders 22a. The solder bumps 23 of FIG. 6B are examples in which the solder 23a is raised in a pyramid shape at four corners on the surface of the electrode pad T, and a recess is formed at the central portion 23A of the four solders 23a. The solder bump 24 shown in FIG. 9C is an embodiment in which the solder 24a is raised along four sides on the surface of the electrode pad T, and a recess is formed at the central portion 24A of the solder 24a on the four sides. Then, the solder bump 25 of FIG.
Are parallel to two sides of the surface of the electrode pad T,
This is an embodiment in which a is raised, and a recess is formed in an intermediate portion 25A where the two sides of the solder 25a face each other.
【００１２】次に、表面実装型電子部品としてフリップ
チップ型ＩＣを実施例として挙げ、その電極パッドに、
図１に示した環状の半田バンプ２１を形成する方法を図
３を用いて説明する。先ず、同図Ａの工程に示したよう
に、フリップチップ型ＩＣ１０の電極パッドＴは、例え
ば、一辺の長さＬａが１１０μｍの正方形のアルミで形
成されており、その電極パッドＴの表面を一辺１００μ
ｍの正方形の開口部を残すようにしてＳｉＯ2 の絶縁膜
３０で覆う。Next, a flip-chip type IC will be described as an example of a surface-mount type electronic component.
A method for forming the annular solder bump 21 shown in FIG. 1 will be described with reference to FIG. First, as shown in the step of FIG. A, the electrode pad T of the flip-chip type IC 10 is formed of, for example, square aluminum having a side length La of 110 μm, and the surface of the electrode pad T is formed on one side. 100μ
It is covered with an insulating film 30 of SiO 2 so as to leave a square opening of m.
【００１３】次に、同図Ｂに示したように、感光性ポリ
イミドを用いて電極パッドＴ上を外径９０μｍφ、内径
３０μｍφの二重円の絶縁樹脂膜３１をパターニングす
る。次に、同図Ｃに示したように、スパッタ装置を用い
て、第１層Ｃｒ、第２層Ｎｉの薄膜３２をフリップチッ
プ型ＩＣ１０全体に成膜する。次に、同図Ｄに示したよ
うに、感光性レジストを用いたフォトリソグラフィー法
を用いて、フリップチップ型ＩＣ１０の電極パッドＴ付
近にＣｒ、Ｎｉの２層膜３２Ａをパターニングする。こ
の場合、電極パッドＴの中心にある絶縁樹脂膜３１の大
部分が露出するようにパターニングする。Next, as shown in FIG. 1B, a double circle insulating resin film 31 having an outer diameter of 90 μmφ and an inner diameter of 30 μmφ is patterned on the electrode pad T using photosensitive polyimide. Next, as shown in FIG. 3C, a thin film 32 of a first layer Cr and a second layer Ni is formed on the entire flip-chip type IC 10 by using a sputtering apparatus. Next, as shown in FIG. D, a two-layer film 32A of Cr and Ni is patterned near the electrode pad T of the flip-chip type IC 10 by using a photolithography method using a photosensitive resist. In this case, patterning is performed so that most of the insulating resin film 31 at the center of the electrode pad T is exposed.
【００１４】次に、同図Ｅに示したように、図Ｄの工程
でパターニングしたＣｒ、Ｎｉ膜３２Ａの大部分を露出
させるように厚膜感光性レジスト３３を用いたフォトリ
ソグラフィー法を用いてパターニングする。この場合、
Ｃｒ、Ｎｉ膜３２Ａが成膜されていない部分は、全て厚
膜感光レジスト３３で覆われている。この工程に続い
て、前記厚膜感光レジスト３３の全表面から真空蒸着装
置を用いて、同図Ｆに示したように、半田３４を成膜す
る。Next, as shown in FIG. 3E, a photolithography method using a thick-film photosensitive resist 33 is used to expose most of the Cr and Ni films 32A patterned in the step of FIG. Perform patterning. in this case,
All portions where the Cr and Ni films 32A are not formed are covered with the thick-film photosensitive resist 33. Subsequent to this step, a solder 34 is formed from the entire surface of the thick-film photosensitive resist 33 using a vacuum evaporation apparatus as shown in FIG.
【００１５】次に、同図Ｇに示したように、図Ｅの工程
で形成した厚膜感光レジスト３３を剥離液を用いて除去
する。この時、厚膜感光レジスト３３上に堆積した半田
３４も同時に除去される。そして、次の最終工程でオー
ブンを使用し、図Ｇの工程で作られた部品を加熱し、半
田３４を溶融する。Next, as shown in FIG. 1G, the thick-film photosensitive resist 33 formed in the step of FIG. 1E is removed using a stripping solution. At this time, the solder 34 deposited on the thick photosensitive resist 33 is also removed at the same time. Then, an oven is used in the next final step to heat the components made in the step of FIG.
【００１６】この場合、図Ｇの工程で形成された半田３
４の膜厚が少なければ、図Ｈに示したように、フリップ
チップ型ＩＣ１０の電極パッドＴの中心に設けられた絶
縁樹脂膜３１上に半田３４が堆積せず、半田バンプ２１
が凹状の形をしたこの発明のフリップチップ型ＩＣ４０
が得られ、また、図Ｇで形成された半田３４の膜厚が厚
ければ、図Ｉに示したように、半田バンプ２１Ａの表面
がほぼ平らな台状のこの発明のフリップチップ型ＩＣ４
０Ａを得ることができる。以上のような工程を経て、図
１に示したこの発明の半田バンプ２１をフリップチップ
型ＩＣ１０の各電極パッドＴ上に形成することができ
る。In this case, the solder 3 formed in the process of FIG.
4, the solder 34 is not deposited on the insulating resin film 31 provided at the center of the electrode pad T of the flip-chip type IC 10 as shown in FIG.
Of the present invention having a concave shape.
If the thickness of the solder 34 formed in FIG. G is large, as shown in FIG. I, the flip-chip type IC 4 according to the present invention has a trapezoidal shape in which the surface of the solder bump 21A is substantially flat.
OA can be obtained. Through the steps described above, the solder bump 21 of the present invention shown in FIG. 1 can be formed on each electrode pad T of the flip-chip type IC 10.
【００１７】次に、図４を用いて、この発明のフリップ
チップ型ＩＣ４０の基板１への表面実装方法を説明す
る。先ず、基板１に形成された導電性ランド２上に半田
３を被着し、その半田３の表面にフラックスを塗布した
後、その表面にフリップチップボンダー用いて、この発
明のフリップチップ型ＩＣ４０を載置する（図４Ａ）。Next, a method of surface mounting the flip-chip type IC 40 of the present invention on the substrate 1 will be described with reference to FIG. First, the solder 3 is applied on the conductive land 2 formed on the substrate 1, and a flux is applied to the surface of the solder 3, and then the flip chip type IC 40 of the present invention is mounted on the surface by using a flip chip bonder. Place (FIG. 4A).
【００１８】この場合、図３Ｈのフリップチップ型ＩＣ
４０を導電性ランド２に載置した時は、その凹状の半田
バンプ２１が導電性ランド２上の凸状の半田３に座るよ
うに配置、合体することにより、フリップチップ型ＩＣ
４０が導電性ランド２からずれるのを防ぐことができる
（図４Ａ）。また、図Ｋのようなフリップチップ型ＩＣ
４０Ａを導電性ランド２の半田３上に載置した時は、そ
の台状の半田バンプ２１Ａが導電性ランド２上の凸状の
半田３に座るように配置、合体することにより、前記半
田バンプ２１程のずれ防止効果はないが、従来の凸状電
極と凸状の導電性ランドの接続と比較すれば遙にずれを
軽減するこができる。In this case, the flip-chip type IC shown in FIG.
When the semiconductor chip 40 is placed on the conductive land 2, the concave solder bumps 21 are arranged and united so as to sit on the convex solder 3 on the conductive land 2, thereby forming a flip-chip type IC.
40 can be prevented from deviating from the conductive land 2 (FIG. 4A). In addition, a flip-chip type IC as shown in FIG.
When the solder bumps 40A are mounted on the solder 3 of the conductive land 2, the trapezoidal solder bumps 21A are arranged so as to sit on the convex solder 3 on the conductive land 2 and are united to form the solder bumps. Although the effect of preventing the displacement is not as great as 21, the displacement can be far reduced as compared with the conventional connection between the convex electrode and the convex conductive land.
【００１９】最後に、オーブンを用い、この合体状態で
両者を加熱処理すると、図４Ｂに示したように、前記電
極パッドＴと導電性ランド２とを半田接合させることが
でき、フリップチップ型ＩＣ４０、４０Ａを基板１に半
田付けできる。Finally, when the both are heat-treated in an integrated state using an oven, the electrode pads T and the conductive lands 2 can be solder-joined as shown in FIG. , 40A can be soldered to the substrate 1.
【００２０】次に、表面実装型電子部品の他の電子部品
として、表面実装型スイッチ（以下、単に「スイッチ」
と記す）を採り挙げ、図５及び図６を用いて、第２の実
施例を説明する。Next, as another electronic component of the surface mount type electronic component, a surface mount type switch (hereinafter simply referred to as "switch") is used.
The second embodiment will be described with reference to FIGS. 5 and 6.
【００２１】図５において、符号５０はこの発明のスイ
ッチを指しており、このスイッチ５０は２個の導電性端
子５１を備えている。これらの導電性端子５１には、同
図Ｂ、Ｃに示したように、中央部が窪んだ凹状の半田バ
ンプ５３が形成されている。この半田バンプ５３は電極
パッドＴの中央部にエポキシ樹脂やシリコーン樹脂など
の樹脂膜５２を薄く塗布し、その後、この電極パッドＴ
を半田にディップし、付着させることにより形成するこ
とができる。In FIG. 5, reference numeral 50 designates a switch of the present invention, and the switch 50 has two conductive terminals 51. As shown in FIGS. B and C, the conductive terminals 51 are formed with concave solder bumps 53 having a concave central portion. The solder bump 53 is formed by applying a thin resin film 52 such as an epoxy resin or a silicone resin to the center of the electrode pad T.
Can be formed by dipping and attaching to a solder.
【００２２】このような構造のスイッチ５０は、前記の
第１の実施例のフリップチップ型ＩＣ４０と同様に、そ
の半田バンプ５３に凹部が形成されているので、基板１
に形成された導電性ランド２の半田３の凸部に座り良く
なり、ずれ難くなる。従って、この状態で仮止めされた
状態になり、この状態で基板１をリフローすることによ
りスイッチ５０の導電性端子５１と基板１に形成された
半田の導電性ランド２とが半田付けされ、接続すること
ができる（図６Ｂ）。なお、符号５４はスイッチ５０の
摘みを指す。The switch 50 having such a structure has a concave portion formed in the solder bump 53 similarly to the flip-chip type IC 40 of the first embodiment.
Therefore, the conductive land 2 formed on the conductive land 2 can be easily seated on the protruding portion of the solder 3 and is hardly displaced. Therefore, in this state, the substrate is temporarily fixed, and in this state, by reflowing the substrate 1, the conductive terminal 51 of the switch 50 and the conductive land 2 of the solder formed on the substrate 1 are soldered and connected. (FIG. 6B). Reference numeral 54 indicates a knob of the switch 50.
【００２３】[0023]
【発明の効果】以上説明したように、この発明の表面実
装型電子部品を用いると、基板上に電子部品を表面実装
し、電子部品の電極と基板の導電性ランドを半田接続す
る作業を行なっても、半田バンプと導電性ランドとがず
れることなく接続することができ、半田付け不良を起こ
さない、信頼性の高い半田付けを行うことができる。As described above, when the surface-mounted electronic component of the present invention is used, the electronic component is surface-mounted on the substrate, and the work of soldering the electrodes of the electronic component to the conductive lands of the substrate is performed. Even so, the solder bumps and the conductive lands can be connected without being shifted, and highly reliable soldering that does not cause soldering failure can be performed.
【図１】 この発明の表面実装型電子部品の半田バンプ
の構造の実施例を示していて、同図Ａはその平面図、同
図Ｂは同図ＡのＡーＡ線上の断面側面図である。FIG. 1 shows an embodiment of the structure of a solder bump of a surface-mounted electronic component of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional side view taken along line AA of FIG. is there.
【図２】 この発明の表面実装型電子部品の半田バンプ
のその他の実施例の構造を示した平面図である。FIG. 2 is a plan view showing the structure of another embodiment of the solder bump of the surface mount electronic component of the present invention.
【図３】 図１に示したこの発明の表面実装型電子部品
の半田バンプの製造方法を説明するための工程図であ
る。FIG. 3 is a process chart for explaining a method for manufacturing a solder bump of the surface-mounted electronic component of the present invention shown in FIG. 1;
【図４】 この発明の表面実装型電子部品を基板に表面
実装する半田付け方法を示していて、同図Ａは基板にこ
の発明の表面実装型電子部品を載置した状態を示した断
面側面図であり、同図Ｂは表面実装型電子部品が基板に
半田付けされた状態を示した断面側面図である。FIG. 4 shows a soldering method for surface-mounting the surface-mounted electronic component of the present invention on a substrate, and FIG. 4A is a sectional side view showing a state where the surface-mounted electronic component of the present invention is mounted on the substrate. FIG. B is a cross-sectional side view showing a state where the surface-mounted electronic component is soldered to a substrate.
【図５】 この発明の表面実装型スイッチを示してい
て、同図Ａはその斜視図、同図Ｂはその導電性端子の構
造の平面図、同図Ｃは同図ＢのＡーＡ線上の断面側面図
である。5A and 5B show a surface mount type switch of the present invention, FIG. 5A is a perspective view, FIG. 5B is a plan view of the structure of the conductive terminal, and FIG. FIG.
【図６】 図５に示した表面実装型スイッチを基板に表
面実装する半田付け方法を示していて、同図Ａは基板に
この発明の表面実装型スイッチを載置する状態を示した
斜視図であり、同図Ｂは表面実装型スイッチが基板に半
田付けされた状態を示した断面側面図である。6 shows a soldering method for surface mounting the surface mount switch shown in FIG. 5 on a substrate, and FIG. 6A is a perspective view showing a state where the surface mount switch of the present invention is mounted on the substrate. FIG. B is a cross-sectional side view showing a state where the surface mount switch is soldered to the substrate.
【図７】 従来技術のフリップチップ型ＩＣの電極の構
造及びそのフリップチップ型ＩＣを基板に表面実装した
場合の状態を示した側面図である。FIG. 7 is a side view showing an electrode structure of a conventional flip-chip type IC and a state where the flip-chip type IC is surface-mounted on a substrate.
Ｔ 電極パッド １ 電気回路配線基板（基板） ２ 導電性ランド ３ 半田 ２１ 断面凹状の半田バンプ ２１Ａ 断面台形状の半田バンプ ３１ 絶縁樹脂膜 ３４ 半田 ４０ 断面凹状の半田バンプを備えたフリップチップ
型ＩＣ ４０Ａ 断面台形状の半田バンプを備えたフリップチ
ップ型ＩＣ ５０ 表面実装型スイッチ ５１ 導電性端子 ５２ 樹脂膜 ５３ 断面凹状の半田バンプT Electrode pad 1 Electric circuit wiring board (substrate) 2 Conductive land 3 Solder 21 Solder bump 21A with concave cross section 21A Solder bump with trapezoidal cross section 31 Insulating resin film 34 Solder 40 Flip chip type IC 40A having solder bump with concave cross section Flip chip type IC having solder bumps with trapezoidal cross section 50 Surface mount type switch 51 Conductive terminal 52 Resin film 53 Solder bump with concave cross section
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−225652（ＪＰ，Ａ) 特開 平４−340240（ＪＰ，Ａ) 特開 昭62−279645（ＪＰ，Ａ) 特開 昭64−8647（ＪＰ，Ａ) 特開 平７−58112（ＪＰ，Ａ) 特開 平５−21523（ＪＰ，Ａ) 特開 平５−235061（ＪＰ，Ａ) 特開 平６−268016（ＪＰ，Ａ) 特開 平６−232205（ＪＰ，Ａ) 実開 昭60−167363（ＪＰ，Ｕ) 実開 平１−67747（ＪＰ，Ｕ) 実開 昭62−172155（ＪＰ，Ｕ) 実開 平３−56136（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-225652 (JP, A) JP-A-4-340240 (JP, A) JP-A-62-279645 (JP, A) JP-A 64-64 8647 (JP, A) JP-A-7-58112 (JP, A) JP-A-5-21523 (JP, A) JP-A-5-235061 (JP, A) JP-A-6-268016 (JP, A) JP-A-6-232205 (JP, A) JP-A-60-167363 (JP, U) JP-A-1-67747 (JP, U) JP-A-62-172155 (JP, U) JP-A-3-56136 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/60
Claims (2)
を絶縁樹脂で被覆した後、前記電極を半田にディップ
し、前記絶縁樹脂で被覆されていない電極の表面上に半
田を付着させて半田バンプを形成することを特徴とする
表面実装型電子部品の製造方法。 [Claim 1] After a central part surface of the surface mount electronic device electrodes was coated with an insulating resin, and dip the electrodes to the solder, said deposited solder on the surface of the electrode which is not covered with an insulating resin A method for manufacturing a surface mount electronic component, comprising forming a solder bump.
成された断面凹状の半田バンプの中央部に絶縁樹脂が充
填されていることを特徴とする表面実装型電子部品。 2. A surface-mounted electronic component, characterized in that a central portion of a solder bump having a concave cross section formed on the surface of an electrode of the surface-mounted electronic component is filled with an insulating resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20976793A JP3263875B2 (en) | 1993-08-24 | 1993-08-24 | Method for manufacturing surface-mounted electronic component and surface-mounted electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20976793A JP3263875B2 (en) | 1993-08-24 | 1993-08-24 | Method for manufacturing surface-mounted electronic component and surface-mounted electronic component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0766207A JPH0766207A (en) | 1995-03-10 |
| JP3263875B2 true JP3263875B2 (en) | 2002-03-11 |
Family
ID=16578284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20976793A Expired - Fee Related JP3263875B2 (en) | 1993-08-24 | 1993-08-24 | Method for manufacturing surface-mounted electronic component and surface-mounted electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3263875B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388203B1 (en) | 1995-04-04 | 2002-05-14 | Unitive International Limited | Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby |
| JP3549208B2 (en) | 1995-04-05 | 2004-08-04 | ユニティヴ・インターナショナル・リミテッド | Integrated redistribution routing conductors, solder vipes and methods of forming structures formed thereby |
| EP0899787A3 (en) * | 1997-07-25 | 2001-05-16 | Mcnc | Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby |
| JP3700563B2 (en) | 2000-09-04 | 2005-09-28 | セイコーエプソン株式会社 | Bump forming method and semiconductor device manufacturing method |
| JP4882718B2 (en) * | 2006-12-14 | 2012-02-22 | 富士通株式会社 | Connection structure and method for manufacturing the same, and semiconductor device and method for manufacturing the same |
| CN111128913B (en) * | 2019-12-24 | 2022-02-11 | 中国航空工业集团公司北京长城航空测控技术研究所 | Flip-chip welding packaging structure and method thereof |
-
1993
- 1993-08-24 JP JP20976793A patent/JP3263875B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766207A (en) | 1995-03-10 |
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