JP3073459B2 - Multiport type programmable ATM adapter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-port programmable ATM adapter having a programmable device mounted thereon and capable of connecting a plurality of input / output ports to an ATM (asynchronous transfer mode) network.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional programmable ATM adapter. In a conventional programmable ATM adapter, optical signal data received via an optical fiber (101) is converted into an electric signal by an O / E converter (optical-electrical converter) (102), and the SDH / ATM processing unit ( 103) (Synchronous digital hierarchy / ATM processing unit) identifies the ATM cell, extracts the cell data, and temporarily stores it in the cell buffer (104). Cell data output from the cell buffer (104) is input to a programmable device (105) such as an FPGA (field programmable gate array) or the like, and is programmed according to a circuit preprogrammed in the programmable devices (105) and (106). It is processed. The processed cell data is output to the SDH / ATM processing unit (103) and is arranged in the SDH payload, and the O / E conversion unit (102)
Is converted into an optical signal and transmitted to the optical fiber (101).

The circuits programmed in the programmable devices (105) and (106) are set and set by the following two methods.
Be changed. In a first method, program circuit data is stored in a flash memory (108) connected to a program bus (107), and the CPU (109) (central processing unit)
The data is read from the flash memory (108) and programmed into the programmable devices (105) and (106). The second method is an I / O port (111) connected to the CPU (109) via a data bus (110).
Host computer (20
1) Receives program data from
This is to program the devices (105) and (106). The choice between these two methods depends on the host computer (201)
When the power of the programmable ATM adapter is turned on when there is no host computer, the program is programmed from the flash memory (108). In the example shown in FIG.
ROM (112) for bus (110) in addition to the configuration described above
(Read only memory) and RAM (113) (random access memory).

[0004]

[Problems to be solved by the invention]

(1) Since a programmable device is more expensive than other components, if it is fully mounted on the motherboard of the programmable ATM adapter from the beginning, the device cost will increase even if it is not used. In order to avoid this, if a plurality of types of devices are manufactured by changing the number of programmable devices, there is much waste and as a result, the cost increases. As described above, in the prior art, a necessary number of programmable
The device could not be mounted.

(2) It is not possible to increase the required number of input / output ports or mount input / output ports having the required interface functions according to the functions realized by the programmable ATM adapter. .

The present invention has been made under such a background, and easily changes the number of programmable devices mounted on a programmable ATM adapter, the number of input / output ports for an ATM network, or the function of input / output ports. It is an object of the present invention to provide a multi-port type programmable ATM adapter capable of performing such operations.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for receiving an optical signal and converting it into an electric signal, and conversely, converting an electric signal into an optical signal.
And an electric signal received through the / E converter and the O / E converter is recognized as an SDH signal, and an ATM cell is taken out of the signal. Conversely, the ATM cell is put into an SDH payload and transmitted as an SDH signal. SDH to do
/ ATM processing unit, a cell buffer for temporarily storing cells taken out by the SDH / ATM processing unit, and a cell output from the cell buffer and data comprising the cell, which are processed according to a pre-programmed circuit. A programmable ATM adapter having a programmable device for outputting processed cells to the SDH / ATM processing unit, and a dual port memory for temporarily storing cells and other data between the programmable device and the programmable device. A first daughter board equipped with an O / E conversion unit, an SDH / ATM processing unit, a programmable device, and a dual port memory; a second daughter board equipped with a programmable device;
At least one of the motherboards with devices
The first and second daughter boards are connected to each other by wires for supplying data signals, clock signals, power supply, etc., and one or a plurality of daughter boards are attached and detached. It is characterized by having a connector to be housed on the motherboard in a possible state.

In short, the present invention provides (1) a second daughter board on which a programmable device is mounted by means of a connector on which the programmable device is mounted on a daughter board and wiring for supplying a data signal, a clock signal, and power supply are connected. Hereinafter, a programmable device daughter board) and the motherboard are detachably housed in the motherboard. Furthermore, when the daughter board is mounted on the motherboard, the setting change to a predetermined circuit connection can be detected automatically and automatically or manually, thereby reducing the amount of processing to be executed by the programmable device. Accordingly, the number of programmable devices can be increased.

(2) Further, the present invention provides an O / E converter and an S / E converter.
A DH / ATM processing unit, a programmable device, and a dual-port memory are mounted on a first daughter board (hereinafter, referred to as an interface daughter board), and a daughter board is connected by a connector connected to wires for supplying data signals, clock signals, power, and the like. It is also characterized in that it can be accommodated in the motherboard in a detachable state between the motherboard. Thus, the number of input / output ports can be increased according to the required number of input / output ports.

According to the present invention, a function to be executed by the programmable device is programmed and realized in the programmable device, or a new daughter board is provided to mount an input / output port having a necessary interface function. be able to.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 (Minimum Configuration of the Present Invention) FIG. 3 shows a first embodiment of the present invention. In addition, 1 in the figure
These lines actually represent a plurality of signal lines directed to the same target (the same applies to the following figures). FIG. 3 shows a minimum configuration according to the present invention, in which one interface daughter board (# 1 (302a)) is mounted on the motherboard (300). On the motherboard (300) shown in FIG. 3, a configuration similar to that shown in FIG.
CPU (109) and ROM (11
2), a RAM (113), and an I / O port (111). A flash memory (108) is connected to the CPU (109) via a program bus (305). Also,
The I / O port (111) is connected to an external personal computer via an RS-232C interface cable, for example.
(PC), workstation (WS), etc.

On the motherboard (300), an interface serving as an interface to the ATM network is provided.
Three connectors for the interface daughter board (301a, 301b, 30) for detachably connecting the daughter board
1c), and three programmable device daughter board connectors (304a, 304b, 304c) for detachably connecting a programmable device daughter board on which the programmable device is mounted.
Connector for each interface daughter board (301
a, 301b, 301c) and connectors (304a, 304b, 304c) for each programmable device daughter board are provided with connection points to the program bus (305). Three connectors (301a, 30) for interface daughter board
1b, 301c) are provided with connection points for parallel signal lines to be input to the programmable device # 0 (303) mounted on the motherboard (300) from the beginning. Wiring for supplying data signals, clock signals, power supply, and the like is connected to each connector.

A parallel signal line output from the programmable device # 0 (303) is connected to a connector # 1 (304a) for a programmable device daughter board and via an automatic change circuit # 1 (306a). , One terminal of another automatic change circuit # 2 (306b) and another automatic change circuit # 3 (306c), a parallel output signal line from the connector # 3 (304c), and three connectors for an interface daughter board ( 301a, 301b, 301c). The other terminals of the automatic change circuits # 2 (306b) and # 3 (306c) are output from the connector # 1 (304a) for the programmable device daughter board and input to the connector # 2 (304b). The parallel signal line and the output from the connector # 2 (304b) are output to the connector # 3 (304b).
c) are connected to parallel signal lines input to c).

The automatic change circuits # 1 to # 3 (306a to 306c)
This circuit detects the connection state of the daughter board in each of the three connectors (304a, 304b, 304c) for the programmable device daughter board and connects or disconnects between the input terminal and the output terminal. As shown in FIG. 2, when the daughter board is not connected to any of the three connectors (304a, 304b, 304c), the automatic change circuits # 1 to # 3 (306a to 306c) are all connected. Become. When a daughter board is connected to the connector (304a), the automatic change circuit # 1 (306a) connects the connectors (304a) and (3
When a daughter board is connected to the daughter board 04b), the automatic change circuits # 1 (306a) and # 2 (306b) are connected to the three connectors (3
04a, 304b, and 304c), when the daughter boards are connected, all of the automatic change circuits # 1 to # 3 (306a to 306c)
Each operates to be in the cutoff state.

In this case, the connector # 1 (301a) for the interface daughter board and the programmable
Between the device # 0 (303) and the connector # 2 (301b) for the programmable device daughter board connector # 1 (3
04a), connector # 3 (301c) and connector # 2 (304
Between b), output signal lines (1101), (1111),
(1121) is provided. Note that there is no condition of the mounting position with respect to the number of mounted interface daughter boards, and the same performance is achieved regardless of the mounting position.

In the interface daughter board # 1 (302a) connected to the interface daughter board connector (301a), an input is made from a transmission line composed of an optical fiber (101) via an I / O circuit (not shown). The optical signal is converted into an electric signal by the O / E converter (401a), and the
/ S at ATM processing unit (or ATM termination circuit) (402a)
The cell is extracted from the payload by performing the DH process, and is output to the programmable device # 4 (403a). A desired process is realized by the programmable device # 4 (403a) and the same device # 0 (303) (however, only the programmable device # 4 (403a) may be used). 4 (403a) to write / read data to / from the dual port RAM (404a) on the interface daughter board # 1 (302a). The processed cell and the data consisting of that cell are SDH / AT
M processing unit (402a) places it in the SDH payload,
The signal is converted into an optical signal by the conversion unit (401a), and is output to the transmission line including the optical fiber (101). In addition, interface
On the daughter board # 1 (302a), an SDH / ATM processing unit (4
02a) and a connection line to the programming bus (305) for the programmable device # 4 (403a).

In this case, since the programmable device daughter board # 1 is not connected to the motherboard via the programmable device daughter board connector # 1 (304a), the automatic change circuit # 1 (306b) is in the connection state. When an interface daughter board is connected to the programmable device # 4 (403a) (and the connectors # 2 (301b) and # 3 (301c)), the output of the programmable device # 0 is mounted on them. Input to the programmable devices # 5 and # 6). Note that the automatic change circuits # 1 to # 3 (306a to 306c) form the same state for the wiring to each interface daughter board regardless of the presence or absence of the interface daughter boards # 1 to # 3 (see the following figures). The same).

[Second Embodiment] (First Example of Expansion of Programmable Devices) FIG. 4 shows a second embodiment of the present invention. FIG. 4 is a diagram showing a programmable device # 4 in the first embodiment.
(403a) and # 0 (303) alone cannot achieve the desired processing, and thus the case where programmable device # 1 (303a) is added. In this case, the programmable device #
1 (303a) is a programmable device daughter board #
1 (307a). The same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

Programmable through connector (304a)
Device / Daughter Board # 1 (307a) replaces motherboard (30
0), the automatic change circuit # 1 (306a) electrically detects this and puts the circuit into a disconnected state. Also, the programmable device daughter board # 2 has a connector (304
Since it is not mounted on the motherboard via b), the automatic change circuit # 2 (306b) is in a connected state, and the output of the programmable device # 0 (303) is programmable.
The signal is input to the device # 1 (303a), and the output of the programmable device # 1 (303a) is
(403a) (and # 5 and # 6).

[Third Embodiment] (Second Example of Expansion of Programmable Devices) FIG. 5 shows a third embodiment of the present invention. FIG. 5 shows the programmable device # 4 in the second embodiment.
(403a) and # 0 (303) and # 1 (303a) alone cannot achieve the desired processing.
(303b) is added. The same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

When the programmable device daughter board # 2 (303b) on which the programmable device # 2 (303b) is mounted is mounted on the motherboard via the connector # 2 (304b), the automatic change circuit # 2 (306b) ) Electrically detects this and turns off the circuit. Also, since the programmable device daughter board # 3 is not mounted on the motherboard via the connector # 3 (304c), the automatic change circuit # 3 (306c) is in a connected state, and the programmable device # 1 (303a) ) Is input to the programmable device # 2 (303b), and the output of the programmable device # 2 (303b) is
4 (403a) (and # 5 and # 6).

[Fourth Embodiment] (Third Example of Expansion of Programmable Devices) FIG. 6 shows a fourth embodiment of the present invention. FIG. 6 is a diagram showing a programmable device # 4 according to the third embodiment.
(403a), # 0 (303), # 1 (303a), and # 2 (303b) alone cannot achieve the desired processing, and thus a programmable device # 3 (303c) is added. The same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

When the programmable device daughter board # 3 (307c) on which the programmable device # 3 (303c) is mounted is mounted on the motherboard via the connector # 3 (304c), the automatic change circuit # 3 (306c) ) Electrically detects this and turns off the circuit. The output line from the programmable device daughter board # 3 (307c) is always connected to the wiring to the programmable device # 4 (403a) and the connectors (301b, 301c) (programmable devices # 5 and # 6). The output of the programmable device # 2 (303b) is input to the programmable device # 3 (303c), and the output of the programmable device # 3 (303c) is input to the programmable device # 4 (4c).
03a) (and # 5 and # 6).

According to the first to third embodiments described above, the number of programmable devices can be increased or decreased according to the processing amount to be realized.

Fifth Embodiment (First Example of Increasing the Number of Interfaces) FIG. 7 shows a fifth embodiment of the present invention. FIG. 7 is a block diagram of the first embodiment, showing an I
This is a case where one I / O port is insufficient and an interface daughter board # 2 (302b) is added. In this case, the interface daughter board # 2 (302b) is connected to the interface daughter board connector (301b). Note that there is no condition of the mounting position with respect to the number of mounted interface daughter boards, and the same performance can be achieved regardless of the mounting position in any combination.

Interface daughter board # 2 (302
b) includes interface daughter board # 1
(302a) The O / E converter (4
01b), SDH / ATM processing unit (402b), programmable
Device # 5 (403b) and dual port RAM (404b)
Is installed.

A first example of usage is a case where a desired process A can be realized with one interface daughter board and half or less of the programmable device # 0 (303) on the motherboard, and two such processes are required. The same processing circuit a1 is realized in the programmable devices # 4 (403a) and # 5 (403b), and the programmable devices # 0 (3
In 03), two necessary processing circuits a2 are realized, and each of them is connected (a1 + a2) to operate the processing A. The case where the desired processing A can be realized only with the interface daughter board is of course included in this.

A second example of the use is to realize two different desired processes A and B. The processing circuit a1 is connected to the interface daughter board # 1 (302a).
The processing circuit b1 is realized by the interface daughter board # 2 (302b), and the processing circuits of the processing circuits a2 and b2 are realized by the programmable device # 0 (303). The processing A and the processing A are connected to each other (a1 + a2, b1 + b2). Process B is operated. The case where the desired processing A or processing B can be realized only with the interface daughter board is of course included in this.

As a third example of usage, two I / Os
Performs some processing on input cells between ports,
This is the case when outputting to the own port or another port. In the programmable device # 0 (303), at least data transfer between ports is performed through this.

In the first to third examples of use, desired processing is performed by using a programmable device on the interface daughter board and a programmable device # 0 (303).
In the case where it is not possible to realize by only the programmable device #, if necessary, as described in the second to fourth embodiments.
1 to # 3 (303a to 303c) are added and realized.

[Embodiment 6] (Second example of increasing the number of interfaces) FIG. 8 shows a sixth embodiment of the present invention. FIG. 8 shows that the first embodiment lacks two I / O ports,
Interface daughter board # 2 (302b) and # 3 (3
02c). In this case, the interface daughter board # 3 (302c) is connected to the interface daughter board connector (301c). Also, the interface daughter board # 3 (302c)
Interface daughter boards # 1 to # 2 (3
O / E converter (401c), SDH / ATM processor (402c), programmable device # 6 (403c), and dual port RAM (4
04c) is installed.

As a first example of use, a desired process A can be realized with one interface daughter board and one third or less of the programmable device # 0 (303) on the motherboard. It is. Programmable devices # 4 (403a) and # 5 (403b) and # 6 (4
In 03c), the same processing circuit a1 is realized, and three necessary processing circuits a2 are realized in the programmable device # 0 (303), and the processing A is operated by connecting (a1 + a2) each of them. The case where the desired processing A can be realized only with the interface daughter board is of course included in this.

A second example of usage is a case where three different desired processes A, B and C are realized.
The processing circuit a1 is processed by the interface daughter board # 1 (302a), the processing circuit b1 is processed by the interface daughter board # 2 (302b), and the interface daughter board # 3 is processed.
(302c) realizes the processing circuit c1, and the programmable device # 0 (303) realizes the processing circuits of the processing circuits a2, b2, and c2, and connects them (a1 + a2, b1 + b2,
c1 + c2) to perform the processing A, the processing B, and the processing C. The case where the desired processing A, processing B, or processing C can be realized only by the interface daughter board is included in the above. Of course, the case where any two of the three processes are the same is also included in this.

As a third example of usage, three I / Os
Performs some processing on input cells between ports,
This is the case when outputting to the own port or another port. In the programmable device # 0 (303), at least data transfer between ports is performed through this. A specific example corresponding to this is a broadcast process to three ports. Also, if any two of the three processes are the same,
Of course, this is included. As a specific example corresponding to this, 2
There is one-to-one multiplexing / separation processing.

In the first to third examples of use, the desired processing is performed by using the programmable device on the interface daughter board and the programmable device # 0 (303).
In the case where it is not possible to realize by only the programmable device #, if necessary, as described in the second to fourth embodiments.
1 to # 3 (303a to 303c) are added to realize desired processing.

Embodiment 7 (Example of Combination of Interface Daughter Board and Programmable Device Daughter Board) FIG. 9 shows a seventh embodiment of the present invention. FIG. 9 shows a case where a programmable device daughter board # 2 (302b) and a programmable device daughter board # 3 (302c) are added in the sixth embodiment.

This is an example of a configuration in which one interface daughter board and one programmable device on the motherboard are required to realize the desired process A, and three sets are required. Programmable device # 4
(403a) and # 0 (303), # 5 (403b) and # 1 (303a),
The # 6 (403c) and the # 2 (303b) are connected to realize the desired processing A. Programmable device # 4 (4
03a), # 5 (403b), and # 6 (403c) implement the same processing circuit a1, and the programmable devices # 0 (303), # 1 (303a), and # 2 (303b) Implements the same processing circuit a2 and connects them (a1 + a2) to operate three processes A.

From the programmable device on the interface daughter board to the programmable device
Signal outputs to the programmable devices on the daughter board use direct wiring. That is, the output from the programmable device # 4 (403a) to the # 0 (303) is the wiring (1101), and the output from the programmable device # 5 (403b) to the # 1 (303a) is the wiring (1111). The output from the programmable device # 6 (403c) to the programmable device # 2 (303b) uses the wiring (1121).

From the programmable device on the daughter device daughter board to the interface
Since there is no direct wiring for the signal output to the programmable device on the daughter board, the output from the programmable device # 0 (303) to the # 4 (403a) is the same as the # 1 (303a)
The wiring is set in # 2 (303b), and the output from the programmable device # 1 (303a) to # 5 (403b) is set in # 2 (303b). This is performed using this.

Embodiment 8 (Example of Combination of Interface Daughter Board and Programmable Device Daughter Board) FIG. 10 shows an eighth embodiment of the present invention. FIG. 10 shows the automatic change circuits # 1 to # 3 (306a) in the seventh embodiment.
306c) can be manually changed for each wiring from the interface daughter board.

On the motherboard (300a) shown in FIG.
In place of the automatic change circuits # 1 to # 3 (306a to 306c) mounted on the motherboard (300) shown in FIG. Manual change circuits # 1 to # 3 (506a to 506c) including DIP switches (dip switches) and the like are provided. In FIG. 10, the same components as those shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

Here, as in the seventh embodiment, one interface daughter board and one programmable device on the motherboard are required to realize the desired processing A, and three sets of these are required. In this case, the same processing circuit a1 is realized in the programmable devices # 4 (403a), # 5 (403b), and # 6 (403c), and the programmable devices # 0 (303) and # 1 (303a). ) And # 2 (30
3b), the same processing circuit a2 is realized, and the programmable devices # 4 (403a) and # 0 (303), # 5 (403b) and # 1 (303a), and # 6 (403c) The process # 2 (303b) is connected to operate the process A.

Also, as in the seventh embodiment, direct wiring is used for signal output wiring from the programmable device on the interface daughter board to the programmable device on the programmable device daughter board.

From the programmable device on the programmable device daughter board to the interface
The signal output to the programmable device on the daughter board is different from that of the seventh embodiment. The wiring for output from the programmable device # 0 (303) to the programmable device # 4 (403a) is the same as that of the programmable device # 1 (303a) and the wiring # 2 (303a).
Without setting the wiring in b), the part corresponding to the wiring from the programmable device # 4 (403a) on the interface daughter board # 1 (302a) in the manual change circuit # 1 (506a) is connected. Then, it is directly connected to the wiring connected to the programmable device # 4 (403a). In addition, wiring for output from the programmable device # 1 (303a) to the programmable device # 5 (403b) is not set in the programmable device # 2 (303b), and the manual change circuit # 2 (303b) is not set. 506b), the portion corresponding to the wiring from the programmable device # 5 (403b) on the interface daughter board # 2 (302b) is connected, and the programmable device # 5 is directly connected.
Connect to the wiring that leads to (403b). Note that the manual change circuit #
As for the automatic change circuit # 3 (306c), all the contacts are brought into the connected state, similarly to the automatic change circuit # 3 (306c).

[Embodiment 9] (Selective programming method of programmable device) As a ninth embodiment of the present invention, a selective programming method of a programmable device will be described. As shown in FIG. 1, in the present invention, circuit data of processing executed by a programmable device is stored in an externally connected I / O port (1).
11) Or download the circuit data from the flash memory (108) and program it. External connection I / O port
(111) is connected to the CPU (109) via the flash memory.
(108) is directly connected to the programming bus (305), to which each of the programmable devices # 0 to # 6 (30
3, 303a, 303b, 303c, 403a, 403b, 403c) are also connected. FIG. 1 shows the motherboard (3) shown in FIGS.
00) Connector for interface board (301a-30
1c) and connector for programmable board (304a-304c)
1 shows a case where a daughter board is connected to each of them. The same components as those in the respective drawings are denoted by the same reference numerals, and description thereof will be omitted.

In order to download the data of each processing circuit executed by each programmable device, first, a programmable device to be set / changed to a desired processing circuit through a device selection wiring in a program bus (305) After setting the mode to data download, data is sent to the program bus to set and change only a specific programmable device. When downloading the same data, a plurality of programmable devices can be set and changed at one time. When downloading circuit data from the flash memory (108), the power-on or system reset triggers the
The PU (109) sequentially reads the setting destination (programmable device) data and its circuit data from the flash memory (108), sets the mode of the programmable device to be set to data download, downloads the circuit data, and processes the circuit data. Set.

From the external connection I / O port (111) to the CPU (10
When downloading circuit data via 9), C
The PU (109) sequentially receives the setting destination (programmable device) data and its circuit data, and sets and changes them in the same manner as described above.

[Embodiment 10] (Interface Daughter Board Compatible with Ethernet) FIG. 11 shows a tenth embodiment of the present invention. Fig. 11 connector
The interface daughter board # 3 (502c) connected to the interface daughter board (301c) is an interface daughter board for Ethernet, and will be described below.

When a programmable ATM adapter is used between an Ethernet LAN and an ATM network, such as between a local LAN and an ATM backbone, it has both an Ethernet interface and an ATM interface and mediates between them. Equipment is required. A from Ethernet frame
The conversion mechanism to a TM cell is roughly as follows.

Interface daughter board # 3 (502
In c), the Ethernet LAN (600) is connected to the connector (60
The MAC frame (medium access control frame) input via 1) is subjected to physical layer termination processing in the Ethernet processing unit (602), taken out as a MAC frame, and it is checked whether the MAC frame is addressed to itself.
If it is addressed to itself, the MAC frame is sent to the celling / decellulation processing unit (603), and if not addressed to itself, it is discarded.

Cell / Decell Processing Unit (603) and SRAM
Processing software runs on the (static RAM) (604) and the DRAM (dynamic RAM) (605),
MAC frames input from the Ethernet LAN (600) are converted to cells and output to the motherboard (300),
Conversely, the cellularized MAC frame input from the motherboard (300) is decellularized, assembled into a MAC frame, and output to the Ethernet LAN (600).

When it is desired to output an IP packet (Internet protocol packet) to the motherboard (300), the output cell / decell processing unit (603) further extracts the IP packet from the MAC frame, And output it to the motherboard (300). vice versa,
When the cellularized IP packet is input from the motherboard (300), it is decellularized and assembled into an IP packet, further embedded in a MAC frame, and output to the Ethernet LAN (600).

The bus control LSI (606) is connected to the local bus (60
8) connected via a cell / decell processing unit (60)
3) Bus control is performed between the SRAM (604), the DRAM (605), and the ROM (607). Processing software is ROM
(607) and loaded at the time of initial operation.

On the motherboard (300), there are two sets of parallel input lines from the interface daughter boards (302a, 302b, 502c) and one set of parallel output lines to the interface daughter boards. Two sets of parallel input lines are connected to the programmable device # 0 (303) installed on the motherboard (300), and the other set is directly connected to each interface daughter board (302a, 302b, 502c). Programmable devices (303, 303a, 303b)
It is wired to. For example, in the case of FIG. 11, there is a direct wiring between the cellization / decellulation processing unit (603) on the interface daughter board # 3 (502c) and the programmable device # 2 (303b).

The cell / decell processing section (60) on the Ethernet-compatible interface daughter board # 3 (502c)
From 3), the same data is stored in the programmable device #
0 (303) and two sets of parallel input lines for the programmable device # 2 (303b).

[Embodiment 11] (VPI / VCI conversion) As an eleventh embodiment of the present invention, a programmable ATM
A case where the adapter is used as a VPI / VCI (virtual path identifier / virtual channel identifier) converter will be described.

The mechanism of the VPI / VCI conversion is roughly as follows. The VPI and / or VCI after conversion for the VPI and / or VCI (virtual path identifier and / or virtual channel identifier) of the input cell is described in advance in a VPI / VCI conversion table provided in advance. When a cell is input, the VPI and / or VCI in the cell header is read, a VPI / VCI conversion table is searched using the read VPI and / or VCI as a key, and the VPI and / or VCI where the key matches is converted. , And rewrites the VPI and / or VCI of the input cell to this, and outputs the cell.

In the programmable ATM adapter, as a first configuration method, cells to be sequentially input via an O / E conversion unit (for example, (401a) in FIG. 3) and an SDH / ATM processing unit (for example, (402a)) are interfaced. VPI stored in a dual-port RAM (404a) via a programmable device (403a) on a daughter board (301a)
Retrieves the VPI and / or VCI of the input cell by retrieving the VPI and / or VCI at the place where the key matches, and sequentially outputs the cell to the SDH / ATM conversion unit. I do.

As a second configuration method, a search for a VPI / VCI conversion table is performed by constructing a function equivalent to a CAM (associative memory) on a programmable device and a dual-port RAM, and directly converting the VPI and // or VCI
There is a way to get

The above processing is performed on a programmable device. However, if the VPI / VCI conversion table and the logic operation circuit for retrieval become large and cannot be realized only by the programmable device on the interface daughter board. Is realized by adding necessary number of programmable device daughter boards.

When it is desired to use a plurality of interfaces (the own interface and another interface or only another interface) as the output destination of the cell after the VPI / VCI conversion, the output interface number is included in the VPI / VCI conversion table. And a circuit for realizing a path for transferring to a target interface daughter board and a circuit for selecting a path according to the number by a programmable device, and rewriting VPI and / or VCI to a broadcast destination Is transferred to the target interface daughter board and output from the O / E conversion unit via the SDH / ATM conversion unit.

[Twelfth Embodiment] (Unassigned / Idle Cell Conversion) As a twelfth embodiment of the present invention, a programmable ATM
A case where the adapter is used as an Unassigned / Idle cell converter will be described.

In a device having a conventional ATM interface, an unassigned cell or an idle cell is used as a cell indicating an empty cell (or invalid cell). If devices having different cell types in the empty cell display are connected, each device mistakenly recognizes an empty cell as a valid cell, and correct communication is not performed. For this reason, Unassigned cells
Idle cell mutual conversion is required.

The mechanism of the Unassigned / Idle cell conversion is roughly as follows. To convert an Unassigned cell to an Idle cell, store the bit pattern of the Unassigned cell in advance, perform bit pattern matching with all cells to be input,
If they match, they are rewritten to the bit pattern of the Idle cell and output, and if they do not match, they are output through without doing anything. Conversely, to convert an Idle cell to an Unassigned cell, the bit pattern of the Idle cell is stored in advance, and pattern matching is performed with all cells to be input.
The output is rewritten with the bit pattern of the gned cell, and if they do not match, the data is output through without doing anything.

In a programmable ATM adapter, one interface board can convert Id from Unassigned cell to Id.
Performs conversion to le cells or conversion from idle cells to unassigned cells. In the case of conversion from Unassigned to Idle cells, the bit pattern of the cell header is extracted from the cells sequentially input via the O / E conversion unit and the SDH / ATM conversion unit, and is compared with the bit pattern of the previously stored Unassigned cell. If they match, they are rewritten to the bit pattern of the Idle cell and output, and if they do not match, they are output through without doing anything. Conversely, in the case of conversion from an idle cell to an unassigned cell, the bit pattern of the cell header is extracted from the cell sequentially input through the O / E conversion unit and the SDH / ATM conversion unit, and the bit of the idle cell stored in advance is extracted. The pattern is compared with the pattern. If the pattern matches, the bit pattern of the unassigned cell is rewritten and output. If the pattern does not match, the data is output without any processing.

The above conversion process may be performed after the data is temporarily stored in a dual-port RAM that operates on a FIFO (first-in first-out) basis, or may be stored in a dual-port RAM that operates on a FIFO after the conversion, and then output.

These processes are performed on a programmable device. If the processing cannot be realized only by the programmable devices on the interface daughter board, a necessary number of programmable device daughter boards are added and realized. I do. Unas to remember in advance
The bit pattern of the signed cell or idle cell can also be stored on a dual port RAM.

When another interface (own interface and another interface or only another interface) is desired to be used as an output destination, a path to be transferred to a target interface daughter board is realized by a programmable device, and conversion is performed. Transferred to the desired interface daughter board, and
Output from the O / E converter via the / ATM converter.

[Thirteenth Embodiment] (Delay) As a thirteenth embodiment of the present invention, a programmable ATM
A case where an adapter is used as a delay device will be described.

There are three mechanisms for delay processing. The first mechanism is to store all input cells including empty cells in the FIFO as they are, measure a delay time specified in advance (one cell time, one byte time, etc.) with a counter, and after a lapse of the delay time, use the FIFO. Is read from.

The second mechanism is that a clock is realized in the apparatus, and only valid input cells are set as time stamp data indicating the input time and stored in a FIFO.
The read time is obtained by adding a delay time specified in advance from the time stamp data of the cell at the head of the IFO, and the cell is read when the read time matches the internal clock.

The third mechanism is that only valid cells are set to FI
It is similar to the second mechanism in that it accumulates in the FO, implements a clock in the device, adds a predetermined delay time to the input time when a valid cell is input, obtains the read time, and obtains the read time. Is stored in the FIFO as a set with the time stamp data indicating the time stamp, and the cell is read when the output time of the time stamp data of the cell at the head of the FIFO matches the internal clock.

In the programmable ATM adapter, O /
Cells to be sequentially input via the E conversion unit and the SDH / ATM conversion unit are stored in the dual port RAM via the programmable device on the interface daughter board. The programmable device implements any of the above-described delay processing mechanisms and stores the dual-port RAM in the FI
FO operation is performed. After the specified delay time, the cells read from the dual port RAM are output from the O / E converter via the SDH / ATM converter.

If the processing circuits and the like become large and cannot be realized only by the programmable devices on the interface daughter board, a necessary number of programmable device daughter boards are added and realized.

If another interface (own interface and another interface or only another interface) is desired to be used as an output destination, a path to be transferred to a target interface daughter board is realized by a programmable device, and conversion is performed. Transferred to the desired interface daughter board, and
Output from the O / E converter via the / ATM converter.

[Embodiment 14] (Cell Broadcasting) As a fourteenth embodiment of the present invention, a programmable ATM
A case where an adapter is used as a cell broadcasting device will be described.

The mechanism of cell broadcasting is roughly as follows. The VP of the input cell is stored in the broadcast table provided in advance.
Broadcast VPI and / or VC for I and / or VCI
I is described in advance. When a cell is input, the VPI and / or VCI in the cell header is read, the broadcast table is searched using the read VPI and / or VCI as a key, and the VPI and / or VC of the broadcast destination where the key matches is read.
I is read sequentially and VPI and / or VC of the input cell
I is rewritten to this, and the cells are sequentially output.

In the programmable ATM adapter, O /
Cells sequentially input through the E conversion unit and the SDH / ATM conversion unit are stored in the dual port RAM via the programmable device on the interface daughter board. Next, the previously created broadcast table is searched by a logical operation or the like, and the VPI and / or V of the broadcast destination where the key matches is searched.
CI is read sequentially, and VPI and / or V
CI is rewritten to this, and the cells are sequentially converted to SDH / ATM.
Output to the converter. These processes are performed on a programmable device. If the broadcast tables and logic operation circuits for searching are too large to be implemented with only the programmable devices on the interface daughter board, add the necessary number of programmable device daughter boards and implement them there. I do.

When a plurality of interfaces (the own interface and another interface or only another interface) are to be used as a broadcast destination,
The output interface number is described in the broadcast table, and a path for transferring to the target interface daughter board and a circuit for selecting a path according to the number are realized by a programmable device, and the VPI and / or V
The cell in which the CI is rewritten as the broadcast destination is transferred to the target interface daughter board, and is output from the O / E converter via the SDH / ATM converter.

[Embodiment 15] (VP / VC Shaping) As a fifteenth embodiment of the present invention, a programmable AT
A case where the M adapter is used as a VP / VC shaping device will be described.

The mechanism of VP / VC (virtual path / virtual channel) shaping is roughly as follows. The VPI (or VPI + VCI) of the VP (or VC) to be shaped is stored, and the V of the input cell is stored.
The PI (or VPI + VCI) is read and collated, and if it does not match, it is output immediately, and if it matches, the cell is stored in the FIFO. The specified VP (or V
In order to shape C), a counter having a required size is provided, and when the value of the counter reaches a set value, the stored cells are read from the FIFO. FI
You can set multiple values for the counter that reads cells from the FO,
Thus, an output pattern with a desired cell interval can be created. Since the counter returns to zero when full, the cell output pattern repeats periodically.

In the programmable ATM adapter, O /
The VPI (or VPI + VCI) of the cell sequentially input through the E conversion unit and the SDH / ATM conversion unit is read out, input to each comparison circuit, and set to a predetermined VPI (or VPI).
+ VCI) is stored in the dual port RAM. The dual port RAM performs a FIFO operation by a control circuit implemented on a programmable device.

A counter is realized on the programmable device, and a counter value, which is a timing for reading cells from the FIFO, is set in one of the comparison circuits in advance, and successive comparison is performed as the counter counts up. Will be In order to generate an output pattern at a desired cell interval, a plurality of comparison circuits are provided for each VP (or VC), and an OR operation of a coincidence signal is performed to obtain a read signal to a corresponding FIFO.

When a read signal is input to the FIFO,
One cell is read from the FIFO, and the cells are sequentially read from the SD
Output to the H / ATM converter. These processes are performed on a programmable device. If the logic operation circuit or the like becomes too large to be realized only by the programmable devices on the interface daughter board, a necessary number of programmable device daughter boards are added and realized.

When a plurality of interfaces (the own interface and another interface or only another interface) are to be used as output destinations,
The output interface number is described in the broadcast table, and a path for transferring to the target interface daughter board and a circuit for selecting a path according to the number are realized by a programmable device, and the cell is connected to the target interface daughter board.・ Transfer to daughter board, SDH / ATM
Output from the O / E conversion unit via the conversion unit.

Embodiment 16 (Cell Flow Shaping) As a sixteenth embodiment of the present invention, a programmable ATM
A case where the adapter is used as a cell flow shaping device will be described.

The mechanism of cell flow shaping is roughly as follows. When a cell flow is input, cells other than invalid cells are sequentially stored in the FIFO. A counter having a size necessary for desired shaping is provided, and when the value of the counter reaches a set value, the stored cells are read from the FIFO. A plurality of counter values for reading cells from the FIFO can be set, thereby making it possible to create an output pattern with a desired cell interval. Since the counter returns to zero when full, the cell output pattern repeats periodically.

In the programmable ATM adapter, O /
The headers of the cells sequentially input through the E conversion unit and the SDH / ATM conversion unit are read, and cells other than invalid cells are stored in the dual port RAM. Dual port RAM
A FIFO operation is performed by a control circuit implemented on a programmable device.

A counter is realized on the programmable device, and a counter value, which is a timing for reading cells from the FIFO, is preset in one of the comparison circuits, and successive comparisons are performed as the counter counts up. Will be In order to generate an output pattern at a desired cell interval, a plurality of comparison circuits are provided, and an OR operation of a coincidence signal is performed to obtain a read signal to a corresponding FIFO.

When the read signal is input to the FIFO,
One cell is read from the FIFO, and the cells are sequentially read from the SD
Output to the H / ATM converter. These processes are performed on a programmable device. If the logic operation circuit or the like becomes too large to be realized only by the programmable devices on the interface daughter board, a necessary number of programmable device daughter boards are added and realized.

When it is desired to use a plurality of interfaces (the own interface and another interface or only another interface) as output destinations,
The output interface number is described in the broadcast table, and a path for transferring to the target interface daughter board and a circuit for selecting a path according to the number are realized by a programmable device, and the cell is connected to the target interface daughter board.・ Transfer to daughter board, SDH / ATM
Output from the O / E conversion unit via the conversion unit.

[Embodiment 17] (Cell-based IP packet / MAC frame transfer) As a seventeenth embodiment of the present invention, a programmable ATM
A case where the adapter is used as an IP packet (or MAC frame) transfer device will be described.

The transfer mechanism of the IP packet (or MAC frame) is roughly as follows. One LAN
When transferring an IP packet (or MAC frame) in an ATM network from the Internet to a plurality of LANs, it is necessary to rewrite the VPI and / or VCI required for the ATM network transfer according to the IP (or MAC) address. . Therefore, the IP (or MA
C) In the address table, the new destination VPI and / or for the IP (or MAC) address of the entered cell
The VCI is described in advance. When a cell is input, it is determined whether the cell is a cell in which the head of an IP packet (or MAC frame) is included in the payload (hereinafter, referred to as the head cell) by the third bit (hereinafter, PT) of the payload type indication bit of the cell header. 3rd bit). That is, one IP packet (or MAC
When the frame is converted into a cell by AAL5 (ATM adaptation layer 5), the end of the cell is displayed as the third bit of the PT contained in the cell payload as "1", and the other cells have the third bit of the PT. Since it is displayed as "0", the cell flow of the same VPI and / or VCI is monitored, and the first input cell after reset and the cell whose PT third bit is "1" are regarded as the first cell.

If the input cell is the first cell, the IP (or MAC) address is read out, and the IP (or MAC) address table is searched using the IP address as a key.
The VPI and / or VCI of the new destination corresponding to the matched IP (or MAC) address is read, the VPI and / or VCI of the input cell is rewritten to this, and the cell is output. Also, the VPI and / or V
A second table capable of recording the VPI and / or VCI of the new destination corresponding to the CI is provided, and the VPI and / or VCI of the new destination obtained by searching the IP (or MAC) address table is stored. , And is recorded in correspondence with the input VPI and / or VCI of the head cell.

When a cell subsequent to the second cell of the IP packet (or MAC frame) is input, it is identified as not the first cell, and the VPI and / or VCI of the input cell is determined.
Is used as a key, the VPIand / or VCI of the new destination where the key matches is read, the VPI and / or VCI of the input cell is rewritten to this, and the cell is output.

In the programmable ATM adapter, as a first configuration method, cells to be sequentially input via the O / E conversion unit and the SDH / ATM conversion unit are transferred to the dual port RAM via the programmable device on the interface daughter board in the FIFO format. It is stored in a format, and the identification circuit for the first cell and the second and subsequent cells, and the IP (or M
AC) An address table and its search circuit, and a second table for the second and subsequent cells and its search circuit are realized on a programmable device, and the cells whose VPI and / or VCI have been rewritten are sequentially converted to an SDH / ATM converter. Output to

As a second configuration method, a function equivalent to a CAM is realized on a programmable device and a dual-port RAM, and the two types of tables are placed here to directly obtain VPI and / or VCI after conversion. There is a way. In that case, a function of storing input cells in the programmable device is realized.

The above processing is carried out on a programmable device. However, if the two types of tables and the logic operation circuit for retrieval become large, the processing of the interface becomes difficult.
If it cannot be realized only by the programmable devices on the daughter board, the necessary number of programmable device daughter boards are added and realized there.

When it is desired to use a plurality of interfaces (the own interface and another interface or only another interface) as the output destination of the cell after rewriting the VPI and / or VCI, the output is performed in the two types of tables. An interface number is described, and a path for transferring to a target interface daughter board and a circuit for selecting a path according to the number are realized by a programmable device, transferred to the target interface daughter board, and transferred to the SDH / Output from the O / E conversion unit via the ATM conversion unit.

[Embodiment 18] (Cell multiplexing / demultiplexing) As an eighteenth embodiment of the present invention, a programmable ATM
A case where the adapter is used as a cell multiplexing / demultiplexing device will be described.

The cell multiplexing / demultiplexing method is roughly as follows. If n-to-1 cell multiplexing / demultiplexing is to be performed, in the case of multiplexing, cells input from n input interface boards are transferred to a predetermined interface board for multiplex output. If cells from different interfaces are to be output to the multiplex output interface, cell contention will occur. In the case of separation, a table in which the VPI and / or VCI and the output interface number are set is provided in advance, a desired correspondence is described in advance, and when a cell is input, the VPI and / or VCI in the cell header is read, and this is read. VP read
Searching the table using I and / or VCI as a key,
Read the interface number where the key matches,
Outputs the input cell to the interface with the specified number.

In the following, interface daughter boards # 1 to # 3 are mounted on the programmable ATM adapter, and cells from # 1 and # 2 are multiplexed and output from # 3, and conversely, The case where the multiplexed cells from # 3 are separated into predetermined # 1 and # 2 cells and output respectively will be described. FIG. 8 assumes the daughter board configuration of the programmable ATM adapter.

[Cell Multiplexing] In the interface daughter board # 1 (302a), the O / E conversion unit (401a) and the SDH /
The cells sequentially input through the ATM conversion unit (402a) are output from the programmable device # 4 (403a) to the programmable device # 0 (303) on the motherboard (300) by direct wiring. Similarly, interface daughter board # 2
In (302b), the cells sequentially input through the O / E converter (401b) and the SDH / ATM converter (402b) are programmed.
Motherboard (300) with direct wiring from device # 5 (403b)
Output to the above programmable device # 0 (303).
Interface daughter boards # 1 (302a) and # 2 (302
b) The cell arriving from
Programmable device # 6 on daughter board (302c)
If an attempt is made to output to (403c), cell conflict occurs between the interface daughter boards # 1 (302a) and # 2 (302b). There are two specific methods.

The first method is to use the dual port R on the interface daughter boards # 1 (302a) and # 2 (302b).
The AM (404a, 404b) is operated in a FIFO manner, and if input cells are stored therein, it is notified by direct wiring, and the programmable device # 0 (3
(00), a cell is output from the dual port RAM (404a, 404b) to the programmable device # 0 (300) when a read signal comes from the selection circuit in (00). As a reading order of the selection circuit, when cells are stored in both the dual-port RAMs (404a, 404b), reading is performed alternately, and when cells are stored in only one of them, reading is continuously performed from there. , Etc.

The second method is that, in the first method, the FIFO realized on the two interface daughter boards (302a, 302b) is replaced with the programmable device # 0.
(303). If the programmable device # 0 (303) on the motherboard (300) cannot be used alone, the necessary number of programmable devices
Device daughter boards # 1 to # 3 (303a to 303c) are added and realized there. The order of reading from these two FIFOs is the same as in the first method.

The cells multiplexed and output from the selection circuit correspond to the interface daughter board # 3 which outputs the multiplexed cell stream.
It is output from the O / E converter (401c) via the programmable device # 6 (403c) on (302c), via the SDH / ATM converter (402c).

[Cell Separation] In the interface daughter board # 3 (302c) to which the multi-cell flow is input, the VPI and
/ or A table in which a VCI and an output interface number are set is provided in advance, and a desired correspondence is described in advance.
The VPI and / or VCI is read from cells sequentially input through the O / E conversion unit (401c) and the SDH / ATM conversion unit (402c), and the table is searched using the read VPI and / or VCI as a key. Is read, and is notified by direct wiring to the distribution circuit in the programmable device # 0 (303) on the motherboard. The distribution circuit outputs cells only to the interface daughter board that has been notified.

In addition to the above-described first realization method, the above table is constructed on the dual port RAM (404c) of the interface daughter board # 3 (302c) by constructing a function corresponding to the CAM and directly converting the VPI and / or or a third method for realizing the table in the programmable device # 0 (303) on the motherboard (300).

The cells selectively output from the distribution circuit to the respective interface daughter boards # 1 (302a) and # 2 (302b) based on the notification are the programmable devices (403a, 403b) on the respective interface daughter boards. Via the SDH / ATM converter (402a, 402b)
It is output from the / E converter (401a, 401b).

The above processing is performed on a programmable device. However, if the logic operation circuit or the like cannot be realized only by a programmable device on an interface daughter board or a motherboard, a necessary number of programmable devices are required.・ Add daughter boards and realize them there.

[Embodiment 19] (Light characteristic conversion) As a ninth embodiment of the present invention, a programmable AT
A case where the M adapter is used as an optical characteristic conversion device will be described.

In general, optical connectors are used for wavelengths of 1.3 μm and 1.5 μm, for modes of single mode and multimode, and for optical power of low output for short distance (intra-office interface) and for high output. For long distance (inter-office interface). In order to transmit and receive ATM signals between these different optical connectors, optical characteristics / connector type conversion is required.

In the programmable ATM adapter, interface daughter boards each having an O / E converter having characteristics to be converted are formed, and the output of the SDH / ATM converter on each interface daughter board is output.
This can be realized by transferring between programmable devices on each interface daughter board via a programmable device on the motherboard.

In the same manner, conversion between optical connectors having different shapes, between coaxial connectors, and between optical connectors can be performed.

[Embodiment 20] (Communication interface conversion) As a 20th embodiment of the present invention, a programmable AT
A case where the M adapter is used as a communication interface converter will be described.

This conversion is necessary when transmitting and receiving IP packets between the interface daughter board corresponding to Ethernet described in the tenth embodiment and the ATM interface daughter board described in the nineteenth embodiment and the like.

In the programmable ATM adapter, an interface daughter board having an interface function to be converted is created, and the output of the IP packet on each interface daughter board is connected via a programmable device on the motherboard. Can be.

[Embodiment 21] (Complex implementation) The various hardware-based configuration methods described in the first to tenth embodiments and the programmable devices described in the eleventh to twentieth embodiments can be implemented in various ways. Programmable ATM with set functions
By combining the usage of the adapters, complex functions can be realized on the programmable ATM adapter.

For example, cells input from two different types of interface daughter boards are multiplexed, shaped, and output from a third type interface daughter board.

[0121]

As described above, according to the present invention, (1) a required number of programmable devices can be realized in accordance with the processing amount to be executed by the programmable devices, which cannot be realized by the conventional programmable ATM adapter. (2) increase the required number of input / output ports or mount input / output ports having the required interface functions according to the functions realized by the programmable ATM adapter; and (3) The setting change to a predetermined circuit connection when the daughter board is mounted on the motherboard can be electrically detected and automatically performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment (a ninth embodiment) of a programmable ATM adapter according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional programmable ATM adapter.

FIG. 3 is a block diagram showing a first embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 4 is a block diagram showing a second embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 5 is a block diagram showing a third embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 6 is a block diagram showing a fourth embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 7 is a block diagram showing a fifth embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 8 is a block diagram showing a sixth embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 9 is a block diagram showing a seventh embodiment in which the number of daughter boards mounted on the programmable ATM adapter shown in FIG. 1 is changed.

FIG. 10 is a block diagram showing an embodiment (eighth embodiment) in which an automatic change circuit of a daughter board is changed to a manual change circuit in the programmable ATM adapter shown in FIG. 1;

FIG. 11 is a block diagram showing an embodiment (a tenth embodiment) in which an interface daughter board mounted on the daughter board in the programmable ATM adapter shown in FIG. 1 is different.

[Explanation of symbols]

300 Motherboard 301a, 301b, 301c, 304a, 304b, 304c Connector 302a, 302b, 302c Interface daughter board 307a, 307b, 307c Programmable device daughter board 303,303a, 303b, 303c, 403a, 403b, 403c Programmable device 306a, 306b , 306c Automatic change circuit 506a, 506b, 506c Manual change circuit 401a, 401b, 401c O / E conversion unit 402a, 402b, 402c SDH / ATM processing unit 404a, 404b, 404c Dual port RAM

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-147590 (JP, A) JP-A-4-365246 (JP, A) IEICE Technical Report CS94-218 96 IEICE Society B-1001 95 Science Society B-588 IEICE Technical Report CS95-192 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (13)

(57) [Claims] 1. An optical signal receiving and converting an electrical signal into an optical signal, and vice versa.
/ E converter, and recognizes an electric signal received through the O / E converter as an SDH signal and takes out an ATM cell from the SDH signal.
An SDH / ATM processing unit for transmitting as an H signal; a cell buffer for temporarily storing cells extracted by the SDH / ATM processing unit; and a cell output from the cell buffer and data comprising the cell. A programmable device for processing according to a pre-programmed circuit and outputting the processed cell to the SDH / ATM processing unit; and a dual port for temporarily storing cells and other data between the programmable device and the programmable device. A programmable ATM adapter having a memory, a first daughter board equipped with an O / E conversion unit, an SDH / ATM processing unit, a programmable device, and a dual port memory; a second daughter board equipped with a programmable device;・ Motherboard with device And at least one first daughter board and a motherboard, wherein the first and second daughter boards are connected to the motherboard by wires for supplying data signals, clock signals, power, and the like, and there is not one A connector for accommodating multiple daughter boards on the motherboard in a detachable manner
And at least two motherboards for the first daughter board.
The cell identifier and the cell to be transferred.
Refer to the table indicating the correspondence with one daughter board, and
Number of cells to each corresponding first daughter board.
Multi-port programmable AT, characterized in that that
M adapter. 2. The multi-port type programmable ATM adapter according to claim 1, wherein the wiring change on the motherboard performed according to the number of the first or second daughter boards accommodated in the motherboard is electrically detected by the presence or absence of the daughter boards. A multi-port type programmable ATM adapter, characterized by having an automatic change circuit for performing automatic operation. 3. The multi-port type programmable ATM adapter according to claim 1, wherein the wiring change on the motherboard according to the number of daughter boards accommodated in the motherboard can be manually performed for each wiring unit from the first daughter board. A multi-port type programmable ATM adapter having a manual change circuit according to the above. 4. The multi-port type programmable ATM adapter according to claim 1, wherein a predetermined conversion table is constructed by a programmable device or a dual-port memory on the first daughter board, and a cell is stored in the programmable device or the dual-port memory. A multi-port type programmable ATM adapter characterized in that a predetermined conversion process is performed on a cell using the conversion table and output while accumulating data. 5. A multiport programmable controller, wherein the conversion table according to claim 4 is a VPI / VCI conversion table for converting a VPI / VCI of a cell to which the cell is input into another predetermined VPI / VCI. ATM adapter. 6. The conversion table according to claim 4, wherein the conversion table is IP / M.
A multi-port type programmable ATM adapter comprising a conversion table indicating a correspondence between an AC address and a VPI / VCI. 7. The conversion table according to claim 4, wherein the conversion table is IP / M.
A multi-port programmable ATM adapter comprising a conversion table between an AC address and a VPI / VCI and information on a first daughter board to which each cell is to be transferred. 8. The multi-port type programmable ATM adapter according to claim 1, wherein the dual-port memory on the first daughter board is R
When the AM is operated as a FIFO, the bit pattern of the cell header input from the O / E conversion unit is extracted while using the dual port memory as a temporary storage unit, and the extracted bit pattern is compared with a predetermined bit pattern stored in advance. A multi-port type programmable ATM adapter characterized by performing conversion to an idle cell or an unassigned cell. 9. The multi-port type programmable ATM adapter according to claim 1, wherein a dual-port memory on said first daughter board is F
A multi-port type programmable ATM adapter, wherein an I / O operation is performed, a cell input from an O / E converter is written into a dual port memory, read after a predetermined time has elapsed, and output from the O / E converter. 10. The multi-port type programmable ATM adapter according to claim 1, wherein cells input from an O / E conversion unit are stored in a dual-port memory on said first daughter board, and a broadcast made in advance is provided. A multi-port type programmable ATM adapter characterized by outputting from an O / E conversion unit while sequentially rewriting stored cell destinations based on a table. 11. The multi-port programmable ATM adapter according to claim 1, wherein the dual-port memory on the first daughter board is F
A multi-port programmable ATM characterized by performing an IFO operation, sequentially writing cells in a dual port memory input from an O / E converter, reading cells sequentially written at predetermined time intervals, and outputting the cells from an O / E converter.
adapter. 12. The multi-port programmable ATM adapter according to claim 1, wherein at least two of said first daughter boards are housed in said motherboard, and said plurality of daughter boards have different types of O / E converters. A multiport type programmable ATM adapter characterized by the following. 13. The multi-port programmable ATM adapter according to any one of claims 4-12, wherein the process for the input cell on programmable devices and at least the motherboard on the first daughterboard A multi-port type programmable ATM adapter, characterized in that it is performed using a circuit programmed in a programmable device together.