JP2874187B2 - Liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device that displays images by arranging liquid crystal display elements in an XY matrix, for example.

[Summary of the Invention]

The present invention relates to a liquid crystal display device, in which a means for adjusting a phase of a drive clock signal of a shift register used for sampling of an input signal is provided so that display of an image signal from a computer or the like is particularly well performed. is there.

[Conventional technology]

For example, it has been proposed to display a television image using a liquid crystal (see Japanese Patent Application Laid-Open No. 59-220793).

That is, in FIG. 5, (1) is an input terminal to which a video signal of a television is supplied, and a signal from this input terminal (1) is a switching element M ₁ , M _2. Are supplied to the lines L ₁ , L ₂ ... Lm in the vertical (Y-axis) direction. Note that m is horizontal (X
This is a number corresponding to the number of pixels in the (axis) direction. Further provided m stages of the shift register (2), the horizontal clock signal [Phi _H of m times the horizontal start signal H _S and the horizontal frequency corresponding to a horizontal synchronizing signal in the shift register (2) is supplied,
A drive pulse signal φ _H1 , which is sequentially scanned by a clock signal φ _H from each output terminal of the shift register (2),
φ _H2 ··· φ _Hm is supplied to the control terminal of the switching element M ₁ ~Mm. The low potential (V _SS ) and the high potential (V _DD ) are supplied to the shift register (2), and drive pulses of these two potentials are formed.

Also, for example, each of the lines L _{1 to} Lm has an N-channel FE, for example.
Switching elements M ₁₁ consisting of _{T, M 21 ··· M n1,} M 12, M 22
··· _{M n2,} ··· M _1m, one end of the M _2m ··· Mnm is connected. Note that n is a number corresponding to the number of horizontal scanning lines. The liquid crystal cell C ₁₁ and the other end of the switching element M ₁₁ ~Mnm respectively,
It is connected to the target terminal (3) through C ₂₁ ··· Cnm.

Provided further n-stage shift register (4), a vertical clock signal [Phi _V of the vertical start signal V _S and the horizontal frequency corresponding to the vertical synchronizing signal to the shift register (4) is supplied, the shift register (4) switching the clock signal Φ drive pulse signals are sequentially scanned by _{V φ V1, φ V2 ··· φ} Vn , through horizontal (X-axis) direction of the gate lines G _1, G ₂ ··· Gn from the output terminals of the each column in the X-axis direction of the element _{M 11 ~Mnm (M 11 ~M 1m} ), (M 21 ~M 2m) ··· (M
_{n1 to} Mnm). Note that _VSS and _VDD are also supplied to the shift register (4) in the same manner as the shift register (2).

That is, in this circuit, the shift register (2),
(4) is supplied with start signals H _S and V _S and clock signals Φ _H and Φ _V as shown in FIGS. 6A and 6B. The shift register (2) outputs φ _H1 to φ _Hm every pixel period as shown in FIG. C, and the shift register (4) outputs φ _V1 every horizontal period as shown in FIG. ~ Φ _Vn is output. Further, the input terminal (1) is supplied with a signal as shown in FIG.

When φ _V1 and φ _H1 are output, the switching elements M ₁ and M _{11 to} M _1m are turned on, and the input terminal (1) → M ₁
Potential difference is supplied _{→ L 1 → M 11 → C} 11 → the target terminal (3) the signal current path is supplied is formed in the input terminal to the liquid crystal cell C ₁₁ (1) of the target terminal (3) . Therefore, a charge corresponding to the potential difference due to the signal of the first pixel is sampled and _{held in} the capacity of the cell C11. The light transmittance of the liquid crystal is changed according to this charge amount. It similar to this is successively performed for the cell C ₁₂ ~Cnm, the following additional fields each cell at the time the signal is supplied C ₁₁
The charge amount of ~ Cnm is rewritten.

In this manner, the light transmittance of the liquid crystal cell C ₁₁ ~Cnm is changed corresponding to each pixel of the video signal, which displays the television image is repeated sequentially.

Further, in the case of performing display using liquid crystal, an AC drive is generally used in order to extend the reliability and the life. For example, in the display of a television image, a signal obtained by inverting a video signal for each field or frame is supplied to the input terminal (1). In a liquid crystal display device, a signal is inverted every horizontal period in order to prevent shooting in a vertical direction of display.
That is, the input terminal (1) is supplied with a signal that is inverted every horizontal period and inverted every field or frame as shown in FIG. 6E.

[Problems to be solved by the invention]

However, in the above-described apparatus, for example, when an image signal from a computer is displayed, an image formed by the computer is formed for each pixel and there is no compatibility between pixels. It becomes a problem.

That is, the number of horizontal pixels of an image signal formed by a computer is set to 640 pixels or the like in a generally used model, and it is possible to manufacture a liquid crystal display device having this number of horizontal pixels. However, for example, as shown in FIG. 7A, when an image signal that changes to black / white for each pixel is input, the drive pulse signals φ _{H1 to} φ _Hm supplied to the switching elements M _{1 to} Mm are the same. As shown in FIG. B, in each of the liquid crystal cells C _{11 to} C nm, display is performed as shown in FIG. C and sufficient resolution can be obtained, but the driving pulse signals φ _{H1 to} φ _Hm are shown in FIG. as in a were the case, each of the liquid crystal cell C ₁₁ ~Cnm is will appear in the middle of the gray monochrome all as shown in Fig. E, resolution becomes 0.

On the other hand, a sufficient resolution can always be obtained by increasing the number of horizontal pixels of the liquid crystal display device so as to be at least twice the number of horizontal pixels of the pixel signal. Needs to be extremely high, which leads to an increase in the price of the product. Further, the clock frequency of the shift register (2) becomes twice or more, and if the clock frequency is increased in such a manner, there is a possibility that the power consumption may be extremely increased.

In a liquid crystal display connected to a conventional computer, the above-described problems do not occur because the driving pulse signals φ _{H1 to} φ _Hm are also formed based on a clock signal generated by the computer. On the other hand, in a liquid crystal display device for displaying a television image, which is the subject of the present application, since the clock signal is formed by multiplying the synchronization signal of the supplied image signal, it is difficult to match the phase with the pixel as described above. It becomes.

The present application has been made in view of such points.

[Means for solving the problem]

The present invention relates to a plurality of first signal lines L ₁ , L ₂ ... L _m arranged in parallel in the vertical direction and a plurality of second signal lines G ₁ arranged in parallel in the horizontal direction. , G ₂ ... G _n, and a selection element M at each intersection of these first and second signal lines.
_11, M ₁₂ ··· M _nm liquid crystal cell through the C _11, C ₁₂ ··· C _nm
In the liquid crystal display device provided, a shift register (2) corresponding to the first signal line is provided, and a clock signal is separated from an input signal (terminal (1)) (synchronous separation circuit (5), clock generation). are circuit (6)) is supplied to the shift register, the said input signal at the output signal of the shift register (the drive pulse signal phi _H1 to [phi] _Hm) is sampled (switching element M ₁ ~M _m) a is supplied to the first signal line, said means for adjusting the phase of the clock signal [Phi _H for driving the shift register (delay unit (7a) ~ (7d), a multiplexer (8)) is provided, the input signal The liquid crystal display device is characterized in that the phase of the clock signal can be adjusted so that the display image according to (1) is the best.

[Action]

According to this, the phase of the clock signal is adjusted by the adjusting means, so that the phase with the pixel can be adjusted, and the display of the image signal from the computer or the like can be performed favorably.

〔Example〕

In FIG. 1, an image signal supplied to an input terminal (1) is supplied to a synchronization separation circuit (5) to separate horizontal and vertical synchronization signals, and the above-mentioned shift registers (2), (4)
The start signal is supplied to the H _S, V _S and the vertical clock signal [Phi _V is formed. Further, the horizontal synchronizing signal H separated by the circuit (5) is supplied to a clock generating circuit (6) to form a signal multiplied by m times. Delay means for a delay time τ of the multiplied signal corresponds to 1/5 of the half period of the horizontal clock signal [Phi _H respectively (7a), (7b), (7c), (7d)
And these delay means (7a) to (7
The signal at the input and output ends of d) is a multiplexer (8)
Supplied to The signal from the multiplexer (8) is supplied to the input terminal of the clock signal [Phi _H shift register (2) through a buffer amplifier (9). The following is the same as the conventional device.

Therefore, in this device, signals whose phases are sequentially changed as shown in FIG. 2A are obtained from the input / output terminals of the delay means (7a) to (7d), and one of these signals is converted into a multiplexer (8). As a result, a signal sufficiently close to the phase of the input image signal as shown in FIG. That which the clock signal is adjusted to the optimum phase, can be supplied to the adjusted clock signal [Phi _H to the shift register (2).

Thus, according to this device, the phase of the clock signal is adjusted by the adjusting means, whereby the phase with the pixel can be matched, and the display of the image signal from the computer or the like can be performed favorably. .

It should be noted that the drive pulse signals φ _{H1 to} φ _Hm output from the shift register (2) in the above-described device are the clock signal φ
It is generated every time _H is inverted.

The selection of the signal by the multiplexer (8) is performed, for example, by supplying a test image signal of the highest resolution that is changed to white / black for each pixel to the input terminal (1), and performing switching control while visually confirming the displayed image. This can be achieved by supplying a control signal for sequentially switching the multiplexer (8) through the terminal (10) and fixing the control signal in a state where the displayed image is optimal.

FIG. 3 shows another example, in which the above-described phase adjustment of the clock signal can be automatically performed. Incidentally, in case this embodiment is for driving a so-called line-sequential, after the image signal from the input terminal (1) is sampled by the switching element M _a1 ~M _am, was held by the buffer amplifier B _a1 .about.B _am, For example, the switching elements M _{b1 to} M _bm that are turned on by the horizontal blanking pulse H _BLK
In being synchronized it is supplied to the signal line L ₁ to L m through buffer amplifier B _b1 .about.B _bm. In this case, the essential operation is the same as in the first embodiment.

That is, in the figure, one end of the second switching element M _X1 ~M _Xm is connected to the signal line L ₁ to L m, these elements
Output terminals of the shift register (11) are connected to control terminals of M _{X1 to} M _Xm , respectively. The start signal will be described later in the shift register (11) X _S and the clock signal [Phi _X is supplied. The other ends of the switching elements M _{X1 to} M _Xm are connected to each other, and a signal at this connection point is extracted.

The extracted signal is supplied to a comparison circuit (14) through a buffer amplifier (12) and a DC conversion circuit (13), and is compared with, for example, a reference potential from a terminal (15). Supplied to This count value is supplied to the control terminal of the phase adjusting means (18) through the latch circuit (17). Here, the phase adjusting means (18) may be the above-mentioned delay means (7a) to (7d) and the multiplexer (8), but in the case of automation, the number of stages can be further increased or a variable delay line can be used. . Other configurations are the same as in the first embodiment.

In this device, for example, an image signal of the highest resolution as shown in FIG. 4A is supplied to the input terminal (1),
Shift register (2) from the figure B, as shown in a drive pulse signal phi _H1 to [phi] _Hm is output by the horizontal blanking pulse H _BLK as shown in C in the drawing is supplied, the signal line L ₁ ~ The above image signal is sampled and supplied to Lm.

The start signal X _S and the clock signal to the shift register (11) in this state corresponding to, for example, a horizontal synchronization signal Φ
By the clock signal [Phi _X twice the period of the _H is supplied from the shift register (11) is a pulse signal phi _X1 to [phi] _Xm as shown in Figure D is outputted. As a result, a signal as shown in FIG. 9E is taken out at the connection point at the other end of the switching elements M _{X1 to} M _Xm .

Here, the extracted signal is a driving pulse signal φ _H1 to
It becomes a high level as shown in E ₁ when the phase of phi _Hm coincides with the pixel, when the phase is shifted becomes low level as shown in E _2. Therefore, a level signal corresponding to a phase shift can be obtained by, for example, rectifying and smoothing this signal to make it DC. Therefore, the phase can be automatically adjusted using this signal.

That is, for example, when the phase adjustment circuit (18) adjusts the phase in five steps by the configuration of the delay means (7a) to (7d) and the multiplexer (8), the counter (16) is set to 1 to 5
When the DC signal level is equal to or lower than the reference level, the comparator (14) outputs and the counter (16) is increased by "1". As a result, when the DC signal level is equal to or lower than the reference level, the counter (16) is incremented by "1", and the selection in the multiplexer (8) is sequentially switched. When the signal level exceeds the reference level, no output is obtained from the comparison circuit (14), the counter (16) is immobilized, and the selection of the multiplexer (8) is fixed.

Therefore, for example, when the signal level becomes higher than the reference level during five adjustment periods, the counter (16) is immobilized thereafter,
The phase-adjusted clock signal is supplied to the shift register (2). After the end of the adjustment period, the count value of the counter (16) is latched by the latch circuit (17) so that a malfunction does not occur thereafter. Even if the number of stages in the phase adjustment circuit (18) is further increased, the counter (16)
It can be applied by increasing the number of counts in the same manner.

Alternatively, when the phase adjustment circuit (18) is, for example, a variable delay line of a voltage control type, the counter (16) is an up / down counter, and the previous signal level is held and supplied to the terminal (15). When the signal level is higher than the previous value, the counter (16) is increased by "1", and when the signal level is lower than the previous value, the counter (16) is decreased by "1". The count value of the counter (16) is D / A converted, for example, and supplied to the control terminal of the variable delay line.

According to this, the phase of the clock signal can be adjusted so that the signal level becomes maximum. Also in this case, after the end of the adjustment period, the value of the counter (16) is changed to the value of the latch circuit (1).
The latched value is D / A-converted and supplied to the variable delay line.

Thus, according to this example, the phase adjustment of the clock signal can be automated.

The above-described automatic adjustment may be repeatedly performed for each vertical blanking period.

〔The invention's effect〕

According to the present invention, the phase of the clock signal is adjusted by the adjusting means, so that the phase with the pixel can be matched, and the display of an image signal from a computer or the like can be performed well. .

[Brief description of the drawings]

FIG. 1 is a block diagram of one example of the present invention, FIG. 2 is a diagram for explaining the same, FIG. 3 is a block diagram of another example, FIG. 4 is a diagram for explaining the same, FIGS. FIG. 7 is a diagram for explaining a conventional apparatus. L ₁ to L m vertical signal lines, G ₁ ~G _n gate lines, M ₁₁ ~Mnm, M ₁
~Mm switching element, C ₁₁ ~Cnm liquid crystal cell, (1)
Is an input terminal, (2) and (4) are shift registers, (5) is a synchronization separation circuit, (6) is a clock generation circuit, and (7a) to (7a) to
(7d) is a delay means, and (8) is a multiplexer.

Claims (1)

(57) [Claims] A plurality of first signal lines arranged in parallel in a vertical direction and a plurality of second signal lines arranged in parallel in a horizontal direction; In a liquid crystal display device in which a liquid crystal cell is provided at each intersection of two signal lines via a selection element, a shift register corresponding to the first signal line is provided, and a clock signal is separated from an input signal. The input signal is supplied to the shift register, the input signal is sampled by the output signal of the shift register, supplied to the first signal line, and the phase of the clock signal for driving the shift register is adjusted. A liquid crystal display device, wherein the phase of the clock signal can be adjusted so that a display image based on the input signal is best.