JP2676916B2 - Liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device that displays images by arranging liquid crystal display elements in an XY matrix, for example.

[Summary of the Invention]

The present invention relates to a liquid crystal display device, in which a second signal line for selecting a horizontal pixel column is reset to a predetermined potential at an arbitrary timing to regulate a signal delay on the signal line, and a vertical resolution due to the signal delay. It is intended to display a good image by eliminating the deterioration.

[Conventional technology]

For example, it has been proposed to display a television image using liquid crystal (see Japanese Patent Laid-Open No. 59-220793).

That is, in FIG. 3, (1) is an input terminal to which a video signal of the television is supplied, and signals from this input terminal (1) are switching elements M ₁ , M _2, ... It is supplied to the vertical (Y-axis) direction of the line L _1, L ₂ ··· L _m through _m. Note that m is horizontal (X
This is a number corresponding to the number of pixels in the (axis) direction. Further, an m-stage shift register (2) is provided, and a horizontal start signal H _S corresponding to a horizontal synchronizing signal and a clock signal Φ _{H that} is m times the horizontal frequency are supplied to the shift register (2). 2) Drive pulse signals φ _H1 and φ _H2 sequentially scanned by the clock signal φ _H from each output terminal
... φ _Hm is supplied to each control terminal of the switching elements M _{1 to} Mm. The low potential (V _SS ) and the high potential (V _DD ) are supplied to the shift register (2), and drive pulses of these two potentials are formed.

Also each example N-channel FE each line L ₁ ~L _m
Switching elements M ₁₁ consisting of _{T, M 21 ··· M n1,} M 12, M 22
・ ・ ・ M _n2 , ・ ・ ・ M _1m , M _2m・ ・ ・ M _nm are connected at one end. Note that n is a number corresponding to the number of horizontal scanning lines. The other ends of the switching elements M _{11 to} M _nm are respectively connected to the liquid crystal cell C ₁₁ ,
Connected to the target terminal (3) through C ₂₁ ... C _nm .

Further, an n-stage shift register (4) is provided, and a vertical start signal V _S corresponding to a vertical synchronizing signal and a clock signal Φ _V having a horizontal frequency are supplied to the shift register (4). Drive pulse signal φ sequentially scanned by the clock signal Φ _V from each output terminal
_V1 , φ _V2 ... φ _Vn is the gate line G ₁ in the horizontal (X-axis) direction,
G ₂ ··· G _n through the switching element M ₁₁ ~M _nm in the X-axis direction each column of _{(M 11 ~M 1m), (} M 21 ~M 2m) ··· (M n1 ~
It is supplied to each control terminal for each M _Nm ). Note that the shift register (4) is the same as the shift register (2).
V _SS and V _DD are supplied.

That is, in this circuit, the shift register (2),
In (4), clock signals Φ _H and Φ as shown in FIGS.
_V is supplied. The shift register (2) outputs φ _H1 to φ _Hm for each pixel period as shown in FIG. 6C, and the shift register (4) outputs _{1 H 1} to φ _Hm as shown in FIG.
Φ _V1 to φ _Vn are output for each horizontal period. Further, the input terminal (1) is supplied with a signal as shown in FIG.

When φ _V1 and φ _H1 are output, the switching elements M ₁ and M _{11 to} M _1m are turned on, and the input terminal (1) → M ₁
→ L ₁ → M ₁₁ → C ₁₁ → The current path of the target terminal (3) is formed, and the potential difference between the signal supplied to the input terminal (11) and the target terminal (3) is supplied to the liquid crystal cell C _11. . Therefore, the charge corresponding to the potential difference due to the signal of the first pixel is sampled and _{held in} the capacity of the cell C ₁₁ . The light transmittance of the liquid crystal is changed according to this charge amount. The same operation is sequentially performed for the cells C _{12 to} C _nm , and at the time when the next field signal is supplied, each cell C ₁₁
The charge amount of ~ C _nm is rewritten.

In this way, the light transmittances of the liquid crystal cells C _{11 to} C _nm are changed corresponding to each pixel of the video signal, and this is repeated sequentially to display the television video.

Further, in the case of performing display using liquid crystal, an AC drive is generally used in order to extend the reliability and the life. For example, in the display of a television image, a signal obtained by inverting a video signal for each field or frame is supplied to the input terminal (1). In a liquid crystal display device, a signal is inverted every horizontal period in order to prevent shooting in a vertical direction of display.
That is, the input terminal (1) is supplied with a signal which is inverted every horizontal period and inverted every field or frame as shown in FIG. 4E.

By the way, in such a device, the time width of the drive pulse signals φ _{H1 to} φ _Hm output from the shift register (2) is In the case of the NTSC system, it is about 100 nsec. On the other hand, when applied to high-definition television, for example, the time of the horizontal effective screen period is about 1/2, and the number of horizontal pixels is about 3 times, so the time width of the pulse is about
It will be shortened to 1/6.

On the other hand, the signals passed through the switching elements M _{1 to} M _m during the period of the drive pulse signals φ _{H1 to} φ _Hm are supplied to the switching elements M _{11 to} M _nm through the lines L _{1 to} L _m. The wiring capacitance of several tens to several tens of pF exists in L _{1 to} L _m ,
Therefore, the signal charges this capacity and the switching element M ₁₁
~ M _nm will be supplied.

In this case, the above-described charging requires a signal supply time of 10
If it is about 0nsec, it can be raised to the signal potential,
If this time is shortened to 1/6, charging is not sufficiently performed when the signal is at a high potential (white or black), and there is a possibility that only an unclear display image with insufficient contrast or the like is obtained. In the case of high-definition television, the wiring capacity is further increased.

[Problems to be solved by the invention]

On the other hand, the input video signal is driven by driving pulses φ _{H1 to} φ _Hm.
The lines L _{1 to} L _m are sufficiently charged by sampling and parallelizing each of the periods and supplying the parallelized signals to the lines L _{1 to} L _m at any time during an arbitrary load period. How to do so is being considered.

That is, in FIG. 5, the video signal supplied to the input terminal (1) is the CMOS element M _a1 ,
Commonly supplied to M _a2 ... M _am , these elements M _{a1 to} M _am
Drive pulse signals Φ _{H to} Φ _Hm from the shift register (2) are supplied to the respective control terminals of the.

The signals from these elements M _{a1 to} M _am are respectively supplied to the non-inverting inputs of the buffer amplifiers B _a1 , B _a2 ... B _am forming the holding means, and these buffer amplifiers B _{a1 to} B _am are supplied.
Is fed back to the inverting input. The signals from these buffer amplifiers B _{a1 to} B _am respectively constitute loading means.
CMOS devices M _b1 , M _b2 ... M _bm are supplied to these devices M
The horizontal blanking pulse (H _BLK ) from the terminal (5) is supplied as a load pulse to the control terminals _{b1 to} M _bm .

The signals from these elements M _{b1 to} M _bm are supplied to the non-inverting inputs of the amplifiers B _b1 , B _b2 ... B _bm as buffer circuits, respectively, and the outputs of these buffer amplifiers B _{b1 to} B _bm are inverted. It is fed back to the input. The signals from these buffer amplifiers B _{b1 to} B _bm are supplied to lines L _{1 to} L _m in the vertical (Y-axis) direction, respectively. Further, the following configuration is the same as the device described in the related art.

Therefore, in this device, when the video signal as shown in FIG. 6A is supplied to the terminal (1), the element M _a1
To M _am are conducted as shown in FIG. B, and the video signals during this conduction period are sampled and buffer amplifiers B _{a1 to} B _am
Hold on. On the other hand, the elements M _{b1 to} M _bm are shown in FIG.
It is conducting a horizontal blanking timing as shown in, respectively held signal buffer amplifier B _b1
It is supplied (loaded) to the lines L _{1 to} L _m through B _bm .
Thereafter, an image is displayed in the same manner as in the related art.

However, in the above-mentioned device, the wirings forming the gate lines G _{1 to} G _n are distributed constants due to the gate capacitances and wiring capacitances of the selection elements M _{11 to} M _nm to be connected. Therefore, for example, when the input video signals as shown in FIG. 7A are synchronized and supplied to the signal lines L _{1 to} L _m as shown in FIG. 7B, the gate lines G _{1 to} G _{n are} Although the drive pulse signals φ _V1 φ _{to Vn} supplied to the above-mentioned become a regular rectangular wave at the end on the shift register (4) side as shown in FIG.
At the opposite end, the waveform becomes dull as shown in FIG. Due to the delay caused by this dullness, the video signal is supplied to the liquid crystal cell through the switching element of the previous column at the time of supplying the next horizontal pixel column, and for example, the shift register shown by hatching in FIG. In case (4), the vertical resolution is deteriorated in the opposite range.

On the other hand, it is possible to reduce the effect of the above delay by lengthening the transition time T _m between the adjacent drive pulse signals φ _{V1 to} φ _Xn, but this shortens the effective write time T _A of the signal. It is not desirable to do.

The present application has been made in view of such points.

[Means for solving the problem]

The present invention includes a plurality of first signal lines L ₁ , L ₂ ... L _m arranged in parallel in the vertical direction and a plurality of second signal lines G ₁ arranged in parallel in the horizontal direction. , G ₂ ... G _m are provided, and the selection element M is provided at each intersection of these first and second signal lines.
_In a liquid crystal display device in which liquid crystal cells C ₁₁ , C ₁₂ ... C _nm are provided through ₁₁ , M ₁₂ ... M _nm , vertical scanning means (shift register (shift register ( 4)) is provided on one end side of the second signal line, and the other end side of the second signal line is connected to a predetermined reset potential via switches (elements M _{X1 to} M _Xn ) (ground). Then, the potential of the second signal line is reset by turning on the switch during an arbitrary transition period (T _m ) of the drive signal from the vertical scanning means. is there.

[Action]

According to this, since the potential of the second signal line is reset during the transition period of the drive signal, the delay of the signal on the signal line is regulated, and the good display without resolution deterioration due to the signal delay can be achieved with a simple configuration. Images can be obtained.

〔Example〕

In FIG. 1, the ends of the gate lines G _{1 to} G _n on the opposite side of the shift register (4) are respectively switching elements M _X1 ,
M _X2 ... M _Xn are connected to each other, and this connection point is V
It is connected to the _SS potential terminal (6). This element M _X1 ~ M
The control terminals of _Xn are commonly connected, and this connection point is connected to the terminal (7) to which the pulse signal φ _R corresponding to the transition period of the drive pulse signals φ _{V1 to} φ _Vn is supplied.

Therefore, in this device, in the same manner as described above, for example, when the input video signals as shown in FIG. 2A are synchronized as shown in FIG. 2B and supplied to the respective signal lines L _{1 to} L _m ,
Drive pulse signals φ _{V1 to} φ supplied to the gate lines G _{1 to} G _n
Vn is as shown in FIG. 7C at the end on the shift register (4) side. On the other hand, the terminal (7) has
A pulse signal φ _R corresponding to the transition period T _m between adjacent drive pulse signals φ _{V1 to} φ _Vn as shown in FIG.
As a result, the switching element M _{X1 is} generated by the pulse signal φ _R.
When ~ M _Xn is turned on, the ends of the gate lines G _{1 to} G _n on the opposite side of the shift register (4) are forcibly reset to V _ss, and the drive pulse signals φ _{V 1} ~ φ _Vn is the same E
As shown in, the delay due to the blunting of the waveform is regulated.

That is, this prevents the video signal from being supplied to the liquid crystal cell through the switching element in the previous column at the time of supplying the next horizontal pixel column, and in the range on the side opposite to the shift register (4) due to the dullness of the drive pulse signal. The deterioration of the vertical resolution of is eliminated.

In this way, according to this device, the potential of the second signal line is reset during the transition period of the drive signal, so that the delay of the signal on the signal line is regulated, and the resolution is not deteriorated due to the signal delay with a simple configuration. It is possible to obtain various display images.

In the above device, switching elements M _{11 to} M _nm
Since the switching elements M _{X1 to} M _Xn for resetting have been described as NMOS elements by _adopting NMOS as the NMOS element, the polarity of the signals of each time chart is reversed when the switching elements M _{11 to} M _nm are PMOS elements. Become. In this case, the reset switching elements M _{X1 to} M _Xn may also be configured by PMOS elements, and the terminal (6) may be pulled up to V _DD instead of V _SS for resetting.

Further, the above-mentioned device can be applied to a dot-sequential type liquid crystal display device.

〔The invention's effect〕

According to the present invention, the potential of the second signal line is reset during the transition period of the drive signal, so that the delay of the signal on the signal line is regulated, and the resolution is not deteriorated due to the signal delay with a simple configuration. You can now get the display image.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 to 8 are diagrams for explaining a conventional device. L _{1 to} L _m are vertical signal lines, G _{1 to} G _n are gate lines, M _{a1 to} M _am , M _b1
〜 M _bm , M _x1 〜 M _x1 , M ₁₁ 〜 M _nm is a switching element, B _a1 〜 B
_am , B _{b1 to} B _bm are buffer amplifiers, C _{11 to} C _nm are liquid crystal cells,
(1) (3) (5) (6) (7) are terminals, (2) (4)
Is a shift register.

Claims (1)

(57) [Claims] 1. A plurality of first signal lines arranged in parallel in the vertical direction and a plurality of second signal lines arranged in parallel in the horizontal direction are provided. In a liquid crystal display device in which a liquid crystal cell is provided at each intersection of two signal lines via selection elements, a vertical scanning means for driving the second signal line is provided at one end side of the second signal line. At the same time, the other end of the second signal line is connected to a predetermined reset potential via a switch, and the switch is turned on during an arbitrary transition period of the drive signal from the vertical scanning means to cause the second signal to flow. A liquid crystal display device characterized in that the electric potential of the signal line is reset.