JP2826914B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2826914B2 JP2826914B2 JP3261132A JP26113291A JP2826914B2 JP 2826914 B2 JP2826914 B2 JP 2826914B2 JP 3261132 A JP3261132 A JP 3261132A JP 26113291 A JP26113291 A JP 26113291A JP 2826914 B2 JP2826914 B2 JP 2826914B2
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- region
- conductivity type
- reverse
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明の半導体装置の構造に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device according to the present invention.
【0002】[0002]
【従来の技術】周知のように、半導体装置の特性改善、
特に、順方向特性、逆方向特性、スイッチング特性につ
いての改善のため、開発が進められ、種々の構造が提案
されている。2. Description of the Related Art As is well known, the characteristics of semiconductor devices have been improved.
Particularly, in order to improve forward characteristics, reverse characteristics, and switching characteristics, development has been promoted and various structures have been proposed.
【0003】図1に従来の半導体装置についての断面構
造図を示す。図1は本発明者等が特願平3−11534
1「ショットキバリア半導体装置」により発明した構造
であり、1は一導電型半導体領域、例えば、N型シリコ
ン半導体、1′は低抵抗の一導電型半導体領域、例え
ば、N+型シリコン半導体、2は逆導電型半導体領域、
例えば、P+型シリコン半導体、3は一電極金属、4は
オ−ミック電極金属、5はトレンチ溝による凹部、6は
凸部、Aはアノ−ド、Cはカソ−ドである。FIG. 1 is a sectional structural view of a conventional semiconductor device. FIG. 1 shows that the present inventors have filed Japanese Patent Application No. Hei 3-11534.
1 is a structure invented by a "Schottky barrier semiconductor device", wherein 1 is a one conductivity type semiconductor region, for example, an N-type silicon semiconductor, 1 'is a low resistance one conductivity type semiconductor region, for example, an N + type silicon semiconductor, 2 Is a reverse conductivity type semiconductor region,
For example, a P + type silicon semiconductor, 3 is a one-electrode metal, 4 is an ohmic electrode metal, 5 is a concave portion formed by a trench, 6 is a convex portion, A is an anode, and C is a cathode.
【0004】前記の特願平3−115341では、一電
極金属3としてショットキバリア接触を形成する公知の
金属を選択し、順方向特性を改善すると共に、逆バイ
(2)アス時には一導電型半導体領域1と一電極金属3
が形成するショットキバリア接触面eから延びる空間電
荷層を逆導電型半導体領域2が形成するPN接合からの
空間電荷層で両側からはさみ込むことにより、ある逆電
圧以上で3方向の空間電荷層が併合し、接触面eにかか
る電界強度Eが低い値におさえられ逆漏れ電流を改善す
る。なお、このような効果は接触面eがショットキバリ
ア接触を形成する場合に限らず、オ−ミック接触であっ
ても同様である。In the above-mentioned Japanese Patent Application No. 3-115341, a well-known metal that forms a Schottky barrier contact is selected as the one-electrode metal 3 to improve the forward characteristics, and at the time of reverse bias (2) assault, use one conductivity type semiconductor. Region 1 and one electrode metal 3
Is formed by sandwiching the space charge layer extending from the Schottky barrier contact surface e formed by the space charge layer from the PN junction formed by the opposite conductivity type semiconductor region 2 from both sides. As a result, the electric field strength E applied to the contact surface e is suppressed to a low value, and the reverse leakage current is improved. Note that such an effect is not limited to the case where the contact surface e forms a Schottky barrier contact, and the same applies to the case of ohmic contact.
【0005】しかして、セルサイズCW内における有効
なチャネル幅を決定する相隣る逆導電型半導体領域2の
最近接距離Wとすると、現在の半導体製造技術では、順
電流有効領域比 α=W/CW<0.2〜0.4 程度と
ならざるを得ない。従って、必要とする順電流を決定す
る最近接距離Wを確保するためにはセルサイズCWは極
めて大きくなる。即ち、特性面で優れていても半導体チ
ップの形状が大きくなり、高価な半導体装置となる。[0005] Assuming that the closest distance W between adjacent opposite conductivity type semiconductor regions 2 that determines an effective channel width within the cell size CW, in the current semiconductor manufacturing technology, the forward current effective region ratio α = W /CW<0.2-0.4. Therefore, the cell size CW becomes extremely large in order to secure the closest distance W for determining the required forward current. That is, even if the semiconductor chip is excellent in characteristics, the shape of the semiconductor chip becomes large, and the semiconductor device becomes expensive.
【0006】[0006]
【発明の目的】本発明は前記せる従来装置の問題点を解
消し、逆漏れ電流、及び順電圧降下が小さく、高速でか
つ、低損失の半導体装置を順電流有効領域比αの大きな
構造で得ることを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the conventional device, and realizes a high-speed, low-loss semiconductor device having a small reverse leakage current and a forward voltage drop with a structure having a large forward current effective area ratio α. The purpose is to gain.
【0007】[0007]
【実施例】本発明の実施例を図2の断面構造図に示し、
図1と同一符号は同一部分をあらわす。2aは凸部6の
上部に形成された第1の逆導電型半導体領域、2bは凸
部6の底部及び側部の下方にわたり形成された第2の逆
導電型半導体領域であり、第1の領域2aと第2の領域
2bがはさむ凸部6の側部に一電極金属3によりショッ
トキ又はオ−ミックの接触面e′を形成する。An embodiment of the present invention is shown in the sectional structural view of FIG.
1 denote the same parts. Reference numeral 2a denotes a first reverse conductivity type semiconductor region formed above the convex portion 6, and 2b denotes a second reverse conductivity type semiconductor region formed below the bottom portion and the side portion of the convex portion 6; A single electrode metal 3 forms a Schottky or ohmic contact surface e 'on the side of the convex portion 6 between the region 2a and the second region 2b.
【0008】具体的には、N型シリコン半導体基板にト
レンチ溝を公知の方法で形成し、凹部5及び凸部6を設
けて、第1の逆導電型半導体領域2a、及び第2の逆
(3)導電型半導体領域2bの位置にボロン原子をイオ
ン注入法又は気相拡散法でP+領域として形成する。次
いで、一電極金属3を蒸着法により形成した。More specifically, a trench is formed in an N-type silicon semiconductor substrate by a known method, a concave portion 5 and a convex portion 6 are provided, and a first reverse conductivity type semiconductor region 2a and a second reverse conductive type are formed. 3) A boron atom is formed as a P + region at the position of the conductive semiconductor region 2b by ion implantation or vapor phase diffusion. Next, one-electrode metal 3 was formed by an evaporation method.
【0009】第2の逆導電型半導体領域2bは凸部6の
底部及び側部の一部に及んで形成することが望ましい
が、少なくとも底部の角部に形成する必要がある。The second opposite conductivity type semiconductor region 2b is desirably formed over a part of the bottom and side portions of the projection 6, but it is necessary to form it at least at a corner of the bottom.
【0010】各部の形状については、第1の領域2aと
第2の領域2bの最近接距離WL、相隣る第2の領域の各
2b間の最近接距離L、接触面e′から延びる零バイア
ス時の空間電荷層の深さWbi、絶縁破壊時の空間電荷層
WB、第2の領域2bにおけるWbiの位置f点での接線
が接触面e′となす角度θとすると、WL及びLが2Wb
iより小さいか、又は、少なくとも2WB以内であり、θ
を60度≦θ≦180度に形成することが好ましい。こ
のようにして、アノ−ドA及びカソ−ドC間に、第1の
領域2aと、それぞれの第2の領域2bによりはさまれ
た2つの金属と半導体の接触面e′をもつ一導電型半導
体1を基体とする半導体装置を形成する。即ち、図2に
おける凸部6の左右それぞれに、接触面e′をもつ、図
1と同様の動作原理による半導体装置を形成できる。Regarding the shape of each part, the closest distance WL between the first area 2a and the second area 2b, the closest distance L between each adjacent second area 2b, and the zero extending from the contact surface e '. Assuming that the depth Wbi of the space charge layer at the time of bias, the space charge layer WB at the time of breakdown, and the angle θ between the tangent at the point f of Wbi in the second region 2b and the contact surface e ′, WL and L are 2Wb
smaller than i or at least within 2WB, θ
Is preferably formed such that 60 degrees ≦ θ ≦ 180 degrees. Thus, between the anode A and the cathode C, one conductive layer having a first region 2a and two metal-semiconductor contact surfaces e 'sandwiched by the respective second regions 2b. A semiconductor device having the mold semiconductor 1 as a base is formed. That is, it is possible to form a semiconductor device having a contact surface e 'on each of the right and left sides of the convex portion 6 in FIG.
【0011】図1の接触面eと図2の接触面e′を同一
面積にすると、図2の本発明構造においては順電流有効
領域比αを図1の従来構造の2倍にできる。When the contact surface e in FIG. 1 and the contact surface e ′ in FIG. 2 have the same area, the forward current effective area ratio α can be doubled in the structure of the present invention in FIG. 2 as compared with the conventional structure in FIG.
【0012】一導電型半導体表面を凹凸状とするトレン
チ溝の形成においては、複数個の短冊状配列トレンチ溝
により、前記の順電流有効領域比αを2倍とすることが
できるが、図3の平面構造図のように、複数個の島状配
列トレンチ溝の形成により、セルの3次元寸法の工夫に
より、有効領域比αを4倍以上とすることも可能であ
る。In the formation of a trench having a one-conductivity-type semiconductor surface with irregularities, the forward current effective area ratio α can be doubled by a plurality of strip-shaped trenches. By forming a plurality of island-shaped trench grooves as shown in the plan view of FIG. 7, the effective area ratio α can be made four times or more by devising the three-dimensional dimensions of the cell.
【0013】以上のごとく、本発明構造は、図1での説
明による逆漏れ電流抑制効果をそ(4)こなうことな
く、接触面e′の拡大、即ち、セル内有効面積の増大が
できる。同一順電流に対し、接触面e′の電流密度を減
少でき、e′がショットキ接触である場合には、その順
電圧降下を低減し得る。又、電流密度を図1の従来構造
と同等とした場合にはチップ寸法を小さくでき、従って
安価な半導体装置を得る。As described above, according to the structure of the present invention, the contact surface e 'can be enlarged, that is, the effective area in the cell can be increased without exerting the effect of suppressing the reverse leakage current described in FIG. it can. For the same forward current, the current density at the contact surface e 'can be reduced, and when e' is a Schottky contact, the forward voltage drop can be reduced. When the current density is made equal to that of the conventional structure shown in FIG. 1, the chip size can be reduced, so that an inexpensive semiconductor device can be obtained.
【0014】又、接触面e′をオ−ミック接触とした場
合は、第1の領域2a及び第2の領域2bの形成にもと
づき一導電型半導体領域内に電子ポテンシアル高さに応
じた電気特性を示し、接触面e′をショットキ接触とし
た場合と同様の順方向、逆方向の整流特性を観測でき
た。When the contact surface e 'is in ohmic contact, the electrical characteristics corresponding to the electron potential height in the one conductivity type semiconductor region based on the formation of the first region 2a and the second region 2b. And the same rectifying characteristics in the forward and reverse directions as in the case where the contact surface e ′ was in Schottky contact were observed.
【0015】図2の断面構造におけるトレンチ溝、即
ち、凹部5の形状は台形、長方形に限定されず、又、第
2の領域2bの形状や各部の距離、寸法関係も実施例に
限定されるものではない。その他の変形、変換、付加等
の変更についても本発明の要旨の範囲で本願権利に包含
される。In the sectional structure of FIG. 2, the shape of the trench groove, that is, the shape of the concave portion 5 is not limited to a trapezoid or a rectangle, and the shape of the second region 2b, the distance of each part, and the dimensional relationship are also limited to the embodiment. Not something. Other modifications, conversions, additions, and other changes are also included in the rights of the present application within the scope of the present invention.
【0016】[0016]
【発明の効果】以上、説明したように、順方向特性、逆
方向特性、及びスイッチング特性の優れた半導体装置を
順電流有効領域比を増大した構造で得ることができ、シ
ョットキ又はオ−ミック接触面の電流密度の低減、又は
チップサイズの減少による経済化を達成でき、パワ−用
をはじめ各種の産業機器に利用される半導体装置に適用
し、その効果極めて大なるものである。As described above, a semiconductor device having excellent forward characteristics, reverse characteristics, and switching characteristics can be obtained with a structure in which the effective area ratio of the forward current is increased, and the Schottky or ohmic contact can be obtained. It is possible to achieve economy by reducing the current density on the surface or reducing the chip size, and it is very effective when applied to semiconductor devices used for various industrial equipment including power.
【図1】従来の半導体装置の断面構造図である。FIG. 1 is a sectional structural view of a conventional semiconductor device.
【図2】本発明の実施例を示す断面構造図である。FIG. 2 is a sectional structural view showing an embodiment of the present invention.
【図3】(5)本発明の実施例を示す平面構造図であ
る。FIG. 3 is a plan view showing an embodiment of the present invention.
1 一導電型半導体領域 1′ 低抵抗の一導電型半導体領域 2 逆導電型半導体領域 2a 第1の逆導電型半導体領域 2b 第2の逆導電型半導体領域 3 一電極金属 4 オ−ミック電極金属 5 凹部 6 凸部 A アノ−ド C カソ−ド e、e′接触面 f 接点 CW セルサイズ W 相隣る2の最近接距離 WL 2aと2b間の最近接距離 Wbi 零バイアス時の空間電荷層の深さ WB 絶縁破壊時の空間電荷層幅 L 相隣る2bの最近接距離 θ 角度 REFERENCE SIGNS LIST 1 one conductivity type semiconductor region 1 ′ low resistance one conductivity type semiconductor region 2 reverse conductivity type semiconductor region 2 a first reverse conductivity type semiconductor region 2 b second reverse conductivity type semiconductor region 3 one electrode metal 4 ohmic electrode metal 5 Concave part 6 Convex part A Anode C Cathode e, e 'Contact surface f Contact CW Cell size W Closest distance between two neighboring WLs Closest distance between 2a and 2b Wbi Space charge layer at zero bias Depth WB Space charge layer width at the time of dielectric breakdown L Closest distance of adjacent 2b θ angle
Claims (1)
ンチ溝を形成した半導体装置において、凸部の上部に第
1の逆導電型半導体領域、凸部の底部又は側部の一部を
含む底部に第2の逆導電型半導体領域を形成し、第1と
第2の逆導電型半導体領域がはさむ凸部の両側部にショ
ットキ又はオーミック接触を形成する金属層を設けたこ
とを特徴とする半導体装置。1. A semiconductor device in which a trench having a one-conductivity-type semiconductor surface with irregularities is formed, wherein a first reverse-conductivity-type semiconductor region, a bottom of the protrusion, or a part of a side portion is included above the protrusion. A second reverse conductivity type semiconductor region is formed at the bottom, and a metal layer for forming a Schottky or ohmic contact is provided on both sides of the projection sandwiching the first and second reverse conductivity type semiconductor regions. Semiconductor device.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3261132A JP2826914B2 (en) | 1991-09-12 | 1991-09-12 | Semiconductor device |
US07/870,268 US5262669A (en) | 1991-04-19 | 1992-04-17 | Semiconductor rectifier having high breakdown voltage and high speed operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3261132A JP2826914B2 (en) | 1991-09-12 | 1991-09-12 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0575098A JPH0575098A (en) | 1993-03-26 |
JP2826914B2 true JP2826914B2 (en) | 1998-11-18 |
Family
ID=17357541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3261132A Expired - Fee Related JP2826914B2 (en) | 1991-04-19 | 1991-09-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2826914B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11297994A (en) * | 1998-04-07 | 1999-10-29 | Hitachi Ltd | Semiconductor device |
JP4097417B2 (en) | 2001-10-26 | 2008-06-11 | 株式会社ルネサステクノロジ | Semiconductor device |
JP5621198B2 (en) * | 2009-03-04 | 2014-11-05 | 日産自動車株式会社 | Semiconductor device |
JP5511019B2 (en) * | 2011-11-04 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2015076592A (en) * | 2013-10-11 | 2015-04-20 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method of the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4568958A (en) * | 1984-01-03 | 1986-02-04 | General Electric Company | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
JPS6212169A (en) * | 1985-07-09 | 1987-01-21 | Matsushita Electronics Corp | Semiconductor device |
JP3061342U (en) * | 1999-02-09 | 1999-09-17 | ビッグボーン商事 株式会社 | Handbag with pocket for mobile phone |
-
1991
- 1991-09-12 JP JP3261132A patent/JP2826914B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0575098A (en) | 1993-03-26 |
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