JP2641856B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a hole required for electrode wiring of a semiconductor element.

[Conventional technology]

2. Description of the Related Art A semiconductor integrated circuit device, particularly an integrated circuit device mounted on a silicon semiconductor substrate, has rapidly increased in capacity and density with the progress of manufacturing process technology, particularly fine processing technology.

However, in the development of such fine processing technology, the area margin of the pattern in view of the misalignment between the circuit formation patterns accompanying the step of transferring the circuit formation patterns greatly inhibits the high density of the integrated circuit. It has been a factor. Hereinafter, this point will be described in detail.

In general, the manufacture of a semiconductor device includes a known photoresist process for transferring a circuit formation pattern to the surface of a semiconductor substrate, and a process of processing the semiconductor surface using the photoresist as a mask. Here, the transfer of the circuit formation pattern requires several photoresist masks, and there are several stages of processing steps accordingly. In each of the processing steps, it is necessary to form a desired processing pattern in a form that matches the processing pattern before that. However, the transfer of the circuit forming pattern requires alignment, and the alignment deviation of the pattern due to the alignment deviation cannot be avoided. This misalignment largely depends on the photoresist technology, but is currently about 0.1 to 0.3 μm. Therefore,
An area margin is provided between the circuit forming patterns in anticipation of the misalignment. This area margin has become apparent as a factor inhibiting high density, particularly in an integrated circuit in which an insulated gate field effect transistor whose density is being advanced is an active element. In such a situation, a margin area between circuit formation patterns accompanying formation of a hole, which is indispensable for electrode wiring of an integrated circuit, is a particularly strong inhibiting factor for hole density.

As shown in FIG. 3, the conventional opening is formed by selectively forming an insulating element isolation region 302 selectively formed on the surface of a silicon semiconductor substrate 301 and a gate film of an insulated gate field effect transistor.
303, gate electrode 304 and source / drain diffusion region 305
Is formed by forming a hole in the interlayer insulating film 306 by using a known lithography technique and an etching technique using a photoresist. After this, the wiring 307 is formed and electrically connected to the diffusion region 305 to form an active element. Here, the protective film 308 is coated in a final step to protect the semiconductor element.

In such a forming method, it is necessary to provide a sufficient area margin between the gate electrode 304 or the insulating element isolation region 302 and the opening in consideration of the misalignment in the lithography technique described above. For this reason, this area increases, and high density is hindered.

[Problems to be solved by the invention]

In the above-described conventional hole formation method, in the manufacture of such an integrated circuit element, the increase in the area of the circuit formation pattern due to the formation of the hole required for electrode extraction is inevitable, and the density of the circuit element is increased. Has the disadvantage that it does not proceed.

[Means for solving the problem]

A method of manufacturing a semiconductor device according to the present invention includes the steps of selectively forming a first conductive film on a semiconductor substrate via a first insulating film, and forming the first conductive film on a semiconductor substrate using the first conductive film as a mask. A step of selectively introducing an impurity to form an impurity region which is self-aligned with the first conductive film; and forming a second insulating film and forming a side wall insulating film on the side surface of the first conductive film by anisotropic etching. Forming a film and exposing a part of the impurity region; and forming a second conductive film extending on the sidewall insulating film in contact with the part of the impurity region;
A step of forming a third insulating film over the entire surface, a step of selectively forming a contact hole exposing a part of the second conductive film in the third insulating film, Forming a wiring extending over the third insulating film in contact with a portion thereof.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. Before that, a method of manufacturing a semiconductor device which is a reference to the present invention will be described with reference to FIGS. 1A to 1I. .

An insulating element isolation region 102 is provided on the surface of a silicon semiconductor substrate 101.
Is formed, and an insulating film 105 is formed so as to cover the upper surface of the gate electrode 104 formed on the gate insulating film 103 of the insulated gate field effect transistor (FIG. 1-b), and then n ⁺ diffusion is performed by arsenic ion implantation. The region 109 is formed (from 1-c to 1-c
Next, an insulating film 106 is formed so as to cover the side surface of the gate electrode 104 (FIGS. 1-e to 1-f). After that, an insulating film 107 different from the insulating film 105 and the insulating film 106 is formed by providing a window (FIGS. 1-g and 1-h).
8 (FIG. 1-i). Thus, the insulating film 10
5, 106, 107 are used as interlayer insulating films to electrically connect the source / drain diffusion region 109 and the wiring 108. Finally protective film
A semiconductor element that covers 110 and has a self-aligned opening is formed. In the first embodiment, the insulating element isolation region 102
The opening is formed in a state of self-alignment with the pattern of the gate electrode 104.

FIG. 4 to FIG. 11 are cross-sectional views showing manufacturing steps which are further reference to the present invention.

As shown in FIG. 4, after a silicon oxide film 402 for a gate film is formed on the surface of a P-type silicon substrate 401 by a thermal oxidation method so as to have a thickness of 100 to 200 °, polysilicon, polycide, or high melting point metal is used. After depositing a conductive film 403 such as by sputtering or CVD, an insulating film 404 such as silicon oxynitride is formed to a thickness of about 2000 to 4000 nm.

Next, as shown in FIG. 5, the lower insulating film 404 and the conductive film 403 were dry-etched using the photoresist layer 405 as a mask by a known lithography technique, and then used as an etching mask as shown in FIG. Photoresist layer 405
After removing arsenic ions 406, implantation energy 50-1
Implantation is performed under the conditions of 00 Kev and an implantation amount of 1 × 10 ¹⁵ ions / cm ² to form an n ⁺ diffusion region 407. Subsequently, as shown in FIG.
08: 2000-500 film thickness by CVD method with good step coverage
Deposit about 0Å. Here, as the insulating film 408, an insulating film
Silicon oxynitride of the same material as 404 or another insulating film may be used.

Thereafter, the insulating film 408 is etched by a highly anisotropic dry etching method until the insulating film 408 on the center of the n ⁺ diffusion region 407 is removed. Due to this high anisotropic etching, the insulating film 408 remains on the side walls of the conductive film 403 and the insulating film 404 as shown in FIG.

Subsequently, as shown in FIG. 9, an insulating film 409 is formed to a thickness of about 4000 A by a CVD method or a coating method. Here this insulating film 4
09 needs to be different from the insulating films 404 and 408. For example, when the insulating films 404 and 408 are formed of a silicon oxynitride film, the insulating film 409 may be formed of a silicon oxide film or a silicon nitride film.

Next, as shown in FIG. 10, etching is performed using the photoresist layer 410 as a mask in order to selectively remove the insulating film 409. This window opening may be either dry etching or wet etching. However, the insulating films 404 and 408 need to have a low etching rate and the insulating film 409 needs to have a high etching rate. For example, insulating films 404, 408
Is silicon oxynitride and the insulating film 409 is a silicon oxide film, an ammonium fluoride solution may be used as a wet etching chemical. Here, in the case of dry etching, a halogenated hydrocarbon gas containing iodine or bromine may be used. The opening formed in the insulating film 409 is for connecting to the n ⁺ diffusion region 407 through the opening surrounded by the insulating film 408, and high precision is not required for alignment. In this manner, the insulating film 409 at the opening is removed, and the portion of the silicon oxide film 402 for the thin gate film surrounded by the insulating film 408 is also removed. Then, as shown in FIG. 411 is formed.

As described above, the n-diffusion region 407 and the wiring 411 are formed through the previously transferred circuit formation pattern, that is, the self-aligned opening automatically formed by the conductive film 403 pattern serving as the gate electrode of the insulated gate field effect transistor. Are electrically connected.

FIG. 2 is a cross-sectional view of a semiconductor device manufactured by a method according to one embodiment of the present invention, and FIGS. 12 to 19 are cross-sectional views of main manufacturing steps showing one embodiment of the present invention. It is. As shown in FIG. 2, as in the case of the first embodiment shown in FIG. 1, the insulating element isolation region 202, the gate film 203 of the insulated gate field effect transistor, the gate electrode 204, the insulating A film 205 and an insulating film 206 are formed, and a thin conductive film is formed to cover a part of the insulating element isolation region 202 and a part of the insulating films 205 and 206. Insulating film 20
An insulating film 208 different from 5,206 is formed in a state where a window is provided above the thin conductive film 207, and a wiring 209 is provided. Thus, the source / drain diffusion region 210 and the wiring 209 are electrically connected via the thin conductive film 207, using the insulating films 205, 206, and 207 as interlayer insulating films. Finally, a semiconductor element having a self-aligned opening is formed by covering the protective film 211.

Next, a manufacturing method of one embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 12, a thick silicon oxide film is selectively formed on the surface of a P-type silicon substrate 201 by a thermal oxidation method to form an insulating element isolation region 202, and then a silicon oxide film 2 for a gate is formed.
03, a conductive film 204 and an insulating film 205 are formed. Here, these film thicknesses may be the same as the values described in the case of the second embodiment.

Next, as shown in FIG. 13, the insulating film 205 and the metal thin film 204 are formed using the photoresist layer 506 as a mask by a known lithography technique.
The After etching, as shown in FIG. 14, n ⁺ diffusion region
The 210 and the insulating film 206 are formed in the same manner as in the second embodiment.

Subsequently, anisotropic dry etching is performed so that the insulating film 206 remains on the side walls of the conductive film 204 and the insulating film 205 as shown in FIG. Thus, after exposing the surface of the n ⁺ diffusion region 210, the first
As shown in FIG. 6, the film thickness including the n-type effective impurity is 500 to
From the surface of the n ⁺ diffusion region 210 exposing the thin conductive film 207 such as a 1000-mm-thick polysilicon thin film layer or a high-melting-point metal-containing thin film layer, the insulating film 206 and the insulating film 205 and the insulating element isolation region 202 It is formed by patterning so as to extend. After this, an insulating film 208 is deposited or applied on the entire surface as shown in FIG. 17, and as shown in FIG. 18, only the region on the thin conductive film 207 is selectively removed using the photoresist 511 as a mask to open a window. After the wiring 209 is applied as shown in FIG.
To form

Also in the present embodiment, a self-aligned type automatically formed by a pattern of a previously formed circuit formation pattern, that is, a pattern of an insulating element isolation region 202 and a conductive film 204 serving as a gate electrode of an insulated gate field effect transistor. Through the opening of
N ⁺ diffusion region 210 and wiring 209 are electrically connected.

Here, the thin conductive film 207 has a role as an etching buffer when the third insulating film 208 is opened in the step shown in FIG. 18, and the lower insulating element isolation region 202 and the insulating film It has a function of preventing the surfaces of 205 and the insulating film 206 from being etched. Furthermore, when aluminum is used for the wiring 209, the wiring 209 has a function of enabling normal connection between the wiring 209 and the n ⁺ diffusion region 210.

〔The invention's effect〕

As described above, the present invention can easily form a self-aligned opening in which the formation of the opening required for electrode extraction can be easily performed automatically with the circuit formation pattern transferred in the previous process. This eliminates the need for an area margin in anticipation of misalignment, and has the effect of facilitating high integration of the semiconductor integrated circuit device.

[Brief description of the drawings]

FIGS. 1-a to 1-i are cross-sectional views of a reference semiconductor device and a cross-sectional view showing a manufacturing process thereof. FIG. 2 is a cross-sectional view of a semiconductor device manufactured by a method according to an embodiment of the present invention. FIG. 3 is a sectional view of a conventional semiconductor device, and FIGS.
FIG. 11 is a cross-sectional view showing a manufacturing process for further reference, and FIGS. 12 to 19 are main cross-sectional views of the manufacturing process showing one embodiment of the present invention. 101, 201, 301 ... silicon semiconductor substrate, 102, 202, 302 ... insulating element isolation region, 103, 203, 303 ... gate film, 104, 204, 304 ... gate electrode, 105, 205 ... insulating film, 106, 206 ... insulating film, 107, 208 ... insulating film, 207 ... thin conductive Conductive film, 108, 209, 307, wiring, 109, 210, 305, diffusion region, 306, interlayer insulating film, 110, 211, 308, protective film, 401, P-type silicon substrate, 402, silicon oxide film, 403, conductive film, 404 ... insulating film, 405, 506 ... photoresist layer, 406 ... arsenic ion, 407 ... n ⁺ diffusion region, 408 ... insulating film, 409 ... insulating film, 410, 511 ... photoresist layer, 411 ... wiring.

Claims (3)

(57) [Claims] A first insulating film formed on the semiconductor substrate via a first insulating film;
Forming a conductive film of the semiconductor substrate to separate a selected surface portion of the semiconductor substrate, and introducing an impurity into the selected surface portion of the semiconductor substrate using the first conductive film as a mask. Forming an impurity region that is self-aligned with the first conductive film; forming a second insulating film and performing anisotropic etching on the insulating film to form a side surface of the first conductive film; Forming a sidewall insulating film on the substrate and exposing a part of the impurity region; and forming a second conductive film extending on the sidewall insulating film in contact with the part of the impurity region. Forming a third insulating film on the entire surface; selectively forming a contact hole exposing a part of the second conductive film in the third insulating film; The conductive film extends on the third insulating film in contact with the portion of the conductive film. The method of manufacturing a semiconductor device characterized by a step of forming a wiring layer. 2. The semiconductor device according to claim 1, wherein said selected surface portion of said semiconductor substrate is defined by a buried insulating film provided so as to be partially buried in said semiconductor substrate together with said first conductive film. 2. The method according to claim 1, wherein a part of the film is formed to extend to the buried insulating film. 3. The semiconductor device according to claim 1, wherein said second conductive film is a polysilicon thin film layer containing impurities or a high melting point metal containing thin film layer. Production method.