JPS62150746A - Wiring formation of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate precision control of the spacing between wirings with an order of angstrom by a method wherein 1st conductivity region and 1st wiring are covered with an insulating layer and the insulating layer is etched by anisotropic etching as far as the 1st conductivity type region is exposed and side walls with predetermined width are formed on the end surfaces of the 1st wiring. CONSTITUTION:After an oxide film 12 is formed by hot oxidation, the surface of a semiconductor substrate 11 is selectively etched and a P-type impurity is introduced into the surface of the exposed semiconductor substrate 11 to form a base region 13. After high melting point metal 14 is applied to the surfaces of the base region 13 and the oxide film 12, the high melting point metal is covered with silicon nitride 15 and, by etching the silicon nitride 15 and the high melting point metal 14 selectively, a base electrode 16 is patterned and a region for emitter forming is exposed. Then the region for emitter forming and the silicon nitride 15 are covered with silicon dioxide film 17. If the silicon nitride film 17 is removed by anisotropic etching as far as the region for emitter forming is exposed again, silicon dioxide is left on the end surfaces of the base electrode 16 to form side walls 18.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for forming wiring in a semiconductor device, and particularly to a method for forming wiring in a semiconductor device suitable for miniaturization of semiconductor elements formed on a semiconductor substrate.

<Prior Art> FIG. 2 is a sectional view showing a typical conventional bipolar transistor. In the figure, 1 indicates a semiconductor substrate, 2 indicates a base region, and 3 indicates an emitter region.

A base electrode 4 is electrically connected to the base region 2 through a contact hole, while an emitter electrode 5 is in contact with the emitter region 3 through the contact hole. In such a conventional bipolar transistor, the lithography process for forming the contact holes 7 and 8 for the base electrode 4 and the emitter electrode 5, respectively, and the step for forming the base electrode 4 and the emitter electrode 5 are separate. The mask used in the lithographic process during electrode formation is formed with a pattern that takes into account errors in mask alignment in each phosphorography process. As a result, the distance between the base electrode 4 and the emitter electrode 5 has increased, and the area occupied by the base region 2 has increased. Such base area 2
An increase in the area of is not only inappropriate for improving the integration density, but also increases the base-collector junction capacitance and increases the base resistance due to the large distance between the base electrode 4 and the emitter electrode 5, which impairs the high frequency characteristics of the bipolar transistor. This was causing the deterioration of the condition.

In view of the shortcomings of conventional bipolar transistors, the applicant of the present invention, in a patent application filed on the same day as the present application, exposes a first conductivity type region on the surface of a semiconductor substrate and connects a first wiring to the first conductivity type region. a step of covering the first conductivity type region and the first wiring with an insulating layer and drilling a hole in the insulating layer to expose a part of the first conductivity type region;
introducing an impurity into a part of the first conductivity type region through a hole drilled in the insulating layer to form a second conductivity type region; The present invention proposed a method for forming wiring for a semiconductor device, which includes a step of forming a second wiring.

<Problems to be Solved by the Invention> In the wiring formation method for a semiconductor device related to the application filed on the same day as the above-mentioned present application, the distance between the first wiring and the second wiring is determined by using a mask for patterning the first wiring. Only the mask alignment error with the mask for forming the hole for forming the second conductivity type region is required as a margin, and the difference between the second wiring and the first wiring electrically connected to the second conductivity type region is sufficient. The distance could be significantly reduced compared to the conventional example.

However, even with the above wiring formation method, the distance between the first wiring and the second wiring still has to be set including mask alignment errors, and the margin is on the order of μm (typically 2 μm). However, there was a problem in that the margin could not be made smaller than the mask alignment error.

Accordingly, an object of the present invention is to provide a method for forming interconnects in a semiconductor device that allows the spacing between interconnects to be precisely controlled on the order of angstroms.

<Means for Solving the Problems> The present invention provides a method for electrically connecting a first wiring patterned with a first wiring material by exposing a first conductivity type region on the surface of a semiconductor substrate to the first conductivity type region. covering the first conductivity type region and the first wiring with an insulating layer; anisotropically etching the insulating layer until the first conductivity type region is exposed; a step of forming a wall, a step of introducing an impurity into a part of the first conductivity type region exposed through the hole defined by the side wall to form a second conductivity type region, and a step of forming a second conductivity type region through the hole. The method includes a step of forming a second wiring electrically connected to the second conductivity type region.

<Example> Figures 1(a) to (f) are cross-sectional views showing each process of an embodiment of the present invention, and this embodiment is an application of the present invention to the manufacturing process of a bipolar transistor. . In the figure, reference numeral 11 indicates an n-type semiconductor substrate, and after an oxide film 12 is grown by thermal oxidation on the surface of the semiconductor substrate 11, it is selectively etched to expose the semiconductor substrate 1.
A p-type impurity is introduced into the surface of the base region 13 to form a base region 13 (FIG. 1(a)).

Subsequently, a high melting point metal 14, such as titanium, molybdenum, tungsten, etc., is deposited on the surfaces of the base region 13 and the oxide film 12 by sputtering, and then this high melting point metal is covered with silicon nitride 15 (FIG. 1). (b)), selectively etching the silicon nitride 15 and the high melting point metal 14 to form a pattern of the base electrode 16;
Expose the area where the emitter is to be formed. Thereafter, the area where the emitter is to be formed and the silicon nitride 15 are covered with a silicon dioxide film 17 (FIG. 1(C)).
7 is removed by anisotropic etching, such as reactive ion etching, until the area where the emitter is to be formed is exposed again (
Figure 1(d)). As a result, silicon dioxide remains on the end face of the base electrode 16, forming a sidewall 18 (FIG. 1(d)).

Thereafter, the emitter formation region, sidewall 18, and silicon nitride 15 are covered with a polysilicon film 19 containing n-type impurities, and an emitter region 20 is formed by diffusion using this polysilicon film 19 as an impurity source (first Figure (e)
). Subsequently, aluminum is deposited on the entire surface and patterned to complete the emitter electrode 21 (FIG. 1(f)). Therefore, the distance between the base electrode 16 and the emitter electrode 21 is approximately equal to the thickness of the silicon dioxide film 1!117, and the thickness of the silicon dioxide film 17 can be controlled on the order of angstroms.
The distance between the emitter electrode 6 and the emitter electrode 21 can be dramatically reduced compared to the case where it has to be set including mask alignment errors.

As a result, the area of the base region 13 can be further reduced, the degree of integration can be improved, the base-emitter junction capacitance can be reduced, and the base resistance can be reduced.

As described above, according to the present invention, a first conductivity type region and a first wiring are covered with an insulating layer, and the insulating layer is anisotropically coated until the first conductivity type region is atomized. Since a sidewall of a predetermined width is formed on the end face of the first wiring by etching, the distance between the first wiring and the second wiring can be controlled by the width of the sidewall, that is, the thickness of the insulating layer. It is possible to miniaturize the structure regardless of mask alignment accuracy in the lithography process, and also to reduce the area of the first conductivity type region. As a result, it is possible to improve the degree of integration and to reduce the deterioration of the characteristics of the device caused by the bonding surface that occurs along the first conductivity type region.

[Brief explanation of drawings]

1(a) to 1(f) are cross-sectional views showing each step of an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device formed according to a conventional example. 11... Semiconductor substrate, 13... First conductivity type region, 16... First wiring, 17... Insulating film, 18. ...Side wall, 20...Second conductivity type region, 21...Second wiring. Patent Applicant: ROHM Co., Ltd. Representative, Patent Attorney: Kiyoshi Kuwai - Figure 1

Claims (1)

[Claims] In a wiring formation method for a semiconductor device in which wiring is connected to regions of mutually different conductivity types on the surface of a semiconductor substrate,
a step of exposing a first conductivity type region on a surface portion of the semiconductor substrate and electrically connecting a first wiring patterned with a first wiring material to the first conductivity type region, and connecting the first conductivity type region and the first wiring. covering with an insulating layer and anisotropically etching the insulating layer until the first conductivity type region is exposed to form a sidewall of a predetermined width on the end face of the first wiring; introducing an impurity into a part of the first conductivity type region exposed through the hole to form a second conductivity type region; and a second conductivity type region electrically connected to the second conductivity type region through the hole.
1. A method for forming wiring in a semiconductor device, the method comprising the step of forming wiring.