JP2018206841A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

To provide a semiconductor device that has good electric characteristics.SOLUTION: Provided is a semiconductor device having a transistor. The transistor has an oxide, a first insulator and a second insulator on the oxide, and a conductor on the first insulator. The oxide has a first region and a second region. The first region has a region contacted with the first insulator. The second region has a smaller oxygen concentration than the first region. The first insulator is arranged so as to have a region along an inner wall of an opening provided on the second insulator. The conductor is arranged so as to bury the opening.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may have a semiconductor device. .

  Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and formed with electrodes serving as connection terminals.

  A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components.

  In addition, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

  A transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).

  As a transistor including an oxide semiconductor, a self-aligned transistor has been proposed. As the self-aligned transistor, a metal film is formed over the source region and the drain region, and heat treatment is performed on the metal film, thereby increasing the resistance of the metal film and reducing the resistance of the source region and the drain region. Is disclosed (see Patent Document 2).

  As a method for manufacturing a transistor including an oxide semiconductor, a metal film is formed over the source region and the drain region, heat treatment is performed, and then a dopant is introduced through the metal film, so that the source region and the drain region are introduced. A method for reducing the resistance of the drain region is disclosed (see Patent Document 3).

  In recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. There is also a need for improved productivity of semiconductor devices including integrated circuits.

JP 2012-257187 A JP 2011-228622 A JP2013-016782A

  In Patent Document 2, when the resistance of the source region and the drain region is reduced, a metal film is formed over the source region and the drain region, and the metal film is heat-treated in an oxygen atmosphere. By performing the heat treatment, the constituent element of the metal film enters the source region and the drain region of the oxide semiconductor film as a dopant to reduce the resistance. In addition, heat treatment is performed in an oxygen atmosphere to oxidize the conductive film and increase the resistance of the conductive film. However, since heat treatment is performed in an oxygen atmosphere, the metal film has a low effect of extracting oxygen from the oxide semiconductor film.

  In Patent Document 2, the oxygen concentration in the channel formation region is described, but the concentration of impurities such as water and hydrogen is not mentioned. That is, the channel formation region has not been highly purified (reduction of impurities such as water and hydrogen, typically dehydration / dehydrogenation), and thus there is a problem that normally-on transistor characteristics are likely to occur. . Note that normally-on transistor characteristics refer to a state in which a channel exists even when a potential is not applied to the gate and current flows through the transistor. On the other hand, normally-off transistor characteristics are states in which no current flows through the transistor when no potential is applied to the gate.

  In view of the above problems, one embodiment of the present invention provides a semiconductor device having favorable electrical characteristics by stably reducing resistance of a source region and a drain region of a transistor and highly purifying a channel formation region. One of the issues is to do.

  Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

  An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a semiconductor device including a transistor, the transistor including an oxide, a first insulator and a second insulator over the oxide, and a conductor over the first insulator. The oxide has a first region and a second region, the first region has a region in contact with the first insulator, and the second region has a first region The oxygen concentration is lower than that of the first region, the first insulator is disposed so as to have a region along the inner wall of the opening provided in the second insulator, and the conductor is disposed so as to embed the opening. A semiconductor device.

  Another embodiment of the present invention is a semiconductor device including a transistor, in which the transistor includes an oxide, a film over the oxide, a first insulator, a second insulator over the film, The oxide has a first region and a second region, and the first region has a region in contact with the first insulator. The second region has a lower oxygen concentration than the first region, the film is provided in contact with the second region, and the first insulator is an inner wall of an opening provided in the second insulator. And the conductor is a semiconductor device that is disposed so as to fill the opening.

  In the above, the oxide may include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

  In the above, the oxide may have more In than the element M in the atomic ratio.

  In the above, the second region may include at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

  In the above, the second region may further contain nitrogen.

  In the above, the first region may have a lower hydrogen concentration than the second region.

  In the above, the transistor may be a normally-off transistor.

  In the above, the film may have a portion mixed with the second region.

  In the above, the film may include at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

  In the above, the film may have aluminum and titanium.

  In the above, the film may further include one or both of nitrogen and oxygen.

  In the above, the thickness of the film may be not less than 0.5 nm and not more than 5 nm.

  Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, the transistor including a first region, an oxide including the second region, a film over the oxide, and the first insulation. Forming a film including a metal, a second insulator on the film, and a conductor on the first insulator, covering the oxide and in contact with the second region; At least the oxide and the film are subjected to a first heat treatment in an atmosphere containing nitrogen, whereby oxygen contained in the second region is extracted to the film.

  In the above, the film may be formed by a sputtering method using any one or a plurality of gases selected from argon, nitrogen, and nitrogen.

  Further, in the above, a second heat treatment may be further performed after the first heat treatment.

  According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly productive semiconductor device can be provided.

  Alternatively, a semiconductor device capable of holding data for a long period can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with a high degree of design freedom can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Schematic diagram illustrating an area division of InGaZnO ₄ in the crystal. InO ₂ surface and (Ga, Zn) and the moving path of hydrogen atoms in the region between the O surface diagram illustrating the activation barrier on the path. The figure explaining the movement path | route of the hydrogen atom in a (Ga, Zn) O area | region, and the activation barrier on the path | route. A moving path of hydrogen atoms in the InO ₂ regions, diagram illustrating the activation barrier on the path. The figure explaining the movement path | route of the hydrogen atom along c-axis direction, and the activation barrier on the path | route. The figure explaining a calculation model. The figure explaining the relative value of the total energy of an oxygen deficiency model. The figure explaining the model of an initial state, and the model of a final state. The figure explaining an activation barrier. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration example of an inverter circuit according to one embodiment of the present invention and a timing chart illustrating an operation example thereof. FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device. FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. 1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. The figure explaining the sheet resistance of the sample of a present Example. The figure explaining the SIMS analysis result of the sample of a present Example.

  Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In the drawings, the size, the thickness of layers, or regions are exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may be omitted in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.

  In this specification and the like, ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  In addition, in this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

  For example, in this specification and the like, when X and Y are directly connected and when X and Y are explicitly described as being connected, X and Y are And the case where X and Y are functionally connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

  Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

  In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and the channel is formed through the region. Thus, a current can flow between the source and the drain. Note that in this specification and the like, a region where a channel is formed refers to a region where current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or a channel in a top view of the transistor. The distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width means, for example, that a source and a drain in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or in a region where a channel is formed The length of the part facing each other. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. By including impurities, for example, DOS (Density of States) of a semiconductor may increase or crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

  Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen in its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. The one included in the concentration range The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. The one included in the concentration range

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, the term “insulator” can be restated as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.

  The transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

  In this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 degrees to 10 degrees. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 degrees to 30 degrees. “Vertical” means a state in which two straight lines are arranged at an angle of 80 degrees to 100 degrees. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

  Note that in this specification, a barrier film refers to a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS). For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said that the transistor includes an oxide or an oxide semiconductor.

In this specification and the like, normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, a current per channel width of 1 μm flowing through the transistor is 1 × 10 ⁻²⁰ at room temperature. A or lower, 1 × 10 ⁻¹⁸ A or lower at 85 ° C., or 1 × 10 ⁻¹⁶ A or lower at 125 ° C.

(Embodiment 1)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

<Configuration example of semiconductor device>
1A, 1B, and 1C are a top view and a cross-sectional view of the transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.

  FIG. 1A is a top view of a semiconductor device including a transistor 200. FIG. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

  The semiconductor device of one embodiment of the present invention includes the transistor 200, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 281, and the insulator 282. In addition, the transistor 200 is electrically connected to the transistor 200 and functions as a wiring, and the conductor 240 (conductor 240a and 240b) functions as a plug.

  Note that the conductor 203 is in contact with the inner wall of the opening of the insulator 212, the first conductor 203a of the conductor 203 is formed, and the second conductor 203b of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same. Note that in the transistor 200, a structure in which the first conductor 203a of the conductor 203 and the second conductor 203b of the conductor 203 are stacked is described; however, the present invention is not limited thereto. For example, the conductor 203 may be provided as a single layer or a stacked structure including three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

  The conductor 240 is in contact with the inner wall of the opening of the layer 242, the insulator 280, the insulator 274, the insulator 281 and the insulator 282, and the first conductor of the conductor 240 is formed. A second conductor of body 240 is formed. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be approximately the same. Note that although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

[Transistor 200]
As illustrated in FIG. 1, the transistor 200 includes an insulator 214 disposed over a substrate (not illustrated), an insulator 216 disposed over the insulator 214, and the insulator 214 and the insulator 216. Conductor 205 disposed to be embedded, insulator 216, insulator 220 disposed on conductor 205, insulator 222 disposed on insulator 220, and insulator 222 The insulator 224 disposed, the oxide 230a disposed on the insulator 224, the oxide 230b disposed on the oxide 230a, the insulator 224, the oxide 230a, and the oxide 230b. In the opening of the layer 242 and the insulator 280 which are provided so as to have at least a region overlapping with the conductor 205. The oxide 230c is disposed so as to have a region in contact with the inner wall of the opening, the insulator 250 is disposed on the oxide 230c, and is disposed on the insulator 250 so as to embed the opening. And the insulator 280 and the insulator 274 disposed on the conductor 260.

  Note that although the transistor 200 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this. For example, a structure in which a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be employed. In the transistor 200, the conductor 260 is illustrated as a single layer structure; however, the present invention is not limited to this. For example, the conductor 260 may have a stacked structure of two or more layers.

  The transistor 200 includes a metal functioning as an oxide semiconductor in an oxide 230 (an oxide 230a, an oxide 230b, and an oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region). It is preferable to use an oxide (hereinafter also referred to as an oxide semiconductor).

  Since the transistor 200 including an oxide semiconductor in a channel formation region has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.

  For example, the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, or neodymium. It is preferable to use a metal oxide such as one or a plurality selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

  Here, an oxide semiconductor forms a metal compound by adding a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements included in the oxide semiconductor, and has low resistance. Turn into. In particular, aluminum, titanium, tantalum, tungsten, or the like is preferably used.

  In order to add the metal element to the oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, by providing the film, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film and the like, thereby forming oxygen vacancies and oxidation. The vicinity of the interface of the physical semiconductor may have a low resistance.

  Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment may be performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, a metal element which is a component of the film is converted into an oxide semiconductor or a component of an oxide semiconductor from a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. A certain metal element diffuses into the film, and the oxide semiconductor and the film form a metal compound, so that resistance can be reduced. The metal element added to the oxide semiconductor reacts with the oxide semiconductor to form a metal compound, whereby the metal element becomes relatively stable. Thus, a highly reliable semiconductor device can be provided.

  In addition, a compound layer (different layer) may be formed at the interface between the metal film, the nitride film containing a metal element, or the oxide film containing a metal element and the oxide semiconductor. Note that a compound layer (different layer) is a layer having a metal compound including a metal film, a nitride film containing a metal element, or a component of an oxide film containing a metal element and a component of an oxide semiconductor. For example, a layer in which a metal element of an oxide semiconductor and an added metal element are alloyed may be formed as the compound layer. The alloyed layer is in a relatively stable state, and a highly reliable semiconductor device can be provided.

  In addition, hydrogen existing in an oxide semiconductor is considered to be relatively stable when it diffuses into a low-resistance region of the oxide semiconductor and enters an oxygen vacancy existing in the low-resistance region. . In addition, hydrogen in oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250 ° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and exists in the low-resistance regions. May enter a relatively stable state. Therefore, the resistance of the oxide semiconductor or the region where the metal compound is formed by heat treatment is further reduced, and the oxide semiconductor that is not reduced in resistance is highly purified (impurities such as water and hydrogen). There is a tendency to increase resistance.

  In the oxide semiconductor, the carrier density is increased when an impurity element such as hydrogen or nitrogen is present. In some cases, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

  Therefore, a high resistance region and a low resistance region can be provided in the oxide semiconductor by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape has a low resistance that functions as a region having a low carrier density and functioning as a source region or a drain region. A region can be provided.

  Here, FIG. 2 shows an enlarged view of a region 239 including the oxide 230b which is selectively reduced in resistance and is surrounded by a broken line in FIG.

  As illustrated in FIG. 2, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) functioning as a source region or a drain region.

  A region 231 functioning as a source region or a drain region is a region having a low oxygen concentration and a low resistance. The region 234 functioning as a channel formation region is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region. Note that although not illustrated in FIG. 2, a region between the region 231 and the region 234 having a higher oxygen concentration and lower carrier density than the region 231, and a lower oxygen concentration and higher carrier density than the region 234. You may have.

  Note that in the region 231, at least one concentration of the metal element and the impurity element such as hydrogen and nitrogen is preferably higher than that of the region 234.

  For example, the region 231 preferably includes any one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium in addition to the oxide 230.

  In order to form the region 231, for example, the layer 242 may be provided as a film containing a metal element in contact with the region 231 of the oxide 230. Note that as the layer 242, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element can be used. At that time, a compound layer may be formed at the interface between the layer 242 and the oxide 230. Note that the compound layer is a layer having a metal compound including the component of the layer 242 and the component of the oxide 230. For example, a layer in which the metal element in the oxide 230 and the added metal element are alloyed may be formed as the compound layer.

  By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230, and the resistance of the region 231 can be reduced. Note that the metal compound is not necessarily formed in the oxide 230. For example, a metal compound may be formed in the layer 242. Further, for example, the oxide layer may be provided on the surface of the oxide 230, the surface of the layer 242, or the compound layer formed at the interface between the layer 242 and the oxide 230.

  Accordingly, the region 231 may include a low-resistance region of the layer 242 or a low-resistance region of a compound layer formed between the layer 242 and the oxide 230. That is, in this specification, a region functioning as a source region or a drain region is referred to as a region 231.

  In FIG. 2, the region 231 is formed in the oxide 230 b, but is not limited thereto. For example, the region 231 may be formed in the layer 242, the compound layer formed between the layer 242 and the oxide 230, the oxide 230a, and the oxide 230c.

  In addition, in the oxide 230, it may be difficult to clearly detect the boundary between the regions. The concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). May be. That is, the closer to the channel formation region, the lower the concentration of the metal element and impurity elements such as hydrogen and nitrogen.

  In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and an impurity is added to a desired region. That's fine. Note that as the impurity, an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

  The region 231 can have high carrier density and low resistance by increasing the content of the above-described metal element that increases conductivity, an element that forms oxygen vacancies, or an element that is trapped by oxygen vacancies. it can.

  In order to reduce the resistance of the region 231, for example, the layer 242 may be formed in contact with the region 231 of the oxide 230. As the layer 242, a metal film, an oxide film containing a metal element, a nitride film containing a metal element, or the like can be used.

  When the oxide 230 and the layer 242 are in contact with each other, the component of the layer 242 and the component of the oxide 230 form a metal compound, which becomes a region 231 and has a low resistance. In addition, part of oxygen in the oxide 230 located in the vicinity of the interface between the oxide 230 and the layer 242 or in the vicinity of the interface is absorbed by the layer 242, and oxygen vacancies are formed in the oxide 230. In some cases, the resistance is lowered and the region 231 is formed.

  Further, heat treatment may be performed in an atmosphere containing nitrogen with the oxide 230 and the layer 242 being in contact with each other. Through the heat treatment, the metal element which is a component of the layer 242 is diffused from the layer 242 to the oxide 230 or the metal element which is a component of the oxide 230 is diffused to the layer 242, so that the oxide 230 and the layer 242 are formed. A metal compound is formed to reduce resistance. At that time, the metal element of the oxide 230 and the metal element of the layer 242 may be alloyed. When the metal element of the oxide 230 and the metal element of the layer 242 are alloyed, the metal element is in a relatively stable state; thus, a highly reliable semiconductor device can be provided.

  Note that in FIG. 2, the metal compound formation region of the oxide 230 described above is indicated by hatching (region 243) as an example. Note that, in this specification and the like, the range (region 243) represented by oblique lines is not limited to the range shown in FIG. For example, in the region near the interface between the oxide 230 and the conductor 240 shown in FIG. 1 or the region where the layer 242 and the oxide 230 overlap with each other, the region from the top surface of the oxide 230 to the bottom surface of the oxide 230 In some cases, the metal compound forming region (or range) having a reduced resistance is formed. The same applies to other drawings.

  In addition, hydrogen in the oxide 230 diffuses into the region 231 and enters a relatively stable state when it enters oxygen vacancies existing in the region 231. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

  On the other hand, since the region 234 of the oxide 230 does not overlap with the layer 242, addition of a metal element is suppressed. In addition, in the region 234 of the oxide 230, oxygen atoms in the oxide 230 are suppressed from being absorbed into the layer 242.

  In addition, when the layer 242 absorbs oxygen in the region 231 of the oxide 230, oxygen vacancies may be generated in the region 231 in some cases. As hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 increases. Accordingly, the resistance of the region 231 of the oxide 230 is reduced.

  Here, in the case where the layer 242 has a property of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the layer 242. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Further, the layer 242 may be removed together with hydrogen absorbed from the oxide 230 in a later step.

  Note that the layer 242 is not necessarily removed. For example, if the layer 242 is insulated and has a high resistance, it may remain. For example, the layer 242 may be oxidized by oxygen absorbed from the oxide 230 to be an insulator and have high resistance. In that case, the layer 242 may function as an interlayer film.

  For example, in the case where a conductive region remains in the layer 242, the region is oxidized by heat treatment, so that the region becomes an insulator and resistance is increased. The heat treatment is preferably performed in an oxidizing atmosphere, for example. In the case where there is a structure including oxygen in the vicinity of the layer 242, the layer 242 may react with oxygen included in the structure and be oxidized by heat treatment.

  By leaving the layer 242 as an insulator, the layer 242 can function as an interlayer film. In the case of the structure, the layer 242 is provided with a thickness that can be insulated in a later step. For example, the layer 242 may be provided with a thickness greater than or equal to 0.5 nm and less than or equal to 5 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm. Note that in the case where the heat treatment is performed in the above oxidizing atmosphere, it is preferable that the heat treatment is performed once in the atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. By performing heat treatment once in an atmosphere containing nitrogen, oxygen in the oxide 230 can easily diffuse into the layer 242.

  Here, in a transistor including an oxide semiconductor, if an impurity and an oxygen vacancy exist in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to change and reliability may be deteriorated. In addition, when an oxygen vacancy is included in a region where a channel is formed in an oxide semiconductor, the transistor is likely to be normally on. Therefore, oxygen vacancies in the region 234 where a channel is formed are preferably reduced as much as possible.

  Therefore, as illustrated in FIGS. 1 and 2, it is preferable to provide an insulator 280 that contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition in proximity to the oxide 230. . Excess oxygen included in the insulator 280 can pass through the layer 242 and diffuse into the oxide 230, so that oxygen vacancies in the oxide 230 can be reduced.

  That is, excess oxygen in the insulator 280 is diffused into the region 234 of the oxide 230, whereby oxygen vacancies in the region 234 of the oxide 230 can be reduced. On the other hand, oxygen vacancies formed in the region 231 of the oxide 230 are also compensated by oxygen supplied from the insulator 280. However, the low resistance region formed in the oxide 230 and the layer 242 is stable because the metal compound is formed. Therefore, lower resistance can be maintained than in the region 234 where the metal compound is not formed.

  In order to provide an oxygen region in the insulator 280, an oxide film may be formed as the insulator 274 in contact with the insulator 280 by a sputtering method. By using a sputtering method for forming an oxide, an insulator containing a large amount of oxygen and containing few impurities such as water or hydrogen can be formed. In the case of using a sputtering method, for example, it is preferable to form a film using a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to a high electric field region between the facing targets, the film formation surface can be formed without being easily damaged by plasma. It is preferable that film formation damage to the insulator 280 and the conductor 260 can be reduced when the insulator to be the insulator 274 is formed. A film formation method using a facing target type sputtering apparatus can be referred to as VDSP (Vapor Deposition SP) (registered trademark).

  During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

  Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles sputtered from the target are ejected. The sputtered particles adhere to and deposit on the film formation surface to form a film. In addition, some ions recoil by the target, pass through the formed film through the film formed as recoil ions, and may be taken into the insulator 280 in contact with the deposition surface. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulator 280. When the ions are taken into the insulator 280, a region into which the ions are taken is formed in the insulator 280. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 280.

  By introducing excess oxygen into the insulator 280, an excess oxygen region can be formed in the insulator 280. Excess oxygen in the insulator 280 is supplied to the oxide 230 through the layer 242 by heat treatment or the like, so that oxygen vacancies in the oxide 230 can be compensated.

  Note that the insulator 280 is preferably formed using silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes. Materials such as silicon oxynitride tend to form excess oxygen regions. On the other hand, compared to the above-described materials such as silicon oxynitride, the oxide 230 tends to hardly form an excess oxygen region even if an oxide film formed by a sputtering method is formed over the oxide 230. Therefore, by providing the insulator 280 having an excess oxygen region around the region 234 of the oxide 230, the excess oxygen of the insulator 280 can be effectively supplied to the region 234 of the oxide 230.

  The insulator 274 is preferably formed using aluminum oxide. Here, it is known that aluminum oxide has a property of extracting hydrogen in an oxide by performing a heat treatment in a state close to the oxide. Therefore, as illustrated in FIG. 1, in the case where the layer 242 and the insulator 280 are provided between the oxide 230 and aluminum oxide, the aluminum oxide absorbs hydrogen in the layer 242 and the insulator 280. The hydrogen-reduced layer 242 may absorb hydrogen in the oxide 230. Therefore, the hydrogen concentration in the oxide 230 may be able to be reduced.

  In addition, when aluminum oxide formed by a sputtering method is used as the insulator 274, the insulator 274 containing a large amount of oxygen can be formed. Accordingly, the insulator 274 can serve as an oxygen supply source, and oxygen can be supplied to the insulator 280 and the region 234 of the oxide 230 as described above.

  By combining the above structure or the above steps, the oxide 230 can be selectively reduced in resistance.

  An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor using an oxide semiconductor in a channel formation region has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.

  As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

  Hereinafter, a detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

  As shown in FIGS. 1A and 1C, the conductor 203 is extended in the channel width direction and functions as a wiring for applying a potential to the conductor 205. Note that the conductor 203 is preferably provided so as to be embedded in the insulator 212.

  The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided in contact with the conductor 203. The conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.

  Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being interlocked. In particular, by applying a negative potential to the conductor 205, Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when a negative potential is not applied.

  Further, by providing the conductor 205 over the conductor 203, the distance between the conductor 203 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed. That is, by providing the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260, parasitic capacitance between the conductor 203 and the conductor 260 can be reduced, and the conductor 203 and the conductor 260 can be reduced. The insulation breakdown voltage can be increased.

  Further, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200 can be improved and the transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 203 is not limited thereto, and the conductor 203 may be extended in the channel length direction of the transistor 200, for example.

  Note that the conductor 205 is provided so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG. The conductor 205 is preferably provided larger than the region 234 in the oxide 230. In particular, as illustrated in FIG. 1C, the conductor 205 is preferably extended also in a region outside the end portion that intersects the channel width direction of the region 234 of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

  That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. . In this specification, a transistor structure in which a channel formation region is electrically surrounded by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

  In addition, the conductor 205 is in contact with the inner walls of the openings of the insulator 214 and the insulator 216 to form a first conductor 205a, and further, a second conductor 205b is formed inside. Here, the heights of the upper surfaces of the first conductor 205a and the second conductor 205b and the height of the upper surface of the insulator 216 can be approximately the same. Note that although the transistor 200 has a structure in which the first conductor 205a and the second conductor 205b are stacked, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a stacked structure including three or more layers. When a structure has a laminated structure, an ordinal number may be given in the order of formation to be distinguished.

Here, the first conductor of the conductor 205 or the conductor 203 (the conductor 205a or the conductor 203a) is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ₂ O, It is preferable to use a conductive material that has a function of suppressing diffusion of impurities such as NO and NO ₂ and copper atoms (the impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.

  The conductor 205 or the first conductor of the conductor 203 (the conductor 205a or the conductor 203a) has a function of suppressing diffusion of oxygen, whereby the conductor 205 or the second conductor of the conductor 203 (conductivity). It is possible to prevent the conductivity from decreasing due to oxidation of the body 205b or the conductor 203b). As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductive material may be a single layer or a stacked layer as the first conductor of the conductor 205 or the conductor 203 (the conductor 205a or the conductor 203a). Accordingly, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side through the conductor 203 and the conductor 205 from the insulator 210 can be suppressed.

  The second conductor 205b of the conductor 205 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that the second conductor 205b of the conductor 205 is illustrated as a single layer, but may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

  In addition, since the second conductor 203b of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor 205b of the conductor 205 is preferably used. For example, a conductive material mainly containing copper or aluminum can be used. The second conductor 203b of the conductor 203 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

  In particular, copper is preferably used for the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the electrical characteristics of the transistor 200 may be deteriorated by diffusing into the oxide 230. Thus, for example, the insulator 214 can be made of copper diffusion by using a material such as aluminum oxide or hafnium oxide having low copper permeability.

  Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

The insulator 210, the insulator 214, and the insulator 282 preferably function as barrier insulating films that suppress entry of impurities such as water or hydrogen into the transistor 200 from the substrate side or from above the insulator 282. . Therefore, the insulator 210, the insulator 214, and the insulator 282 include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N ₂ O, NO, NO _{2, and the} like), a copper atom, and the like. It is preferable to use an insulating material having a function of suppressing diffusion of impurities (the above impurities are difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).

  For example, aluminum oxide or the like is preferably used for the insulator 210 and the insulator 282, and silicon nitride or the like is preferably used for the insulator 214. Thus, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 200 side with respect to the insulator 210 and the insulator 214. Alternatively, diffusion of oxygen contained in the insulator 224 and the like to the substrate side with respect to the insulator 210 and the insulator 214 can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water from the upper side of the insulator 282 to the transistor 200 side can be suppressed.

  In addition, by providing a structure in which the conductor 205 is stacked over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even when a metal that easily diffuses, such as copper, is used for the second conductor of the conductor 203, by providing silicon nitride or the like as the insulator 214, the metal diffuses into a layer above the insulator 214. Can be suppressed.

  The insulator 212, the insulator 216, and the insulator 281 that function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

For example, the insulator 212, the insulator 216, and the insulator 281 include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and titanic acid. An insulator such as strontium (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  The insulator 220, the insulator 222, and the insulator 224 function as gate insulators.

  Here, the insulator 224 in contact with the oxide 230 is preferably an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

  In the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). It is preferable.

  Since the insulator 222 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region included in the insulator 224 can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. . In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is, for example, so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

  In particular, an insulator including one or both oxides of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to transmit) is preferably used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Acts as a layer.

  Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  The insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high relative dielectric constant can be obtained by combining an insulator of a high-k material and the insulator 220. Can do.

  Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.

  The oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Further, by including the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

  Note that the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

  The energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is preferably higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.

  Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined. In order to achieve this, the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.

  Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed. can do. For example, in the case where the oxide 230b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.

  At this time, the main path of carriers is the oxide 230b. When the oxide 230a and the oxide 230c have the above structure, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence on the carrier conduction due to the interface scattering is reduced, and the transistor 200 can obtain a high on-state current.

  The oxide 230 includes a region 231 and a region 234. Note that at least part of the region 231 includes a region in contact with the layer 242.

  Note that when the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least part of the region 234 functions as a region where a channel is formed.

  That is, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics that meet the requirements in accordance with circuit design.

  As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide used for the region 234, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.

  Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in the temperature programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorbed oxygen converted to oxygen molecules is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ^19. An oxide film having atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

  Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

  An insulator from which oxygen is released by heating is provided as the insulator 250 so as to be in contact with the upper surface of the oxide 230c, whereby oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b through the oxide 230c. Can be supplied. Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

  Further, a metal oxide may be provided between the insulator 250 and the conductor 260 in order to efficiently supply excess oxygen included in the insulator 250 to the oxide 230. The metal oxide preferably suppresses oxygen diffusion from the insulator 250. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

  Note that the metal oxide may have a function as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide can be reduced, whereby the conductor can be obtained. This can be called an OC (Oxide Conductor) electrode.

  In addition, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a metal oxide that is a high-k material with a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure having high relative dielectric constant and stability against heat can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.

  In the case where the metal oxide functions as a gate electrode, the on-state current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Alternatively, in the case where the metal oxide functions as a gate insulator, the distance between the conductor 260 and the oxide 230 is maintained depending on the physical thickness of the insulator 250 and the metal oxide. In addition, leakage current between the conductor 260 and the oxide 230 can be suppressed. Therefore, by providing the insulator 250 and a stacked structure of the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be reduced. It can be easily adjusted as appropriate.

  Specifically, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230 as the metal oxide, the metal oxide can be used as the metal oxide. Alternatively, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

  In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process. Note that the metal oxide is not an essential component. What is necessary is just to design suitably according to the transistor characteristic to require.

The conductor 260 functioning as the first gate electrode is shown as a single-layer structure in FIG. 1, but may have a stacked structure of two or more layers. For example, in the case where the conductor 260 has a two-layer structure, the first layer of the conductor 260 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen, like the first conductor 205a of the conductor 205. It is preferable to use a conductive material having a function of suppressing diffusion of impurities such as molecules, nitric oxide molecules (N ₂ O, NO, NO _2, etc.) and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules).

  Since the first layer of the conductor 260 has a function of suppressing the diffusion of oxygen, the second layer of the conductor 260 is prevented from being oxidized and reduced in conductivity due to excess oxygen of the insulator 250. Can do. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion.

  The second layer of the conductor 260 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductor 260 also functions as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The second layer of the conductor 260 may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

  In addition, as illustrated in FIG. 1C, when the conductor 205 extends in a region outside the end portion that intersects the channel width direction of the oxide 230, the conductor 260 It is preferable to overlap with the insulator 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230. The area can be covered.

  That is, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .

  Further, an insulator functioning as a barrier film may be provided over the second layer of the conductor 260. As the insulator, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, it is possible to suppress the conductor 260 from being oxidized by oxygen from above the insulator. In addition, impurities such as water or hydrogen from above the insulator can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

  The layer 242 is provided so as to have at least a region in contact with the region 231 of the oxide 230. As the layer 242, a metal film, an oxide film containing a metal element, a nitride film containing a metal element, or the like can be used. As described above, the layer 242 is a layer for forming a metal compound layer on the oxide 230. Note that as described later in <Method for Manufacturing Semiconductor Device>, the metal compound layer is not formed only by forming a film to be the layer 242 over the oxide 230. The metal compound layer is formed by performing heat treatment after forming the film to be the layer 242 over the oxide 230. At this time, the film to be the layer 242 reacts with oxygen contained in the oxide 230 or the like to become an insulator, which increases resistance. That is, the film to be the layer 242 has a property as a conductor at a stage after the film formation, but has a property as an insulator at a stage after the heat treatment. Therefore, in FIG. 1 which shows a completed diagram of the transistor 200, the layer 242 is an insulator and functions as an interlayer film.

  The insulator 280 is provided over the insulator 224 and the oxide 230b with the layer 242 interposed therebetween. The insulator 280 preferably has an excess oxygen region. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

  As described above, the insulator 280 preferably has an excess oxygen region. An insulator from which oxygen is released by heating is provided as the insulator 280 over the oxide 230b and the insulator 224 and in contact with the oxide 230c, whereby the oxygen in the insulator 280 can be converted into the oxide 230c or the layer 242. Through this, it can be efficiently supplied to the region 234 of the oxide 230. Note that the concentration of impurities such as water or hydrogen in the insulator 280 is preferably reduced.

  Here, oxygen contained in the insulator 280 is supplied to the entire oxide 230 through the layer 242 by heating. However, the low resistance region (region 231) in contact with the layer 242 of the oxide 230 is stable because the metal compound is formed. Therefore, oxygen supplied from the insulator 280 to the oxide 230 reacts mainly in a region where the metal compound of the oxide 230 is not formed, that is, the region 234. Therefore, by supplying oxygen from the insulator 280, oxygen vacancies in the region 234 can be selectively compensated while the low resistance state of the region 231 is maintained.

  The insulator 274 is provided over the insulator 280 and the conductor 260. By depositing the insulator 274 by a sputtering method, an excess oxygen region can be provided in the insulator 280. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region. In addition, when the insulator 274 is provided over the region 231 of the oxide 230, hydrogen in the oxide 230 can be extracted to the insulator 274 through the insulator 280 by heat treatment or the like in some cases.

  For example, as the insulator 274, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. Can do.

  In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and function as a barrier film for impurities such as hydrogen. For example, by using aluminum oxide formed by a sputtering method for the insulator 274, the insulator 274 supplies oxygen to the insulator 280, and impurities such as hydrogen from above the insulator 274 are exposed to the insulator 280. It can suppress mixing in the side.

  Further, an insulator 281 that functions as an interlayer film is preferably provided over the insulator 274. As in the case of the insulator 224, the insulator 281 preferably has reduced concentration of impurities such as water or hydrogen in the film.

  In addition, an insulator 282 made of the same material as the insulator 274 is preferably provided over the insulator 281. With this structure, impurities such as hydrogen from above the insulator 282 can be prevented from entering the transistor 200 side. In some cases, hydrogen contained in the insulator 281 can be extracted to the insulator 282. Note that an insulator similar to the insulator 281 may be provided over the insulator 282.

  In addition, the conductor 240a and the conductor 240b are provided in openings formed in the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the layer 242. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240a and 240b may be flush with the top surface of the insulator 282.

  The conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200, and the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode.

  Note that the first conductor of the conductor 240 a is formed in contact with the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the inner wall of the opening of the layer 242. A region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, the first conductor of the conductor 240b is formed in contact with the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the inner wall of the opening of the layer 242. A region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

  Here, FIG. 3 is a cross-sectional view of the portion indicated by the alternate long and short dash line in FIG. 1A, that is, the source region or the drain region of the transistor 200. As shown in FIG. 3, the conductor 240 a (conductor 240 b) is preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230. In particular, the conductor 240a (conductor 240b) is preferably in contact with both or one of the side surface on the A5 side and the side surface on the A6 side on the side surface intersecting the channel width direction of the oxide 230. Alternatively, the conductor 240a (conductor 240b) may be in contact with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230. In this manner, the conductor 240a and the conductor 240b are in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact between the conductor 240a and the conductor 240b and the oxide 230 is obtained. The contact area of the contact portion can be increased without increasing the upper area of the portion, and the contact resistance between the conductor 240a and the conductor 240b and the oxide 230 can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.

  The conductor 240a and the conductor 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

  Here, for example, when the openings are formed in the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the layer 242, the region where the resistance of the region 231 is reduced in the oxide 230 is removed, so that the low Oxide 230 that is not resisted may be exposed. In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor used for a conductor in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having the same. That is, when the oxide 230 whose resistance has not been reduced is in contact with the first conductor of the conductor 240, oxygen vacancies are formed in the metal compound or the oxide 230, and the region 231 of the oxide 230 has low resistance. Turn into. Therefore, the contact resistance between the oxide 230 and the conductor 240 can be reduced by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240. Therefore, the first conductor of the conductor 240 preferably includes a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten.

  In the case where the conductor 240 has a stacked structure, the layer 242, the insulator 280, the insulator 274, the insulator 281, and the conductor in contact with the insulator 282 include the first conductor 205 a of the conductor 205 and the like. Similarly, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 282 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.

  Although not illustrated, a conductor functioning as a wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. As the conductor functioning as the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the conductive material. Note that like the conductor 203 and the like, the conductor may be formed so as to be embedded in an opening provided in the insulator.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described.

<< Board >>
As a substrate over which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  Further, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. As the substrate that is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.

<< Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

  For example, when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the voltage during transistor operation can be reduced while maintaining the physical film thickness. On the other hand, for an insulator functioning as an interlayer film, a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.

  Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. For example, an oxynitride having silicon, or a nitride having silicon and hafnium.

  Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, For example, silicon oxide having a hole or resin may be used.

  In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.

  In addition, a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.

  Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  For example, as the insulator 274 and the insulator 282, a metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like An oxide can be used.

  In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be increased by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, appropriate addition amounts of hydrogen and nitrogen can be adjusted.

  For example, the insulator 224 and the insulator 250 that function as part of the gate insulator are preferably insulators having an excess oxygen region. For example, by using a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

  For example, in the insulator 222 that functions as part of the gate insulator, an insulator including one or a plurality of oxides of aluminum, hafnium, and gallium can be used. In particular, as the insulator including one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

  For example, the insulator 220 is preferably formed using silicon oxide or silicon oxynitride which is stable against heat. The gate insulator has a heat-stable film and a laminated structure with a high relative dielectric constant, so that the equivalent oxide thickness (EOT) of the gate insulator can be reduced while maintaining the physical film thickness. It becomes.

  With the stacked structure, the on-state current can be improved without weakening the influence of the electric field from the gate electrode. In addition, the leakage current between the gate electrode and the channel formation region can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed depending on the physical thickness of the gate insulator. .

  The insulator 212, the insulator 216, the insulator 280, and the insulator 281 preferably include an insulator with a low relative dielectric constant. For example, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and It is preferable to include silicon oxide to which nitrogen is added, silicon oxide having holes, or a resin. Alternatively, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and the like. It is preferable to have a stacked structure of silicon oxide to which nitrogen is added or silicon oxide having pores and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

  As the insulator 210, the insulator 214, the insulator 274, and the insulator 282, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used. As the insulator 210, the insulator 214, the insulator 274, and the insulator 282, for example, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or oxide A metal oxide such as tantalum, silicon nitride oxide, silicon nitride, or the like may be used.

<< Conductor >>
As the conductor, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

  A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

  Note that in the case where an oxide is used for a channel formation region of the transistor, the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

  In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

  As the conductor 260, the conductor 203, the conductor 205, and the conductor 240, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

<< Metal oxide >>
As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.

  The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably included. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

  In addition, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a semiconductor layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

  Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, it is difficult to check a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.

  The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, since it is difficult to confirm a clear crystal grain boundary in the CAAC-OS, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. Moreover, since the crystallinity of the metal oxide that may be reduced by such generation of contamination and defects impurities, CAAC-OS impurities and defects (oxygen deficiency _(V O:. Oxygen vacancy also referred) etc.) with less metal It can be said that it is an oxide. Therefore, the physical properties of the metal oxide including a CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide including indium, gallium, and zinc, may have a stable structure by using the above-described nanocrystal. is there. In particular, since IGZO tends to be difficult to grow in the atmosphere, a crystal smaller than a large crystal (here, a crystal of several millimeters or a crystal of several centimeters) (for example, the above-mentioned nanocrystal) is used. However, it may be structurally stable.

  The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

  Oxide semiconductors (metal oxides) have various structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with metal oxide]
Next, the case where the metal oxide is used for a channel formation region of a transistor will be described.

  Note that by using the metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, a metal oxide with low carrier density is preferably used. In the case where the carrier density of the metal oxide film is lowered, the impurity concentration in the metal oxide film may be lowered and the defect level density may be lowered. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

  In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

  In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is included in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, in the metal oxide, nitrogen in the channel formation region is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS, Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

  In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including a metal oxide containing hydrogen is likely to be normally on.

  In addition, hydrogen contained in the metal oxide may form a shallow defect level (sDOS) in the metal oxide. The shallow defect level refers to an interface level located near the lower end of the conduction band. It is presumed that the shallow defect level exists in the vicinity of the boundary between the high density region and the low density region in the metal oxide. Here, the high density region and the low density region in the metal oxide are distinguished by the amount of hydrogen contained in the region. In other words, the high density region is a region containing more hydrogen than the low density region. In the vicinity of the boundary between the high density region and the low density region in the metal oxide, minute cracks are likely to occur due to stress strain between the two regions, and oxygen deficiency and indium dangling bonds are generated near the crack. It is presumed that shallow defect levels are formed when impurities such as hydrogen or water are localized.

  In addition, the high-density region in the metal oxide may have higher crystallinity than the low-density region. The high density region in the metal oxide may have a higher film density than the low density region. In the case where the metal oxide has a composition including indium, gallium, and zinc, the high-density region includes indium, gallium, and zinc, and the low-density region includes indium, zinc, and the like. , May have. In other words, the low density region may have a smaller percentage of gallium than the high density region.

  The shallow defect level is presumed to be caused by oxygen vacancies. When oxygen vacancies in the metal oxide increase, it is estimated that deep defect levels (dDOS: deep level of states) increase as well as shallow defect levels. This is because deep defect levels are also considered to be due to oxygen vacancies. Note that the deep defect level refers to a defect level located near the center of the band gap.

  Therefore, by suppressing oxygen vacancies in the metal oxide, it is possible to reduce both the shallow defect level and the deep defect level. In addition, the shallow defect level may be controlled to some extent by adjusting the temperature at the time of forming the metal oxide. Specifically, when the temperature at the time of forming the metal oxide film is set to 170 ° C. or the vicinity thereof, preferably 130 ° C. or the vicinity thereof, and more preferably room temperature, the shallow defect level can be reduced.

  In addition, the shallow defect level of the metal oxide affects the electrical characteristics of a transistor in which the metal oxide is used for the semiconductor layer. That is, due to the shallow defect level, in the drain current-gate voltage (Id-Vg) characteristic of the transistor, the change of the drain current Id with respect to the gate voltage Vg becomes gradual, and the rising characteristic from the off state to the on state of the transistor is good or bad. The S value (also referred to as Subthreshold Swing, SS), which is one of the criteria for the above, deteriorates. This is probably because electrons were trapped in shallow defect levels.

For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be imparted.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. 4 to 11, (A) in each drawing shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each drawing is a cross-sectional view corresponding to the portion indicated by the one-dot chain line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of each figure (A), some elements are omitted for the sake of clarity.

  First, a substrate (not shown) is prepared, and an insulator 210 is formed over the substrate. The insulator 210 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD method. (Atomic Layer Deposition) method or the like can be used.

  The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

  In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

  The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since ALD does not cause plasma damage during film formation, a film with few defects can be obtained. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, a film provided by the ALD method may contain a larger amount of impurities such as carbon than a film provided by another film formation method. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

  The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

  In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation is shortened as compared with the case where film formation is performed using a plurality of film formation chambers because the time required for conveyance and pressure adjustment is not required. can do. Therefore, the productivity of the semiconductor device may be increased.

  In this embodiment, an aluminum oxide film is formed as the insulator 210 by a sputtering method. The insulator 210 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed on the aluminum oxide by a sputtering method.

  Next, the insulator 212 is formed over the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 212 by a CVD method.

  Next, an opening reaching the insulator 210 is formed in the insulator 212. The opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing. The insulator 210 is preferably selected from an insulator that functions as an etching stopper film when the opening is formed by etching the insulator 212. For example, in the case where a silicon oxide film is used for the insulator 212 that forms the opening, the insulator 210 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film as an insulating film that functions as an etching stopper film.

  After the opening is formed, a conductive film to be a first conductor of the conductor 203 is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the first conductor of the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, as the conductive film to be the first conductor of the conductor 203, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the first conductor of the conductor 203, even if a metal that is easily diffused, such as copper, is used in the second conductor of the conductor 203, which will be described later, the metal is the conductor 203. It is possible to suppress the diffusion from the first conductor.

  Next, a conductive film to be the second conductor of the conductor 203 is formed over the conductive film to be the first conductor of the conductor 203. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to be the second conductor of the conductor 203.

  Next, by performing CMP treatment, the conductive film to be the first conductor of the conductor 203 and part of the conductive film to be the first conductor of the conductor 203 are removed, and the insulator 212 is exposed. To do. As a result, the conductive film to be the second conductor of the conductor 203 and the conductive film to be the second conductor of the conductor 203 remain only in the opening. Accordingly, the conductor 203 including the first conductor of the conductor 203 and the second conductor of the conductor 203 having a flat upper surface can be formed (see FIG. 4). Note that part of the insulator 212 may be removed by the CMP treatment.

  Next, the insulator 214 is formed over the insulator 212 and the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that hardly transmits copper, such as silicon nitride, as the insulator 214, even if a metal that easily diffuses such as copper is used for the second conductor of the conductor 203, the metal is insulated. Diffusion to a layer above the body 214 can be suppressed.

  Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.

  Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216. A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing.

  After the opening is formed, a conductive film to be a first conductor of the conductor 205 is formed. The conductive film to be the first conductor of the conductor 205 preferably includes a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductive film to be the first conductor of the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, tantalum nitride is formed by a sputtering method as the conductive film to be the first conductor of the conductor 205.

  Next, a conductive film to be the second conductor of the conductor 205 is formed over the conductive film to be the first conductor of the conductor 205. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, as a conductive film to be the second conductor of the conductor 205, titanium nitride is formed by a CVD method, and tungsten is formed by a CVD method on the titanium nitride.

  Next, by performing CMP treatment, the conductive film to be the first conductor of the conductor 205 and part of the conductive film to be the second conductor of the conductor 205 are removed, and the insulator 216 is exposed. To do. As a result, the conductive film which becomes the first conductor of the conductor 205 and the second conductor of the conductor 205 remains only in the opening. Accordingly, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat upper surface can be formed (see FIG. 4). Note that part of the insulator 216 may be removed by the CMP treatment.

  Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 220 by a CVD method.

  Next, the insulator 222 is formed over the insulator 220. As the insulator 222, an insulator including one or both of aluminum and hafnium may be formed. Note that as the insulator including one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.

  The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 224 by a CVD method.

  Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere. Good.

  In this embodiment, as the heat treatment, treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed. By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.

  The heat treatment can also be performed at the timing after the insulator 220 is formed and after the insulator 222 is formed. Although the heat treatment conditions described above can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.

  Here, in order to form an excess oxygen region in the insulator 224, plasma treatment including oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, for example, an apparatus having a power source that generates high-density plasma using microwaves is preferably used. Alternatively, a power supply for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. it can. Alternatively, after performing plasma treatment containing an inert gas using this apparatus, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.

  Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 4). Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

  The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, in the case where the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the oxide film is formed by a sputtering method, the In-M-Zn oxide target can be used.

  In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.

  In the case where the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have a relatively high field-effect mobility.

  In this embodiment, the oxide film 230A is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. The oxide film 230B is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Note that each oxide film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

  Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.

  Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 5). Note that part of the insulator 224 may be removed by the processing.

  Here, the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially. Further, the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased. Note that the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.

  In addition, a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the oxide 230b. By not having a corner at the end, the coverage of the film in the subsequent film forming process is improved.

  Note that the oxide film may be processed by a lithography method. For the processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.

  In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, writing is performed directly on the resist, so that the resist exposure mask described above becomes unnecessary. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process. .

  Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after the resist mask is removed, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

  As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

  In addition, by performing the above-described treatment such as dry etching, impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a and the oxide 230b. Examples of impurities include fluorine and chlorine.

  Cleaning is performed in order to remove the impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be combined as appropriate.

  The wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

  Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

  Next, a film 242A is formed over the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 6). Note that the film 242A has a thickness of 0.5 nm to 5 nm, preferably, 1 nm to 3 nm. As the film 242A, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used. The film 242A is a film containing a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium. Note that the film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 280 is formed over the film 242A. The insulator 280 preferably includes an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, or resin It is preferable to have. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes for the insulating film 280 because an excess oxygen region can be easily formed in the insulator 280 in a later step. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. The insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used. . In this embodiment, silicon oxynitride is formed as the insulator 280 by a CVD method.

  Note that the insulator 280 is preferably formed so that an upper surface thereof has flatness. For example, the insulator 280 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.

  Next, the insulator 280 and the film 242A are processed so as to have at least a region overlapping with the conductor 205, so that the opening 245 and the layer 242 are formed (see FIG. 7). A wet etching method may be used for forming the opening, but a dry etching method is preferable for fine processing. Note that in some cases, part of the oxide 230b is removed by the processing.

  Subsequently, heat treatment is performed (see FIG. 8). The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. For example, the heat treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.

  Through the heat treatment in an atmosphere containing nitrogen, the above-described metal element diffuses from the layer 242 to the oxide 230, and the metal element can be added to the oxide 230. In addition, oxygen in the vicinity of the interface between the oxide 230 and the layer 242 may be absorbed by the layer 242. As a result, the vicinity of the interface of the oxide 230 with the layer 242 becomes a metal compound, and the resistance is reduced. At that time, part of the oxide 230 and the metal element described above may be alloyed. When a part of the oxide 230 and the metal element are alloyed, the metal element added to the oxide 230 is in a relatively stable state; thus, a highly reliable semiconductor device can be provided. Note that in FIG. 8B, the low-resistance region of the oxide 230 is indicated by hatching as an example.

  In addition, hydrogen in the oxide 230 diffuses into the region 231 and enters a relatively stable state when it enters oxygen vacancies existing in the region 231. Further, hydrogen in the oxygen vacancy existing in the region 234 escapes from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffuses into the region 231, enters the oxygen vacancy existing in the region 231, and is in a relatively stable state. Become. Therefore, by the heat treatment, the region 231 has a lower resistance, and the region 234 has a higher purity (reduction of impurities such as water and hydrogen) and has a higher resistance.

  Further, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.

  Further, in the case where a region having conductivity remains in the layer 242, it is oxidized by performing heat treatment in an oxidizing atmosphere, whereby an insulator is formed and resistance is increased. By leaving the layer 242 as an insulator, the layer 242 can function as an interlayer film.

  Note that in the heat treatment after the formation of the film 242A or after the formation of the layer 242, oxygen vacancies are generated in the region 231 because the film 242A or the layer 242 absorbs oxygen in the region 231 of the oxide 230. There is a case. As hydrogen in the oxide 230 enters the oxygen vacancies, the carrier density in the region 231 increases. Accordingly, the region 231 of the oxide 230 is n-type and has a low resistance.

  Next, an oxide film 230 </ b> C is formed over the insulator 280 so as to have a region in contact with the inner wall of the opening 245.

  The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c. In this embodiment, the oxide film 230C is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

  Subsequently, an insulating film 250A and a conductive film 260A are sequentially formed over the oxide film 230C (see FIG. 9).

  First, the insulating film 250A is formed. The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, silicon oxynitride is preferably formed by a CVD method. Note that the deposition temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly preferably around 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator with few impurities can be formed.

  Note that oxygen can be introduced into the insulating film 250A by exciting oxygen with a microwave to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.

  Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.

  Subsequently, a conductive film 260A is formed. Note that a metal oxide film may be separately formed before the formation of the conductive film 260A. As the metal oxide film, an In—Ga—Zn oxide is formed by a sputtering method, for example. As a method for forming the metal oxide film, a sputtering method is preferably used in an atmosphere containing oxygen gas. By forming the metal oxide film in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. The excess oxygen added to the insulating film 250 </ b> A can compensate oxygen vacancies in the oxide 230 by supplying oxygen to the oxide 230.

  Here, as a means for forming the metal oxide film, oxygen is introduced into the insulating film 250A while forming the metal oxide film by forming the film in an oxygen gas atmosphere using a sputtering apparatus. Can do. In addition, by using one or both of aluminum and hafnium having barrier properties for the metal oxide film, excess oxygen introduced into the insulating film 250A can be effectively contained.

  The conductive film 260A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the conductive film 260A may have a stacked structure of two or more layers. For example, titanium nitride may be formed as the first layer of the conductive film 260A, and tungsten may be formed as the second layer of the conductive film 260A.

  For example, a metal nitride may be formed by a sputtering method as the first layer of the conductive film 260A. For example, in the case where an oxide semiconductor typified by an In—Ga—Zn oxide is used as the above-described metal oxide film over the insulating film 250A, the metal oxide film is supplied with nitrogen or hydrogen, Carrier density increases. That is, the metal oxide film functions as an oxide conductor (OC: Oxide Conductor). Therefore, as a first layer of the conductive film 260A, a metal nitride is formed by a sputtering method, so that a constituent element (particularly nitrogen) in the metal nitride is diffused into the metal oxide film, and the metal oxide film is low. Make resistance. Further, the metal oxide film has a low resistance due to damage (for example, sputtering damage) at the time of forming the first layer of the conductive film 260A. Therefore, the carrier density of the metal oxide film is increased, and the conductivity of the metal oxide film is increased.

  Further, by stacking a low-resistance metal film as the second layer of the conductive film 260A, a transistor with a low driving voltage can be provided.

  Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. Through this heat treatment, excess oxygen is added to the insulating film 250A from the above-described metal oxide film, and an excess oxygen region can be easily formed in the insulating film 250A.

  Next, the oxide film 230C, the insulating film 250A, and the conductive film 260A are etched by a lithography method to form the oxide 230c, the insulator 250, and the conductor 260 (see FIG. 10). Note that part of the insulator 280 may be removed by the etching treatment.

  The oxide 230c, the insulator 250, and the conductor 260 are formed so that at least a part thereof overlaps with the conductor 205, the oxide 230a, and the oxide 230b.

  Here, an insulating film having a function as a barrier film may be separately formed. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thus, the conductor 260 can be prevented from being oxidized by oxygen or the like supplied from the conductor 274 to be formed later. Further, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed.

  Next, the insulator 274 is formed over the insulator 280 and the conductor 260 (see FIG. 11). The insulator 274 is preferably formed using aluminum oxide by a sputtering method. By using a sputtering method, an aluminum oxide film containing a large amount of oxygen and containing a small amount of impurities such as water or hydrogen can be formed.

  Alternatively, oxygen can be introduced into the insulator 280 while the insulator 274 is formed by forming a film in an oxygen gas atmosphere using a sputtering apparatus. Accordingly, oxygen in the insulator 274 is supplied to the insulator 280 using the insulator 274 as an oxygen supply source, and an excess oxygen region can be formed in the insulator 280.

  The insulator 280 in which the excess oxygen region is formed as described above can effectively supply oxygen from the excess oxygen region to the region 234 of the oxide 230 through the layer 242.

  Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed into the insulator 274 through the layer 242 and the insulator 280, so that hydrogen in the oxide 230 is reduced. You may be able to.

  Next, the insulator 281 is formed over the insulator 274. The insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used. . In this embodiment, silicon oxynitride is used as the insulator 281.

  Next, part of the insulator 281 is removed. The insulator 281 is preferably formed so that the top surface has flatness. For example, the insulator 281 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator 281 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 281 does not necessarily have flatness.

  Next, the insulator 282 is formed over the insulator 281. The insulator 282 is preferably provided with an insulator 282 made of the same material as the insulator 274. With this structure, impurities such as hydrogen and water from above the insulator 282 can be prevented from entering the transistor 200 side. In some cases, hydrogen contained in the insulator 281 can be extracted to the insulator 282.

  Next, an opening reaching the oxide 230 is formed in the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the layer 242. The opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.

  Next, a conductive film to be a first conductor of the conductor 240 and a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, for example, when the openings are formed in the insulator 282, the insulator 281, the insulator 274, the insulator 280, and the layer 242, the region of the oxide 230 in which the resistance is reduced may be removed. . Alternatively, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used as the first conductor of the conductor 240. Accordingly, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or an oxygen vacancy is formed in the region, and the contact region between the oxide 230 and the conductor 240 is reduced in resistance. Can be By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured. Therefore, the first conductor of the conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium.

  Next, a part of the conductive film to be the conductor 240a and the conductor 240b is removed by performing CMP treatment, and the insulator 282 is exposed. As a result, the conductor 240a and the conductor 240b having a flat upper surface can be formed by leaving the conductive film only in the openings (see FIG. 1). Note that part of the insulator 282 may be removed by the CMP treatment.

  Through the above steps, a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 4 to 11, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.

  According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

<Modification Example 1 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that described in the above <Structure example of semiconductor device> will be described with reference to FIGS.

  FIG. 12A is a top view of a semiconductor device including the transistor 200. FIG. 12B and 12C are cross-sectional views of the semiconductor device. Here, FIG. 12B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 12A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 12C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 12A and is a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 12A, some elements are omitted for clarity.

  Note that in the semiconductor device illustrated in FIGS. 12A and 12B, structures having the same functions as those of the semiconductor device illustrated in <Structure Example of Semiconductor Device> (see FIG. 1) are denoted by the same reference numerals.

  Hereinafter, the structure of the transistor 200 will be described with reference to FIGS. Note that also in this item, the material described in detail in <Structure example of semiconductor device> can be used as the constituent material of the transistor 200.

  The semiconductor device illustrated in FIG. 12 is different from the semiconductor device illustrated in <Structure example of semiconductor device> (see FIG. 1) in that the transistor 200 includes a conductor 251a and a conductor 251b. In the case where the transistor 200 has the above structure, the conductor 251a and the conductor 251b function as a source electrode or a drain electrode. Therefore, in this structure, the layer 242 sandwiched between the low resistance region (region 231) of the oxide 230 and the conductor 251a (conductor 251b) is different from the transistor 200 illustrated in FIG. It is necessary to have. That is, in the transistor 200 illustrated in FIG. 1, the layer 242 has an insulating property and functions as an interlayer film. However, in the transistor 200 illustrated in FIG. 12, the layer 242 has conductivity and the region 231a (the region 231b ) And the conductor 251a (the conductor 251b), and functions as a part of the source electrode or the drain electrode.

  Note that although the transistor 200 illustrated in FIG. 12 includes the layer 242, one embodiment of the present invention is not limited thereto. For example, the transistor 200 may not include the layer 242 and the conductors 251a and 251b and the oxide 230 may be in direct contact with each other. In the case where the transistor 200 has the above structure, after the film 242A described in <Method for manufacturing semiconductor device> is formed (see FIG. 6), a region of the film 242A which overlaps with the conductor 205 is removed to form the layer 242. It is preferable. After that, heat treatment is performed to reduce the resistance of the region where the oxide 230 and the layer 242 overlap, and then the layer 242 may be removed. Next, the opening 245 is formed after the insulator 280 is formed. Subsequently, through the steps illustrated in FIGS. 9 to 11, the semiconductor device including the transistor 200 illustrated in FIG. 12 can be manufactured.

<Second Modification of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that described in the above <Structure example of semiconductor device> will be described with reference to FIGS.

  FIG. 13A is a top view of a semiconductor device including the transistor 200. FIG. FIGS. 13B and 13C are cross-sectional views of the semiconductor device. Here, FIG. 13B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 13A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 13C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 13A and also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 13A, some elements are omitted for clarity.

  Note that in the semiconductor device illustrated in FIGS. 13A and 13B, structures having the same functions as those of the semiconductor device illustrated in <Structure Example of Semiconductor Device> (see FIG. 1) are denoted by the same reference numerals.

  Hereinafter, the structure of the transistor 200 will be described with reference to FIGS. Note that also in this item, the material described in detail in <Structure example of semiconductor device> can be used as the constituent material of the transistor 200.

  The semiconductor device illustrated in FIG. 13 is different from the semiconductor device illustrated in <Structure example of semiconductor device> (see FIG. 1) in which the side surfaces of the oxide 230a and the oxide 230b are parallel to the substrate surface. The difference is that it has a tapered structure. Specifically, as illustrated in FIG. 13B, the taper angle of the side surfaces of the oxide 230a and the oxide 230b may be 45 degrees to 80 degrees, preferably 50 degrees to 70 degrees.

  Therefore, as compared with the semiconductor device having a structure having no tapered shape (see FIG. 1), the side surface of the oxide 230a and the oxide 230b is also in contact with the film 242A (see FIG. 6). Become. Accordingly, the metal compound is reliably formed on the side surfaces of the oxide 230a and the oxide 230b, and the resistance can be reduced. That is, the region 231 can be reliably formed also on the side surface of the oxide 230. Further, when the side surfaces of the oxide 230a and the oxide 230b have a tapered structure, the film property of the structure formed in an upper layer than the oxide 230a and the oxide 230b can be improved.

<Modification 3 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that described in the above <Example of structure of semiconductor device> will be described with reference to FIGS.

  FIG. 14A is a top view of a semiconductor device including the transistor 200. FIG. FIGS. 14B and 14C are cross-sectional views of the semiconductor device. Here, FIG. 14B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 14A and also a cross-sectional view in the channel length direction of the transistor 200. 14C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 14A and is a cross-sectional view in the channel width direction of the transistor 200. FIG. Note that in the top view of FIG. 14A, some elements are omitted for clarity.

  Note that in the semiconductor device illustrated in FIGS. 14A and 14B, structures having the same functions as those of the semiconductor device illustrated in <Structure Example of Semiconductor Device> (see FIG. 1) are denoted by the same reference numerals.

  Hereinafter, the structure of the transistor 200 will be described with reference to FIGS. Note that also in this item, the material described in detail in <Structure example of semiconductor device> can be used as the constituent material of the transistor 200.

  The semiconductor device illustrated in FIG. 14 is different from the semiconductor device illustrated in <Structure example of semiconductor device> (see FIG. 1) in the shapes of the oxide 230c, the insulator 250, and the conductor 260 included in the transistor 200. Specifically, in the transistor 200 illustrated in FIG. 1, the oxide 230c, the insulator 250, and the conductor 260 are partly formed over the insulator 280, whereas the transistor 200 illustrated in FIG. The difference is that the heights of the top surfaces of the oxide 230c, the insulator 250, and the conductor 260 are approximately the same as the height of the top surface of the insulator 280.

  Note that the oxide 230c, the insulator 250, and the conductor 260 included in the transistor 200 illustrated in FIGS. 12A and 12B are formed after the oxide film 230C, the insulating film 250A, and the conductive film 260A described in <Method for manufacturing semiconductor device> are formed. (See FIG. 9), planarization treatment can be performed until the insulator 280 is exposed.

<Modification 4 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that described in the above <Structure example of semiconductor device> will be described with reference to FIGS.

  FIG. 15A is a top view of a semiconductor device including the transistor 200. FIG. FIGS. 15B and 15C are cross-sectional views of the semiconductor device. Here, FIG. 15B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 15A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 15C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 15A and is a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 15A, some elements are omitted for clarity.

  Note that in the semiconductor device illustrated in FIGS. 15A and 15B, structures having the same functions as those of the semiconductor device illustrated in <Structure Example of Semiconductor Device> (see FIG. 1) are denoted by the same reference numerals.

  Hereinafter, the structure of the transistor 200 will be described with reference to FIGS. Note that also in this item, the material described in detail in <Structure example of semiconductor device> can be used as the constituent material of the transistor 200.

  In the semiconductor device illustrated in FIG. 15, the heights of the top surfaces of the oxide 230 c, the insulator 250, and the conductor 260 are approximately the same as the height of the top surface of the insulator 280, as in the semiconductor device illustrated in FIG. 14 described above. This is different from the semiconductor device (see FIG. 1) described in <Structure example of semiconductor device>. When compared with the semiconductor device illustrated in FIG. 14, the shapes of the oxide 230c, the insulator 250, and the conductor 260 are different. Specifically, in the semiconductor device illustrated in FIG. 14, the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 included in the transistor 200 have a tapered shape with respect to the substrate surface. 15 is different in that the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 included in the transistor 200 have a shape substantially perpendicular to the substrate surface. As shown in FIG. 15, the conductor 260 having a function as the first gate electrode of the transistor 200 has a shape substantially perpendicular to the substrate surface, so that the conductor 240a having a function as a plug is electrically connected to the conductor 240a. The distance from the body 240b can be reduced, and the transistor 200 can be miniaturized.

  As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)
Hereinafter, hydrogen in IGZO that can be used as an oxide semiconductor in the transistor 200 according to one embodiment of the present invention is described.

<1. Transfer of hydrogen atoms>
Here, the ease of movement of hydrogen atoms in the IGZO crystal was evaluated from the viewpoint of the activation barrier on the movement path of hydrogen atoms. Note that hopping from one oxygen to another and movement on one oxygen were assumed as the movement mode of hydrogen atoms.

FIG. 16 shows a schematic diagram of region division in InGaZnO ₄ crystal in which the movement path of hydrogen atoms was examined. Here, the path (in the ab plane direction) and each region in the InO ₂ region, the (Ga, Zn) O region, and the region between the InO ₂ surface and the (Ga, Zn) O surface shown in FIG. The traversing path (c-axis direction) was examined.

  The evaluation of the activation barrier was performed using the first-principles electronic state / molecular dynamics calculation package VASP (Vienna ab initio simulation package), and the NEB (Nudged Elastic Band) method, which is a chemical reaction path search method, was used. The NEB method is a technique for finding a state where the required energy is the lowest among the states connecting the two states from the initial state and the final state. The activation barrier was the difference between the maximum energy in the pathway and the energy of the most stable structure on the pathway.

<< Area between InO ₂ plane and (Ga, Zn) O plane >>
FIG. 17 shows a movement path of hydrogen atoms in a region between the InO ₂ plane and the (Ga, Zn) O plane and an activation barrier on the path. However, based on the most stable structure on the path, the energy of the structure was used as the energy origin. FIGS. 17A and 17C show the movement of hydrogen atoms, which are referred to as path A and path B, respectively. Note that in FIGS. 17A to 17D, numerals indicate the order of movement of hydrogen atoms. The path A is a linear path with respect to the path from 3 to 4 for the hydrogen atoms. On the other hand, in the path B, the path through which hydrogen atoms go from 3 to 4 is a path through 5.

  FIG. 17B shows an activation barrier in the path A (path in which hydrogen atoms move from 1 to 4), and FIG. 17D shows the path B (in which hydrogen atoms move from 1 to 4 to 5). The activation barrier in the route traveled via).

The activation barrier on the path A shown in FIG. 17B was 1.12 eV, and the activation barrier on the path B shown in FIG. 17D was 0.23 eV. Since the activation barrier on the path B is smaller than the path A, it is considered that the path B having a low barrier on the path is likely to occur when the hydrogen atoms go from 3 to 4. That is, when hydrogen atoms move in the region between the InO ₂ surface and the (Ga, Zn) O surface, it is presumed that the path B having a low barrier on the path is likely to occur.

<< (Ga, Zn) O region >>
Next, the movement path of hydrogen atoms in the (Ga, Zn) O region and the activation barrier on the path are shown in FIG. However, the most stable structure on the path was used as a reference, and the structure was used as the origin of energy. FIG. 18A shows the movement of hydrogen atoms in the (Ga, Zn) O region. In FIG. 18A, numbers indicate the order of movement of hydrogen atoms. FIG. 18B shows an activation barrier in the path in which hydrogen atoms move from 1 to 4 in FIG.

From FIG. 18B, the activation barrier on the movement path of hydrogen atoms in the (Ga, Zn) O region is 0.16 eV, which is smaller than the activation barrier shown in FIG. Recognize. Considering only the height of the barrier, when hydrogen atoms are present in the (Ga, Zn) O region, compared to the case where they are present in the region between the InO ₂ surface and the (Ga, Zn) O surface, The movement of hydrogen atoms is expected to occur easily.

<< InO ₂ region >>
Next, FIG. 19 shows a movement path of hydrogen atoms in the InO ₂ region and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and the structure was used as the origin of energy. FIG. 19A shows how hydrogen moves in the InO ₂ region. In FIG. 19A, numbers indicate the order of movement of hydrogen atoms. FIG. 19B shows an activation barrier in the path in which hydrogen atoms move from 1 to 4 in FIG.

From FIG. 19B, the activation barrier when hydrogen atoms move from one oxygen to another in the InO ₂ region was 1.2 eV or more. That is, it can be seen that the activation barrier on the migration path of hydrogen atoms in the InO ₂ region is very large as compared with the activation barrier shown in FIGS. 17D and 18B. Therefore, it is considered that hydrogen atoms are less likely to move in the InO ₂ region than in other regions.

  Next, FIG. 20 shows a movement path of hydrogen atoms along the c-axis direction and an activation barrier on the path. However, the most stable structure on the path was used as a reference, and the structure was used as the origin of energy. FIG. 20A shows the movement of hydrogen atoms along the c-axis direction. In FIG. 20A, the numbers indicate the order of movement of hydrogen atoms. FIG. 20B shows an activation barrier in the path in which hydrogen atoms move from 1 to 8 in FIG.

From FIG. 20B, the activation barrier in the path in which hydrogen atoms move from 2 to 5 was 0.9 eV. That is, it can be seen that there is a large activation barrier when hydrogen atoms enter or leave the (Ga, Zn) O region. This is thought to be because the movement path of hydrogen atoms blocks the bond between metal atoms and oxygen atoms. In addition, from FIG. 20B, the activation barrier in the path through which hydrogen atoms move from 7 to 8 was about 1.3 eV. That is, the presence of a large activation barrier is confirmed even by the movement of hydrogen atoms in the InO ₂ region. For this reason, it is expected that continuous movement of hydrogen atoms in the c-axis direction hardly occurs. One possible cause of the large activation barrier is the large In ion radius.

  Here, the movement frequency (Γ) was calculated from the activation barrier obtained by the calculation and the following Equation 1.

Here, E _a is an activation barrier, k _B is a Boltzmann constant, T is an absolute temperature, and ν is a frequency factor.

  Finally, Table 1 shows the movement frequency estimated from the maximum barrier on each path.

At both 27 ° C. and 450 ° C., the frequency of movement in the ab plane direction in the region between the InO ₂ surface and the (Ga, Zn) O surface and in the (Ga, Zn) O region is the highest, while c in the InO ₂ region It was found that the frequency of movement in the axial direction tends to be low. That is, it is suggested that in a complete crystal system, hydrogen preferentially diffuses along the ab plane. However, it was found that in the heat treatment at 450 ° C., hydrogen diffuses sufficiently in the IGZO film.

<2. Site where oxygen deficiency _VO is easy to create>
Since the strength of the bond between the metal atom and the oxygen atom varies depending on the type and valence of the metal, the ease of oxygen deficiency V _{O in} IGZO depends on the type, number, distance, etc. of the metal that becomes the bond partner of the oxygen atom. It is estimated that a difference will occur. Therefore, the ease of oxygen deficiency was calculated for the InGaZnO ₄ crystal model.

InGaZnO ₄ crystal model (112 atoms) was used for the calculation. This model is shown in FIG. Ga and Zn in the (Ga, Zn) O region were arranged so as to be stable in terms of energy. At this time, there are four types of oxygen sites based on the binding partner and number (1 to 4 shown in FIG. 21). It shows in Table 2 about each oxygen site.

  An oxygen deficiency model was created by extracting one oxygen atom from the oxygen site from the above model, and the total energy after structure optimization was compared. Table 3 shows the calculation conditions.

  A comparison of the total energy for the optimized structure was made. The relative value of the total energy is shown in FIG. 22 with the total energy of the oxygen deficiency model at the oxygen site 4 as a reference (0.0 eV). From FIG. 22, it is estimated that oxygen vacancies are easily formed at the oxygen sites 4 and the oxygen sites 2 are also relatively easily formed. On the other hand, it is estimated that the oxygen site 1 and the oxygen site 3 are less likely to be formed as compared with the oxygen site 2 and the oxygen site 4.

<3. Ease of formation and stability of H 2 _O >
In IGZO, the calculation results show that hydrogen diffuses particularly during heat treatment, <1. This has been explained in <Transfer of hydrogen atom>. Therefore, if the oxygen deficiency V _O is present, hydrogen in an oxygen-deficient V _O has been calculated for one get out of oxygen vacancies V _O. Here, a state in which a hydrogen atom is present in the oxygen deficiency V 2 _O is denoted as H 2 _O (may be denoted as V _O H).

The InGaZnO ₄ crystal model shown in FIG. 21 was used for the calculation. Here, hydrogen atoms in the oxygen-deficient V _O is exit the V _O, the movement path of the hydrogen atoms to bind oxygen atom, activation barrier to (E _a) was calculated using the NEB method. Table 4 shows the calculation conditions.

The calculation result that the oxygen site that is most likely to form the oxygen deficient V _O is the oxygen site 4 shown in FIG. This is explained in “Site where oxygen deficiency V 2 _O easily occurs”. Therefore, either when present on the oxygen sites in which oxygen vacancies V _O is bonded to one of Ga and two Zn (4 shown in FIG. 21), hydrogen atoms in the oxygen-deficient V _O is get out of oxygen vacancies V _O The calculation was performed.

The model in the initial state is shown in FIG. 23A, and the model in the final state is shown in FIG. Note that the initial state here is a state where a hydrogen atom is present in the oxygen deficiency V 2 _O (H 2 _{O 3} ), and the final state is a bond between the oxygen deficiency V 2 _O , one Ga and two Zn. It is a structure which has the state (H-O) which the oxygen atom and hydrogen atom which were performed. FIG. 24 shows an activation barrier in a path through which hydrogen atoms move from the initial state to the final state. Here, the total energy in the initial state was set as a reference (0.0 eV).

As a result of the calculation, the activation barrier (E _a ) when hydrogen atoms in oxygen-deficient V 2 _O escape from Vo was about 1.70 eV.

Then, from the calculated with resulting activation barrier (E _a) and the above equation 1, per hour, the hydrogen atoms in the oxygen vacancy V _O is to calculate an average number of times to get out of oxygen vacancy V _O.

Assuming the frequency factor ^{ν = 10 13 [1 / sec} ], at room temperature and 250 ° C., the hydrogen atoms in the oxygen vacancy _{V O} is to calculate an average number of times to get out of oxygen vacancy _{V O.} The average number of times hydrogen atoms move from the model shown in FIG. 23A to the model shown in FIG. ^23B was about 1 × 10 ⁻¹² [times] at room temperature. Therefore, at room temperature, the probability that hydrogen atoms in the oxygen vacancy V _O exits from the oxygen vacancies V _O is very low, the state of H _O is suggested to be stable. Further, the average number of times hydrogen atoms move from the model shown in FIG. 23A to the model shown in FIG. 23B was about 2 [times] at 250 ° C. Therefore, when the baking for one hour at 250 ° C. or higher, it is suggested the hydrogen atoms in the oxygen vacancy V _O is possible to get out of oxygen vacancy V _O.

From the above, it was found that hydrogen in the oxygen deficiency V _O existing in the channel formation region escapes from the oxygen deficiency V _O by the heat treatment. Further, it has been found that hydrogen escaped from the oxygen deficiency diffuses into the low resistance region, enters the oxygen deficiency V _O existing in the low resistance region, and easily becomes H 2 _O. Therefore, the channel formation region is highly purified (reduction of impurities such as water and hydrogen) by heat treatment, and normally-off transistor characteristics are obtained.

  As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 3)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

<Configuration Example 1 of Semiconductor Device>
25A, 25B, and 25C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.

  FIG. 25A is a top view of a cell 600 including the transistor 200 and the capacitor 100. 25B and 25C are cross-sectional views of the cell 600. FIG. Here, FIG. 25B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 25A and also a cross-sectional view in the channel length direction of the transistor 200. FIG. 25C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 25A and is a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 25A, some elements are omitted for clarity.

[Cell 600]
The semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulators 281 and 282 which function as interlayer films. In addition, a conductor 240 (a conductor 240a, a conductor 240b, and a conductor 240c) that is electrically connected to the transistor 200 and functions as a plug is included.

  In the cell 600 illustrated in FIG. 25, the transistor 200 and the capacitor 100 are provided in the same layer, so that part of the structure included in the transistor 200 is used in combination with part of the structure included in the capacitor 100. be able to. That is, part of the structure of the transistor 200 may function as part of the structure of the capacitor 100.

  In addition, when the capacitor 200 is partially or entirely overlapped with the transistor 200, the total area of the projected area of the transistor 200 and the projected area of the capacitor 100 can be reduced.

  Further, the conductor 240b functioning as a plug or wiring electrically connected to the transistor 200 and the conductor 207 are provided below the region where the capacitor 100 and the transistor 200 overlap with each other, whereby the cell 600 can be miniaturized. Or high integration becomes easy. In addition, since the conductor 207 can be formed in the same process as the conductor 205 which is the structure of the transistor 200, the process can be shortened. In the capacitor 100, similarly to the transistor 200, a conductor 203 functioning as a wiring may be provided in contact with the lower surface of the conductor 207.

  Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on a required capacitance value.

  For example, the area of the capacitor 100 is determined by the area where the region 231b of the oxide 230 overlaps with the conductor 120. Therefore, in the case where the capacitance value necessary for the cell 600 cannot be obtained with the capacitor 100 illustrated in FIGS. 25A and 25B, the width in the A3-A4 direction in the region 231b of the oxide 230a and the oxide 230b Can be made larger than the width in the A3-A4 direction in the region 234 of the oxide 230a and the oxide 230b, whereby the capacitance value can be increased.

  For example, the length in the A1-A2 direction in the region 231b of the oxide 230 may be longer than the length in the A1-A2 direction in the conductor 120. In that case, the conductor 240 b can be embedded in the insulator 280, the insulator 274, the insulator 281, and the insulator 282. That is, the oxide 230 region 231b and the conductor 240b may be provided in contact with each other in a region where the oxide 230 region 231b and the conductor 120 do not overlap. Therefore, the process can be shortened by forming the conductor 240a, the conductor 240b, and the conductor 240c in the same process.

  With the above structure, miniaturization or high integration is possible. In addition, the degree of freedom in design can be increased. The transistor 200 is formed in the same process as the capacitor 100. Therefore, since the process can be shortened, productivity can be improved.

[Transistor 200]
As the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 200 illustrated in FIGS. 25A and 25B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

[Capacitance element 100]
As shown in FIG. 25, the capacitor 100 has a structure in common with the transistor 200. In this embodiment, the region 231 b provided in the oxide 230 of the transistor 200 is described as an example of the capacitor 100 that functions as one of the electrodes of the capacitor 100.

  The capacitor 100 includes a region 231b of the oxide 230, a layer 242 over the region 231b, an insulator 291 over the layer 242, an insulator 292 over the insulator 291, an insulator 293 over the insulator 292, and an insulator 293. A conductor 120 is included. Further, the conductor 120 is preferably provided over the layer 242, the insulator 291, the insulator 292, and the insulator 293 so that at least part of the conductor 120 overlaps with the region 231b of the oxide 230. In addition, the conductor 240c is preferably disposed in contact with the conductor 120.

  The region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 functions as the other of the electrodes of the capacitor 100. The layer 242, the insulator 291, the insulator 292, and the insulator 293 function as a dielectric of the capacitor 100. The region 231b of the oxide 230 has a reduced resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.

  FIG. 25 illustrates a four-layer structure in which the layer 242, the insulator 291, the insulator 292, and the insulator 293 are provided as the dielectric of the capacitor 100; however, the present invention is not limited to this. For example, in addition to the layer 242, the insulator 291, the insulator 292, and the insulator 293, a structure in which an insulator for dielectric is separately stacked (a structure of five layers or more) may be employed. Alternatively, a single-layer, two-layer, or three-layer structure including any of the layer 242, the insulator 291, the insulator 292, and the insulator 293 may be used.

  The conductor 120 is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. Although not illustrated, the conductor 120 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.

<Configuration Example 2 of Semiconductor Device>
A cell 600 illustrated in FIG. 26 is a structural example of a cell different from the cell 600 (see FIG. 25) described in <Structural Example 1 of Semiconductor Device>.

  FIG. 26A is a top view of a cell 600 including the transistor 200 and the capacitor 100. FIG. 26B and FIG. 26C are cross-sectional views of the cell 600. Here, FIG. 26B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 26A and is a cross-sectional view in the channel length direction of the transistor 200. FIG. 26C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 26A and is a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 26A, some elements are omitted for clarity.

  A cell 600 illustrated in FIG. 26 is different from the cell 600 illustrated in FIG. 25 in that a transistor having the structure illustrated in FIG. Specifically, the transistor 200 is different from the cell 600 illustrated in FIGS. 25A and 25B in that the transistor 200 includes a conductor 251a and a conductor 251b functioning as a source electrode and a drain electrode.

  26 has the above structure, the conductor 251b functions as one of the electrodes of the capacitor 100. For the structures other than the above, the contents described in <Structure Example 1 of Semiconductor Device> can be referred to.

<Structure of cell array>
Here, an example of the cell array of this embodiment is illustrated in FIGS. For example, the cell array including the transistor 200 and the capacitor 600 including the capacitor 100 illustrated in FIG. 25 can be arranged in a matrix or matrix.

  FIG. 27A is a circuit diagram illustrating an embodiment in which the cells 600 illustrated in FIG. 25 are arranged in a matrix. In FIG. 27A, one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of a source and a drain of a transistor included in a cell arranged in the column direction. On the other hand, the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.

  FIG. 27B illustrates a circuit 610 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. It is sectional drawing extracted. FIG. 27B is a cross-sectional view of the cell 600a and the cell 600b.

  The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

  One of a source and a drain of the transistor 200a and one of a source and a drain of the transistor 200b are both electrically connected to BL02.

  With the above structure, by sharing a wiring electrically connected to one of the source and the drain, the occupied area of the cell array can be further reduced.

  FIG. 28A is a circuit diagram illustrating a mode different from FIG. 27A in a circuit in which the cells 600 illustrated in FIG. 25 are arranged in a matrix. In FIG. 28A, the first gate of the transistor included in the cell 600 arranged in the row direction is electrically connected to the common WL (WL01, WL02, WL03). In addition, one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, the transistor included in each cell 600 may be provided with the second gate BG. Vth of the transistor can be controlled by a potential applied to BG. In addition, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL. Here, as shown in FIG. 28A, the second electrode having the capacity of the cell 600 is electrically connected to the common PL with the second electrode having the capacity of the cell 600 adjacent to the cell 600. It is good also as a structure.

  FIG. 28B illustrates a circuit 620 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. It is sectional drawing extracted. FIG. 28B is a cross-sectional view of the cell 600a and the cell 600b.

  The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

  The second electrode of the capacitor 100a and the second electrode of the capacitor 100b use a common conductor, and the conductor is electrically connected to the PL.

  In addition, the cells 600 may be arranged not only in a plane but also in a stacked manner. FIG. 29 is a cross-sectional view of a configuration in which n + 1 layers of a cell array including the circuit 610 are stacked. As shown in FIG. 29, by stacking a plurality of cell arrays, the cells can be integrated and arranged without increasing the exclusive area of the cell array. That is, a 3D cell array can be configured.

  As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 4)
In this embodiment, one embodiment of a semiconductor device will be described with reference to FIGS.

<Storage device 1>
The memory device illustrated in FIGS. 30, 31, and 32 includes the transistor 300, the transistor 200, and the capacitor 100. 30 and 32 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction. FIG. 31 is a cross-sectional view in the channel width direction of the transistor 300 in the vicinity of the transistor 300.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

  In the memory device illustrated in FIGS. 30 and 32, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. Yes. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The memory device illustrated in FIGS. 30 and 32 has the characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.

  Information writing and holding will be described. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is supplied to the node SN that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is supplied to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as a Low level charge and a High level charge) that gives two different potential levels is given. After that, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, whereby charge is held at the node SN (holding).

  When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is applied to the wiring 1001, the wiring 1002 has a potential corresponding to the amount of charge held in the node SN. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 300 is the case where a low level charge is applied to the gate of the transistor 300 This is because it becomes lower than the apparent threshold voltage _{Vth_L} . Here, the apparent threshold voltage refers to the potential of the wiring 1005 necessary for bringing the transistor 300 into a conductive state. Therefore, the charge given to the node SN can be determined by _setting the potential of the wiring 1005 to the potential V ₀ between V _{th_H} and V _{th_L} . For example, in writing, when a high-level charge is _{supplied to} the node SN, the transistor 300 is turned on when the potential of the wiring 1005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is applied to the node SN, the transistor 300 remains non-conductive even when the potential of the wiring 1005 is V ₀ (<V _{th_L} ). Therefore, by determining the potential of the wiring 1002, information held in the node SN can be read.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.

  In the transistor 300, as illustrated in FIG. 31, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with a conductor 316 with an insulator 315 interposed therebetween. In this manner, when the transistor 300 is of the Fin type, an effective channel width is increased, whereby the on-state characteristics of the transistor 300 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 300 can be improved.

  The transistor 300 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that Vth of the transistor can be adjusted by determining a work function depending on a material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIGS. 30A and 30B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.

  As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. ¹⁵ atom / cm ² or less, and may be preferably 5 × ¹⁰ 15 atom / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 30, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. The insulator 350, the insulator 352, and the insulator 354 are each provided with a conductor 356. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 30, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 30, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 30, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described above, the memory device according to this embodiment is It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

  An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

  For example, the insulator 210 and the insulator 214 are each formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  As the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  For example, the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (the conductor 205) included in the transistor 200, and the like. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

  A transistor 200 is provided above the insulator 216. Note that as the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. A transistor 200 illustrated in FIGS. 30A and 30B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 281 is provided above the transistor 200.

  An insulator 282 is provided over the insulator 281. The insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. For example, the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  An insulator 286 is provided over the insulator 282. The insulator 286 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 274, the insulator 281, the insulator 282, and the insulator 286 are embedded with a conductor 246, a conductor 248, and the like. Yes.

  The conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, the capacitor element 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

  Further, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 functions as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

  The conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  In FIG. 30, the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  The conductor 120 is provided so as to overlap with the conductor 110 with the insulator 130 interposed therebetween. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

  By using this structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification of Storage Device 1>
Hereinafter, an example of a memory device according to one embodiment of the present invention will be described with reference to FIG.

  FIG. 32 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. Note that in the memory device illustrated in FIG. 32, structures having the same functions as those of the semiconductor device described in the above embodiment and <Structure of the memory device 1> and a structure forming the memory device are denoted by the same reference numerals. To do.

  32 differs from the storage device shown in <Structure of storage device 1> in that the cell 600 described in the above embodiment is provided.

  Specifically, as illustrated in FIG. 32, instead of the capacitor 100 and the transistor 200, a cell 600 sharing a part of the structure of the capacitor 100 and a part of the structure of the transistor 200 is provided.

  With the above structure, part or the whole of the cell 600 and the transistor 300 overlap with each other, whereby the total area of the projected areas of the memory device can be reduced. Accordingly, the cell 600 can be easily miniaturized or highly integrated. In addition, the process can be shortened.

<Storage device 2>
A semiconductor device illustrated in FIG. 33 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. Hereinafter, one mode as a storage device will be described with reference to FIG.

  FIG. 33A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 33B is a cross-sectional view of the semiconductor device in which the wiring 1004 to the wiring 1010 illustrated in FIG.

  Transistor 200 and transistor 400 formed over a substrate (not shown) have different structures. For example, the transistor 400 may have a structure in which the drain current when the bottom gate potential and the top gate potential are 0 V is smaller than that of the transistor 200. The transistor 400 is used as a switching element so that the potential of the bottom gate of the transistor 200 can be controlled. Accordingly, after the node connected to the bottom gate of the transistor 200 is set to a desired potential, the transistor 400 is turned off, whereby the charge of the node connected to the bottom gate of the transistor 200 is prevented from being lost. it can.

  As illustrated in FIG. 33, the transistor 200 has a gate electrically connected to the wiring 1004, one of a source and a drain is electrically connected to the wiring 1003, and the other of the source and the drain is electrically connected to one of the electrodes of the capacitor 100. In addition, the other electrode of the capacitor 100 is electrically connected to the wiring 1005. In addition, the drain of the transistor 400 is electrically connected to the wiring 1010. In addition, as illustrated in FIG. 33B, the bottom gate of the transistor 200 and the source, top gate, and bottom gate of the transistor 400 are electrically connected to each other through a wiring 1006, a wiring 1007, a wiring 1008, and a wiring 1009. Connected.

  Here, by applying a potential to the wiring 1004, the on state and the off state of the transistor 200 can be controlled. When the transistor 200 is turned on and a potential is applied to the wiring 1003, electric charge can be supplied to the capacitor 100 through the transistor 200. At this time, the charge supplied to the capacitor 100 can be held by turning off the transistor 200. The wiring 1005 can be controlled to have a potential at a connection portion between the transistor 200 and the capacitor 100 by capacitive coupling by applying an arbitrary potential. For example, when the ground potential is applied to the wiring 1005, the charge is easily held. Further, by applying a negative potential to the wiring 1010, a negative potential is applied to the bottom gate of the transistor 200 through the transistor 400, the Vth of the transistor 200 is made larger than 0 V, the off current is reduced, and Icut is Can be very small. Here, Icut refers to the drain current when the potential applied to the top gate is 0V.

  When the top gate and the bottom gate of the transistor 400 are diode-connected to the source and the source of the transistor 400 is connected to the bottom gate of the transistor 200, the bottom gate potential of the transistor 200 can be controlled by the wiring 1010. . When the negative potential of the bottom gate of the transistor 200 is held, the voltage between the top gate and the source of the transistor 400 and the voltage between the bottom gate and the source are 0V. Since Icut of the transistor 400 is very small and Vth is larger than that of the transistor 200, the negative potential of the bottom gate of the transistor 200 can be maintained for a long time without supplying power to the transistor 400 with this structure. .

  Further, by maintaining the negative potential of the bottom gate of the transistor 200, Icut of the transistor 200 can be extremely reduced without supplying power to the transistor 200. That is, electric charge can be held in the capacitor 100 for a long time without supplying power to the transistor 200 and the transistor 400. For example, by using such a semiconductor device as a memory element, long-term memory retention can be performed without power supply. Therefore, a memory device that has a low refresh operation frequency or does not require a refresh operation can be provided.

  Note that the connection relation of the transistor 200, the transistor 400, and the capacitor 100 is not limited to that illustrated in FIGS. 33A and 33B. The connection relationship can be changed as appropriate according to the required circuit configuration.

<Structure of storage device 2>
FIG. 33B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device illustrated in FIG. 33, structures that have the same functions as those of the semiconductor device described in the above embodiment and <Structure of the memory device 1> and the structure of the memory device are denoted by the same reference numerals. To do.

  A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 200 and the transistor 400.

  Note that as the capacitor 100 and the transistor 200, the capacitor and the transistor included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 30 and 32 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 33A and 33B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, an insulator 450 functioning as a gate insulator, an oxide 430c having a region where a channel is formed, The oxide 431a and the oxide 431b functioning as one of the source and the drain and the oxide 432a and the oxide 432b functioning as the other of the source and the drain are included. In addition, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 functioning as a wiring.

  In the transistor 400, the conductor 405 is the same layer as the conductor 205. The oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260.

  In the oxide 430c functioning as a channel formation region of the transistor 400, oxygen vacancies are reduced and impurities such as hydrogen or water are reduced as in the oxide 230 and the like. Accordingly, Vth of the transistor 400 can be increased from 0 V, the off-state current can be reduced, and the drain current when the bottom gate potential and the top gate potential are 0 V can be extremely reduced.

  As described above, the oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. Thus, the oxide 431a, the oxide 432a, the oxide 431b, and the oxide 432b are formed with low resistance regions corresponding to the region 231a and the region 231b.

  By using this structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
A semiconductor device illustrated in FIG. 34 is a memory device including the transistor 300, the transistor 200, and the capacitor 100. Hereinafter, one embodiment of a storage device will be described with reference to FIG.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

  34, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. . The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the bottom gate of the transistor 400, and the wiring 1010 is connected to the drain of the transistor 400. And are electrically connected. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

  The semiconductor device illustrated in FIG. 34 has a characteristic that the potential of the gate of the transistor 300 can be held, so that data can be written, held, and read as described below.

  Information writing and holding will be described. First, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 1003 is supplied to the node SN that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is supplied to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as a Low level charge and a High level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node SN (holding).

  When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 1005 in a state where a predetermined potential (constant potential) is applied to the first wiring 1001, the second wiring 1002 has a charge held in the node SN. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 300 is the case where a low level charge is applied to the gate of the transistor 300 This is because it becomes lower than the apparent threshold voltage _{Vth_L} . Here, the apparent threshold voltage refers to the potential of the fifth wiring 1005 necessary for bringing the transistor 300 into a conductive state. Therefore, by _setting the potential of the fifth wiring 1005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node SN can be determined. For example, in writing, when a high-level charge is applied to the node SN, the transistor 300 is _{turned on} when the potential of the fifth wiring 1005 is V ₀ (> V th — _H ). On the other hand, when a low-level charge is applied to the node SN, the transistor 300 remains non-conductive even when the potential of the fifth wiring 1005 is V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 1002, the information held in the node SN can be read.

<Structure of storage device 3>

  FIG. 34 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. 34 has the same function as the structure of the semiconductor device and the memory device shown in the above embodiment, <Structure of memory device 1>, and <Structure of memory device 2>. The same symbols are added to the structures having the same.

  The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

  Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 34A and 34B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  In the memory device illustrated in FIG. 34, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, the layer 242, the insulator 280, the insulator 274, and the insulator 281 have openings. In the example, the portion 500 is provided and the insulator 210 and the insulator 282 are connected. With such a structure, the transistor 200 and the transistor 400 are surrounded by the insulator 210 and the insulator 282 and thus are not easily affected by impurities such as water and hydrogen. In addition, release of oxygen in the oxide or the insulator to the outside is reduced. A memory device having such a structure is preferable because reliability is improved. Note that the opening 500 is not necessarily provided.

  By using this structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

  An example of the memory cell array of this embodiment is illustrated in FIG. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

  Note that the memory device illustrated in FIG. 35 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIGS. 30 and 34 in a matrix. Note that one transistor 400 can control the bottom gate potential of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.

  Therefore, the transistor 400 illustrated in FIG. 34 is not illustrated in FIG. FIG. 35 is a cross-sectional view of a part of a row in the case where the memory devices shown in FIGS. 30 and 34 are arranged in a matrix.

  Further, the structure of the transistor 300 is different from that in FIG. In the transistor 300 illustrated in FIG. 35, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

  In the memory device shown in FIG. 35, a memory cell 650a and a memory cell 650b are arranged adjacent to each other. The memory cell 650a and the memory cell 650b each include the transistor 300, the transistor 200, and the capacitor 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006. In the memory cell 650a and the memory cell 650b, a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is a node SN. Note that the wiring 1002 is a wiring common to the adjacent memory cells 650a and 650b.

When memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, when the memory cell array has a NOR structure, only information on a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned off regardless of the charge applied to the node SN, that is, a potential lower than V _{th_H} may be _supplied to the wiring 1005 connected to the memory cell from which information is not read. . Alternatively, for example, when the memory cell array has a NAND structure, only information on a desired memory cell can be read by turning on the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned on regardless of the charge applied to the node SN, that is, a potential higher than V _{th_L} may be _supplied to the wiring 1005 connected to the memory cell from which information is not read.

  By using this structure, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

  As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 5)
In this embodiment, an inverter circuit using the semiconductor device described in the above embodiment is described. Note that in this specification, a high power supply voltage may be referred to as an H level (or VDD), and a low power supply voltage may be referred to as an L level (or GND).

<Configuration example of inverter circuit>
A circuit INV illustrated in FIG. 36A includes a capacitor C1, and a transistor M1, a transistor M2, and a transistor M3 connected in series. The circuit INV has a function as an inverter circuit.

  The transistors M1 to M3 are n-channel transistors. Since the circuit INV includes only n-channel transistors, manufacturing cost can be reduced as compared with an inverter circuit including CMOS transistors.

  As the transistors M1 to M3, the transistor 200 described in the above embodiment is preferably used.

  The transistor M1 has a first gate and a second gate that are electrically connected to each other. The first gate and the second gate have regions overlapping each other with a semiconductor layer interposed therebetween. The same applies to the transistors M2 and M3. The first gate may be referred to as a top gate and the second gate may be referred to as a bottom gate.

  The circuit INV includes a terminal IN, a terminal OUT, a terminal CLK, and a terminal CLKB. The terminal IN functions as an input terminal, and the terminal OUT functions as an output terminal. A clock signal is input to the terminal CLK, and an inverted signal of the clock signal input to the terminal CLK is input to the terminal CLKB.

  The circuit INV is supplied with VDD and VSS as power supply voltages. VDD is a high power supply voltage and is input to the drain of the transistor M1. VSS is a low power supply voltage and is input to the source of the transistor M3.

  In the transistor M1, the top gate and the bottom gate are electrically connected to the terminal CLK, and the source is electrically connected to the drain of the transistor M2.

  In the transistor M2, the top gate and the bottom gate are electrically connected to the terminal CLKB, and the source is electrically connected to the drain of the transistor M3.

  In the transistor M3, the top gate and the bottom gate are electrically connected to the terminal IN.

  The first terminal of the capacitor C1 is electrically connected to the source of the transistor M1. VSS is input to the second terminal of the capacitive element C1.

  The terminal OUT is electrically connected to the source of the transistor M1, the drain of the transistor M2, and the first terminal of the capacitor C1.

  Note that the capacitance element C1 may be replaced with a parasitic capacitance of a wiring or a gate capacitance of a transistor. In that case, the area occupied by these semiconductor devices can be reduced.

  Next, the operation of the circuit INV will be described.

  FIG. 36B is a timing chart for explaining the operation of the circuit INV. Each represents a change in potential of the terminal IN, the terminal CLK, the terminal CLKB, and the terminal OUT. Further, FIG. 36B is classified into three periods of a period P1, a period P2, and a period P3.

  The terminal IN is given an H level during the periods P1 to P3. That is, the transistor M3 is on in the periods P1 to P3.

  In the period P1, the potential VH is input to the terminal CLK, and the potential VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. At this time, VDD is supplied to the capacitor C1, and the capacitor C1 starts to be charged (precharge).

  Note that VH is preferably equal to or higher than the potential (VDD + Vth) obtained by adding VDD and Vth of the transistor M1. By doing so, VDD can be accurately transmitted to the terminal OUT. VL may be a low power supply potential (or GND). Note that VH is sometimes called a high potential and VL is sometimes called a low potential.

  In the period P2, VL is input to the terminal CLK and VH is input to the terminal CLKB. Transistor M1 is turned off and transistor M2 is turned on. At this time, since the transistor M3 is on, the first terminal of the capacitor C1 and the source of the transistor M3 are brought into conduction, and the capacitor C1 starts discharging. Finally, the terminal OUT outputs the L level. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

  In the period P3, VH is input to the terminal CLK and VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. Similar to the period P1, the capacitive element C1 starts precharging again.

  When the input of the terminal IN in the periods P1 to P3 is set to the L level, the terminal OUT outputs the H level in the period P2. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

  From the above, it can be seen that the circuit INV precharges the capacitor C1 when the terminal CLK is VH and operates as an inverter circuit when the terminal CLK is VL.

  It can also be seen that the circuit INV functions as a dynamic logic circuit that operates by repeatedly charging and discharging the capacitive element C1. The transistor M1 functions as a precharging transistor that charges the capacitor C1, and the transistor M2 functions as a discharging transistor that discharges the charge accumulated in the capacitor C1.

  As the transistors M1 to M3, OS transistors with low off-state current are preferably used. For example, the transistor 200 described in the above embodiment is preferably used.

  By using OS transistors as the transistors M1 to M3, the circuit INV can reduce the through current. As a result, the circuit INV can reduce power consumption.

  In addition, by using OS transistors as the transistors M1 to M3, the charge precharged in the capacitor C1 is not lost due to the leakage current. As a result, the circuit INV can transmit data more accurately.

  In the transistor M1, by electrically connecting the top gate and the bottom gate, a gate potential can be applied to the semiconductor layer from the top gate and the bottom gate at the same time, and an on-current can be increased. The same applies to the transistor M2 and the transistor M3. As a result, the circuit INV can realize an inverter circuit having a high operating frequency.

  In the circuit INV, the terminal IN may be electrically connected to the top gate and the bottom gate of the transistor M2, and the terminal CLKB may be electrically connected to the top gate and the bottom gate of the transistor M3.

  Further, the bottom gates of the transistors M1 to M3 may have different potentials from the top gate. For example, a common fixed potential may be applied to the bottom gates of the transistors M1 to M3. By doing so, the circuit INV can control Vth of the transistors M1 to M3.

  In some cases, the circuit INV may omit all the bottom gates of the transistors M1 to M3. In that case, the circuit INV can simplify the manufacturing process.

  As described above, the circuit INV can provide an inverter circuit including a unipolar transistor with low power consumption. In addition, an inverter circuit including a unipolar transistor with a high operating frequency can be provided.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 6)
In this embodiment, with reference to FIGS. 37 to 39, a transistor in which an oxide is used for a semiconductor (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention is applied. As an example of the apparatus, NOSRAM will be described. NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Hereinafter, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.

  In the NOSRAM, a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied. The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

<< NOSRAM 1600 >>
FIG. 37 shows a configuration example of NOSRAM. A NOSRAM 1600 illustrated in FIG. 37 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.

  The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (eight values) data.

  The controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0]. The controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.

  The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

  The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.

  The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.

  The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL. A function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.

  The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the potential of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The potential of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.

  Note that the structures of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Depending on the configuration or driving method of the memory cell array 1610, the arrangement of these drivers and wirings connected to the drivers may be changed, or the functions of these drivers and wirings connected to the drivers may be changed. Or you may add. For example, the bit line BL may have a part of the function of the source line SL.

  Note that although the amount of information held in each memory cell 1611 is 3 bits in the above, the structure of the memory device described in this embodiment is not limited thereto. The amount of information held in each memory cell 1611 may be 2 bits or less, or 4 bits or more. For example, when the amount of information held in each memory cell 1611 is 1 bit, the DAC 1663 and the ADC 1672 may be omitted.

<Memory cells 1611 to 1614>
FIG. 38A is a circuit diagram illustrating a structural example of the memory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is formed of a p-channel Si transistor, for example. The capacitor C61 is a storage capacitor for holding the potential of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

  Since the write transistor of the memory cell 1611 includes the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

  In the example of FIG. 38A, the bit line is a common bit line for writing and reading, but as shown in FIG. 38B, the bit line WBL functioning as the writing bit line and the reading bit line And a bit line RBL that functions as:

  FIG. 38C to FIG. 38E show other configuration examples of the memory cell. FIGS. 38C to 38E show an example in which a write bit line WBL and a read bit line RBL are provided, but writing and reading are shared as shown in FIG. A bit line may be provided.

  A memory cell 1612 illustrated in FIG. 38C is a modification example of the memory cell 1611 in which the reading transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

  In the memory cell 1611 and the memory cell 1612, the OS transistor MO61 may be an OS transistor without a bottom gate.

  A memory cell 1613 illustrated in FIG. 38D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit line WBL, the bit line RBL, the source line SL, the wiring BGL, and the wiring PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

  A memory cell 1614 shown in FIG. 38E is a modification example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (a transistor MN62 and a transistor MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

  The OS transistors provided in the memory cells 1611 to 1614 may be transistors without a bottom gate or transistors with a bottom gate.

  In the above description, a so-called NOR memory device in which the memory cells 1611 and the like are connected in parallel has been described; however, the memory device described in this embodiment is not limited thereto. For example, a so-called NAND memory device in which memory cells 1615 as described below are connected in series may be used.

  FIG. 39 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. A memory cell array 1610 illustrated in FIG. 39 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitor C63. Here, the transistor MN64 is composed of, for example, an n-channel Si transistor. Without being limited thereto, the transistor MN64 may be a p-channel Si transistor or an OS transistor.

  Hereinafter, the memory cell 1615a and the memory cell 1615b illustrated in FIG. 39 will be described as an example. Here, the reference numerals of the wirings or circuit elements connected to either the memory cell 1615a or the memory cell 1615b are denoted by a or b.

  In the memory cell 1615a, the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitor C63a are electrically connected. The bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. The word line WWLa and the gate of the OS transistor MO63a are electrically connected. In addition, the wiring BGLa and the bottom gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other electrode of the capacitor C63a are electrically connected.

  The memory cell 1615b can be provided symmetrically with the memory cell 1615a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit elements included in the memory cell 1615b are also connected to the wiring in the same manner as the memory cell 1615a.

  Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615. In this manner, in the NAND type memory cell array 1610, the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

  In the memory device having the memory cell array 1610 shown in FIG. 39, a write operation and a read operation are performed for each of a plurality of memory cells (hereinafter referred to as memory cell columns) connected to the same word line WWL (or word line RWL). Do. For example, the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, so that the OS transistor MO63 of the memory cell column to be written is turned on. As a result, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 and the electrode of the capacitor C63 in the designated memory cell column, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 in the memory cell column is turned off, a predetermined charge given to the gate can be held. In this manner, data can be written into the memory cell 1615 in the designated memory cell column.

  For example, the read operation can be performed as follows. First, a potential that turns on the transistor MN64 is applied to the word line RWL that is not connected to the memory cell column to be read regardless of the charge applied to the gate of the transistor MN64, and the memory cell column to be read is read. The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column from which reading is performed, so that the on state or the off state of the transistor MN64 is selected by the charge of the gate of the transistor MN64. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is set in an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are turned on except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is read. It is determined by the state (ON state or OFF state) of the transistor MN64 in the memory cell column. Since the conductance of the transistor varies depending on the charge of the gate of the transistor MN64 of the memory cell column to be read, the potential of the bit line RBL takes a different value accordingly. By reading the potential of the bit line RBL by the reading circuit, information can be read from the memory cell 1615 of the designated memory cell column.

  Since data is rewritten by charging / discharging the capacitive element C61, the capacitive element C62, or the capacitive element C63, the NOSRAM 1600 has no limitation on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.

  In the case where the semiconductor device described in any of the above embodiments is used for the memory cell 1611, the memory cell 1612, the memory cell 1613, the memory cell 1614, and the memory cell 1615, the transistor 200 is used as the OS transistor MO61, the OS transistor MO62, and the OS transistor MO63. The capacitor 100 can be used as the element C61, the capacitor C62, and the capacitor C63, and the transistor 300 can be used as the transistor MP61, the transistor MP62, the transistor MP63, the transistor MN61, the transistor MN62, the transistor MN63, and the transistor MN64. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 7)
In this embodiment, DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. DOSRAM (registered trademark) is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. OS memory is applied to DOSRAM as well as NOSRAM.

<< DOSRAM 1400 >>
FIG. 40 shows a configuration example of the DOSRAM. As shown in FIG. 40, the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).

  The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. The global bit line GBLL and the global bit line GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.

  The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N-1>. FIG. 41A shows a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a plurality of bit lines BLR. In the example of FIG. 41A, the structure of the local memory cell array 1425 is an open bit line type, but it may be a folded bit line type.

  FIG. 41B illustrates a circuit configuration example of a pair of memory cells 1445a and 1445b connected to a common bit line BLL (bit line BLR). The memory cell 1445a includes a transistor MW1a, a capacitor CS1a, a terminal B1a, and a terminal B2a, and is connected to the word line WLa and the bit line BLL (bit line BLR). The memory cell 1445b includes a transistor MW1b, a capacitor CS1b, a terminal B1b, and a terminal B2b, and is connected to the word line WLb and the bit line BLL (bit line BLR). Note that in the following description, when either the memory cell 1445a or the memory cell 1445b is not particularly limited, the symbol a or b may not be attached to the memory cell 1445 and the structure attached thereto.

  The transistor MW1a has a function of controlling charge / discharge of the capacitor CS1a, and the transistor MW1b has a function of controlling charge / discharge of the capacitor CS1b. The gate of the transistor MW1a is electrically connected to the word line WLa, the first terminal is electrically connected to the bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1a. Has been. The gate of the transistor MW1b is electrically connected to the word line WLb, the first terminal is electrically connected to the bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1b. It is connected to the. Thus, the bit line BLL (bit line BLR) is used in common for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.

  The transistor MW1 has a function of controlling charging / discharging of the capacitor CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant potential (for example, a low power supply potential) is input to the terminal B2.

  In the case where the semiconductor device described in any of the above embodiments is used for the memory cell 1445a and the memory cell 1445b, the transistor 200a is used as the transistor MW1a, the transistor 200b is used as the transistor MW1b, the capacitor 100a is used as the capacitor CS1a, and the capacitor is used as 100b can be used. Thus, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.

  The transistor MW1 includes a bottom gate, and the bottom gate is electrically connected to the terminal B1. Therefore, Vth of the transistor MW1 can be changed by the potential of the terminal B1. For example, the potential of the terminal B1 may be a fixed potential (for example, a negative constant potential), or the potential of the terminal B1 may be changed in accordance with the operation of the DOSRAM 1400.

  The bottom gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1. Alternatively, the bottom gate is not necessarily provided in the transistor MW1.

  The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference between the bit line pair, and a function of holding this potential difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.

  Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (BLL, BLR) are also represented.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.

  A column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

  The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.

  An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.

  An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

  Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.

  The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.

  Since the MC-SA array 1420 has a stacked structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 8)
In this embodiment, an FPGA (field programmable gate array) is described as an example of a semiconductor device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. To do. In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.

<< OS-FPGA >>
FIG. 42A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 illustrated in FIG. 42A is capable of context switching by a multi-context structure, fine-grain power gating, and NOFF (normally off) computing. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

  The programmable area 3115 has two input / output blocks (IOB) 3117 and a core 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 includes a plurality of PLE 3121s. FIG. 42B shows an example in which the LAB 3120 is composed of five PLE 3121s. As shown in FIG. 42C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.

  The SB 3131 will be described with reference to FIGS. 43 (A) to 43 (C). Data, dataab, signal context [1: 0], and signal word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.

  The SB 3131 includes a PRS (programmable routing switch) 3133 [0] and a PRS 3133 [1]. The PRS 3133 [0] and the PRS 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.

  FIG. 43B illustrates a circuit configuration example of the PRS 3133 [0]. PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration. PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal. The signal context [0] and the signal word [0] are input to the PRS 3133 [0], and the signal context [1] and the signal word [1] are input to the PRS 3133 [1]. For example, in the SB 3131, when the signal context [0] becomes “H”, the PRS 3133 [0] becomes active.

  The PRS 3133 [0] includes a CM 3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 includes a memory circuit 3137 and a memory circuit 3137B. The memory circuit 3137 and the memory circuit 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.

  When the semiconductor device described in any of the above embodiments is used for the SAB 3130, the transistor 200 can be used as the OS transistor MO31 and the OS transistor MOB31, and the capacitor 100 can be used as the capacitor C31 and the capacitor CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

  The OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 each have a bottom gate, and each bottom gate is electrically connected to a power supply line that supplies a fixed potential.

  The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. The nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.

  Data held in the memory circuit 3137 and the memory circuit 3137B are in a complementary relationship. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.

  With reference to FIG. 43C, an operation example of the PRS 3133 [0] will be described. Configuration data has already been written in the PRS 3133 [0], the node N32 of the PRS 3133 [0] is “H”, and the node NB32 is “L”.

  While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.

  While the signal context [0] is “H”, the PRS 3133 [0] is active. When the signal context [0] changes to “H”, the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.

  When the input terminal changes to “H” during a period in which PRS 3133 [0] is active, the OS transistor MO32 of the memory circuit 3137 is a source follower, and thus the gate potential of the Si transistor M31 is increased by boosting. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.

  In the PRS 3133 having a multi-context function, the CM 3135 also has a function of a multiplexer.

  FIG. 44 shows a configuration example of the PLE 3121. The PLE 3121 includes an LUT (Look Up Table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the inputs inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration stored in the CM 3126.

  The PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.

  In order to realize NOFF computing, the register block 3124 is configured by a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.

  The register block 3124 includes OS-FFs 3140 [1] 3140 [2]. The signal user_res, the signal load, and the signal store are input to the OS-FF 3140 [1] and the OS-FF 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 45A illustrates a configuration example of the OS-FF 3140.

  The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. Nodes Q and QB have a complementary logic relationship.

  The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.

  The shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, an Si transistor M37, an Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B. The memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. The nodes N36 and NB36 are the gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes. The nodes N37 and NB37 are the gates of the Si transistor M37 and the Si transistor MB37.

  When the semiconductor device described in any of the above embodiments is used for the LAB 3120, the transistor 200 can be used as the OS transistor MO35 and the OS transistor MOB35, and the capacitor 100 can be used as the capacitor C36 and the capacitor CB36. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

  The OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 each have a bottom gate, and each bottom gate is electrically connected to a power supply line that supplies a fixed potential.

  An example of an operating method of the OS-FF 3140 will be described with reference to FIG.

(backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. The data of the node Q and the node QB of the FF 3141 is lost, but the shadow register 3142 holds the backed up data even when the power is turned off.

(recovery)
The power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.

  By combining the fine grain power gating and the backup / recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.

  An error that may occur in the memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair. An OS memory using an OS transistor has high soft error resistance. Therefore, by installing the OS memory, a highly reliable OS-FPGA 3110 can be provided.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 9)
In this embodiment, an AI system to which the semiconductor device described in any of the above embodiments is applied will be described with reference to FIGS.

  FIG. 46 is a block diagram illustrating a configuration example of the AI system 4041. The AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

  The arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014. As the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.

  The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, an SRAM (Static Random Access Memory) 4024, Memory ROM 4024 A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

  The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.

  The arithmetic unit 4010 can execute learning or inference using a neural network.

  The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.

  The analog arithmetic circuit 4011 is preferably formed using an OS transistor. An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.

  The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. The DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.

  In the calculation using the neural network, the input data may exceed 1000. When the input data is stored in the SRAM, the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions. The DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can efficiently store the input data.

  A NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data than other nonvolatile memories such as a flash memory, a ReRAM (Resistive Random Access Memory), and an MRAM (Magnetic Responsive Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.

  The NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.

  The NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit. Note that in this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. The multi-value data described above may be included in the analog data.

  Data and parameters used for calculation of the neural network can be temporarily stored in the NOSRAM 4013. The data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021. However, the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.

  The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM). A neural network connection, such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.

  The FPGA 4014 is an FPGA having an OS transistor. The OS-FPGA can reduce the area of the memory compared to the FPGA configured with SRAM. Therefore, even if a context switching function is added, the area increase is small. The OS-FPGA can transmit data and parameters at high speed by boosting.

  In the AI system 4041, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption. In addition, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

  Note that the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.

  The AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). Operations such as DBN). The PROM 4025 can store a program for executing these calculations. Further, a part or all of these programs may be stored in the NOSRAM 4013.

  Many existing programs that exist as libraries are premised on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. The AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.

  The power supply circuit 4027 not only generates a low voltage potential for a logic circuit but also generates a potential for analog calculation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.

  The PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.

  The CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.

  The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.

  The AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM. The memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.

  Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.

  Data used for neural network calculation is often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.

  Since learning and inference using a neural network often handle audio and video, the AI system 4041 includes an audio codec 4032 and a video codec 4033. The audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data, and the video codec 4033 encodes and decodes video data.

  The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus), I2C (Inter-Integrated Circuit), and the like.

  The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.

  The analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. In addition, it is very difficult to form a multilevel flash memory in an embedded manner (an arithmetic circuit and a memory are formed on the same die).

  The analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy. Furthermore, since the device has two terminals, circuit design for separating data writing and reading becomes complicated.

  The analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has a problem in terms of storage accuracy.

  In view of the above, the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 10)
<Application example of AI system>
In this embodiment, application examples of the AI system described in the above embodiment are described with reference to FIGS.

  FIG. 47A shows an AI system 4041A in which the AI systems 4041 described in FIG. 46 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.

  An AI system 4041A illustrated in FIG. 47A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.

  FIG. 47B shows an AI system 4041B in which the AI system 4041 described in FIG. 46 is arranged in parallel as in FIG. 47A and signals can be transmitted and received between systems via a network. is there.

  An AI system 4041B illustrated in FIG. 47B includes a plurality of AI systems 4041_1 to 4041_n. The AI systems 4041_1 to 4041_n are connected to each other via a network 4099.

  The network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication. The communication module can communicate via an antenna. For example, the Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (MetropoliAW, MAN) Each electronic device can be connected to a computer network such as a network (network) or GAN (global area network) to perform communication. When performing wireless communication, as communication protocols or communication technologies, LTE (Long Term Evolution), GSM (Global System for Mobile Communications: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (CDMA 2000), CDMA2000 (CD2000). , Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.

  With the configurations shown in FIGS. 47A and 47B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information, can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and analog signals can be processed by separate AI systems it can. By performing signal processing or learning in each separate AI system, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 11)
In this embodiment, an example of an IC in which the AI system described in the above embodiment is incorporated is described.

  The AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.

  FIG. 48 shows an example of an IC incorporating an AI system. An AI system IC 7000 shown in FIG. 48 has a lead 7001 and a circuit portion 7003. The AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004). The circuit portion 7003 is provided with the various circuits described in the above embodiment in one die. As described in the above embodiment, the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.

  In FIG. 48, QFP (Quad Flat Package) is applied to the package of the AI system IC 7000, but the package mode is not limited to this.

  A digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and OS memories such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 12)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 49 and 50 illustrate specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

  A robot 5000 illustrated in FIG. 49A includes an arithmetic device 5001, a sensor 5002, a light 5003, a lift 5004, a driver 5005, and a moving mechanism 5011, and can capture a still image or a moving image while moving. Such a robot can be used as a security system or a monitoring system.

  The robot 5000 may further include a communication unit 5006, a speaker 5007, a microphone 5008, a display unit 5009, a light emitting unit 5010, and the like.

  The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 5001. For the arithmetic device 5001, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used. The sensor 5002 has a function as a camera that captures an image around the robot 5000. The light 5003 can be used as a light when the sensor 5002 captures the surroundings of the robot 5000. Note that when the sensor 5002 captures a still image, the light 5003 preferably functions as a flashlight. The sensor 5002 is connected to the robot body via a lift 5004. The height of the sensor 5002 can be adjusted by a lift 5004. The lift 5004 is preferably a telescopic type. The lift 5004 may be a foldable type constituted by a plurality of booms. In addition, since the robot 5000 is provided with a driving unit 5005 and a moving mechanism 5011 connected to the driving unit 5005, an imaging range by the sensor 5002, that is, a monitoring range is widened, which is preferable.

  The communication unit 5006 can transmit information captured by the sensor 5002 to an administrator or a server owned by the administrator. In addition, when the information captured by the sensor 5002 is analyzed by the arithmetic device 5001, and it is determined that an emergency such as a crime, an accident, or a fire, the security company, the police, the fire department, the medical institution, the owner of the land or building You can contact me. The speaker 5007 can transmit information to the surroundings of the robot, such as warning a criminal, asking an injured person or a suddenly ill person, and guiding evacuation. The microphone 5008 can be used for acquiring sound around the robot 5000. Further, the robot 5000 can function as a telephone by being used in combination with the communication unit 5006 and the speaker 5007. A person around the robot 5000 can talk with an administrator or any person. The display unit 5009 can display arbitrary information. In case of an emergency, disaster information and evacuation routes can be displayed. Further, the robot 5000 can function as a videophone by being used in combination with the communication unit 5006, the speaker 5007, and the microphone 5008. A person around the robot 5000 can talk with an administrator or an arbitrary person while watching the display unit 5009.

  The light emitting unit 5010 can indicate the traveling direction and stop state of the robot 5000 with characters and light. It may also indicate an emergency situation.

  FIG. 49B is a block diagram illustrating a configuration of the robot 5000. The arithmetic device 5001 turns on and off the light 5003 and adjusts brightness based on information such as an image obtained by the sensor 5002. In addition, the height of the lift 5004 is adjusted or the drive unit 5005 is controlled to align the robot 5000 and the sensor 5002. In addition, an operation state of the driving unit 5005 can be indicated using the light emitting unit 5010. In addition, information around the robot 5000 obtained from the sensor 5002 and the microphone 5008 can be transmitted to the manager or a server owned by the manager using the communication unit 5006. In addition, information can be transmitted to the surroundings of the robot 5000 using the speaker 5007 or the display unit 5009 based on the judgment of the arithmetic device 5001 or the administrator.

  When a sensor that can capture an image even when the surrounding is dark is used as the sensor 5002, the light 5003 is not necessarily provided. As such a sensor, an image sensor using selenium (Se) as a light receiving portion can be used.

  Such a robot 5000 can be used for security in commercial facilities and offices. Information obtained from the sensor 5002 or the microphone 5008 is stored in the arithmetic device 5001 or a server. The stored information is analyzed by the AI system to determine whether there is an abnormality such as a lost or damaged article, a suspicious person invading, or a disaster such as a fire. Deep learning may be used for information analysis. If it is determined that an abnormality has occurred, the robot 5000 contacts the administrator and transmits information to the surroundings and records the surrounding situation.

  Further, the robot 5000 may be used for monitoring the growth state of agricultural products. A robot 5000 installed in a rice field or a field monitors the shape, size, and color of crop leaves or fruits using a sensor 5002 to determine whether the patient is ill or has no pests attached. Since the robot 5000 is provided with the moving mechanism 5011, it is possible to monitor the growth status of a wide range of agricultural products. In addition, since the robot 5000 is provided with a lift 5004, it is possible to monitor leaves and fruits of any height regardless of the type of crop and the growth situation. The monitoring result is sent to the producer using the communication means 5006, and the producer can determine the type and amount of fertilizer and pesticide necessary for the agricultural crop, and the spraying time. Further, the monitoring result may be analyzed by the AI system using the arithmetic device 5001, and the type, amount, and spraying time of fertilizer and pesticide necessary for the crop may be determined and notified to the producer. Deep learning may be used for analyzing the monitoring result.

  FIG. 50A shows a sorting system 6000 using a robot 6001. The robot 6001 includes an arithmetic device 6002, a boom 6003, and an arm 6004. The robot 6001 may include a wired or wireless communication unit 6011. In addition, the sorting system 6000 includes a housing 6008 having a sensor 6009. The housing 6008 has communication means 6010. The housing 6008 is provided on the sorting system 6000 or the ceiling, wall, and beam (all not shown) of the sorting work area. The housing 6008 may be provided in the robot 6001. For example, the boom 6003 or the arm 6004 may be provided. When the housing 6008 is provided in the robot 6001, information obtained by the sensor 6009 may be sent to the arithmetic device 6002 for processing without passing through the communication unit 6010 and the communication unit 6011.

  The boom 6003 is movable, and the arm 6004 can be disposed at a desired position. Further, the arm 6004 may be telescopic. The arm 6004 may be moved by the boom 6003 after the arm placed on the desired article 6007 is extended, the desired article 6007 is gripped, and the arm 6004 is contracted.

  The sorting system 6000 can move the article 6007 in the container 6005 to the container 6006. The container 6005 and the container 6006 may have the same shape or different shapes. In addition, a plurality of articles 6007 placed in one container 6005 may be distributed and moved to a plurality of containers 6006.

  As the container 6005 and the container 6006, a container, a cardboard box, a box for packing products, a case, a film, or a bag, a food storage bat, a lunch box, or the like is used. Further, at least one of the container 6005 and the container 6006 may be a cooking utensil such as a pan or a frying pan.

  The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 6002. For the arithmetic device 6002, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used.

  The sensor 6009 reads the position of the container 6005, the position of the container 6006, the state of the container 6005, and the state of the article 6007 in the container 6005, and transmits information to the arithmetic device 6002 using the communication unit 6010. Information is transmitted wirelessly or by wire. Further, information may be transmitted by wire without using the communication unit 6010. The arithmetic device 6002 analyzes the transmitted information. Here, the state of the article 6007 indicates the shape, number, overlap of the articles 6007, and the like. The arithmetic device 6002 performs analysis based on information from the sensor 6009 and derives detailed information on the article 6007. Compared with data stored in the arithmetic device 6002 or a server capable of communicating with the robot 6001, the three-dimensional shape and hardness (softness) of the article 6007 are derived. Further, the shape of the arm 6004 can be changed based on the three-dimensional shape and hardness (softness) of the article 6007.

  In order to derive the detailed information of the article 6007, analysis using an AI system can be used. Deep learning may be used for information analysis.

  FIG. 50B illustrates an arm in which a pair of plates 6021 can move in the horizontal direction and can sandwich an article 6007. By moving the pair of plates 6021 in the horizontal direction toward the center, the article 6007 can be sandwiched. Such an arm can grasp the article 6007 by a surface and is suitable for grasping the article 6007 having a columnar shape such as a cube or a rectangular parallelepiped. FIG. 50C illustrates an arm in which a plurality of bars 6022 can move in the horizontal direction and sandwich an article 6007. The articles 6007 can be sandwiched by the plurality of bars 6022 moving in the horizontal direction toward the center. Such an arm can grasp the article 6007 with a point, and is suitable for grasping an article 6007 having a spherical shape, or when the shape of the article 6007 is not constant, that is, an irregular article 6007. In FIG. 50C, the number of bars 6022 is four, but this embodiment is not limited to this. There may be three bars 6022, or five or more bars. FIG. 50D illustrates an arm that can sandwich the article 6007 when the pair of plates 6023 rotate around a common axis so as to approach each other. Such an arm can grasp the article 6007 by a surface and is suitable for grasping the article 6007 having a thin film shape such as paper or film. FIG. 50E illustrates an arm that can sandwich the article 6007 by rotating a pair of hook-shaped plates 6024 around a common axis so that the tips of each other approach each other. Such an arm can capture the article 6007 with dots or lines, and is suitable for grasping an article 6007 having a thin-film shape, such as paper or film, or an article 6007 having a smaller granular shape. . In addition, as shown in FIG. 50F, a spatula 6025 may be attached to the tip of the arm, and an article 6007 having a smaller granular shape may be scooped.

  The arms illustrated in FIGS. 50A to 50F are examples, and one embodiment of the present invention is not limited to these shapes. The description of the use of each arm is also an example, and one embodiment of the present invention is not limited to these descriptions.

  The robot 6001 moves the boom 6003 based on a signal from the arithmetic device 6002 and moves the arm 6004 onto a desired article 6007 in the container 6005. In the case of the extendable arm 6004, the arm 6004 is extended and the tip of the arm 6004 is lowered to the height of the article 6007. The tip of the arm is moved and the desired article 6007 is gripped. While holding the object 6007, the arm is contracted. The boom 6003 is moved again, and the arm 6004 is moved to a desired position of the container 6006. At this time, the arm 6004 may be rotated in order to adjust the angle of the article 6007 with respect to the container 6006. The arm 6004 is extended, the article 6007 is placed in the container 6006, and the arm 6004 releases the article 6007. By repeating the above operation, the robot 6001 can move the article 6007 from the container 6005 to the container 6006.

  Since the position information of the container 6005 and the container 6006 and the state of the article 6007 are analyzed using the AI system, the article 6007 can be reliably moved regardless of the shape and rigidity of the article 6007. Examples of the article 6007 include not only an article packed in a cube or rectangular parallelepiped box, or a box or case of any shape, but also a molded processed food such as an egg, a hamburger, a croquette, a potato or a tomato. Examples include regular foods such as vegetables, machine parts such as screws and nuts, and thin films such as paper and film. Since the sorting system 6000 shown in this embodiment can change the shape of the arm in consideration of the shape and rigidity of the article 6007, the article 6007 exemplified above can be used as a container regardless of the shape and rigidity. The container 6006 can be moved from 6005.

  For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  In addition, for example, an IC in which the AI system is incorporated can be used in the arithmetic device of the electronic device described above. Accordingly, the electronic device described in this embodiment can perform an accurate operation according to the situation with low power consumption by using the AI system.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

In this example, the transition of the sheet resistance of the oxide when a metal compound was formed on the oxide was measured. The sheet resistance measuring instrument has a measurement upper limit of 6.0 × 10 ⁶ Ω / sq. The thing which is is used. The transition of the sheet resistance of the oxide is shown in FIG. The sample used for evaluation of transition of sheet resistance will be described below.

A method for manufacturing Sample 1 will be described. The surface of the substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a 100 nm silicon oxide film on the substrate. Next, an oxide with a thickness of 5 nm is formed over the silicon oxide film by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. An oxide with a thickness of 15 nm was formed using a target of Zn: 4: 2: 4.1 [atomic ratio]. Next, the formed oxide was subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and continuously subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere. When the sheet resistance of the oxide of Sample 1 was measured, it was overranged, and the oxide sheet resistance was 6.0 × 10 ⁶ Ω / sq. It turns out that it is above.

Next, a manufacturing method of Sample 2 will be described. Similar to Sample 1, a silicon oxide film and an oxide were formed over the substrate, and heat treatment was performed. After the heat treatment, a metal compound having a thickness of 2 nm was formed over the oxide by a sputtering method using a target of Ti: Al = 1: 1 [atomic ratio] in an atmosphere containing nitrogen. The obtained metal compound contains titanium, aluminum, and nitrogen, and can be expressed as TiAlNx. When the sheet resistance of the oxide of Sample 2 was measured, it was 3.8 × 10 ³ Ω / sq. Met. By forming a metal compound on the oxide, the sheet resistance value of the oxide was reduced.

Next, a method for manufacturing Sample 3 will be described. Similar to Sample 2, a silicon oxide film and an oxide were formed over the substrate, and heat treatment was performed. After the heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere. When the sheet resistance of the oxide of Sample 3 was measured, it was 2.9 × 10 ³ Ω / sq. Met. Although there was almost no change in the sheet resistance value of the oxide reduced by the formation of the metal compound, the sheet resistance value of the oxide of Sample 3 was reduced as compared with Sample 2.

Next, a method for manufacturing Sample 4 will be described. Similarly to Sample 3, a silicon oxide film and an oxide were formed over the substrate, and heat treatment was performed. After the heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, heat treatment was performed. After the heat treatment, a 20-nm-thick aluminum oxide film was formed by sputtering using a target containing aluminum oxide (Al ₂ O ₃ ) in an atmosphere containing argon and oxygen. It is considered that oxygen (excess oxygen) is supplied to the oxide by the formation of aluminum oxide. Here, when oxygen is supplied to the oxide, the resistance value of the oxide increases and may approach the I-type semiconductor. When the sheet resistance of the oxide of Sample 4 was measured, it was 1.9 × 10 ³ Ω / sq. Met. In Sample 4, the oxide sheet resistance was measured after removing the aluminum oxide. In the oxide having a reduced sheet resistance value due to the formation of the metal compound, the increase in the sheet resistance value due to the formation of aluminum oxide was not observed, and the sheet resistance value of the oxide of the sample 4 was reduced compared to the sample 3. .

Next, a method for manufacturing Sample 5 will be described. Similar to Sample 4, a silicon oxide film and an oxide were formed over the substrate, and heat treatment was performed. After the heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, heat treatment was performed. After the heat treatment, aluminum oxide was formed. After the formation of aluminum oxide, heat treatment was performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere, and then heat treatment was performed for 1 hour at a temperature of 400 ° C. in an oxygen atmosphere. It is conceivable that oxygen contained in aluminum oxide diffuses into the oxide by the heat treatment. When the sheet resistance of the oxide of Sample 5 was measured, it was 1.5 × 10 ³ Ω / sq. Met. In Sample 5, the oxide sheet resistance was measured after removing the aluminum oxide. In the oxide whose sheet resistance value was reduced by the formation of the metal compound, formation of aluminum oxide and increase in sheet resistance value due to heat treatment were not observed. In addition, the sheet resistance value of the oxide of Sample 5 was reduced as compared with Sample 3 and Sample 4.

  This example can be implemented in combination with any of the structures described in the other embodiments and examples as appropriate.

  In this example, a result of evaluating the hydrogen concentration in an oxide of a sample in which a metal compound is provided over an oxide and the metal oxide is provided over the metal compound will be described. For the evaluation of the hydrogen concentration, SSDP (Substrate Side Depth Profile) -SIMS analysis was used.

  Hereinafter, a method for manufacturing Sample 6 and Sample 7 used in SSDP-SIMS analysis will be described.

A method for manufacturing Sample 6 will be described. The surface of the substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a 100 nm silicon oxide film on the substrate. Next, an oxide with a thickness of 50 nm was formed over the silicon oxide film by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, the formed oxide is subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and then continuously subjected to a first heat treatment at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere. It was. After the first heat treatment, a metal compound having a thickness of 2 nm was formed over the oxide by a sputtering method using a target of Ti: Al = 1: 1 [atomic ratio] in an atmosphere containing nitrogen. Next, after the formation of the metal compound, a second heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere. After the second heat treatment, Sample 6 was obtained by forming a 20 nm-thick aluminum oxide film in an atmosphere containing argon and oxygen using a target containing aluminum oxide (Al ₂ O ₃ ) by a sputtering method.

  Next, a method for manufacturing Sample 7 will be described. Similarly to Sample 6, a silicon oxide film and an oxide were formed over the substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After the formation of the metal compound, a second heat treatment was performed. Aluminum oxide was formed after the second heat treatment. After the formation of aluminum oxide, a heat treatment was performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and a third heat treatment was continuously performed at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere.

FIG. 52 shows the result of detecting hydrogen by performing SSDP-SIMS analysis on Sample 6 and Sample 7 produced as described above. In FIG. 52, the horizontal axis represents the depth [nm], and the vertical axis represents the hydrogen concentration [atoms / cm ³ ]. The hydrogen concentration of sample 6 is indicated by a broken line, and the hydrogen concentration of sample 7 is indicated by practice. In addition, the background level of the hydrogen concentration in the SSDP-SIMS analysis is 3.8 × 10 ¹⁸ atoms / cm ³ , and is indicated by a long broken line in the graph. The SSDP-SIMS analysis of Sample 6 and Sample 7 was performed by digging a sample from the silicon wafer side. In the SSDP-SIMS analysis of Sample 6 and Sample 7, the oxide (IGZO) hydrogen concentration was converted by quantifying the oxide (denoted as IGZO in the figure). The SIMS analysis was performed using a quadrupole mass spectrometer (ADEPT 1010) manufactured by ULVAC-PHI. The detection area of sample 6 and sample 7 was 60 μm × 60 μm.

  As shown in FIG. 52, in sample 6, hydrogen is detected in the oxide (IGZO). On the other hand, in the sample 7 subjected to the heat treatment, the hydrogen concentration in the oxide (IGZO) is reduced, and in particular, the hydrogen concentration on the metal compound side is reduced to the background level.

  As described above, the hydrogen concentration in the oxide was reduced by performing heat treatment on the sample in which the metal compound was provided over the oxide and the metal oxide was provided over the metal compound. This evaluation suggests that hydrogen in the oxide is extracted by the metal oxide through the metal compound. That is, it was suggested that by providing a metal oxide in the vicinity of the oxide, hydrogen in the oxide is extracted to the metal oxide. Thus, the phenomenon in which the metal oxide abstracts hydrogen from the oxide can be referred to as gettering.

  This example can be implemented in combination with any of the structures described in the other embodiments and examples as appropriate.

100 Capacitor 100a Capacitor 100b Capacitor 110 Conductor 112 Conductor 120 Conductor 130 Insulator 150 Insulator 200 Transistor 200a Transistor 200b Transistor 203 Conductor 203a Conductor 203b Conductor 205 Conductor 205a Conductor 205b Conductor 207 Conductor Body 210 insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230A oxide film 230b oxide 230B oxide film 230c oxide 230C oxide film 231 region 231a region 231b region 234 region 239 region 240 conductor 240a conductor 240b conductor 240c conductor 242 layer 242A film 243 region 245 opening 246 conductor 248 conductor 250 insulator 25 0A insulating film 251a conductor 251b conductor 260 conductor 260A conductive film 274 insulator 280 insulator 281 insulator 282 insulator 286 insulator 291 insulator 292 insulator 293 insulator 300 transistor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 insulator 350 insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 Conductor 370 insulator 372 insulator 374 insulator 376 conductor 380 insulator 382 insulator 384 insulator 386 conductor 400 transistor 403 conductor 405 conductor 430c oxide 431a oxide 431b oxide 432a oxide 432b Oxide 450 Insulator 460 Conductor 500 Opening 600 Cell 600a Cell 600b Cell 610 Circuit 620 Circuit 650a Memory cell 650b Memory cell 1001 Wiring 1002 Wiring 1003 Wiring 1004 Wiring 1005 Wiring 1006 Wiring 1007 Wiring 1008 Wiring 1009 Wiring 1010 Wiring 1400 DOSRAM
1405 Controller 1410 Row circuit 1411 Decoder 1412 Word line driver circuit 1413 Column selector 1414 Sense amplifier driver circuit 1415 Column circuit 1416 Global sense amplifier array 1417 Input / output circuit 1420 MC-SA array 1422 Memory cell array 1423 Sense amplifier array 1425 Local memory cell array 1426 Local Sense amplifier array 1444 Switch array 1445 Memory cell 1445a Memory cell 1445b Memory cell 1446 Sense amplifier 1447 Global sense amplifier 1600 NOSRAM
1610 memory cell array 1611 memory cell 1612 memory cell 1613 memory cell 1614 memory cell 1615 memory cell 1615a memory cell 1615b memory cell 1640 controller 1650 row driver 1651 row decoder 1652 word line driver 1660 column driver 1661 column decoder 1662 driver 1663 DAC
1670 output driver 1671 selector 1672 ADC
1673 Output buffer 3110 OS-FPGA
3111 Controller 3112 Word driver 3113 Data driver 3115 Programmable area 3117 IOB
3119 Core 3120 LAB
3121 PLE
3123 LUT block 3124 register block 3125 selector 3126 CM
3127 Power Switch 3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 Memory circuit 3137B Memory circuit 3140 OS-FF
3141 FF
3142 Shadow register 3143 Memory circuit 3143B Memory circuit 3188 Inverter circuit 3189 Inverter circuit 4010 Operation unit 4011 Analog operation circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 control unit 4021 CPU
4022 GPU
4023 PLL
4024 SRAM
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 Input / output unit 4031 External storage control circuit 4032 Audio codec 4033 Video codec 4034 General-purpose input / output module 4035 Communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 Bus line 4099 Network 5000 Robot 5001 Arithmetic unit 5002 Sensor 5003 Light 5004 Lift 5005 Driving unit 5006 Communication unit 5007 Speaker 5008 Microphone 5009 Display unit 5010 Light emitting unit 5011 Moving mechanism 6000 Sorting system 6001 Robot 6002 Computing device 6003 Boom 6004 Arm 6005 Container 6006 Container 6007 Article 6008 Housing 6009 Sensor 6010 Communication unit 6011 Communication means 6021 plate 6022 bar 6023 plate 6024 plate 6025 spatula 7000 AI system IC
7001 Lead 7002 Printed circuit board 7003 Circuit part 7004 Mounting substrate 7031 Si transistor layer 7032 Wiring layer 7033 OS transistor layer

Claims (16)

A semiconductor device having a transistor,
The transistor is
Oxides,
A first insulator and a second insulator on the oxide;
A conductor on the first insulator;
The oxide has a first region and a second region,
The first region has a region in contact with the first insulator;
The second region has a lower oxygen concentration than the first region,
The first insulator is disposed so as to have a region along an inner wall of an opening provided in the second insulator;
The conductor is disposed to embed the opening;
A semiconductor device. A semiconductor device having a transistor,
The transistor is
Oxides,
A film on the oxide and a first insulator;
A second insulator on the film;
A conductor on the first insulator;
The oxide has a first region and a second region,
The first region has a region in contact with the first insulator;
The second region has a lower oxygen concentration than the first region,
The film is provided in contact with the second region;
The first insulator is disposed so as to have a region along an inner wall of an opening provided in the second insulator;
The conductor is disposed to embed the opening;
A semiconductor device. In claim 1 or claim 2,
The oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
A semiconductor device. In claim 3,
The oxide has more In than the element M in the atomic ratio.
A semiconductor device. In any one of Claims 1 thru | or 4,
The second region comprises at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten;
A semiconductor device. In any one of Claims 1 thru | or 5,
The second region further comprises nitrogen;
A semiconductor device. In any one of Claims 1 thru | or 6,
The first region has a lower hydrogen concentration than the second region;
A semiconductor device. In any one of Claims 1 thru | or 7,
The transistor is a normally-off type.
A semiconductor device. In claim 2,
The membrane has a portion that mixes with the second region;
A semiconductor device. In claim 2 or claim 9,
The film comprises at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten;
A semiconductor device. In claim 2 or claim 10,
The film comprises aluminum and titanium;
A semiconductor device. In any one of Claim 2, Claim 10, or Claim 11,
The film further includes one or both of nitrogen and oxygen,
A semiconductor device. In claim 2, or any one of claims 9 to 12,
The thickness of the film is 0.5 nm or more and 5 nm or less.
A semiconductor device. A method for manufacturing a semiconductor device having a transistor,
The transistor is
An oxide comprising a first region and a second region;
A film on the oxide and a first insulator;
A second insulator on the film;
A conductor on the first insulator;
Forming a film containing a metal so as to cover the oxide and to be in contact with the second region;
At least the oxide and the film are subjected to a first heat treatment in an atmosphere containing nitrogen, whereby oxygen contained in the second region is extracted to the film.
A method for manufacturing a semiconductor device. In claim 14,
The film is formed by sputtering using one or more gases selected from argon, nitrogen, and nitrogen.
A method for manufacturing a semiconductor device. In claim 14 or claim 15,
A method for manufacturing a semiconductor device, wherein a second heat treatment is further performed after the first heat treatment.