JP2018164139A - Imaging device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device capable of shortening a time for correcting a long-time noise.SOLUTION: An imaging device comprises: an imaging unit that has a function of acquiring first image data; a controller that has a function of controlling a light exposure time; a temperature sensor that has a function of acquiring a temperature of the imaging unit; and an image processing unit that has a neural network for generating second image data by using the light exposure time at the time when the first image data is acquired and the temperature of the imaging unit as input data. Second image data is subtracted from the first image data to generate third image data.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to an imaging device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

The performance of an image pickup apparatus using a solid-state image pickup device has been improved, and sufficient image quality can be obtained even in a low illumination environment as in the case of using a high-sensitivity silver salt film. In addition, a technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a structure in which a transistor including an oxide semiconductor and having extremely low off-state current is used for a pixel circuit.

JP 2011-119711 A

However, the imaging device also has unique problems. Transistors several times as many as the number of pixels are provided in the pixel region of the solid-state imaging device, but it is extremely difficult to manufacture all of them having the same electrical characteristics.

For example, transistors with slightly higher leakage current than the reference value may be scattered due to incomplete structure or non-uniform material. The presence of such a transistor does not affect imaging with a relatively short exposure time in a bright environment. However, when imaging a night view or a starry sky, exposure may be performed for several seconds to several tens of minutes. Under such an imaging condition, due to the above-described leakage current, a bright spot is generated in a region that is originally a black level image.

The bright spot is known as long-time noise, and if the imaging conditions are the same, the same level of noise occurs in the same region. Therefore, as a long-time noise correction method, a method of subtracting dark image data captured under the same conditions from original image data is used. However, since acquisition of dark data is performed continuously after the original image has been captured, the imaging time is doubled, which hinders imaging throughput.

Therefore, an object of one embodiment of the present invention is to provide an imaging device that can reduce the correction time of long-time noise. Another object is to provide an imaging device with high throughput. Another object is to provide an imaging device that can easily perform imaging under low illuminance. Another object is to provide an imaging device with low power consumption. Another object is to provide a highly reliable imaging device. Another object is to provide a novel imaging device or the like. Another object is to provide a novel semiconductor device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention relates to an imaging device that obtains an image with reduced noise for a long time using a neural network.

One embodiment of the present invention is an imaging device including an imaging unit, a control unit, a temperature sensor, and an image processing unit, and the imaging unit has a function of acquiring first image data and performs control. The unit has a function of controlling the exposure time in the imaging unit, the temperature sensor has a function of acquiring the temperature of the imaging unit, the image processing unit has a neural network, and the neural network has a second The image processing unit is an imaging device having a function of generating image data, and the image processing unit has a function of generating third image data by subtracting the second image data from the first image data.

The neural network has a function of generating second image data using the exposure time and temperature when the first image data is acquired as input data.

The imaging apparatus has an interface connected to an external device, and a value input from the external device can be used as the weighting coefficient of the neural network.

The imaging unit has a function of acquiring the fourth image data, and the image processing unit uses the exposure time and the temperature of the imaging unit when the fourth image data is acquired as input data, and uses the fourth image data as a teacher. It has a function of correcting the weighting coefficient of the neural network as data.

The neural network includes a product-sum operation element, and the product-sum operation element includes a memory circuit including a first transistor, a second transistor, and a capacitor, and the source or drain of the first transistor Is electrically connected to the gate of the second transistor, one of the source and drain of the first transistor is electrically connected to the capacitor, and the first transistor is metal-oxidized in the channel formation region. Can have things.

A pixel in the imaging portion can include a third transistor including a metal oxide in a channel formation region and a photoelectric conversion element including selenium or a selenium compound.

By using one embodiment of the present invention, an imaging device capable of reducing noise correction time for a long time can be provided. Alternatively, an imaging device with high throughput can be provided. Alternatively, an imaging device that can easily perform imaging under low illuminance can be provided. Alternatively, an imaging device with low power consumption can be provided. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a novel semiconductor device or the like can be provided.

FIG. 10 is a block diagram illustrating an imaging device and an external device. The figure explaining long-time noise and its removal. The figure which divided the image of noise for a long time. The figure explaining the production | generation of the image by a neural network. 6A and 6B illustrate an operation for removing noise for a long time by an imaging device. The figure which shows the structural example of a neural network. FIG. 9 illustrates a configuration example of a semiconductor device. FIG. 6 illustrates a configuration example of a memory circuit. The figure which shows the structural example of a memory cell. The figure which shows the structural example of a circuit. 6 is a timing chart illustrating operation of a semiconductor device. The figure explaining a pixel circuit and the timing chart explaining the operation | movement of imaging. The figure which shows the structure of the pixel of an imaging device, and the block diagram of an imaging device. Sectional drawing which shows the structure of an imaging device. Sectional drawing which shows the structure of an imaging device. Sectional drawing which shows the structure of an imaging device. The perspective view of the package which accommodated the imaging device. FIG. 9 illustrates a configuration example of an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

(Embodiment 1)
In this embodiment, an imaging device that is one embodiment of the present invention will be described with reference to drawings. One embodiment of the present invention is an imaging device having an image generation function using a neural network.

In an imaging device, bright spots called long-term noise or fixed pattern noise may occur. The bright spot is generated when the potential of the charge holding portion of the pixel is changed due to the leakage current of the transistor.

Up to now, long-time noise correction has been performed by acquiring second image data in a dark state captured under the same conditions after acquiring the first image data as the original image, and then acquiring the second image data from the first image data. Was done by subtracting. Therefore, it has been a problem that the imaging time is doubled.

In one embodiment of the present invention, the second image data is generated using a neural network weighted by prior machine learning. Therefore, the imaging operation of the second image data can be omitted. As an effect, even when the first image data is acquired by long exposure, the second image data can be generated in a short time, and the imaging throughput can be improved.

FIG. 1 is an example of a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device 10 includes an imaging unit 11, a control unit 12, a calculation unit 13, an image processing unit 14, a temperature sensor 15, a storage unit 16, a storage unit 17, and an interface 18. These elements are electrically connected to each other, and can exchange signals and data as necessary. Note that any element may not be electrically connected to any other element. In addition, other elements may have the function of any element. In some cases, the function of one element is distributed to a plurality of elements.

The imaging unit 11 has a function of imaging image data, and specifically, a CMOS image sensor or the like can be used. The control unit 12 has a function of controlling operations related to imaging. The calculation unit 13 has a function of performing calculations related to the operation of the entire imaging apparatus, and for example, a central processing unit (CPU) can be used. The image processing unit 14 has a function of performing data processing relating to an image, and for example, an image processing apparatus (GPU: Graphics Processing Unit) can be used. The image processing unit 14 has a neural network 19 for generating image data. The temperature sensor 15 has a function of acquiring the temperature of the imaging unit.

The storage unit 16 preferably has a function of storing programs and setting items related to operations in the imaging apparatus 10 and is preferably a rewritable memory. The storage unit 17 is a memory for storing data such as captured images, and may be a removable storage medium. The interface 18 has a function of connecting the external device 20.

The external device 20 includes a control unit 21, an image processing unit 22, a storage unit 23, and the like. The image processing unit 22 includes a neural network 24 having a configuration equivalent to that of the neural network 19. The neural networks 19 and 24 may be configured by software.

Here, the above-described long-time noise correction will be described. FIG. 2A is an example of an image 30 of a night view including a building and the sky taken with a long exposure. For example, when the exposure time is set to a long time such as several seconds or more, unnatural luminescent spots 31 and 32 may occur in an empty area that should normally be a black level. The bright spots 31 and 32 are called long-time noises, and are often recognized when a plurality of adjacent pixels output abnormal values. In addition, the position where the noise appears for a long time and the conditions for the appearance vary depending on the product.

In images taken with the same product, noise for a long time basically occurs in the same region, but because the cause is the leakage current of a specific transistor, the noise state (brightness and darkness) that appears in the image depends on the exposure time and temperature. Dependent. In particular, when the temperature is high, the leakage current increases, and a vicious cycle occurs such that heat is generated by the leakage current. Therefore, conventionally, a dark image 35 (see FIG. 2B) captured under the same conditions as the image 30 using a mechanical shutter or the like is acquired, and the data of the image 35 is subtracted from the data of the image 30. Thus, a method of acquiring an image 37 with reduced noise for a long time has been used (see FIG. 2C).

However, in this method, since the image 35 is captured with the same exposure time as that of the image 30 after the image 30 is captured, the exposure time is doubled. In addition, the exposure time can be the same under the image capturing conditions of the image 30 and the image 35, but the temperature varies depending on the environment. Therefore, in one aspect of the present invention, means for generating the image 35 using a neural network is used instead of acquiring the image 35 by an imaging operation.

Next, machine learning of the neural network will be described. The machine learning can be performed using the imaging device 10 and the external device 20 illustrated in FIG. The imaging device 10 and the external device 20 are connected via the interface 18. At this time, the imaging apparatus 10 can perform an imaging operation with the external device 20.

First, the imaging device 10 is controlled by the control unit 21 of the external device 20 to obtain a plurality of dark state image data using the exposure time and temperature as parameters. The acquired image data is stored in the storage unit 23 of the external device 20 as teacher data. Then, the teacher data stored in the storage unit 23 is read, and learning is performed by the neural network 24 in the image processing unit 22 using the corresponding exposure time and temperature as input data.

An area where noise occurs for a long time can be identified relatively easily, but the amount of imaging data for obtaining long-time noise brightness information becomes enormous, and it takes time to acquire teacher data. For this reason, image data generated by extrapolation from information of a plurality of image data may be used as teacher data.

There are only a few regions where bright spots occur due to long-term noise over the entire image. FIG. 3A is a diagram in which a dark image 36 is recursively divided to specify a region where noise occurs for a long time. That is, detailed learning may be performed only on the region 31b and the region 32b.

FIG. 3B is an enlarged view of the region 32b, and shows a state where presence / absence of noise for a long time is classified into the pixel level. Further, as shown in FIGS. 3C to 3E, the image can be divided to narrow down the pixels that may generate noise for a long time to the pixels where the bright spots are generated and the surrounding pixels. . The image may be divided until it finally becomes one pixel unit.

Using multiple teacher data, the image is divided as described above to learn the pixels that may generate noise for a long time and their brightness, and the noise is reproduced for a long time using the exposure time and temperature as input data. An image can be generated by the neural network 24.

FIG. 4 is a diagram for explaining the flow of operations for obtaining an image in which noise is reproduced for a long time by the neural network 24. The input information 40a and 40b correspond to the exposure time and temperature when the image capturing apparatus 10 acquires an image that is to be subject to noise removal for a long time. Note that ISO sensitivity may be further added as input information.

The input information 40a and 40b are input to the input layers 41 and 42, respectively, and the weighted information is input to the first layer of the intermediate layer 43. Here, the intermediate layer 43 has an arbitrary number of nodes and layers. Then, information output from the final layer of the intermediate layer is input to the output layer 44, and the output layer 44 outputs information constituting an image 37 that reproduces noise for a long time.

The image generated by the neural network 24 is an entire image such as the image 37 shown in FIG. 4A, a local image such as the images 38 and 39 shown in FIG. A part of the image obtained by dividing 38 and 39 may be used. In the case of local images such as the images 38 and 39, address information indicating the position with respect to the entire image is also given. When the subtraction process is performed from the original image, only the area having the same address needs to be processed.

Further, the neural network 24 may learn the operation of selecting an image. For example, images such as those shown in FIGS. 3B to 3E are extracted from the teacher data, and an image with long-term noise estimated using the exposure time and temperature as input data can be selected and output. . In this case, since a selection is made from a limited number of images, the reproducibility of noise for a long time may be inferior, but the operation of generating an image is simplified and can be operated at high speed. .

After the learning in the neural network 24 is completed, the determined weight coefficient is stored in the neural network 19. Therefore, the neural network 19 can perform the same operation as the learned neural network 24. The weight coefficient may be stored in the storage unit 16 and read from the storage unit 16 before the neural network 19 is operated. When performing the above-described operation of selecting an image, a plurality of images extracted from the teacher data are stored in the storage unit 16.

The learning operation using the external device 20 and the storage of the weighting factor in the imaging device 10 are preferably performed before the shipment of the imaging device 10 to the factory, and work on the user side is unnecessary. However, if it is desired to reduce noise more strictly for a long time, the user takes a dark image, uses the exposure time and temperature as input data, and corrects the weighting coefficient of the neural network 19 using the image as teacher data. May be. In this case, the imaging device 10 is preferably provided with a mechanical shutter for performing imaging in a dark state.

Next, the flow of the long-term noise removal operation in the imaging apparatus 10 will be described using the flowchart shown in FIG.

First, the first image is picked up by the image pickup unit 11 (S1). Here, the first image is an image captured by the user regardless of the imaging conditions. At this time, the data of the first image is temporarily stored in the image processing unit 14 or the storage unit 16.

Next, it is determined whether or not the conditions (exposure time, temperature) for capturing the first image are conditions for generating noise for a long time (S2). When the conditions are such that noise does not occur for a long time (exposure time is short, temperature is low, etc.), the image processing unit 14 performs conversion to an image format designated in advance (S6), and the storage unit 17 Saved (S7).

If the first image is captured for a long time (such as a long exposure time or high temperature), check whether it is set to remove noise for a long time. (S3).

If the user has set in advance that the noise removal operation is not performed for a long time, the process proceeds to S6. When noise is removed for a long time, the second image is generated by the neural network 19 using the imaging condition (exposure time, temperature) of the first image data as input data (S4). At this time, the data of the second image is temporarily stored in the image processing unit 14 or the storage unit 16.

Next, the image processing unit 14 performs processing for subtracting the second image data from the first image data to generate third image data from which noise has been removed for a long time.

Then, the third image data is converted into an image format designated in advance by the image processing unit 14 (S6) and stored in the storage unit 17 (S7).

With the above operation, acquisition of an image obtained by removing noise from the first image for a long time is completed.

In the flowchart of FIG. 5, the order of S2 and S3 may be switched. If the determination in S2 is Yes, S3 may be omitted and the process may proceed to S4.

On the assumption that there is no temperature change, the process proceeds to S2 after acquiring a plurality of first images with the same exposure time in S1, and the length of the plurality of first images using one second image generated in S4. You may perform the operation | movement which removes a time noise.

Next, a configuration example of the neural network will be described with reference to FIGS. The neural network NN includes a neuron circuit and a synapse circuit provided between the neuron circuits.

FIG. 6A shows a configuration example of the neuron circuit NC and the synapse circuit SC that constitute the neural network NN. Input data x _{1 to} x _L (L is a natural number) is input to the synapse circuit SC. The synapse circuit SC has a function of storing a weight coefficient w _k (k is an integer of 1 or more and L or less). The weighting factor w _k corresponds to the strength of the connection between the neuron circuits NC.

When the input data x _{1 to} x _{L are} input to the synapse circuit SC, the neuron circuit NC has a product of the input data x _k input to the synapse circuit CN and the weight coefficient w _k stored in the synapse circuit CN ( x _k w _k ) obtained by adding up k = 1 to L (x ₁ w ₁ + x ₂ w ₂ +... + x _L w _L ), that is, obtained by a product-sum operation using x _k and w _k Values are supplied. When this value exceeds the threshold value θ _O of the neuron circuit NC, the neuron circuit NC outputs a high level signal. This phenomenon is called firing of the neuron circuit NC.

FIG. 6B shows an example of a model of the neural network NN. The neural network NN has a hierarchical perceptron configuration using a neuron circuit NC and a synapse circuit SC, and has an input layer IL, a hidden layer (intermediate layer) HL, and an output layer OL.

Input layer IL can be output to the hidden layer HL, the input data _{x 1} to _{x L.} The hidden layer HL has a hidden synapse circuit HS and a hidden neuron circuit HN. The output layer OL has an output synapse circuit OS and an output neuron circuit ON.

The hidden neuron circuit HN is supplied with a value obtained by a product-sum operation using the input data x _k and the weighting coefficient w _k held in the hidden synapse circuit HS. The output neuron circuit ON is supplied with the value obtained by the product-sum operation using the output of the hidden neuron circuit HN and the weighting coefficient w _k held in the output synapse circuit OS. Then, the output neuron circuit ON, the output data _{y 1} to _{y n} are output.

As described above, the neural network NN given predetermined input data has a function of outputting, as output data, a weight coefficient held in the synapse circuit SC and a value corresponding to the threshold value θ of the neuron circuit.

The neural network NN can perform supervised learning by inputting teacher data. FIG. 6C shows a model of the neural network NN that performs supervised learning using the error back propagation method.

The error back propagation method is a method of changing the weight coefficient w _k of the synapse circuit so that the error between the output data of the neural network and the teacher signal becomes small. Specifically, according to the error [delta] _O, which is determined on the basis of the output data y ₁ to y _n and teacher data t ₁ to t _L, the weighting factor w _k hidden synapse circuit HS is changed. Further, in accordance with the change amount of the weighting coefficient w _k of the hidden synapse circuit HS, further weighting factor w _k of the preceding stage of the synapse circuit SC is changed. As described above, the neural network NN can be learned by sequentially changing the weighting coefficient of the synapse circuit SC based on the teacher data t _{1 to} t _L.

The configuration of the neural network shown in FIG. 6 can be used for the neural networks 19 and 24 in FIG. Further, the error back propagation method described above can be used for learning of the neural network 24. In that case, the input data x ₁ to the exposure time as x _L and temperature are used, the image of the dark state is used which is previously captured in the teacher data.

6B and 6C show one hidden layer HL, the number of hidden layers HL can be two or more. Deep learning can be performed by using a neural network having two or more hidden layers HL (deep neural network (DNN)). Thereby, the precision of image generation can be improved.

As described above, a second image including noise for a long time can be generated by using one embodiment of the present invention, and the second image is subtracted from the first image that is the original image. A third image with reduced noise for a long time can be obtained. Therefore, the operation of acquiring the second image by the imaging operation can be omitted, and the imaging throughput can be improved.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a structure example of a semiconductor device that can be used for the neural network described in the above embodiment will be described.

When the neural network is configured by hardware, the product-sum operation in the neural network can be performed using a product-sum operation element. In the present embodiment, a configuration example of a semiconductor device that can be used as a product-sum operation element in the neural network 19 or the neural network 24 will be described.

<Configuration example of semiconductor device>
An example of the configuration of the semiconductor device 100 is shown in FIG. A semiconductor device 100 illustrated in FIG. 7 includes a memory circuit 110 (MEM), a reference memory circuit 120 (RMEM), a circuit 130, and a circuit 140. The semiconductor device 100 may further include a current source circuit 150 (CREF).

The memory circuit 110 (MEM) includes a memory cell MC exemplified by a memory cell MC [i, j] and a memory cell MC [i + 1, j]. Each memory cell MC includes an element having a function of converting an input potential into a current. As an element having the above function, for example, an active element such as a transistor can be used. FIG. 7 illustrates a case where each memory cell MC includes a transistor Tr11.

Then, the first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The first analog potential corresponds to the first analog data. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr11 obtained when the first analog potential is supplied to the gate of the transistor Tr11 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is I [i, j], and the current flowing through the memory cell MC [i + 1, j] is I [i + 1, j].

Note that when the transistor Tr11 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr11 in the saturation region. In order to operate the transistor Tr11 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to a voltage in a range in which the transistor Tr11 operates in the saturation region.

Specifically, in the semiconductor device 100 illustrated in FIG. 7, the first analog potential Vx [i, j] or the first analog potential Vx [i, j] from the wiring WD [j] to the memory cell MC [i, j]. ] Is input according to the above. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

Specifically, in the semiconductor device 100 illustrated in FIG. 7, the first analog potential Vx [i + 1, j] or the first analog potential Vx [i + 1] from the wiring WD [j] to the memory cell MC [i + 1, j]. , J] is input. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

The memory cell MC has a function of holding the first analog potential. In other words, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

In addition, the second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The second analog potential corresponds to the second analog data. The memory cell MC has a function of adding the second analog potential or a potential corresponding to the second analog potential to the already held first analog potential, and a third analog potential obtained by the addition. Holding function. The memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding the second analog current corresponding to the third analog potential by holding the third analog potential.

Specifically, in the semiconductor device 100 illustrated in FIG. 7, the second analog potential Vw [i, j] is input from the wiring RW [i] to the memory cell MC [i, j]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

In the semiconductor device 100 illustrated in FIG. 7, the second analog potential Vw [i + 1, j] is input to the memory cell MC [i + 1, j] from the wiring RW [i + 1]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

The current I [i, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i + 1, j]. Therefore, the current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] is passed through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It flows between the wiring BL [j] and the wiring VR [j].

The reference memory circuit 120 (RMEM) includes a memory cell MCR exemplified by a memory cell MCR [i] and a memory cell MCR [i + 1]. A first reference potential VPR is input to the memory cell MCR from the wiring WDREF. The memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

Specifically, in the semiconductor device 100 illustrated in FIG. 7, the first reference potential VPR is input to the memory cell MCR [i] from the wiring WDREF [i]. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

In the semiconductor device 100 illustrated in FIG. 7, the first reference potential VPR is input to the memory cell MCR [i + 1] from the wiring WDREF. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

In addition, the second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR adds the second analog potential or a potential corresponding to the second analog potential to the already held first reference potential VPR, and holds the second reference potential obtained by the addition. It has the function to do. The memory cell MCR has a function of generating a second reference current corresponding to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference potential corresponding to the second reference potential by holding the second reference potential.

Specifically, in the semiconductor device 100 illustrated in FIG. 7, the second analog potential Vw [i, j] is input to the memory cell MCR [i] from the wiring RW [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

In the semiconductor device 100 illustrated in FIG. 7, the second analog potential Vw [i + 1, j] is input from the wiring RW [i + 1] to the memory cell MCR [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current corresponding to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR [i + 1]. Therefore, a current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

The current source circuit 150 has a function of supplying a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF to the wiring BL. When setting an offset current described later, a current flowing between the wiring BL [j] and the wiring VR [j] through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. When I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the difference current flows in the circuit 130 or the circuit 140. The circuit 130 has a function as a current source circuit, and the circuit 140 has a function as a current sink circuit.

Specifically, when the current I [j] is larger than the current IREF, the circuit 130 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The circuit 130 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the circuit 130 has a function of holding the current ΔI [j].

When the current I [j] is smaller than the current IREF, the circuit 140 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. The circuit 140 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the circuit 140 has a function of holding the current ΔI [j].

Next, an example of operation of the semiconductor device 100 illustrated in FIG. 7 will be described.

First, a potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, a potential VPR−Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is set to the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] is generated. For example, the first reference potential VPR is a high level potential higher than the ground potential. Specifically, it is desirable that the potential is higher than the ground potential and is approximately equal to or lower than the high-level potential VDD supplied to the current source circuit 150.

Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the potential VPR is input to the memory cell MCR [i] through the wiring WDREF. In the Mori cell MCR [i], the potential VPR is held. In the memory cell MCR [i], a current IREF [i] corresponding to the potential VPR is generated.

In addition, a potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR−Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is connected to the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] is generated.

In addition, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the potential VPR is input to the memory cell MCR [i + 1] through the wiring WDREF. In the Mori cell MCR [i + 1], the potential VPR is held. In the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the potential VPR is generated.

In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, a ground potential, a low-level potential VSS lower than the reference potential, or the like can be used as the reference potential. Alternatively, when a potential between the potential VSS and the potential VDD is used as the reference potential, even if the second analog potential Vw is positive or negative, the potential of the wiring RW can be higher than the ground potential, thereby facilitating signal generation. This is preferable because product operation can be performed on positive and negative analog data.

Through the above operation, currents that are combined with currents generated in the memory cells MC connected to the wiring BL [j] flow through the wiring BL [j]. Specifically, in FIG. 7, the current I [i, j] generated in the memory cell MC [i, j] is combined with the current I [i + 1, j] generated in the memory cell MC [i + 1, j]. Current I [j] flows. Further, by the above operation, currents that are combined with currents generated in the memory cells MCR connected to the wiring BLREF flow through the wiring BLREF. Specifically, in FIG. 7, a current IREF that is a combination of the current IREF [i] generated in the memory cell MCR [i] and the current IREF [i + 1] generated in the memory cell MCR [i + 1] flows.

Next, from the difference between the current I [j] obtained by the first analog potential and the current IREF obtained by the first reference potential, with the potentials of the wiring RW [i] and the wiring RW [i + 1] being the reference potential. The obtained offset current Ioffset [j] is held in the circuit 130 or the circuit 140.

Specifically, when the current I [j] is larger than the current IREF, the circuit 130 supplies the current Ioffset [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the circuit 130 corresponds to the current Ioffset [j]. The value of the current ICM [j] is held in the circuit 130. When the current I [j] is smaller than the current IREF, the circuit 140 draws the current Ioffset [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the circuit 140 corresponds to the current Ioffset [j]. The value of the current ICP [j] is held in the circuit 140.

Then, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher by Vw [i] than the reference potential, the second analog potential Vw [i] is stored in the memory via the wiring RW [i]. Input to cell MC [i, j]. In the memory cell MC [i, j], the potential VPR−Vx [i, j] + Vw [i] is held. In the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR−Vx [i, j] + Vw [i] is generated.

Further, according to the second analog potential or the second analog potential so as to be added to the first analog potential already held in the memory cell MC [i + 1, j] or the potential according to the first analog potential. The stored potential is stored in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] higher by Vw [i + 1] than the reference potential, the second analog potential Vw [i + 1] is stored in the memory through the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR−Vx [i + 1, j] + Vw [i + 1] is held. In the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR−Vx [i + 1, j] + Vw [i + 1] is generated.

Note that in the case where the transistor Tr11 that operates in the saturation region is used as an element that converts potential into current, the potential of the wiring RW [i] is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that the drain current of the transistor Tr11 included in the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following Equation 1. Note that k is a coefficient and Vth is a threshold voltage of the transistor Tr11.

I [i, j] = k (Vw [i] −Vth + VPR−Vx [i, j]) ² (Formula 1)

Further, since the drain current of the transistor Tr11 included in the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is expressed by the following Expression 2.

IREF [i] = k (Vw [i] −Vth + VPR) ² (Formula 2)

The current I [j] corresponding to the sum of the current I [i, j] flowing through the memory cell MC [i, j] and the current I [i + 1, j] flowing through the memory cell MC [i + 1, j] is: I [j] = Σ _i I [i, j], and the current corresponding to the sum of the current IREF [i] flowing through the memory cell MCR [i] and the current IREF [i + 1] flowing through the memory cell MCR [i + 1] IREF becomes IREF = Σ _i IREF [i], and current ΔI [j] corresponding to the difference is expressed by the following Expression 3.

ΔI [j] = IREF−I [j] = Σ _i IREF [i] −Σ _i I [i, j] (Formula 3)

From Equation 1, Equation 2, and Equation 3, current ΔI [j] is derived as in Equation 4 below.

ΔI [j]
= Σ _i {k (Vw [i] −Vth + VPR) ² −k (Vw [i] −Vth + VPR−Vx [i, j]) ² }
_{= 2kΣ i (Vw [i]} · Vx [i, j]) - 2kΣ i (Vth-VPR) · Vx [i, j] -kΣ i Vx [i, j] 2 ( Equation 4)

In Equation 4, the term represented by 2kΣ _i (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i], This corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Further, Ioffset [j] is when the potential of the wiring RW [i] is all set as the reference potential, that is, when the second analog potential Vw [i] is 0 and the second analog potential Vw [i + 1] is 0. If the current ΔI [j] is, then the following equation 5 is derived from the equation 4.

_{Ioffset [j] = - 2kΣ i} (Vth-VPR) · Vx [i, j] -kΣ i Vx [i, j] 2 ( Equation 5)

Therefore, from Expressions 3 to 5, 2kΣ _i (Vw [i] · Vx [i, j]) corresponding to the product sum value of the first analog data and the second analog data is expressed by Expression 6 below. You can see that

2kΣ _i (Vw [i] · Vx [i, j]) = IREF−I [j] −Ioffset [j] (Formula 6)

When the sum of currents flowing through the memory cell MC is current I [j], the sum of currents flowing through the memory cell MCR is current IREF, and the current flowing through the circuit 130 or the circuit 140 is current Ioffset [j], the wiring RW [i] ] Is Vw [i] and the wiring RW [i + 1] is Vw [i + 1], the current Iout [j] flowing out of the wiring BL [j] is IREF-I [j] -Ioffset [j]. It is represented by From Equation 6, the current Iout [j] is 2kΣ _i (Vw [i] · Vx [i, j]), the first analog potential Vx [i, j] and the second analog potential Vw [i]. This is equivalent to the sum of the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Note that the transistor Tr11 is desirably operated in a saturation region, but even if the operation region of the transistor Tr11 is different from an ideal saturation region, the first analog potential Vx [i, j] and the second analog potential are A current corresponding to the sum of the product of Vw [i] and the product of the second analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] is obtained without any problem with accuracy within a desired range. If it can, the transistor Tr11 can be regarded as operating in the saturation region.

According to one embodiment of the present invention, arithmetic processing of analog data can be executed without being converted into digital data, so that the circuit scale of the semiconductor device can be reduced. Further, according to one embodiment of the present invention, analog data arithmetic processing can be performed without being converted into digital data, so that the time required for analog data arithmetic processing can be reduced. According to one embodiment of the present invention, low power consumption of a semiconductor device can be realized while suppressing time required for arithmetic processing of analog data.

<Configuration example of memory circuit>
Next, examples of specific structures of the memory circuit 110 (MEM) and the reference memory circuit 120 (RMEM) will be described with reference to FIGS.

FIG. 8 illustrates a case where the memory circuit 110 (MEM) has a plurality of memory cells MC in y rows and x columns, and the reference memory circuit 120 (RMEM) has a plurality of memory cells MCR in y rows and 1 column. ing.

The memory circuit 110 is connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. In FIG. 8, the wirings RW [1] to RW [y] are connected to the memory cells MC in each row, the wirings WW [1] to WW [y] are connected to the memory cells MC in each row, and the wiring WD. [1] to wiring WD [y] are connected to the memory cells MC in each column, and wirings BL [1] to BL [y] are connected to the memory cells MC in each column. Yes. FIG. 8 illustrates the case where the wirings VR [1] to VR [y] are connected to the memory cells MC in each column, respectively. Note that the wirings VR [1] to VR [y] may be connected to each other.

The reference memory circuit 120 is connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. In FIG. 8, the wirings RW [1] to RW [y] are connected to the memory cells MCR in each row, the wirings WW [1] to WW [y] are connected to the memory cells MCR in each row, and the wiring WDREF is connected. Are respectively connected to one row of memory cells MCR, the wiring BLREF is connected to one row of memory cells MCR, and the wiring VRREF is connected to one row of memory cells MCR. Note that the wiring VRREF may be connected to the wirings VR [1] to VR [y].

Next, among the plurality of memory cells MC shown in FIG. 8, any two rows and two columns of memory cells MC, and among the plurality of memory cells MCR shown in FIG. 8, any two rows and one column of memory cells MCR. FIG. 9 shows a specific circuit configuration and connection relationship as an example.

Specifically, in FIG. 9, the memory cell MC [i, j] in the i-th row and j-th column, the memory cell MC [i + 1, j] in the i + 1-th row and j-th column, and the memory cell MC [i in the i-th row j + 1-th column. , J + 1] and the memory cell MC [i + 1, j + 1] in the (i + 1) th row and j + 1th column. Specifically, FIG. 9 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1-th row. Note that i and i + 1 are each an arbitrary number from 1 to y, and j and j + 1 are each an arbitrary number from 1 to x.

The i-th row memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] are connected to the wiring RW [i] and the wiring WW [i]. Further, the memory cell MC [i + 1, j] in the i + 1th row, the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] are connected to the wiring RW [i + 1] and the wiring WW [i + 1]. Yes.

The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. The memory cell MC [i, j + 1] in the j + 1 column and the memory cell MC [i + 1, j + 1] are connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. . The memory cell MCR [i] and the memory cell MCR [i + 1] in the (i + 1) th row are connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

Each memory cell MC and each memory cell MCR includes a transistor Tr11, a transistor Tr12, and a capacitor C11. The transistor Tr12 has a function of controlling input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr11 has a function of generating an analog current in accordance with the potential input to the gate. The capacitor C11 has a first analog potential held in the memory cell MC or the memory cell MCR or a potential corresponding to the first analog potential, and a potential corresponding to the second analog potential or the second analog potential. Has the function of adding.

Specifically, in the memory cell MC illustrated in FIG. 9, the transistor Tr12 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WD, and the other of the source and the drain connected to the gate of the transistor Tr11. ing. In the transistor Tr11, one of a source and a drain is connected to the wiring VR, and the other of the source and the drain is connected to the wiring BL. In the capacitor C11, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr11.

In the memory cell MCR shown in FIG. 9, the transistor Tr12 has a gate connected to the wiring WW, one of the source and the drain connected to the wiring WDREF, and the other of the source and the drain connected to the gate of the transistor Tr11. . In the transistor Tr11, one of a source and a drain is connected to the wiring VRREF, and the other of the source and the drain is connected to the wiring BLREF. In the capacitor C11, the first electrode is connected to the wiring RW, and the second electrode is connected to the gate of the transistor Tr11.

In the memory cell MC, when the gate of the transistor Tr11 is a node N, in the memory cell MC, the first analog potential is input to the node N through the transistor Tr12. Then, when the transistor Tr12 is turned off, the node N is in a floating state. The node N holds the first analog potential or the potential corresponding to the first analog potential. In the memory cell MC, when the node N is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is applied to the node N. With the above operation, the node N has a potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first analog potential or the first analog potential. Become.

Note that since the potential of the first electrode of the capacitor C11 is applied to the node N via the capacitor C11, in practice, the amount of change in the potential of the first electrode is directly reflected in the amount of change in the potential of the node N. It is not done. Specifically, the amount of change in potential of the first electrode is multiplied by a coupling coefficient that is uniquely determined from the capacitance value of the capacitive element C11, the capacitance value of the gate capacitance of the transistor Tr11, and the capacitance value of the parasitic capacitance. The amount of change in the potential of the node N can be accurately calculated. Hereinafter, in order to make the description easy to understand, it is assumed that the change amount of the potential of the first electrode is reflected in the change amount of the potential of the node N.

The drain current of the transistor Tr11 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr12, the value of the drain current of the transistor Tr11 is also held. The drain current reflects the first analog potential and the second analog potential.

Further, when the gate of the transistor Tr11 in the memory cell MCR is the node NREF, in the memory cell MCR, a first reference potential or a potential corresponding to the first reference potential is input to the node NREF through the transistor Tr12, and then the transistor When Tr12 is turned off, the node NREF enters a floating state, and the first reference potential or a potential corresponding to the first reference potential is held at the node NREF. In the memory cell MCR, when the node NREF is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is applied to the node NREF. Through the above operation, the node NREF has the potential obtained by adding the second analog potential or the potential corresponding to the second analog potential to the potential corresponding to the first reference potential or the first reference potential. Become.

The drain current of the transistor Tr11 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is held by turning off the transistor Tr12, the value of the drain current of the transistor Tr11 is also held. The drain current reflects the first reference potential and the second analog potential.

If the drain current flowing through the transistor Tr12 of the memory cell MC [i, j] is current I [i, j] and the drain current flowing through the transistor Tr12 of the memory cell MC [i + 1, j] is current I [i + 1, j]. The sum of the currents supplied from the wiring BL [j] to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current I [j]. Further, the drain current flowing through the transistor Tr12 of the memory cell MC [i, j + 1] is defined as a current I [i, j + 1], and the drain current flowing through the transistor Tr12 of the memory cell MC [i + 1, j + 1] is defined as a current I [i + 1, j + 1]. Then, a sum of currents supplied from the wiring BL [j + 1] to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is a current I [j + 1]. Further, if the drain current flowing through the transistor Tr12 of the memory cell MCR [i] is the current IREF [i] and the drain current flowing through the transistor Tr12 of the memory cell MCR [i + 1] is the current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to MCR [i] and memory cell MCR [i + 1] is current IREF.

<Configuration Example of Circuit 130 / Circuit 140 / Current Source Circuit>
Next, examples of specific structures of the circuit 130, the circuit 140, and the current source circuit 150 (CREF) will be described with reference to FIGS.

FIG. 10 shows an example of the configuration of the circuit 130, the circuit 140, and the current source circuit 150 corresponding to the memory cell MC and the memory cell MCR shown in FIG. Specifically, the circuit 130 illustrated in FIG. 10 includes a circuit 130 [j] corresponding to the memory cell MC in the jth column and a circuit 130 [j + 1] corresponding to the memory cell MC in the j + 1th column. The circuit 140 illustrated in FIG. 10 includes a circuit 140 [j] corresponding to the memory cell MC in the jth column and a circuit 140 [j + 1] corresponding to the memory cell MC in the j + 1th column.

The circuit 130 [j] and the circuit 140 [j] are connected to the wiring BL [j]. The circuit 130 [j + 1] and the circuit 140 [j + 1] are connected to the wiring BL [j + 1].

The current source circuit 150 is connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 150 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Have

Specifically, the circuit 130 [j] and the circuit 130 [j + 1] include transistors Tr24 to Tr26 and a capacitor C22, respectively. In setting the offset current, in the circuit 130 [j], the transistor Tr24 causes the current ICM [corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. j]. In the circuit 130 [j + 1], the transistor Tr24 has a function of generating a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. Have. The current ICM [j] and the current ICM [j + 1] are supplied from the circuit 130 [j] and the circuit 130 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

In the circuit 130 [j] and the circuit 130 [j + 1], in the transistor Tr24, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is a wiring to which a predetermined potential is supplied. It is connected. In the transistor Tr25, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr24. In the transistor Tr26, one of the source and the drain is connected to the gate of the transistor Tr24, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C22, the first electrode is connected to the gate of the transistor Tr24, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

The gate of the transistor Tr25 is connected to the wiring OSM, and the gate of the transistor Tr26 is connected to the wiring ORM.

Note that FIG. 10 illustrates a case where the transistor Tr24 is a p-channel type and the transistors Tr25 and Tr26 are an n-channel type.

Further, the circuit 140 [j] and the circuit 140 [j + 1] each include transistors Tr21 to Tr23 and a capacitor C21. In setting the offset current, in the circuit 140 [j], the transistor Tr21 causes the current ICP [corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. j]. In the circuit 140 [j + 1], the transistor Tr21 has a function of generating a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. Have. The current ICP [j] and the current ICP [j + 1] are drawn from the wiring BL [j] and the wiring BL [j + 1] to the circuit 140 [j] and the circuit 140 [j + 1].

Note that the current ICM [j] and the current ICP [j] correspond to Ioffset [j]. Note that the current ICM [j + 1] and the current ICP [j + 1] correspond to Ioffset [j + 1].

In the circuit 140 [j] and the circuit 140 [j + 1], in the transistor Tr21, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is a wiring to which a predetermined potential is supplied. It is connected. In the transistor Tr22, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr21. In the transistor Tr23, one of a source and a drain is connected to the gate of the transistor Tr21, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the capacitor C21, the first electrode is connected to the gate of the transistor Tr21, and the second electrode is connected to a wiring to which a predetermined potential is supplied.

The gate of the transistor Tr22 is connected to the wiring OSP, and the gate of the transistor Tr23 is connected to the wiring ORP.

Note that FIG. 10 illustrates the case where the transistors Tr21 to Tr23 are n-channel type.

The current source circuit 150 includes a transistor Tr27 corresponding to the wiring BL and a transistor Tr28 corresponding to the wiring BLREF. Specifically, the current source circuit 150 illustrated in FIG. 10 includes, as the transistor Tr27, a transistor Tr27 [j] corresponding to the wiring BL [j] and a transistor Tr27 [j + 1] corresponding to the wiring BL [j + 1]. Is illustrated.

The gate of the transistor Tr27 is connected to the gate of the transistor Tr28. In the transistor Tr27, one of the source and the drain is connected to the corresponding wiring BL, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied. In the transistor Tr28, one of a source and a drain is connected to the wiring BLREF, and the other of the source and the drain is connected to a wiring to which a predetermined potential is supplied.

The transistor Tr27 and the transistor Tr28 have the same polarity. FIG. 10 illustrates a case where both the transistor Tr27 and the transistor Tr28 have a p-channel type.

The drain current of the transistor Tr28 corresponds to the current IREF. Since the transistor Tr27 and the transistor Tr28 have a function as a current mirror circuit, the drain current of the transistor Tr27 has almost the same value as the drain current of the transistor Tr28 or a value corresponding to the drain current of the transistor Tr28.

<Operation example of semiconductor device>
Next, an example of a specific operation of the semiconductor device 100 according to one embodiment of the present invention will be described with reference to FIGS.

FIG. 11 corresponds to an example of a timing chart illustrating operations of the memory cell MC and the memory cell MCR illustrated in FIG. 9 and the circuit 130, the circuit 140, and the current source circuit 150 illustrated in FIG. In FIG. 11, from time T01 to time T04, the operation of storing the first analog data in the memory cell MC and the memory cell MCR is performed. From time T05 to time T10, an operation for setting the offset current Ioffset in the circuit 130 and the circuit 140 is performed. From time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog data and the second analog data is performed.

Note that a low-level potential is supplied to the power supply line VR [j] and the power supply line VR [j + 1]. In addition, a wiring having a predetermined potential connected to the circuit 130 is supplied with a high-level potential VDD. In addition, all the wirings having a predetermined potential connected to the circuit 140 are supplied with the low-level potential VSS. In addition, all the wirings having a predetermined potential connected to the current source circuit 150 are supplied with the high-level potential VDD.

The transistors Tr11, Tr21, Tr24, Tr27 [j], Tr27 [j + 1], and Tr28 operate in the saturation region.

First, from time T01 to time T02, a high-level potential is applied to the wiring WW [i], and a low-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr12 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] illustrated in FIG. Further, the transistor Tr12 is kept off in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

From time T01 to time T02, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR-Vx [i, j] is applied to the wiring WD [j], and the potential VPR-Vx [i, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, the potential (VDD + VSS) / 2. Given.

Therefore, the potential VPR−Vx [i, j] is applied to the node N [i, j] of the memory cell MC [i, j] illustrated in FIG. 9 through the transistor Tr12, and the memory cell MC [i, j + 1] is supplied. Node N [i, j + 1] is supplied with the potential VPR−Vx [i, j + 1] through the transistor Tr12, and the node NREF [i] of the memory cell MCR [i] is supplied with the potential VPR through the transistor Tr12. Given.

When the time T02 ends, the potential applied to the wiring WW [i] illustrated in FIG. 9 changes from the high level to the low level, the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR. In [i], the transistor Tr12 is turned off. Through the above operation, the node N [i, j] holds the potential VPR−Vx [i, j], the node N [i, j + 1] holds the potential VPR−Vx [i, j + 1], and the node NREF [I] holds the potential VPR.

Next, in time T03 to time T04, the potential of the wiring WW [i] illustrated in FIG. 9 is maintained at a low level, and a high-level potential is applied to the wiring WW [i + 1]. Through the above operation, the transistor Tr12 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] illustrated in FIG. Further, the transistor Tr12 is kept off in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

From time T03 to time T04, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to the wiring WD [j] and the wiring WD [j + 1] illustrated in FIG. Specifically, the potential VPR−Vx [i + 1, j] is applied to the wiring WD [j], and the potential VPR−Vx [i + 1, j + 1] is applied to the wiring WD [j + 1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD as a reference potential, for example, the potential (VDD + VSS) / 2. Given.

Accordingly, the node N [i + 1, j] of the memory cell MC [i + 1, j] illustrated in FIG. 9 is supplied with the potential VPR−Vx [i + 1, j] through the transistor Tr12, and the memory cell MC [i + 1, j + 1]. Node N [i + 1, j + 1] is supplied with the potential VPR-Vx [i + 1, j + 1] via the transistor Tr12, and the node NREF [i + 1] of the memory cell MCR [i + 1] is supplied with the potential VPR via the transistor Tr12. Given.

When the time T04 ends, the potential applied to the wiring WW [i + 1] illustrated in FIG. 9 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR. In [i + 1], the transistor Tr12 is turned off. Through the above operation, the node N [i + 1, j] holds the potential VPR−Vx [i + 1, j], the node N [i + 1, j + 1] holds the potential VPR−Vx [i + 1, j + 1], and the node NREF [I + 1] holds the potential VPR.

Next, at time T05 to time T06, a high-level potential is applied to the wiring ORP and the wiring ORM illustrated in FIG. In the circuit 130 [j] and the circuit 130 [j + 1] illustrated in FIG. 10, when a high-level potential is applied to the wiring ORM, the transistor Tr26 is turned on, and the gate of the transistor Tr24 is reset when the potential VDD is applied. Is done. Further, in the circuit 140 [j] and the circuit 140 [j + 1] illustrated in FIG. 10, when the high-level potential is applied to the wiring ORP, the transistor Tr23 is turned on, and the potential VSS is applied to the gate of the transistor Tr21. To reset.

When the time T06 ends, the potentials applied to the wiring ORP and the wiring ORM illustrated in FIG. 9 change from a high level to a low level, the transistor Tr26 is turned off in the circuit 130 [j] and the circuit 130 [j + 1], and the circuit 140 In [j] and the circuit 140 [j + 1], the transistor Tr23 is turned off. With the above operation, the potential VDD is held at the gate of the transistor Tr24 in the circuit 130 [j] and the circuit 130 [j + 1], and the potential VSS is held at the gate of the transistor Tr21 in the circuit 140 [j] and the circuit 140 [j + 1]. .

Next, at time T07 to time T08, a high-level potential is applied to the wiring OSP illustrated in FIG. Further, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is applied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When a high-level potential is applied to the wiring OSP, the transistor Tr22 is turned on in the circuit 140 [j] and the circuit 140 [j + 1].

When I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the transistor Tr28 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr28 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr27 [j]. Therefore, when the current ΔI [j] is positive and the transistor Tr22 is turned on in the circuit 140 [j], part of the drain current of the transistor Tr27 [j] flows into the gate of the transistor Tr21, and the potential of the gate increases. Begin to. When the drain current of the transistor Tr21 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr21 converges to a predetermined value. At this time, the gate potential of the transistor Tr21 corresponds to a potential at which the drain current of the transistor Tr21 becomes the current ΔI [j], that is, Ioffset [j] (= ICP [j]). That is, it can be said that the transistor Tr21 of the circuit 140 [j] is set to a current source that can flow the current ICP [j].

Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, the transistor Tr22 is turned on in the circuit 140 [j + 1]. Part of the drain current of the transistor Tr27 [j + 1] flows into the gate of the transistor Tr21, and the potential of the gate starts to rise. When the drain current of the transistor Tr21 becomes substantially equal to the current ΔI [j + 1], the gate potential of the transistor Tr21 converges to a predetermined value. The potential of the gate of the transistor Tr21 at this time corresponds to a potential at which the drain current of the transistor Tr21 becomes the current ΔI [j + 1], that is, Ioffset [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr21 of the circuit 140 [j + 1] is set to a current source that can flow the current ICP [j + 1].

When the time T08 ends, the potential applied to the wiring OSP illustrated in FIG. 10 changes from a high level to a low level, and the transistor Tr22 is turned off in the circuit 140 [j] and the circuit 140 [j + 1]. Through the above operation, the potential of the gate of the transistor Tr21 is maintained. Therefore, the circuit 140 [j] maintains a state set as a current source capable of flowing the current ICP [j], and the circuit 140 [j + 1] maintains a state set as a current source capable of flowing the current ICP [j + 1]. To do.

Next, at time T09 to time T10, a high-level potential is applied to the wiring OSM illustrated in FIG. Further, a potential between the potential VSS and the potential VDD, for example, a potential (VDD + VSS) / 2 is applied as a reference potential to the wiring RW [i] and the wiring RW [i + 1] illustrated in FIG. When the high-level potential is applied to the wiring OSM, the transistor Tr25 is turned on in the circuit 130 [j] and the circuit 130 [j + 1].

When I [j] flowing through the wiring BL [j] is larger than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is negative, the transistor Tr28 of the memory cell MC [i, j] illustrated in FIG. This means that the sum of the current that can be drawn and the current that can be drawn by the transistor Tr28 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr27 [j]. Therefore, when the current ΔI [j] is negative, when the transistor Tr25 is turned on in the circuit 130 [j], current flows from the gate of the transistor Tr24 to the wiring BL [j], and the potential of the gate starts to decrease. When the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr24 converges to a predetermined value. At this time, the gate potential of the transistor Tr24 corresponds to a potential at which the drain current of the transistor Tr24 becomes the current ΔI [j], that is, Ioffset [j] (= ICM [j]). That is, it can be said that the transistor Tr24 of the circuit 130 [j] is set to a current source that can flow the current ICM [j].

Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, the transistor Tr25 is turned on in the circuit 130 [j + 1]. A current flows from the gate of the transistor Tr24 to the wiring BL [j + 1], and the potential of the gate starts to decrease. When the drain current of the transistor Tr24 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 is equal to the current ΔI [j + 1], that is, the absolute value of Ioffset [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr24 of the circuit 130 [j + 1] is set to a current source that can flow the current ICM [j + 1].

When the time T08 ends, the potential applied to the wiring OSM illustrated in FIG. 10 changes from a high level to a low level, and the transistor Tr25 is turned off in the circuit 130 [j] and the circuit 130 [j + 1]. With the above operation, the potential of the gate of the transistor Tr24 is maintained. Therefore, the circuit 130 [j] maintains a state set as a current source capable of flowing the current ICM [j], and the circuit 130 [j + 1] maintains a state set as a current source capable of flowing the current ICM [j + 1]. To do.

Note that in the circuit 140 [j] and the circuit 140 [j + 1], the transistor Tr21 has a function of drawing current. Therefore, when the current I [j] that flows through the wiring BL [j] is larger than the current IREF that flows through the wiring BLREF from time T07 to time T08 and ΔI [j] is negative, or the current I that flows through the wiring BL [j + 1] When [j + 1] is larger than the current IREF flowing through the wiring BLREF and ΔI [j + 1] is negative, the current flows from the circuit 140 [j] or 140 [j + 1] to the wiring BL [j] or the wiring BL [j + 1] without excess or deficiency. May be difficult to supply. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] with the current flowing through the wiring BLREF, the transistor Tr11 of the memory cell MC, the circuit 140 [j], or the circuit 140 [j + 1]. ] Transistor Tr21 and transistor Tr27 [j] or Tr27 [j + 1] may both be difficult to operate in the saturation region.

Even when ΔI [j] is negative from time T07 to time T08, in order to ensure the operation in the saturation region of the transistor Tr11, Tr21, Tr27 [j], or Tr27 [j + 1], the transistor from time T05 to time T06 Instead of resetting the gate of Tr24 to the potential VDD, the gate potential of the transistor Tr24 may be set to such a level that a predetermined drain current can be obtained. With the above structure, since current is supplied from the transistor Tr24 in addition to the drain current of the transistor Tr27 [j] or Tr27 [j + 1], a current that cannot be drawn in the transistor Tr11 can be drawn to some extent in the transistor Tr21. The operation in the saturation region of the transistors Tr11, Tr21, Tr27 [j] or Tr27 [j + 1] can be ensured.

Note that in the period from time T09 to time T10, when I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j] is positive, the circuit 140 is processed from time T07 to time T08. Since [j] is already set as a current source capable of flowing the current ICP [j], the potential of the gate of the transistor Tr24 remains substantially at the potential VDD in the circuit 130 [j]. Similarly, when I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when ΔI [j + 1] is positive, the circuit 140 [j + 1] is switched to the current ICP from time T07 to time T08. Since the current source that can flow [j + 1] is already set, the potential of the gate of the transistor Tr24 in the circuit 130 [j + 1] remains substantially at the potential VDD.

Next, at time T11 to time T12, the second analog potential Vw [i] is applied to the wiring RW [i] illustrated in FIG. The wiring RW [i + 1] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For easy understanding, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. From the above equation 6, the sum of products of the first analog data and the second analog data corresponding to the memory cell MC [i, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. In other words, it is reflected in the current Iout [j] flowing out from the wiring BL [j]. The product sum of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that the current Iout [j + 1] flowing out from j + 1] is reflected.

When the time T12 ends, the wiring RW [i] is again supplied with a potential between the potential VSS and the potential VDD which is the reference potential, for example, the potential (VDD + VSS) / 2.

Next, at time T13 to time T14, the second analog potential Vw [i + 1] is applied to the wiring RW [i + 1] illustrated in FIG. The wiring RW [i] is still supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as the reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by a potential difference Vw [i + 1] than the potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. For ease of explanation, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

When it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N. The potential of the node N in the cell MC [i + 1, j] is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1] + Vw. [I + 1]. From the above equation 6, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i + 1, j] is the current obtained by subtracting Ioffset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in Iout [j]. The product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i + 1, j + 1] is a current obtained by subtracting Ioffset [j + 1] from the current ΔI [j + 1], that is, Iout [j + 1]. ] Is reflected in the

When the time T12 ends, the wiring RW [i + 1] is again supplied with a potential between the potential VSS which is the reference potential and the potential VDD, for example, the potential (VDD + VSS) / 2.

Next, at time T15 to time T16, the second analog potential Vw [i] is supplied to the wiring RW [i] illustrated in FIG. 9, and the second analog potential Vw [i + 1] is supplied to the wiring RW [i + 1]. . Specifically, the potential of the wiring RW [i] is higher by a potential difference Vw [i] than a potential between the reference potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of (i + 1) is higher than the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 by a potential difference Vw [i + 1]. Further, it is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

When it is assumed that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitor C11 is substantially reflected in the amount of change in the potential of the node N, the memory illustrated in FIG. The potential of the node N in the cell MC [i, j] is VPR−Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR−Vx [i, j + 1] + Vw. [I]. Further, when it is assumed that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitor C11 is reflected in the amount of change in the potential of the node N, FIG. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR−Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR−Vx [i + 1, j + 1. ] + Vw [i + 1].

From Equation 6 above, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j] and the memory cell MC [i + 1, j] is the current ΔI [j ] Is subtracted from Ioffset [j], that is, the current Iout [j] is reflected. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is obtained from the current ΔI [j + 1] to Ioffset [j + 1]. It can be seen that the current is subtracted from the current Iout [j + 1].

When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again supplied with a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2.

With the above configuration, the product-sum operation can be performed with a small circuit scale. In addition, with the above configuration, the product-sum operation can be performed at high speed. In addition, with the above configuration, the product-sum operation can be performed with low power consumption.

Note that a transistor with extremely low off-state current is preferably used as the transistors Tr12, Tr22, Tr23, Tr25, or Tr26. By using a transistor with an extremely low off-state current as the transistor Tr12, the potential of the node N can be held for a long time. Further, by using transistors with extremely low off-state current for the transistors Tr22 and Tr23, the potential of the gate of the transistor Tr21 can be held for a long time. In addition, by using transistors with extremely low off-state current for the transistors Tr25 and Tr26, the potential of the gate of the transistor Tr24 can be held for a long time.

A transistor using a metal oxide for a semiconductor layer (hereinafter referred to as an OS transistor) may be used as a transistor with extremely low off-state current. The leakage current of the OS transistor normalized by the channel width can be 10 × 10 ⁻²¹ A / μm (10 zept A / μm) or less when the source drain voltage is 10 V and room temperature (about 25 ° C.). is there.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium. For example, a CAC-OS described later can be used.

The semiconductor layer is represented by an In-M-Zn-based oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a membrane.

In the case where the oxide semiconductor included in the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ , and an oxide semiconductor having a carrier density of 1 × 10 ⁻⁹ / cm ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Accordingly, it can be said that the oxide semiconductor has stable characteristics because the impurity concentration is low and the density of defect states is low.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .

In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of Group 14 elements, is included, oxygen deficiency increases and the n-type semiconductor is formed. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. For this reason, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor is easily n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The semiconductor layer may have a non-single crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Crystalline Oxide Semiconductor Semiconductor having a crystal oriented in the c-axis, or a C-Axis Aligned and A-B-Plane Annealed Crystal Oxide Crystal Structure, Includes a microcrystalline structure or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

Note that the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.

Hereinafter, a structure of a CAC (Cloud-Aligned Composite) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less. .

The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Therefore, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, thereby increasing the An on-current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is suitable as a constituent material for various semiconductor devices.

By using the semiconductor device described above, the product-sum operation in the neural network 19 or the neural network 24 can be performed.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of an imaging device to which one embodiment of the present invention can be applied is described with reference to drawings.

FIG. 12A illustrates a pixel circuit of the imaging device. The pixel circuit includes a photoelectric conversion element 50, a transistor 51, a transistor 52, a transistor 53, and a transistor 54.

One electrode (anode) of the photoelectric conversion element 50 is electrically connected to one of a source and a drain of the transistor 51. One electrode of the photoelectric conversion element 50 is electrically connected to one of a source and a drain of the transistor 52. The other of the source and the drain of the transistor 51 is electrically connected to the gate of the transistor 53. One of the source and the drain of the transistor 53 is electrically connected to one of the source and the drain of the transistor 54. Note that a capacitor which is electrically connected to the gate of the transistor 53 may be provided.

The other electrode (cathode) of the photoelectric conversion element 50 is electrically connected to the wiring 72. A gate of the transistor 51 is electrically connected to the wiring 75. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 79. A gate of the transistor 52 is electrically connected to the wiring 76. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 73. The other of the source and the drain of the transistor 54 is electrically connected to the wiring 71. A gate of the transistor 54 is electrically connected to the wiring 78. The wiring 72 is electrically connected to one terminal of the power supply 56, and the other terminal of the power supply 56 is electrically connected to the wiring 77.

Here, the wiring 71 can function as an output line for outputting a signal from the pixel. The wiring 73, the wiring 77, and the wiring 79 can function as power supply lines. For example, the wiring 73 and the wiring 77 can function as a low potential power supply line, and the wiring 79 can function as a high potential power supply line. The wiring 75, the wiring 76, and the wiring 78 can function as signal lines for controlling on / off of each transistor.

For the photoelectric conversion element 50, it is preferable to use a photoelectric conversion element that produces an avalanche multiplication effect in order to increase the light detection sensitivity at low illuminance. In order to produce the avalanche multiplication effect, a relatively high potential HVDD is required. Therefore, the power source 56 has a function of supplying the potential HVDD, and the potential HVDD is supplied to the other electrode of the photoelectric conversion element 50 through the wiring 72. The photoelectric conversion element 50 can also be used by applying a potential that does not produce an avalanche multiplication effect.

The transistor 51 can have a function of transferring the potential of the charge storage unit (NR) that changes in accordance with the output of the photoelectric conversion element 50 to the charge detection unit (ND). The transistor 52 can have a function of initializing the potentials of the charge storage portion (NR) and the charge detection portion (ND). The transistor 53 can have a function of outputting a signal corresponding to the potential of the charge detection portion (ND). The transistor 54 can have a function of selecting a pixel from which a signal is read.

When a high voltage is applied to the photoelectric conversion element 50, it is necessary to use a high breakdown voltage transistor that can withstand the high voltage as a transistor connected to the photoelectric conversion element 50. For example, an OS transistor or the like can be used as the high voltage transistor. Specifically, OS transistors are preferably used as the transistor 51 and the transistor 52.

The transistors 51 and 52 are desired to have excellent switching characteristics, but the transistor 53 is preferably a transistor with high on-state current because it is desired to have excellent amplification characteristics. Therefore, it is preferable to apply a transistor using silicon as an active layer or an active region (hereinafter, Si transistor) as the transistor 53 and the transistor 54.

With the above-described structures of the transistors 51 to 54, an imaging device with high light detection sensitivity at low illuminance and capable of outputting a signal with little noise can be manufactured. In addition, since the light detection sensitivity is high, the light capture time can be shortened and imaging can be performed at high speed.

Note that the transistor is not limited to the above structure, and an OS transistor may be applied to the transistor 53 and the transistor 54. Alternatively, Si transistors may be applied to the transistors 51 and 52. In any case, the imaging operation of the pixel circuit is possible.

Next, operation of the pixel is described with reference to a timing chart in FIG. Note that in an example of operation described below, the wiring 76 connected to the gate of the transistor 52 is supplied with HVDD as “H” and GND as “L”. The wiring 75 connected to the gate of the transistor 51 and the wiring 78 connected to the gate of the transistor 54 are supplied with VDD as “H” and GND as “L”. Further, the potential of VDD is supplied to the wiring 79 connected to the source of the transistor 53. Note that a potential other than the above may be supplied to each wiring.

At time T1, the wiring 76 is set to “H”, the wiring 75 is set to “H”, and the potentials of the charge storage portion (NR) and the charge detection portion (ND) are set to the reset potential (GND) (reset operation). Note that the potential VDD may be supplied to the wiring 76 as “H” during the reset operation.

By setting the wiring 76 to “L” and the wiring 75 to “L” at time T2, the potential of the charge storage portion (NR) changes (accumulation operation). The potential of the charge storage unit (NR) changes from GND to HVDD at the maximum according to the intensity of light incident on the photoelectric conversion element 50.

At time T3, the wiring 75 is set to “H”, and the charge in the charge storage portion (NR) is transferred to the charge detection portion (ND) (transfer operation).

At time T4, the wiring 76 is set to “L” and the wiring 75 is set to “L”, and the transfer operation is finished. At this point, the potential of the charge detection unit (ND) is determined.

In a period from time T5 to T6, the wiring 76 is set to “L”, the wiring 75 is set to “L”, and the wiring 78 is set to “H”, and a signal corresponding to the potential of the charge detection portion (ND) is output to the wiring 71. That is, an output signal corresponding to the intensity of light incident on the photoelectric conversion element 50 in the accumulation operation can be obtained.

FIG. 13A illustrates an example of a pixel structure of an imaging device including the pixel circuit described above. The imaging device can include a layer 61, a layer 62, and a layer 63, each having a region that overlaps with each other.

The layer 61 has the configuration of the photoelectric conversion element 50. The photoelectric conversion element 50 includes an electrode 65 corresponding to a pixel electrode, a photoelectric conversion unit 66, and an electrode 67 corresponding to a common electrode.

The electrode 65 is preferably a low-resistance metal layer. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

For the electrode 67, a conductive layer having a high light-transmitting property with respect to visible light is preferably used. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the electrode 67 may be omitted.

For the photoelectric conversion unit 66, for example, a pn junction photodiode using a selenium-based material as a photoelectric conversion layer can be used. It is preferable to use a selenium-based material that is a p-type semiconductor for the layer 66a and a gallium oxide that is an n-type semiconductor for the layer 66b.

A photoelectric conversion element using a selenium-based material has a high external quantum efficiency with respect to visible light. In the photoelectric conversion element, by using the avalanche multiplication effect, a highly sensitive sensor with a large amplification of electrons with respect to the amount of incident light can be obtained. In addition, since the selenium-based material has a high light absorption coefficient, it has production advantages such that the photoelectric conversion layer can be formed as a thin film. A thin film of a selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

Examples of the selenium-based material include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, selenium compound (CIS), or copper, indium, gallium, selenium compound (CIGS), etc. Can be used.

The n-type semiconductor is preferably formed using a material having a wide band gap and a light-transmitting property with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. These materials also have a function as a hole injection blocking layer, and can reduce the dark current.

Note that the layer 61 is not limited to the above structure, and a pn junction photodiode using one of a p-type silicon semiconductor and an n-type silicon semiconductor as the layer 66a and the other of the p-type silicon semiconductor and the n-type silicon semiconductor as the layer 66b. It may be. Alternatively, a pin junction photodiode in which an i-type silicon semiconductor layer is provided between the layer 66a and the layer 66b may be used.

The pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. At this time, it is preferable that the layer 61 and the layer 62 are electrically joined using a bonding process. Further, the pin junction photodiode can be formed using a thin film such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon.

The layer 62 can be, for example, a layer including an OS transistor (the transistor 51 and the transistor 52). In the circuit configuration of the pixel shown in FIG. 12A, the potential of the charge detection portion (ND) is small when the intensity of light incident on the photoelectric conversion element 50 is small. Since the OS transistor has an extremely low off-state current, a current corresponding to the gate potential can be accurately output even when the gate potential is extremely small. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be expanded.

Further, due to the low off-state current characteristics of the transistor 51 and the transistor 52, the period in which charges can be held in the charge detection portion (ND) and the charge accumulation portion (NR) can be extremely long. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method.

The layer 63 can be a supporting substrate or a layer having a Si transistor (transistor 53, transistor 54). The Si transistor can have a structure having an active region on a single crystal silicon substrate and a crystalline silicon active layer on an insulating surface. Note that in the case where a single crystal silicon substrate is used for the layer 63, a pn junction photodiode or a pin junction photodiode may be formed over the single crystal silicon substrate. In this case, the layer 61 can be omitted.

FIG. 13B is a block diagram illustrating a circuit configuration of the imaging device of one embodiment of the present invention. The imaging apparatus includes a pixel array 81 having pixels 80 arranged in a matrix, a circuit 82 (row driver) having a function of selecting a row of the pixel array 81, and a correlation double with respect to an output signal of the pixel 80. A circuit 83 (CDS circuit) for performing sampling processing, a circuit 84 (A / D conversion circuit or the like) having a function of converting analog data output from the circuit 83 into digital data, and data converted by the circuit 84 And a circuit 85 (column driver) having a function of selecting and reading out. Note that the circuit 83 may be omitted.

For example, the elements of the pixel array 81 excluding the photoelectric conversion element can be provided in the layer 62 illustrated in FIG. Elements of the circuits 82 to 85 can be provided in the layer 63. These circuits can be constituted by CMOS circuits using silicon transistors.

With such a structure, a transistor suitable for each circuit can be used, and the area of the imaging device can be reduced.

14A, 14B, and 14C are diagrams illustrating a specific structure of the imaging device illustrated in FIG. FIG. 14A is a cross-sectional view illustrating the channel length direction of the transistors 51, 52, 53, and 54. 14B is a cross-sectional view taken along alternate long and short dash line A1-A2, and shows a cross section of the transistor 52 in the channel width direction. 14C is a cross-sectional view taken along dashed-dotted line B1-B2, and shows a cross section of the transistor 53 in the channel width direction.

The imaging device can be a stack of layers 61 to 63. The layer 61 can include a partition 92 in addition to the photoelectric conversion element 50 having a selenium layer. The partition wall 92 is provided so as to cover the step of the electrode 65. The selenium layer used for the photoelectric conversion element 50 has a high resistance and can be configured not to be separated between pixels.

The layer 62 is provided with transistors 51 and 52 which are OS transistors. Although the transistors 51 and 52 both have a structure having the back gate 91, any of the transistors 51 and 52 may have a back gate. As shown in FIG. 14B, the back gate 91 may be electrically connected to a front gate of a transistor provided to face the back gate 91. Alternatively, the back gate 91 may be configured to be able to supply a fixed potential different from that of the front gate.

14A illustrates a self-aligned top gate transistor as the OS transistor, but may be a non-self-aligned transistor as illustrated in FIG. 15A.

In the layer 63, a transistor 53 and a transistor 54 which are Si transistors are provided. 14A illustrates a structure in which the Si transistor includes a fin-type semiconductor layer provided on the silicon substrate 200. However, as illustrated in FIG. 15B, a planar substrate having an active region in the silicon substrate 201 is illustrated. It may be a mold. Alternatively, as illustrated in FIG. 12C, a transistor including a silicon thin film semiconductor layer 210 may be used. The semiconductor layer 210 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 220 on the silicon substrate 202. Alternatively, it may be polycrystalline silicon formed on an insulating surface such as a glass substrate. In addition, the layer 63 can be provided with a circuit for driving a pixel.

An insulating layer 93 having a function of preventing hydrogen diffusion is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided in the vicinity of the active regions of the transistors 53 and 54 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is an active layer of the transistors 51 and 52 is one of the factors that generate carriers in the oxide semiconductor layer.

The reliability of the transistors 53 and 54 can be improved by confining hydrogen in one layer by the insulating layer 93. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistors 51 and 52 can be improved.

As the insulating layer 93, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

FIG. 16A is a cross-sectional view illustrating an example in which a color filter or the like is added to the imaging device of one embodiment of the present invention. In the cross-sectional view, a part of a region having a pixel circuit for three pixels is shown. An insulating layer 300 is formed on the layer 61 where the photoelectric conversion element 50 is formed. The insulating layer 300 can be formed using a silicon oxide film having high light-transmitting property with respect to visible light. A silicon nitride film may be stacked as a passivation film. Further, a dielectric film such as hafnium oxide may be laminated as the antireflection film.

A light shielding layer 310 may be formed on the insulating layer 300. The light shielding layer 310 has a function of preventing color mixing of light passing through the upper color filter. For the light-blocking layer 310, a metal layer such as aluminum or tungsten can be used. Further, the metal layer and a dielectric film having a function as an antireflection film may be stacked.

An organic resin layer 320 can be provided as a planarization film over the insulating layer 300 and the light shielding layer 310. A color filter 330 (color filter 330a, color filter 330b, color filter 330c) is formed for each pixel. For example, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 330a, 330b, and 330c. Thus, a color image can be obtained.

An insulating layer 360 having a light-transmitting property with respect to visible light or the like can be provided over the color filter 330.

In addition, as illustrated in FIG. 16B, an optical conversion layer 350 may be used instead of the color filter 330. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.

For example, if a filter that blocks light having a wavelength shorter than or equal to that of visible light is used for the optical conversion layer 350, an infrared imaging device can be obtained. If a filter that blocks light having a wavelength of near infrared or shorter is used for the optical conversion layer 350, a far infrared imaging device can be obtained. If a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 350, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 350, an imaging device that can be used for an X-ray imaging device or the like and obtain an image that visualizes the intensity of radiation can be obtained. When radiation such as X-rays transmitted through the subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion element 50. Further, the imaging device having the configuration may be used for a radiation detector or the like.

A scintillator contains a substance that emits visible light or ultraviolet light by absorbing energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. What was disperse | distributed to resin or ceramics can be used.

Note that the photoelectric conversion element 50 using a selenium-based material can directly convert radiation such as X-rays into electric charges, and thus can be configured to eliminate a scintillator.

Further, as illustrated in FIG. 16C, a microlens array 340 may be provided over the color filter 330a, the color filter 330b, and the color filter 330c. Light passing through the individual lenses included in the microlens array 340 passes through the color filter directly below and is irradiated onto the photoelectric conversion element 50. Alternatively, the microlens array 340 may be provided over the optical conversion layer 350 illustrated in FIG.

Hereinafter, an example of a package and a camera module containing an image sensor chip will be described. The configuration of the imaging device can be used for the image sensor chip.

FIG. 17A1 is an external perspective view of the upper surface side of the package containing the image sensor chip. The package includes a package substrate 410 for fixing the image sensor chip 450, a cover glass 420, and an adhesive 430 for bonding the two.

FIG. 17A2 is an external perspective view of the lower surface side of the package. The bottom surface of the package has a BGA (Ball Grid Array) configuration with solder balls as bumps 440. In addition, not only BGA but LGA (Land grid array), PGA (Pin Grid Array), etc. may be sufficient.

FIG. 17A3 is a perspective view of the package shown with a part of the cover glass 420 and the adhesive 430 omitted. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected through a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.

FIG. 17B1 is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 that fixes the image sensor chip 451, a lens cover 421, a lens 435, and the like. Further, an IC chip 490 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package). Yes.

FIG. 17B2 is an external perspective view of the lower surface side of the camera module. The package substrate 411 has a QFN (Quad Flat No-Lead Package) configuration in which mounting lands 441 are provided on a lower surface and side surfaces. Note that this configuration is an example, and a QFP (Quad Flat Package), the above-described BGA, or the like may be used.

FIG. 17B3 is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by wires 471.

By mounting the image sensor chip in a package having the above-described form, mounting on a printed board or the like is facilitated, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
Electronic devices that can use the imaging device according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, a portable game machine, and a portable data terminal , Digital book terminals, video cameras, digital still cameras and other cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices Automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 18A illustrates a monitoring camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the monitoring camera. The surveillance camera is an idiomatic name and does not limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 18B illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the video camera.

FIG. 18C illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the digital camera.

FIG. 18D illustrates a wristwatch-type information terminal, which includes a housing 931, a display portion 932, a wristband 933, operation buttons 935, a crown 936, a camera 939, and the like. The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the information terminal.

FIG. 18E illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. All operations such as making a call or inputting characters can be performed by touching the display portion 982 with a finger, a stylus, or the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the mobile phone.

FIG. 18F illustrates a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by a touch panel function of the display portion 912. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the portable data terminal.

This embodiment can be combined with any of the other embodiments as appropriate.

C11 capacitive element C21 capacitive element C22 capacitive element Tr11 transistor Tr12 transistor Tr21 transistor Tr22 transistor Tr23 transistor Tr24 transistor Tr25 transistor Tr26 transistor Tr27 transistor Tr28 transistor 10 imaging device 11 imaging unit 12 control unit 13 calculation unit 14 image processing unit 15 temperature sensor 16 storage Unit 17 Storage unit 18 Interface 19 Neural network 20 External device 21 Control unit 22 Image processing unit 23 Storage unit 24 Neural network 30 Image 31 Bright point 31b Region 32 Bright point 32b Region 35 Image 36 Image 37 Image 38 Image 39 Image 40a Input information 40b Input information 41 Input layer 42 Input layer 43 Intermediate layer 44 Output layer 50 Photoelectric conversion element 51 Transistor 5 2 Transistor 53 Transistor 54 Transistor 56 Power supply 61 Layer 62 Layer 63 Layer 65 Electrode 66 Photoelectric converter 66a Layer 66b Layer 67 Electrode 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 80 Pixel 81 Pixel array 82 Circuit 83 Circuit 84 Circuit 85 Circuit 91 Back gate 92 Bulkhead 93 Insulating layer 100 Semiconductor device 110 Memory circuit 120 Reference memory circuit 130 Circuit 140 Circuit 150 Current source circuit 200 Silicon substrate 201 Silicon substrate 202 Silicon substrate 210 Semiconductor layer 220 Insulating layer 300 Insulating layer 310 Light-shielding layer 320 Organic resin layer 330 Color filter 330a Color filter 330b Color filter 330c Color filter 340 Microlens array 350 Optical conversion layer 360 Insulating layer 410 Package Plate 411 Package substrate 420 Cover glass 421 Lens cover 430 Adhesive 435 Lens 440 Bump 441 Land 450 Image sensor chip 451 Image sensor chip 460 Electrode pad 461 Electrode pad 470 Wire 471 Wire 490 IC chip 911 Housing 912 Display unit 919 Camera 931 Housing Body 932 Display portion 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support portion 961 Case 962 Shutter button 963 Microphone 965 Lens 967 Light emitting portion 971 Case 972 Case 973 Display portion 974 Operation key 975 Lens 976 Connection Unit 981 housing 982 display unit 983 operation button 984 external connection port 985 speaker 986 microphone 987 camera

Claims (7)

An imaging apparatus having an imaging unit, a control unit, a temperature sensor, and an image processing unit,
The imaging unit has a function of acquiring first image data,
The control unit has a function of controlling an exposure time in the imaging unit,
The temperature sensor has a function of acquiring the temperature of the imaging unit,
The image processing unit has a neural network,
The neural network has a function of generating second image data,
The image processing unit has a function of subtracting the second image data from the first image data to generate third image data. In claim 1,
The neural network has a function of generating the second image data by using the exposure time and the temperature when the first image data is acquired as input data. In claim 1 or 2,
The imaging device has an interface for connecting to an external device,
An imaging apparatus using a value input from the external device as a weighting coefficient of the neural network. In any one of Claims 1 thru | or 3,
The imaging unit has a function of acquiring fourth image data;
The image processing unit has a function of correcting the weighting coefficient of the neural network using the exposure time when the fourth image data is acquired and the temperature of the imaging unit as input data, and using the fourth image data as teacher data. An imaging apparatus having In any one of Claims 1 thru | or 4,
The neural network has a product-sum operation element,
The product-sum operation element includes a memory circuit including a first transistor, a second transistor, and a capacitor.
One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor;
One of a source and a drain of the first transistor is electrically connected to the capacitor;
The first transistor is an imaging device having a metal oxide in a channel formation region. In any one of Claims 1 thru | or 5,
The pixels of the imaging unit are
A third transistor having a metal oxide in a channel formation region;
A photoelectric conversion element having selenium or a selenium compound;
An imaging apparatus having An electronic apparatus comprising the imaging device according to any one of claims 1 to 6 and a display device.

Images