JP2017168969A - Counter circuit, time measurement circuit, and temperature sensor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for integrating a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources.SOLUTION: A counter circuit 8 comprises: JK type flip flops FF in a plurality of stages; a plurality of first switches SW1 and a plurality of second switches SW2. The first switches SW1 are respectively configured such that a clock signal is input to a clock terminal in a synchronous mode, and that an output of the JK type flip flop FF in a previous stage is input to the clock terminal in an asynchronous mode. The second switches SW2 are configured such that a carry signal S2 is input to an input terminal in the synchronous mode, and that a high signal is input to the input terminal in the asynchronous mode.SELECTED DRAWING: Figure 6

Description

  The technology disclosed in this specification relates to a counter circuit, a time measurement circuit, and a temperature sensor circuit.

  A time measurement circuit that measures time using a clock signal is known. Such a time measuring circuit is required in various situations. For example, Patent Document 1 discloses a temperature sensor circuit including this type of time measurement circuit. In the temperature sensor circuit of Patent Document 1, the time measurement circuit is used to measure the delay time of a delay signal having temperature dependent characteristics.

  In this type of time measurement circuit, it is desired to improve time resolution. Patent Document 2 discloses a time measuring circuit that uses a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency. The time measurement circuit is configured to switch from the low-speed clock signal to the high-speed clock signal when the time from the start of measurement of the measurement target time reaches a set value. Thereby, since this time measurement circuit can measure using a high-speed clock signal in a period close to the end timing of the measurement target time, the measurement target time can be measured with high resolution.

JP 2013-185985 A JP-A-5-34474

  In time measurement using a clock signal, a counter circuit having a plurality of stages of flip-flops is used to measure the number of clocks. As such a counter circuit, a synchronous counter circuit and an asynchronous counter circuit are known. The synchronous counter circuit is good at accurate measurement using a low-speed clock signal. However, the synchronous counter circuit has a problem that a delay between each bit is large and it is difficult to measure accurately when a high-speed clock signal is used. On the other hand, the asynchronous counter circuit is good at measurement using a high-speed clock signal because the delay between each bit is small. However, the asynchronous counter circuit has a problem that accurate measurement is difficult particularly in a subsequent flip-flop because a delay between bits accumulates.

  Therefore, in order to achieve high-precision time measurement using low-speed clock signals and high-speed clock signals, a synchronous counter circuit is prepared for low-speed clock signals, and an asynchronous counter circuit is prepared for high-speed clock signals. There is a need to. However, if a synchronous counter circuit and an asynchronous counter circuit are prepared separately, many circuit resources are required.

  In the above, the time measurement circuit using the low-speed clock signal and the high-speed clock signal is illustrated, and the scene where both the synchronous counter circuit and the asynchronous counter circuit are necessary has been described. However, the present invention is not limited to the time measuring circuit, and various circuits require both a synchronous counter circuit and an asynchronous counter circuit. The present specification provides a technique for integrating a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources.

  One embodiment of the counter circuit disclosed in this specification includes a plurality of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK flip-flop, a T flip-flop, or a D flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the input terminal. The plurality of first switches and the plurality of second switches form a wiring pattern so that a plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and in the asynchronous mode, the plurality of stages of flip-flops are an asynchronous counter. The wiring pattern is configured so that The counter circuit of this embodiment can switch signals input to the clock terminal and the input terminal by switching the first switch and the second switch. Thereby, the counter circuit of this embodiment can be switched to a synchronous counter circuit and an asynchronous counter circuit, and a synchronous counter circuit and an asynchronous counter circuit can be integrated. When the flip-flop is a JK flip-flop or a T-type flip-flop, the first switch is configured to input a clock signal to the clock terminal in the synchronous mode, and the output of the preceding flip-flop to the clock terminal in the asynchronous mode. Is configured to input. The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the low-order bit flip-flops are Hi, and when all are Hi, it is Hi, and the others are Lo. The counter circuit of this embodiment can be switched between a synchronous counter circuit and an asynchronous counter circuit by switching the first switch and the second switch. The counter circuit of this embodiment can integrate a synchronous counter circuit and an asynchronous counter circuit using JK flip-flops or T flip-flops while suppressing an increase in circuit resources.

  One embodiment of a time measurement circuit disclosed in the present specification includes an oscillation circuit and a counter circuit. The oscillation circuit generates a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency. The counter circuit measures the target time based on the low-speed clock signal or the high-speed clock signal output from the oscillation circuit. For example, the counter circuit may measure a time corresponding to the edge of the pulse signal. The counter circuit may measure the target time by switching between the low-speed clock signal and the high-speed clock signal during measurement of the target time. Typically, the counter circuit may start measuring the target time using the low-speed clock signal, and measure the remaining target time by switching from the low-speed clock signal to the high-speed clock signal during the measurement. The counter circuit includes a plurality of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK flip-flop, a T flip-flop, or a D flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the input terminal. The plurality of first switches and the plurality of second switches form a wiring pattern so that a plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and in the asynchronous mode, the plurality of stages of flip-flops are an asynchronous counter. The wiring pattern is configured so that Since the time measuring circuit of this embodiment can be switched between a synchronous counter circuit and an asynchronous counter circuit by switching the first switch and the second switch, the time can be accurately measured while suppressing an increase in circuit resources. It can be measured. When the flip-flop is a JK flip-flop or a T-type flip-flop, the first flip-flop is configured so that a low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode. Configured to input. The first switch is configured to input a low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the output of the preceding flip-flop to the clock terminal in the asynchronous mode. The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the low-order bit flip-flops are Hi, and when all are Hi, it is Hi, and the others are Lo. The counter circuit of the time measuring circuit of this embodiment can be switched between a synchronous counter circuit using a JK flip-flop or a T flip-flop and an asynchronous counter circuit by switching the first switch and the second switch. it can. The counter circuit of the time measuring circuit of this embodiment can integrate a synchronous counter circuit and an asynchronous counter circuit using JK flip-flops or T flip-flops while suppressing an increase in circuit resources. Therefore, the time measuring circuit of this embodiment can measure time with high accuracy while suppressing an increase in circuit resources.

  One embodiment of the temperature sensor circuit disclosed in this specification includes an oscillation circuit, a delay circuit, and a counter circuit. The oscillation circuit generates a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency. The delay circuit generates a delay signal having a delay time having temperature dependent characteristics. The counter circuit measures the delay time of the delay signal based on the low-speed clock signal or the high-speed clock signal output from the oscillation circuit. For example, the counter circuit may measure the delay time by switching between the low-speed clock signal and the high-speed clock signal during the measurement of the delay time. Typically, the counter circuit may start the measurement of the delay time using the low-speed clock signal, and measure the remaining delay time by switching from the low-speed clock signal to the high-speed clock signal during the measurement. The counter circuit includes a plurality of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK flip-flop, a T flip-flop, or a D flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and is configured to switch a signal input to the input terminal. The plurality of first switches and the plurality of second switches form a wiring pattern so that a plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and in the asynchronous mode, the plurality of stages of flip-flops are an asynchronous counter. The wiring pattern is configured so that Since the temperature sensor circuit of this embodiment can be switched between a synchronous counter circuit and an asynchronous counter circuit by switching the first switch and the second switch, the temperature can be accurately controlled while suppressing an increase in circuit resources. Can be measured. When the flip-flop is a JK flip-flop or a T-type flip-flop, the first flip-flop is configured so that a low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode. Configured to input. The first switch is configured to input a low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the output of the preceding flip-flop to the clock terminal in the asynchronous mode. The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the low-order bit flip-flops are Hi, and when all are Hi, it is Hi, and the others are Lo. The counter circuit of the temperature sensor circuit of this embodiment can be switched between a synchronous counter circuit using a JK flip-flop or a T flip-flop and an asynchronous counter circuit by switching the first switch and the second switch. it can. The counter circuit of the temperature sensor circuit of this embodiment can integrate a synchronous counter circuit using a JK flip-flop or a T flip-flop and an asynchronous counter circuit while suppressing the consumption of circuit increase. Therefore, the temperature sensor circuit of this embodiment can measure temperature with high accuracy while suppressing an increase in circuit resources.

It is a block diagram which shows the outline of a temperature sensor circuit. It is a block diagram which shows the outline of an oscillation circuit. It is a circuit diagram which shows the outline of the ring oscillator contained in an oscillation circuit. It is a circuit diagram which shows the outline of the inverter chain contained in a delay circuit. It is a circuit diagram of the CMOS inverter which comprises a ring oscillator and an inverter chain. It is a circuit diagram which shows the outline of a counter circuit, and shows a mode that a 1st switch and a 2nd switch switch in synchronous mode (A) and asynchronous mode (B). It is a timing chart which shows the mode of operation of a temperature sensor circuit. It is a figure which shows the outline of a switching signal generation circuit. It is a circuit diagram of a bootstrap type CMOS inverter constituting a ring oscillator. It is a circuit diagram which shows the outline of the counter circuit of a modification, and shows a mode that a 1st switch and a 2nd switch switch in synchronous mode (A) and asynchronous mode (B). It is a circuit diagram which shows the outline of the counter circuit of a modification, and shows a mode that a 1st switch and a 2nd switch switch in synchronous mode (A) and asynchronous mode (B).

  As shown in FIG. 1, the temperature sensor circuit 1 is an integrated circuit formed on a single chip, and includes an oscillation circuit 2, a pulse generation circuit 4, a delay circuit 6, a counter circuit 8, and a switching signal generation circuit 10.

  The oscillation circuit 2 is configured to generate a low-speed clock signal CLK1 having a relatively low frequency and a high-speed clock signal CLK2 having a relatively high frequency. These clock signals CLK1 and CLK2 are rectangular waves with a duty ratio of 50%, for example. The pulse generation circuit 4 is configured to generate a pulse signal V1. The pulse generation circuit 4 may be configured to generate the pulse signal V1 using the clock signals CLK1 and CLK2 generated by the oscillation circuit 2. For example, the pulse generation circuit 4 may be configured to generate the pulse signal V1 by lowering the frequency of the low-speed clock signal CLK1 using a frequency dividing circuit. The delay circuit 6 is configured to generate a delayed pulse signal V2 obtained by delaying the pulse signal V1. The counter circuit 8 is configured to measure the time difference between the pulse signal V1 and the delay pulse signal V2 (corresponding to the delay time of the delay pulse signal V2) based on the number of clocks of the low-speed clock signal CLK1 and the high-speed clock signal CLK2. Yes. As will be described later, the counter circuit 8 uses the clock signal selected from the low-speed clock signal CLK1 and the high-speed clock signal CLK2, and uses the time difference between the pulse signal V1 and the delay pulse signal V2 (the delay time of the delay pulse signal V2). Equivalent). The counter circuit 8 is configured to output the measured number of clocks as digital temperature information Dout. The switching signal generation circuit 10 is configured to generate the switching signal S1 based on the number of clocks measured by the counter circuit 8.

  As shown in FIG. 2, the oscillation circuit 2 includes a low-speed clock signal generation circuit 2A and a high-speed clock signal generation circuit 2B. The low-speed clock signal generation circuit 2A is configured to generate a low-speed clock signal CLK1. The high-speed clock signal generation circuit 2B is configured to generate a high-speed clock signal CLK2. The oscillation circuit 2 selects either the low speed clock signal generation circuit 2A or the high speed clock signal generation circuit 2B based on the switching signal S1 from the switching signal generation circuit 10 and outputs the clock signals CLK1 and CLK2. It is configured.

  As shown in FIG. 3, each of the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B of the oscillation circuit 2 is configured by a ring oscillator in which a plurality of first inverters INV1 are connected in a ring shape. . The number of stages of the first inverter INV1 of each of the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B is different, whereby the frequencies of the clock signals CLK1 and CLK2 to be oscillated are different. In this example, the number of stages of the low-speed clock signal generation circuit 2A is larger than the number of stages of the high-speed clock signal generation circuit 2B. For example, the low-speed clock signal generation circuit 2A includes a first inverter INV1 having 15 stages. The high-speed clock signal generation circuit 2B has a three-stage first inverter INV1.

  As shown in FIG. 4, the delay circuit 6 includes an inverter chain in which a plurality of second inverters INV2 are connected in series. For example, the inverter chain includes a second inverter INV2 having 50 stages.

  As shown in FIG. 5, the first inverter INV1 of the ring oscillator and the second inverter INV2 of the inverter chain are both connected in series between the positive power supply line (Vdd line) and the negative power supply line (Vss). A CMOS having one transistor Tr1 and a second transistor Tr2 is provided. The first transistor Tr1 is a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the Vdd line, and the drain is connected to the drain of the second transistor Tr2. The second transistor Tr2 is an n-type MOSFET, the drain is connected to the drain of the first transistor Tr1, and the source is connected to the negative power supply line Vss. The connection point between the first transistor Tr1 and the second transistor Tr2 is connected to the gate of the transistor constituting the next stage CMOS inverter.

  The temperature sensor circuit 1 is configured such that the channel length modulation effect by the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator is different from the channel length modulation effect by the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. It is characterized by being. Specifically, when the gate width is constant, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are equal to the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Shorter than that. In this example, the gate length of the first transistor Tr1 of the first inverter INV1 is shorter than the gate length of the first transistor Tr1 of the second inverter INV2, and the gate length of the second transistor Tr2 of the first inverter INV1 is The gate length of the second transistor Tr2 of the second inverter INV2 is shorter. Instead of this example, only the gate length of either the first transistor Tr1 or the second transistor Tr2 of the first inverter INV1 may be short.

  Usually, the transistors Tr1 and Tr2 have a lower operating current at a higher temperature than a lower temperature, and the operating speed is reduced. For this reason, in the first inverter INV1 of the ring oscillator, the operation speed decreases at a temperature higher than the low temperature, so that the period of the oscillating clock signals CLK1 and CLK2 increases (frequency decreases). That is, the period of the clock signals CLK1 and CLK2 has a positive temperature dependency characteristic that increases with a substantially linear function with respect to the temperature. Also, in the second inverter INV2 of the inverter chain, the operation speed decreases at a temperature higher than the low temperature, so that the delay time of the delay pulse signal V2 increases. That is, the delay time of the delayed pulse signal V2 also has a positive temperature dependence characteristic that increases with a substantially linear function with respect to temperature. Here, the channel length modulation effect refers to the amount of current increase in the saturation region of the IV characteristics. For this reason, that the channel length modulation effect is different means that the amount of current increase in the saturation region of the IV characteristic is different. In this embodiment, the gate lengths of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are shorter than the gate lengths of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Regarding the current increase amount at, the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator are larger than the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. For this reason, when the temperature changes from low to high, the amount of current change in the transistors Tr1 and Tr2 of the ring oscillator is relatively small, and the amount of current change in the transistors Tr1 and Tr2 of the inverter chain is relatively large. As a result, when the temperature changes from low to high, the amount of decrease in the operating speed of the ring oscillator is relatively small, and the amount of decrease in the operating speed of the inverter chain is relatively large.

  In the temperature sensor circuit 1, the channel length modulation effect of the transistors Tr1 and Tr2 constituting the first inverter INV1 of the ring oscillator is different from the channel length modulation effect of the transistors Tr1 and Tr2 constituting the second inverter INV2 of the inverter chain. Therefore, in this embodiment, when the temperature is changed from low temperature to high temperature, the amount of decrease in the operating speed of the ring oscillator is different from the amount of decrease in the operating speed of the inverter chain, and the clock signals CLK1, CLK2 generated by the ring oscillator are different. Is different from the temperature dependency characteristic of the delayed pulse signal V2 generated by the inverter chain. As described above, the period of the clock signals CLK1 and CLK2 has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to the temperature. The delay time of the delayed pulse signal V2 also has a positive temperature dependence characteristic that increases with a substantially linear function with respect to the temperature. Further, the rate of change of the delay time of the delay pulse signal V2 with respect to the temperature (ratio of the delay time at any temperature when the delay time of the reference temperature is “1”) is the rate of change of the cycle of the clock signals CLK1 and CLK2 with respect to the temperature ( (The ratio of the period at an arbitrary temperature when the period of the reference temperature is “1”), and the temperature-dependent characteristics of both are different.

  As described above, if the temperature dependency characteristics of the clock signals CLK1 and CLK2 generated by the ring oscillator are different from the temperature dependency characteristic of the delay pulse signal V2 generated by the inverter chain, the number of clocks measured by the counter circuit 8 is different. Fluctuates with temperature. In the temperature sensor circuit 1, the temperature information Dout can be obtained by utilizing the difference between the temperature dependency characteristics of the clock signals CLK1 and CLK2 and the temperature dependency characteristic of the delayed pulse signal V2.

  FIG. 6 shows a circuit diagram of the counter circuit 8. In FIG. 6, the 4-bit counter circuit 8 is illustrated, but the number of bits is not limited to this example. The counter circuit 8 is configured to be able to dynamically switch between the synchronous mode shown in (A) and the asynchronous mode shown in (B). The counter circuit 8 includes a plurality of stages of JK flip-flops FF, a plurality of first switches SW1, a plurality of second switches SW2, and a plurality of AND circuits 9. The combination of the first switch SW1 and the second switch SW2 is provided corresponding to each of the second and subsequent JK flip-flops FF. The AND circuit 9 is provided corresponding to each of the third and subsequent JK flip-flops FF.

  The first-stage JK flip-flop FF has clock signals CLK1 and CLK2 input to its clock terminal (CLK), Hi is input to its input terminals (both J input and K input), and its output terminal (Q). The first switch SW1 and the second switch SW2 of the JK flip-flop FF at the next stage are connected. Further, the first-stage JK flip-flop FF is configured such that the low-speed clock signal CLK1 is input to the clock terminal (CLK) in the synchronous mode (A), and the high-speed clock signal (CLK) in the asynchronous mode (B). The clock signal CLK2 is input. In the JK flip-flops FF in the second and subsequent stages, the first switch SW1 is connected to its clock terminal (CLK), the second switch SW2 is connected to its input terminal (both J input and K input), and its output The first switch SW1 of the next stage is connected to the terminal (Q). The AND circuit 9 is configured to generate a carry signal S2 in which the output is Hi when the outputs of the output terminals (Q) of the lower bits are all Hi, and the others are Lo.

  The first switch SW1 and the second switch SW2 are configured to switch the connection destination in synchronization with the synchronous mode (A) and the asynchronous mode (B) in synchronization with the switching signal S1 from the switching signal generation circuit 10. Has been. The first switch SW1 is configured such that the low-speed clock signal CLK1 is input to the clock terminal (CLK) of the JK type flip-flop FF in the synchronous mode (A), and the first switch SW1 of the JK type flip-flop FF in the asynchronous mode (B). The output of the output terminal (Q) of the preceding JK flip-flop FF is input to the clock terminal (CLK). In the synchronous mode (A), the second switch SW2 is connected to the input terminal of the JK-type flip-flop FF and the output terminal of the AND circuit 9 (however, the second-stage JK-type flip-flop FF is the preceding JK-type flip-flop FF). Output terminal (Q)) is connected, and Hi is input to the input terminal of the JK flip-flop FF in the asynchronous mode (B). As described above, the counter circuit 8 operates as a synchronous counter circuit in the synchronous mode (A) by switching between the first switch SW1 and the second switch SW2, and in the asynchronous mode (B), the asynchronous counter. It can operate as a circuit.

  FIG. 7 shows how the temperature sensor circuit 1 measures the delay time. In this example, the time from timing T1 to timing T2 corresponds to the delay time. Timing T1 corresponds to the rising edge of the pulse signal V1, and timing T2 corresponds to the rising edge of the delayed pulse signal V2 (see FIGS. 1 and 4).

  The temperature sensor circuit 1 performs temporary measurement and actual measurement. The provisional measurement is characterized in that the delay time is measured using only the low-speed clock signal CLK1. In actual measurement, the delay time is measured using the low-speed clock signal CLK1 and the high-speed clock signal CLK2. In actual measurement, the timing of switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 is when the time from the start of the delay time measurement reaches a set value. Specifically, the timing of switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 is when the number of clocks of the low-speed clock signal CLK1 from the start of the delay time measurement reaches a set number. This set number is calculated by subtracting a predetermined number of clocks from the number of clocks of the low-speed clock signal CLK1 measured in the provisional measurement.

  The timing for switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 is controlled by the switching signal generation circuit 10 (see FIG. 1). As shown in FIG. 8, the switching signal generation circuit 10 includes a subtraction circuit 11, a register 13, a comparison circuit 15, a measurement count recording circuit 17, and an AND circuit 19.

  Dc1 is a digital count value output from the counter circuit 8, and corresponds to the number of clocks of the low-speed clock signal CLK1 measured by provisional measurement. K is a predetermined digital value. The predetermined value K may be a fixed value or a value that can be appropriately changed. The subtraction circuit 11 calculates a value (Dc1-K) obtained by subtracting a predetermined value K from the counter value Dc1. The value (Dc1-K) is a set number that determines the timing for switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 in actual measurement. The register 13 stores the set number (Dc1-K).

  Dc2 is a digital count value output from the counter circuit 8, and corresponds to the number of clocks of the low-speed clock signal CLK1 measured by actual measurement. The comparison circuit 15 switches the output from low to high when the counter value Dc2 exceeds the set number (Dc1-K). The measurement count recording circuit 17 is a 1-bit memory, and outputs low during temporary measurement and outputs high during actual measurement. The AND circuit 19 performs the actual measurement, and when the counter value Dc2 exceeds the set number (Dc1-K), that is, the number of clocks of the low-speed clock signal CLK1 after the start of the delay time measurement in the actual measurement is the set number. When reaching (Dc1-K), the switching signal S1 is output.

  1 and 2, when the switching signal S1 is input, the oscillation circuit 2 changes the connection destination of the switch from the low-speed clock signal generation circuit 2A to the high-speed clock signal generation circuit 2B, and the counter circuit 8 Is switched from the low-speed clock signal CLK1 to the high-speed clock signal CLK2. Thus, the switching signal generation circuit 10 can control the timing of switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 in actual measurement.

  As shown in FIG. 1 and FIG. 6, when the switching signal S1 is input, the counter circuit 8 switches the connection destination of the first switch SW1 and the second switch SW2 to perform asynchronous operation from the synchronous mode (A). It can switch to formula mode (B). The counter circuit 8 resets the counter value when the switching signal S1 is input. As described above, the counter circuit 8 can operate in the synchronous mode (A) in the temporary measurement, and can operate in the synchronous mode (A) and the asynchronous mode (B) in the actual measurement. The counter circuit 8 can integrate a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources. For example, the number of gates of the counter circuit 8 is reduced by about 43% as compared with a case where a 4-bit synchronous counter circuit and an asynchronous counter circuit are separately integrated.

  Generally, a synchronous counter circuit can read a counter value from each bit in real time because a delay between the bits is constant with respect to a clock signal. For this reason, the synchronous counter circuit can accurately measure the number of clocks. On the other hand, the synchronous counter circuit is not suitable for speeding up the clock signal because the delay between each bit is relatively large. For this reason, it is desirable to use a low-speed clock signal for the synchronous counter circuit.

  In general, an asynchronous counter circuit has no logic gate other than a flip-flop, so that a delay between bits is relatively small. Therefore, the asynchronous counter circuit can cope with a high-speed clock signal. On the other hand, since an asynchronous counter circuit accumulates delays between bits, it is not suitable to read a counter value from each bit in real time. For this reason, it is desirable to use a high-speed clock signal for the asynchronous counter circuit.

  As described above, the counter circuit 8 can operate to measure the low-speed clock signal CLK1 in the synchronous mode (A) and can operate to measure the high-speed clock signal CLK2 in the asynchronous mode (B). . Therefore, the counter circuit 8 can accurately measure the counter value Dc1 in the tentative measurement by executing the synchronous mode (A), and further increases the set number (Dc1-K) in the actual measurement. Accurately measure when you reach it. In addition, the counter circuit 8 executes the asynchronous mode (B), so that a period from the reaching of the set number (Dc1-K) in actual measurement to the timing T2 (see FIG. 7) at which the delay time ends is obtained. Accurate measurement is possible. Thus, the counter circuit 8 can accurately measure the delay time of the delayed pulse signal V2. As a result, the temperature sensor circuit 1 can accurately measure the temperature.

  The counter circuit 8 of the temperature sensor circuit 1 provides a set value (Dc1-K) and a counter value based on the high-speed clock signal CLK2 as the temperature information Dout. The counter value based on the high-speed clock signal CLK2 is obtained by resetting the counter value of the counter circuit 8 in synchronization with the switching signal S1 of the switching signal generation circuit 10 in actual measurement. Thus, the temperature sensor circuit 1 can output the count number measured using the low-speed clock signal CLK1 and the counter number measured using the high-speed clock signal CLK2 as temperature information Dout in actual measurement.

  The oscillation circuit 2 of the temperature sensor circuit 1 changes the connection destination of the switch from the low-speed clock signal generation circuit 2A to the high-speed clock signal generation circuit 2B, so that the clock signal provided to the counter circuit 8 is changed from the low-speed clock signal CLK1. Switch to the high-speed clock signal CLK2. Instead, as shown in FIG. 9, the ring oscillator of the oscillation circuit 2 may be configured by a bootstrap type CMOS inverter.

  As shown in FIG. 9, the first inverter INV1, which is a bootstrap type CMOS inverter, has a plurality of switch circuits SW11, SW12, SW13, SW14 and a plurality of capacitors C1, C2 as compared with the example of FIG. . The switch circuits SW11 and SW12 are configured to switch between a state in which the capacitor C1 is connected to the gate of the first transistor Tr1 and a state in which the capacitor C1 is not connected. The switch circuits SW13 and SW14 are configured to switch between a state in which the capacitor C2 is connected to the gate of the second transistor Tr2 and a state in which the capacitor C2 is not connected.

  In this bootstrap type first inverter INV1, the bootstrap is activated when the switching signal S1 of the switching signal generation circuit 10 is input, the switch circuits SW11 and SW12 connect the capacitor C1 to the gate of the first transistor Tr1, and the switch circuit SW13 and SW14 connect the capacitor C2 to the gate of the second transistor Tr2. The capacitor C1 is charged in advance so that the gate side of the first transistor Tr1 is negative, whereby the first transistor Tr1 can operate at high speed. The capacitor C2 is charged in advance so that the gate side of the second transistor Tr2 is positive, and thus the second transistor Tr2 can operate at high speed.

  As described above, when the bootstrap type first inverter INV1 is adopted as the ring oscillator of the oscillation circuit 2 of the temperature sensor circuit 1, the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B are provided as in the example of FIG. There is no need to prepare them individually, and an increase in circuit resources can be suppressed. Further, since the high-speed clock signal CLK2 can be generated only when necessary, power consumption can be suppressed low.

  The counter circuit 8 is composed of a plurality of JK flip-flops FF. Instead of this, the counter circuit 8 may be composed of a plurality of T-type flip-flops FF as shown in FIG. The wiring pattern of the counter circuit 8 composed of a plurality of stages of T-type flip-flops FF is the same as that of the case where the counter circuit 8 is composed of a plurality of stages of J-type flip-flops FF. Further, the counter circuit 8 may be composed of a plurality of stages of D-type flip-flops FF as shown in FIG. In this example, the second switch SW2 switches a signal input to the XOR circuit between the synchronous mode and the asynchronous mode. Accordingly, the second switch SW2 is configured so that the exclusive OR of the carry signal S2 and the output Q is input to the input terminal of the D-type flip-flop FF in the synchronous mode (A), and the asynchronous mode (B ), The exclusive OR of the Hi signal and the output Q is input to the input terminal of the D-type flip-flop FF. Both the counter circuit 8 shown in FIGS. 10 and 11 integrates a synchronous counter circuit and an asynchronous counter circuit that have been conventionally known only by mounting a plurality of first switches SW1 and a plurality of second switches SW2. can do.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: Temperature sensor circuit 2: Oscillator circuit 3: Frequency divider circuit 4: Delay circuit 5: Delay time measurement circuit 6: Switching signal generation circuit CLK1: Low speed clock signal CLK2: High speed clock signal

Claims (9)

A counter circuit,
A multi-stage flip-flop;
A plurality of first switches, each of the plurality of first switches being provided corresponding to a clock terminal of each of the second and subsequent stages of flip-flops, and a signal input to the clock terminal A plurality of first switches configured to switch between;
A plurality of second switches, each of the plurality of second switches being provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and a signal input to the input terminal A plurality of second switches configured to switch between, and
The plurality of first switches and the plurality of second switches form a wiring pattern so that the plurality of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of flip-flops in the asynchronous mode A counter circuit that configures a wiring pattern so that becomes an asynchronous counter. The first switch is configured to input a clock signal to the clock terminal in the synchronous mode, and configured to input the output of the previous flip-flop to the clock terminal in the asynchronous mode.
The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The counter circuit described in 1.   The counter circuit according to claim 2, wherein the flip-flop is a JK flip-flop. A time measurement circuit,
An oscillation circuit that generates a relatively low-frequency low-speed clock signal and a relatively high-frequency high-speed clock signal;
A counter circuit that measures a target time based on the low-speed clock signal or the high-speed clock signal output from the oscillation circuit,
The counter circuit is
A multi-stage flip-flop;
A plurality of first switches, each of the plurality of first switches being provided corresponding to a clock terminal of each of the second and subsequent stages of flip-flops, and a signal input to the clock terminal A plurality of first switches configured to switch between;
A plurality of second switches, each of the plurality of second switches being provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and a signal input to the input terminal A plurality of second switches configured to switch between, and
The plurality of first switches and the plurality of second switches form a wiring pattern so that the plurality of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of flip-flops in the asynchronous mode A time measurement circuit that configures the wiring pattern so that becomes an asynchronous counter. The first-stage flip-flop is configured to input the low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the high-speed clock signal to the clock terminal in the asynchronous mode.
The first switch is configured to input the low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the output of the previous flip-flop to the clock terminal in the asynchronous mode. And
The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The time measuring circuit described in 1.   The time measuring circuit according to claim 5, wherein the flip-flop is a JK flip-flop. A temperature sensor circuit,
An oscillation circuit that generates a relatively low-frequency low-speed clock signal and a relatively high-frequency high-speed clock signal;
A delay circuit for generating a delay signal having a delay time having temperature dependent characteristics;
A counter circuit that measures a delay time of the delay signal based on the low-speed clock signal or the high-speed clock signal output from the oscillation circuit,
The counter circuit is
A multi-stage flip-flop;
A plurality of first switches, each of the plurality of first switches being provided corresponding to a clock terminal of each of the second and subsequent stages of flip-flops, and a signal input to the clock terminal A plurality of first switches configured to switch between;
A plurality of second switches, each of the plurality of second switches being provided corresponding to each input terminal of the second and subsequent stages of flip-flops, and a signal input to the input terminal A plurality of second switches configured to switch between, and
The plurality of first switches and the plurality of second switches form a wiring pattern so that the plurality of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of flip-flops in the asynchronous mode A temperature sensor circuit that configures the wiring pattern so that becomes an asynchronous counter. The first-stage flip-flop is configured to input the low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the high-speed clock signal to the clock terminal in the asynchronous mode.
The first switch is configured to input the low-speed clock signal to the clock terminal in the synchronous mode, and configured to input the output of the previous flip-flop to the clock terminal in the asynchronous mode. And
The second switch is configured to input a carry signal to the input terminal in the synchronous mode, and configured to input a high signal to the input terminal in the asynchronous mode. The temperature sensor circuit described in 1.   The temperature sensor circuit according to claim 8, wherein the flip-flop is a JK flip-flop.

Images