JP2017055024A - Semiconductor element mounting substrate, semiconductor device, and manufacturing methods thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element mounting substrate which is suitable for flip chip mounting and capable of reducing the size of a chip, reduces quality defect in adhesiveness of a resin of an external terminal part or the like, while improving productivity, a semiconductor device, and manufacturing methods thereof.SOLUTION: The semiconductor element mounting substrate comprises: a conductive substrate 10 in which a semiconductor element is mounted in a semiconductor element mounting region 11 and which can be removed after resin sealing; an internal terminal support part 20 which is provided in a layered state in the semiconductor element mounting region 11 and a region including an internal terminal part 31 to which an electrode of the semiconductor element is connectable, on a surface of the conductive substrate 10, and can be removed simultaneously with the conductive substrate 10; and a layered lead part 30 which is formed continuously with a step difference between the internal terminal support part 20 and a surface of the conductive substrate 10 so as to cross a region serving as the internal terminal part 31 in the internal terminal support part 20, and the conductive substrate 10, and has a bottom face, which is to be exposed when the conductive substrate 10 is removed, serving as an external terminal part 32.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a substrate for mounting a semiconductor element, a semiconductor device, and a manufacturing method thereof.

  In recent years, as represented by mobile phones, electronic devices are rapidly becoming smaller and lighter, and semiconductor devices used in these electronic devices are also required to be smaller, lighter, and more functional. In particular, the thickness of the semiconductor device is required to be reduced. In order to meet such a demand, a semiconductor device that finally removes the following conductive substrate has been developed from a semiconductor device using a lead frame obtained by processing a metal material such as QFP (Quad Flat Package).

  Specifically, a resist mask subjected to predetermined patterning is formed on one surface side of a conductive substrate. The substrate exposed from the resist mask is plated with a conductive metal to form a die pad portion for mounting a semiconductor element and a lead portion for connecting to the outside, and the resist mask is removed to thereby change the substrate for mounting a semiconductor element. Form. A semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, and the conductive substrate is removed to expose the die pad portion and the lead portion, thereby completing the semiconductor device. There has also been proposed a method in which a recess is formed in a part of a conductive substrate, and a conductive metal is plated on the part. (For example, refer to Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 10-116935 JP 2006-93575 A

  By the way, when connecting a semiconductor element and a lead part, the wire bonding system using a gold wire was generally adopted. However, due to the recent rise in the price of Au, the use of a flip chip method in which a semiconductor element and a lead portion are directly connected without using a gold wire is increasing. In the flip chip method, the positions of the external terminal portion connected to the external device and the internal terminal portion connected to the semiconductor element are different. The external terminal portions are arranged at a standardized designated pitch. On the other hand, in the flip chip method, the internal terminal portion is arranged near the outer periphery of the chip size, and the chip size tends to be integrated and reduced for cost reduction. For this reason, in the semiconductor device described in Patent Literature 1 or Patent Literature 2, the external terminal portion and the internal terminal portion are connected by a plating layer to form a wiring portion. For example, FIG. 27 of Patent Document 1 and FIG. 1 of Patent Document 2 correspond to this.

  In the semiconductor device described above, in the semiconductor device described in Patent Document 1, the external terminal portion is formed of a resin protrusion, and the surface layer is plated. For this reason, the adhesion between the plating layer and the resin is weak, and problems such as peeling of the plating may occur. In the semiconductor device described in Patent Document 2, a concave portion is formed in a part of a conductive substrate, and via filling liquid used in a wiring substrate or the like is used for the concave portion, and hole filling electrolytic copper plating is performed. However, hole filling electrolytic copper plating using a via filling liquid tends to concentrate the plating current at the bottom of the recess and make the plating in the recess thicker. There is a problem that a difference is easily generated and it is difficult to control the plating thickness.

  Therefore, the present invention is particularly suitable for flip chip mounting, can be reduced in chip size, has less quality defects such as adhesion of the resin of the external terminal portion, and has high productivity and semiconductor device mounting substrate and semiconductor device It is an object to provide a manufacturing method thereof.

In order to achieve the above object, a substrate for mounting a semiconductor element according to one aspect of the present invention has a semiconductor element mounting region in which a semiconductor element can be mounted, and the semiconductor element is mounted in the semiconductor element mounting region, A conductive substrate that can be removed after being stopped;
An internal terminal support portion provided in a layered manner on a surface of the conductive substrate in a region including the semiconductor element mounting region and an internal terminal portion to which an electrode of the semiconductor element can be connected, and removable simultaneously with the conductive substrate; ,
A step is formed continuously on the surface of the internal terminal support part and the conductive substrate so as to straddle the region to be the internal terminal part in the internal terminal support part and the conductive substrate, The bottom surface exposed when the conductive substrate is removed has a layered lead portion serving as an external terminal portion.

A semiconductor device according to another aspect of the present invention includes a semiconductor element provided in a predetermined semiconductor mounting region,
A layered first resin provided facing the semiconductor element and provided to include the semiconductor element mounting region in a top view;
The first resin is formed in a continuous layer with a step so as to straddle the first resin and the outside of the first resin, and the bottom surface of the outer region of the first resin is formed of the first resin. A lead portion provided to form the same surface continuous with the bottom surface, and having an internal terminal portion on the first resin and an external terminal portion on the external bottom surface of the first resin;
Connection means for electrically connecting the semiconductor element and the internal terminal portion;
The semiconductor element excluding the bottom surface of the first resin and the external terminal portion, the top surface and side surfaces of the lead portion, and a second resin that seals the connection means.

The method for manufacturing a semiconductor element mounting substrate according to another aspect of the present invention includes a step of forming a first plating layer on a conductive substrate so as to include a semiconductor element mounting region and a region to be an internal terminal portion. ,
A step is continuously straddled across the surface of the region to be the internal terminal portion in the first plating layer and the surface of the conductive substrate outside the first plating layer. Forming a lead portion by forming a second plating layer.

A method for manufacturing a semiconductor device according to another aspect of the present invention includes mounting a semiconductor element on the semiconductor element mounting region of a semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate. Electrically connecting an electrode to the internal terminal using a predetermined connection means;
A step of resin-sealing the conductive substrate with a first resin including the first plating layer, the second plating layer, the connection means, and the semiconductor element;
Removing the conductive substrate and the first plating layer;
Sealing the region in which the first plating layer was formed with a second resin.

  According to the present invention, the chip size can be reduced and the productivity can be increased.

It is sectional drawing which shows an example of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention. It is the elements on larger scale which expanded and showed the part in which the edge part and lead part of the internal terminal support part were formed. It is sectional drawing of an example of the semiconductor device which concerns on embodiment of this invention. It is the figure which showed the structural example of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention. FIG. 4A is a cross-sectional view showing an example of a semiconductor element mounting substrate according to an embodiment of the present invention. FIG. 4B is a plan view showing an example of a semiconductor element mounting substrate according to the embodiment of the present invention. It is the figure which showed the series of processes of the first half of an example of the manufacturing method of the semiconductor element mounting substrate which concerns on embodiment of this invention. FIG. 5A is a diagram showing an example of a conductive substrate preparation process. FIG. 5B is a diagram showing an example of a resist forming process for plating the internal terminal support portion. FIG. 5C is a diagram showing an example of the internal terminal support portion plating step. FIG. 5D is a diagram showing an example of a resist stripping process for plating the internal terminal support portion. It is the figure which showed a series of processes of the latter half of an example of the manufacturing method of the board | substrate for semiconductor element mounting concerning embodiment of this invention. FIG. 6A is a diagram showing an example of a resist forming process for lead portion plating. FIG. 6B is a diagram showing an example of the lead portion plating step. FIG. 6C is a diagram showing an example of a resist peeling process for lead portion plating. It is the figure which showed a series of processes of the first half of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. FIG. 7A is a diagram showing an example of a bump forming process, and FIG. 7B is a diagram showing an example of a semiconductor element mounting process. FIG. 7C is a diagram showing an example of the first resin sealing step. It is the figure which showed a series of processes of the latter half of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. FIG. 8A shows an example of the conductive substrate removing process. FIG. 8B is a diagram showing an example of the second resin sealing step. FIG. 8C is a diagram showing an example of the singulation process.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[Semiconductor element mounting substrate and semiconductor device]
FIG. 1 is a cross-sectional view illustrating an example of a semiconductor element mounting substrate according to an embodiment of the present invention. The substrate 50 for mounting a semiconductor element according to the present embodiment includes a conductive substrate 10, an internal terminal support portion 20 disposed on the surface thereof, and a lead portion 30. A semiconductor element mounting region 11 for mounting a semiconductor element is provided on the surface of the conductive substrate 10, and an internal terminal support portion 20 is provided so as to include the semiconductor element mounting region 11. The lead portion 30 is continuously provided with a step so as to straddle the surface of the end portion of the internal terminal support portion 20 and the surface of the conductive substrate 10 outside the internal terminal support portion 20.

  The semiconductor element mounting area 11 is an area in which a semiconductor element on the surface of the conductive substrate 10 can be mounted. For example, the semiconductor element mounting area 11 is provided in the central area of the conductive substrate 10.

  The conductive substrate 10 is a substrate on which the internal terminal support portion 20 and the lead portion 30 are formed on the surface, and is conductive so that the internal terminal support portion 20 and the lead portion 30 can be formed by electroplating. It is comprised from the material which has. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used. Further, the conductive substrate 10 is removed by dissolving a semiconductor element or the like after resin sealing in the process of manufacturing a semiconductor device. Generally, Cu or Cu alloy that can be selectively removed is used.

  The lead part 30 is a plating layer formed on the surface of the conductive substrate 10 by plating. The lead part 30 has an internal terminal part 31 and an external terminal part 32. The internal terminal portion 31 is a plating layer formed on the internal terminal support portion 20. The external terminal portion 32 is a plating layer in which the conductive substrate 10 is in contact with the bottom surface. The internal terminal portion 31 and the external terminal portion 32 are plated at the same time, and are formed as one continuous plating layer. Since it is continuously formed so as to straddle the end portion of the internal terminal support portion 20, the plating layer is formed so as to stride over the step formed between the internal terminal support portion 20 and the conductive substrate 10. Formed as. Details of the lead part 30 will be described later.

  The internal terminal support portion 20 is a plating layer formed to support the internal terminal portion 31 in the lead portion 30. The internal terminal portion 31 is preferably arranged at a position higher than the external terminal portion 32 because the electrodes of the semiconductor element are connected by solder bumps by a flip chip method and the semiconductor element is directly mounted. The internal terminal support portion 20 has a predetermined thickness and a surface higher than the surface of the conductive substrate 10, and supports the internal terminal portion 31 at a position higher than the surface of the conductive substrate 10.

  The internal terminal support portion 20 is set to a size including the semiconductor element mounting region 11 and further including a region where at least a part of the internal terminal portion 31 is formed. In the case of the flip chip method, it is necessary that at least a part of the semiconductor element mounting region 11 and the internal terminal portion 31 overlap with each other when viewed from above, and the internal terminal support portion 20 includes the semiconductor mounting region 11 and internal terminal portion 31. Are included so as to include a position where they overlap each other when viewed from above.

  FIG. 2 is a partially enlarged cross-sectional view showing an enlarged portion where the end portion of the internal terminal support portion 20 and the lead portion 30 are formed. As shown in FIG. 2, an internal terminal support portion 20 is formed on the surface of the conductive substrate 10, and a lead portion 30 is formed so as to cover the outer peripheral boundary line of the internal terminal support portion 20. Of the lead part 30, the part formed on the internal terminal support part 20 becomes the internal terminal part 31, and the part formed on the surface of the conductive substrate 10 becomes the external terminal part 32. Since the internal terminal portion 31 and the external terminal portion 32 are formed with different heights, a step is formed between them, and a step portion 33 is formed. The step portion 33 protrudes slightly higher than the surface of the internal terminal portion 31 and gently descends toward the external terminal portion 32 to form an inclined surface.

  The internal terminal support part 20 can be set to various heights as long as the internal terminal part 31 can be supported higher than the external terminal part 32. For example, the internal terminal support part 20 is preferably set to 20 μm or more and 100 μm or less, and preferably 20 μm or more and 40 μm or less. More preferably, it is set to. The internal terminal support portion 20 may be made of various materials, but is preferably made of a material that can be removed together with the conductive substrate 10 during the manufacturing process of the semiconductor device. For example, when the conductive substrate 10 is made of Cu or Cu alloy, if the internal terminal support portion 20 is made of Cu, the internal terminal support portion 20 is also dissolved and removed simultaneously with a solvent used for dissolving and removing the conductive substrate 10. It is possible to simplify the manufacturing process.

  The internal terminal portion 31 has solder bumps formed on the surface, and a semiconductor element is mounted on the surface. On the other hand, the external terminal portion 32 has a bottom surface exposed when the conductive substrate 10 is removed, and the bottom surface functions as a connection surface of the external terminal portion 32. Therefore, it is preferable that the lead part 30 is comprised from the material suitable for connecting as a terminal, for example, it is preferable to select the metal material which the wettability of a solder bump becomes favorable. Examples of such metals include noble metals such as Au, Ni, and Pd. For example, the lead part 30 may be composed of a plating layer of Au, Ni, Pd or a multilayer plating layer thereof.

  Next, an example of a semiconductor device using the semiconductor element mounting substrate according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of an example of a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 3, in the semiconductor device 100 according to the embodiment of the present invention, the semiconductor element 60 is configured such that the electrode 61 of the semiconductor element 60 and the internal terminal part 31 of the lead part 30 are flip-chip, and the bump 70 and the like. Connected through. In addition, the entire structure including the connection portions such as the semiconductor element 60 and the bumps 70 and the internal terminal portions 31 of the lead portions 30 is sealed with a first sealing resin 80. Further, at least the lower surface of the internal terminal portion 31 of the lead portion 30 is resin-sealed with a second sealing resin 90. The bottom surface of the external terminal portion 32 is exposed from the first sealing resin 80 and the second sealing resin 90 and serves as an external connection terminal for soldering to an external device.

  Further, the conductive substrate 10 and the internal terminal support 20 that existed in FIG. 1 do not exist. The conductive substrate 10 and the internal terminal support 20 are dissolved and removed after the resin sealing is performed with the first sealing resin 80. That is, the lead part 30 of the semiconductor element mounting substrate 50 shown in FIG. 1 and the electrode 61 of the semiconductor element 60 are connected via the bump 70 by flip chip mounting, and then the first on the semiconductor element mounting substrate 50. Resin sealing is performed by the sealing resin 80. After the resin sealing, the conductive substrate 10 and the internal terminal support 20 are removed.

  A feature of the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention is that at least the internal terminal support portion 20 is formed on the lower surface of the internal terminal portion 31 of the lead portion 30, and then the conductive substrate 10 and It is to be removed at the same time.

  The internal terminal support portion 20 is formed before the lead portion 30 is plated on the conductive substrate 10. Thereafter, the lead part 30 is formed by plating as one continuous plating layer so that the external terminal part 32 is located on the conductive substrate 10 and the internal terminal part 31 is located on the internal terminal support part 20. . Thereafter, the semiconductor element 60 and the internal terminal portion 31 are connected. For example, when the semiconductor element 60 is mounted by the flip-chip method, the internal terminal support portion 20 is provided on the lower side portion of the internal terminal portion 31, so that it can be carried out without any problem even if heating or pressurization is applied. Thereafter, the upper surface of the conductive substrate 10 including the internal terminal portion 31, the external terminal portion 32, the semiconductor element 60, and the bump 70 is sealed with resin, and then the internal terminal support portion 20 is used when the conductive substrate 10 is dissolved and removed. Are simultaneously dissolved and removed. By removing the internal terminal support portion 20, the internal terminal portions 31 are independent from each other except for the bumps 70, and the lower surface of the internal terminal portion 31 is at a position where it is depressed by the thickness of the internal terminal support portion 20. Exposed from the sealing resin 80. After that, the second sealing resin 90 is resin-sealed in the hollow portion, and the lower surface of the internal terminal portion 31 exposed in the previous process is covered with the second sealing resin 90. Therefore, finally, only the lower surface of the external terminal portion 32 is exposed from the first sealing resin 80 and the second sealing resin 90. As a result, the lower surface of the internal terminal portion 31 is not exposed to the outside, and the risk of contact with an external device is eliminated.

  Further, in the embodiment of the present invention, when the lead portion 30 is formed by plating, plating is performed substantially on a flat surface, and thus there is an effect of suppressing variation in plating thickness. In Patent Document 2 described above, a recess is formed in the conductive substrate 10, and then a plating resist is prepared including the recess, and a plating layer is formed by filling the portion where the conductive substrate without the resist is exposed. There is a statement to that effect. As for this hole filling plating, it is described that a via filling liquid used in a wiring board or the like is preferably used. When a via filling liquid is used, the plating current is concentrated on the bottom surface of the recess, and the plating of the recess becomes thick, so that the hole can be filled. However, since the concave portion and the wiring portion on the conductive substrate are plated at the same time, there is a difference in plating thickness between the concave portion and the tip portion of the wiring portion, and the concave portion tends to be high. Moreover, because of the hole filling plating using a via filling solution, it is difficult to individually control the plating thickness of the wiring portion, resulting in variations. For this reason, it may be difficult to ensure the flatness of the connection part (suppress variation in the plating thickness of the wiring part). When the connection method is a wire bonding method, it is sufficient if a certain plating thickness can be secured. However, in flip chip mounting, each internal terminal portion is mounted simultaneously in one semiconductor device, so the connecting portion of each internal terminal portion If the thickness of the plating is not the same, an unsuccessful defect occurs. In the flip-chip connection method, it is generally necessary to suppress the difference in plating thickness in one semiconductor device to at least 3 μm, preferably 2 μm. In the above-described manufacturing method, mounting of semiconductor elements by the flip-chip method is not possible. very difficult.

  The present invention has been proposed based on the above-mentioned problems. In the embodiment of the present invention, the step of providing a concave portion in the conductive substrate and performing hole filling plating on the portion as in Patent Document 2 is not performed. In the present embodiment, first, the internal terminal portion 31 and the external terminal portion 32 are stepped so that the internal terminal portion 31 is not exposed from the sealing resins 80 and 90 when the semiconductor device 100 is formed. The internal terminal support part 20 is formed below the conductive substrate 10 and a step is provided. Then, a lead portion 30 having a predetermined shape is formed so as to straddle the step between the internal terminal portion 31 and the external terminal portion 32. The external terminal portion 32 is formed on the surface of the conductive substrate 10, and the internal terminal portion 31 is formed on the internal terminal support portion 20 by plating. Since each is formed on a flat surface, variations in plating thickness are minimized as compared with hole-filling plating or the like. In addition, when plating is performed on the recess, a phenomenon occurs in which the plating thickness at the end of the recess having a side surface increases due to the edge effect. In the embodiment of the present invention, a step at the boundary between the internal terminal portion 31 and the external terminal portion 32 is generated. This is only the portion 33, and the influence of the phenomenon that the plating thickness increases due to the edge effect is small. In addition, as shown in FIG. 2, the plating shape of the stepped portion 33 is formed in a gentle R shape.

  Accordingly, in the semiconductor element mounting substrate according to the embodiment of the present invention, variations in the plating thickness of the lead portion 30 can be suppressed. Such a configuration is particularly effective by a flip-chip connection method.

  Next, the configuration of the lead portion 30 and the internal terminal support portion 20 formed on the conductive substrate 10, which is a feature of the semiconductor element mounting substrate 50 according to the embodiment of the present invention, will be described using FIG. 4. FIG. 4 is a view showing a configuration example of a semiconductor element mounting substrate according to the embodiment of the present invention. FIG. 4A is a cross-sectional view showing an example of a semiconductor element mounting substrate according to an embodiment of the present invention. FIG. 4B is a plan view showing an example of a semiconductor element mounting substrate according to the embodiment of the present invention.

  As shown in FIGS. 4A and 4B, the range of the internal terminal support portion 20 is at least the range of the lower surface of the internal terminal portion 31. Further, as shown in FIG. 4B, each semiconductor device may have a shape including the semiconductor element 60 and the internal terminal portion 31. Moreover, you may connect with the internal terminal support part 31 of an adjacent semiconductor device. After dissolving and removing the internal terminal support portion 20, the removed and recessed portion is resin-sealed with the second sealing resin 90. Therefore, in consideration of the workability of the second sealing resin 90, a square including the semiconductor element 60 and the internal terminal portion 31 for each semiconductor device, rather than setting a radial range for each internal terminal portion 31 individually. It is preferable to set a wide and simple range of the shape. In FIG. 4B, an internal terminal support having a rectangular region wider than the semiconductor element mounting region 11 where the semiconductor element 60 is mounted and the region 22 where the internal terminal portion 31 is formed is included. Part 20 is formed. Thus, it is preferable that the internal terminal support part 20 is configured in a slightly wide and simple shape so as not to complicate the manufacturing process.

  As described above, the plating type of the internal terminal support portion 20 is such that when the semiconductor element 60 is mounted and then resin-sealed and the conductive substrate 10 is dissolved and removed, the internal terminal support portion 20 can be dissolved and removed at the same time. It is preferable to select the same type of metal as that of the conductive substrate 10. For example, when the conductive substrate 10 is Cu or a Cu alloy, the internal terminal support 20 is preferably a Cu plating layer.

  The thickness of the internal terminal support portion 20 is preferably 0.02 mm or more and 0.1 mm or less (20 μm or more and 100 μm or less). If it is less than 0.02 mm, the thickness of the second sealing resin 90 is thin, the adhesion with the first sealing resin 80 is insufficient, and peeling is likely to occur. On the other hand, when the internal terminal support part 20 becomes thick, when the entire surface is covered with a dry film resist after the internal terminal support part 20 is formed, air may enter due to a step. Therefore, considering the formation of the lead plating resist, the thickness of the internal terminal support 20 is more preferably 0.02 mm to 0.04 mm (20 μm or more and 40 μm or less).

  Next, the plating layer constituting the lead part 30 will be described. The plating layer of the lead part 30 is formed by simultaneously plating the external terminal part 32 and the internal terminal part 31. The external terminal portion 32 is formed on the conductive substrate 10, and the internal terminal portion 31 is formed on the internal terminal portion support portion 20.

  There is no particular limitation on the type of the plating layer constituting the lead part 30. Since the lower surface of the external terminal portion 32 becomes an external connection terminal, the type of plating having good connectivity with the solder alloy is selected. Since the upper surface of the internal terminal portion 31 is connected to the semiconductor element 60, noble metal plating such as Au, Ag, Pd is preferable. For example, the lead portion 30 may be formed of a five-layer plating layer that is formed in the order of Au plating, Pd plating, Ni plating, Pd plating, and Au plating from the bottom surface.

[Method of Manufacturing Semiconductor Device Mounting Board]
Next, with reference to FIG. 5, the manufacturing method of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention is demonstrated. FIG. 5 is a diagram showing a series of steps in the first half of an example of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.

  FIG. 5A is a diagram showing an example of a conductive substrate preparation process. As shown in FIG. 5A, in manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention, first, a conductive substrate 10 is prepared. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but Cu alloy or Cu is generally used.

  FIG. 5B is a diagram showing an example of a resist forming process for plating the internal terminal support portion. In the internal terminal support part plating resist formation step, in detail, resist coating, exposure, and development are performed to form an internal terminal support part plating resist mask 42. The entire front and back surfaces of the conductive substrate 10 are covered with a resist 40. As the resist 40 to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by applying and drying a liquid resist can be used. Next, in the exposure, after the resist 40 is coated on the front and back surfaces of the conductive substrate 10 in the previous resist coating step, a desired pattern is formed on the resist 40 at a position where the inner terminal support portion 20 is formed on the front surface. Is covered with a mask (ultraviolet light shielding glass mask) on which a pattern covering the entire surface is formed, and exposure is performed.

  In the development, by removing the mask and developing the resist 40, a portion (uncured portion) where a recess is formed on the surface is removed, an opening 41 is formed, and the surface of the conductive substrate 10 is exposed. As a result, the resist 40 left after being cured and the internal terminal support portion plating mask 42 including the openings are formed.

  FIG. 5C is a diagram showing an example of the internal terminal support portion plating step. As shown in FIG. 5C, plating is performed on the surface of the conductive substrate 10 using the formed resist mask 42 as an internal terminal support part plating mask to form the internal terminal support part 20. The thickness of the plating layer is 0.02 mm to 0.1 mm, preferably 0.02 mm to 0.04 mm.

  FIG. 5D is a diagram showing an example of a resist stripping process for plating the internal terminal support portion. In the resist stripping step for plating the internal terminal support portion, the hardened resist 40 is stripped. As a result, the internal terminal support 20 is formed on the surface of the conductive substrate 10.

  FIG. 6 is a diagram showing a series of steps in the latter half of the example of the method for manufacturing the semiconductor element mounting substrate according to the embodiment of the present invention.

  FIG. 6A is a diagram showing an example of a resist forming process for lead portion plating. In the lead portion plating resist forming step, in detail, resist coating, exposure, and development are performed to form a lead portion plating resist mask 45. In FIG. 5D, the resist 43 covers the surface on which the internal terminal support 20 is formed on the conductive substrate 10 and the entire back surface of the conductive substrate 10. As the resist 43 to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by applying and drying a liquid resist can be used. When the lamination method is used, if the internal terminal support portion 20 is thick, bubbles may enter the boundary portion. Therefore, a vacuum laminator or the like is used to prevent the generation of bubbles. Next, in exposure, after the resist 43 is coated on the front and back surfaces of the conductive substrate 10 with the previous resist coating, on the front surface side, the external terminal portion 32 is placed on the conductive substrate 10 and the internal terminal portion 31 internal terminal support portion. A predetermined pattern is formed so that a plating layer can be formed on 20. On the other hand, the back surface of the conductive substrate 10 is covered with a mask (ultraviolet light shielding glass mask) in which a pattern covering the entire surface is formed, and exposure is performed.

In the development, the resist 43 is developed by removing the mask, thereby removing the portion (uncured portion) where the lead portion 30 is to be formed to form the opening 44, and the surfaces of the conductive substrate 10 and the internal terminal support portion 20. To expose. As a result, a lead portion plating mask 45 including the resist 43 and the opening 44 remaining after being cured is formed.
FIG. 6B is a diagram showing an example of the lead portion plating step. In the lead portion plating step, the resist mask 45 for lead portion plating formed in FIG. 6A is used, and the external terminal portion 32 is formed on the surface of the conductive substrate 10 and the internal terminal portion is formed on the surface of the internal terminal support portion 20. 31 is simultaneously formed by plating. There is no limitation in particular in the kind of plating metal. Also, the plating thickness is not particularly limited. For example, Au plating 0.003 μm to 0.1 μm, Pd plating 0.01 μm to 0.2 μm, Ni plating 5.0 μm to 40.0 μm, Pd plating 0.01 μm to 0.2 μm, Au plating 0.003 μm to 0.2 μm. Lamination plating performed in the order of 1 μm may be used. The lead part 30 becomes the internal terminal part 31 and the external terminal part 32 and functions as a connection terminal. Therefore, the lead part 30 can be formed according to the use by using a plating material suitable for the connection terminal.

  FIG. 6C is a diagram showing an example of a resist peeling process for lead portion plating. In the lead part plating resist peeling step, the hardened resist 43 is peeled off.

  Thereby, the semiconductor element mounting substrate 50 is completed. If necessary, it may be cut into a predetermined size and formed into a sheet.

  As described above, the semiconductor element mounting substrate 50 according to the embodiment of the present invention is manufactured by sequentially performing the above-described steps.

[Method for Manufacturing Semiconductor Device]
Next, an example of a manufacturing method of the semiconductor device 100 that manufactures the semiconductor device 100 using the semiconductor element mounting substrate 50 manufactured by the above-described manufacturing method will be described with reference to FIGS. 7 and 8, an example in which the connection method between the semiconductor element 60 and the lead part 30 is a flip chip method will be described. This connection method can also be a known wire bonding method.

  FIG. 7 is a diagram showing a series of steps in the first half of an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  FIG. 7A is a diagram illustrating an example of a bump forming process. In the bump forming step, bumps 70 for connecting to the semiconductor element 60 are formed on the surface of the internal terminal part 31 of the lead part 30 of the semiconductor element mounting substrate 50.

  FIG. 7B is a diagram showing an example of a semiconductor element mounting process. The electrode part 61 of the semiconductor element 60 is connected to the bump 70 formed in FIG. 7A, and the semiconductor element 60 is mounted on the upper side of the internal terminal part 31 of the lead part 30.

  FIG. 7C is a diagram showing an example of the first resin sealing step. In the first resin sealing step, the entire surface on which the semiconductor element 60 of the semiconductor element mounting substrate 50 is mounted is resin-sealed with the first sealing resin 80.

  FIG. 8 is a diagram illustrating a series of steps in the latter half of the example of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

  FIG. 8A shows an example of the conductive substrate removing process. In the conductive substrate removing step, the conductive substrate 10 and the internal terminal portion support portion 20 are simultaneously removed from the resin sealing portion by the first sealing resin 80. The conductive substrate 10 and the internal terminal support portion 20 are formed of the same kind of metal, and the removal is performed by dissolving and removing using the same kind of solution. Thereby, the location where the internal terminal support part 20 was formed becomes the hollow part 120, and the bottom face of the lead part 30 is exposed.

  FIG. 8B is a diagram showing an example of the second resin sealing step. In the second resin sealing step, the inner terminal support portion 20 is removed in FIG. 8A, and the lower surface of the inner terminal portion 31 exposed from the first sealing resin 80 is replaced with the second sealing resin. 90. Resin sealing is performed. Thereby, the semiconductor device 100 in which only the bottom surface of the external terminal portion 32 is exposed from the first sealing resin 80 and the second sealing resin 90 is obtained.

  FIG. 8C is a diagram showing an example of the singulation process. Finally, in the singulation step, as shown in FIG. 8C, the semiconductor device 100 is completed by cutting to a predetermined size of the semiconductor device 100.

  Thus, according to the manufacturing method of the semiconductor device according to the present embodiment, the conductive substrate 10 and the internal terminal support portion 20 are dissolved and removed, and the hollow portion 120 where the internal terminal support portion 20 is located is second sealed. What is necessary is just to seal with resin 90, it becomes unnecessary to perform a complicated etching process for forming an external connection terminal, and the production cost can be reduced and the productivity can be increased.

  Examples of manufacturing and implementing a semiconductor element mounting substrate and a semiconductor device according to embodiments of the present invention will be described below.

[Example 1]
As a conductive base material, a Cu plate having a thickness of 0.2 mm (Furukawa Electric Co., Ltd .: EFTEC64-T) is processed into a long plate shape having a width of 140 mm, and then a photosensitive dry film resist having a thickness of 0.05 mm ( Asahi Kasei E-Materials AQ-5038) was laminated on both sides of the conductive substrate with a laminate roll.

  Next, a glass mask having a desired pattern in which a region for mounting a semiconductor element and a region including an internal terminal portion as an internal terminal support portion was formed was placed on the dry film resist and exposed to ultraviolet light.

  Thereafter, using a sodium carbonate solution, development treatment was performed to dissolve uncured dry film resist that was not exposed to ultraviolet light and was not exposed to light.

  Next, Cu plating was applied at a thickness of 0.02 mm to the exposed surface of the conductive substrate in the opening from which the resist layer was removed. Thereafter, the dry film resist was peeled off with a sodium hydroxide solution. Thereby, the internal terminal support part was formed on the conductive substrate.

  Next, a photosensitive dry film resist (AQ-5038 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was again attached to both surfaces of the conductive substrate with a laminate roll. Here, a bubble laminator device was used to prevent bubbles at the boundary portion of the internal terminal support.

  Next, a glass mask on which a desired pattern corresponding to the lead portion was formed was placed on the dry film resist and exposed to ultraviolet light.

  Thereafter, using a sodium carbonate solution, development treatment was performed to dissolve uncured dry film resist that was not exposed to ultraviolet light and was not exposed to light.

  Next, the lead part was plated in the opening from which the resist layer was removed. Au plating was approximately 0.003 μm, Pd plating was 0.01 μm, Ni plating was 30 μm, Pd plating was 0.01 μm, and Au plating was approximately 0.003 μm in this order. Thereafter, the dry film resist was peeled off with a sodium hydroxide solution to form lead portions on the conductive substrate.

  Then, the board | substrate for semiconductor element mounting which concerns on Example 1 of this invention was obtained by cut | disconnecting to a predetermined dimension.

  Subsequently, flip-chip bumps were formed in the connection region of the internal terminal portion of the manufactured semiconductor element mounting substrate. Next, the electrode part of the semiconductor element and the bump were mounted by a flip chip method, and the semiconductor element and the lead part were connected. Next, the surface on which the semiconductor element was mounted was resin-sealed with a first sealing resin, and then the conductive substrate and the internal terminal support portion were simultaneously dissolved and removed from the resin-sealed portion. Then, the hollow part equivalent to the internal terminal support part including the lower surface of the internal terminal part exposed from the first sealing resin was resin-sealed with the second sealing resin.

  Finally, the semiconductor device was completed by cutting to a predetermined semiconductor device size.

[Example 2]
In Example 2, the range of the internal terminal support part in Example 1 was set to be connected to the internal terminal support part of the adjacent semiconductor device. Others are the same as in the first embodiment.

  As a result of confirming the plating time of the lead part in Examples 1 and 2, it was confirmed that it was several tens of minutes.

  In the semiconductor device manufacturing process, mounting was performed by a flip chip method, but there was little variation in plating thickness, and there was no occurrence of problems such as non-flip mounting. Finally, solder bonding was performed on the semiconductor device, and the bonding state of the external terminals was confirmed with a microscope. There were no problems such as a connection failure in the external connection terminal and a dropout of the terminal.

  In addition, in the semiconductor element mounting substrate of each example, when the variation in the plating thickness of the connection region of the internal terminal portion in each semiconductor device unit was confirmed, the example was within approximately ± 2 μm, which was suitable for flip chip mounting. It was confirmed that it was in a sufficiently usable range.

  As described above, according to the embodiments and examples of the present invention, the semiconductor element mounting substrate, the semiconductor device, and the manufacturing method thereof are particularly suitable for flip chip mounting, and the chip size can be reduced. Thus, it is possible to provide a semiconductor element mounting substrate and a semiconductor device that are less prone to quality defects such as resin adhesion in the external terminal portion and that have high productivity.

  The preferred embodiments and examples of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples can be performed without departing from the scope of the present invention. Various modifications and substitutions can be made to the embodiments.

DESCRIPTION OF SYMBOLS 10 Conductive board | substrate 11 Semiconductor element mounting area | region 20 Internal terminal support part 30 Lead part 31 Internal terminal part 32 External terminal part 50 Semiconductor element mounting board | substrate 60 Semiconductor element 61 Electrode 70 Bump 80, 90 Sealing resin 100 Semiconductor device

Claims (15)

A conductive substrate having a semiconductor element mounting region on which a semiconductor element can be mounted, the semiconductor element being mounted in the semiconductor element mounting region, and being removable after being sealed with a resin;
An internal terminal support portion provided in a layered manner on a surface of the conductive substrate in a region including the semiconductor element mounting region and an internal terminal portion to which an electrode of the semiconductor element can be connected, and removable simultaneously with the conductive substrate; ,
A step is formed continuously on the surface of the internal terminal support part and the conductive substrate so as to straddle the region to be the internal terminal part in the internal terminal support part and the conductive substrate, A semiconductor element mounting substrate comprising: a layered lead portion whose bottom surface exposed when the conductive substrate is removed becomes an external terminal portion. The conductive substrate is made of a copper alloy,
The semiconductor element mounting substrate according to claim 1, wherein the internal terminal support portion is made of copper.   The substrate for mounting a semiconductor element according to claim 1, wherein the internal terminal portion includes a portion included in the semiconductor element mounting region so that the semiconductor element can be connected to the internal terminal portion by a flip chip method. .   4. The semiconductor element mounting substrate according to claim 1, wherein the internal terminal support portion and the lead portion are formed of a plating layer. 5.   The thickness of the said internal terminal support part is 20 micrometers or more and 100 micrometers or less, The board | substrate for semiconductor element mounting as described in any one of Claim 1 thru | or 4. A semiconductor element provided in a predetermined semiconductor element mounting region;
A layered first resin provided facing the semiconductor element and provided to include the semiconductor element mounting region in a top view;
The first resin is formed in a continuous layer with a step so as to straddle the first resin and the outside of the first resin, and the bottom surface of the outer region of the first resin is formed of the first resin. A lead portion provided to form the same surface continuous with the bottom surface, and having an internal terminal portion on the first resin and an external terminal portion on the external bottom surface of the first resin;
Connection means for electrically connecting the semiconductor element and the internal terminal portion;
A semiconductor device comprising: the semiconductor element excluding the bottom surface of the first resin and the external terminal portion; the top surface and side surfaces of the lead portion; and a second resin that seals the connection means. The internal terminal portion has a portion overlapping the semiconductor element in a top view,
The semiconductor device according to claim 6, wherein the semiconductor element and the internal terminal portion are connected by a flip chip method.   The semiconductor device according to claim 6, wherein the lead portion includes a plating layer. Forming a first plating layer on the conductive substrate so as to include a region to be a semiconductor element mounting region and an internal terminal portion; and
A step is continuously straddled across the surface of the region to be the internal terminal portion in the first plating layer and the surface of the conductive substrate outside the first plating layer. Forming a lead portion by forming a second plating layer, and a method of manufacturing a substrate for mounting a semiconductor element. The conductive substrate is made of a copper alloy,
The method for manufacturing a substrate for mounting a semiconductor element according to claim 9, wherein the first plating layer is a copper plating layer.   The method for manufacturing a substrate for mounting a semiconductor element according to claim 9 or 10, wherein the first plating layer is formed so that at least a part of a region to be the internal terminal portion is included in the semiconductor element mounting region.   The method for manufacturing a substrate for mounting a semiconductor element according to claim 9, wherein the first plating layer is formed to a thickness of 20 μm to 100 μm. A semiconductor element is mounted on the semiconductor element mounting region of the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to any one of claims 9 to 12, and an electrode of the semiconductor element is mounted. Electrically connecting to the internal terminal portion using a predetermined connection means;
A step of resin-sealing the conductive substrate with a first resin including the first plating layer, the second plating layer, the connection means, and the semiconductor element;
Removing the conductive substrate and the first plating layer;
Sealing the region where the first plating layer has been formed with a second resin.   The method of manufacturing a semiconductor device according to claim 13, wherein the electrode of the semiconductor element is connected to the internal terminal portion by a flip chip method.   15. The method of manufacturing a semiconductor device according to claim 13, wherein the conductive substrate and the first plating layer are removed by dissolution.

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