JP2016178345A - Solid state imaging element, solid state imaging element manufacturing method and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging element which achieves refinement and high-speed reading operation.SOLUTION: A solid state imaging element includes: a semiconductor substrate on which a pixel region where pixels each including a photoelectric conversion element and an amplification MOS transistor for outputting a signal corresponding to charge of the photoelectric conversion element to a column signal line are arranged; and a peripheral circuit region including a circuit for driving the pixel or processing the signal output to the column signal line are arranged, in which resistance of a source region of the amplification MOS transistor is lower than resistance of a drain region of the amplification MOS transistor.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging system.

  As a solid-state image sensor, there is a MOS type solid-state image sensor having a pixel region and a peripheral circuit region. The pixel region includes a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to the column signal line. The peripheral circuit region includes a pixel region and a circuit for processing the pixel or processing a signal output to the column signal line. As a cause of noise generated in the MOS type solid-state imaging device, there is a hot carrier generated in the MOS transistor. Hot carriers are carriers generated when a strong electric field is applied to a PN junction composed of a drain region and a channel end when a voltage is applied to the gate of a MOS transistor. Noise generated by such hot carriers can be a particular problem in devices that handle minute signals such as MOS type solid-state imaging devices.

  As an example of this noise reduction method, the impurity concentration in the source region and drain region of the MOS transistor in the pixel region is made lower than that in the peripheral circuit region. Further, there is a method in which the peripheral MOS transistor in the peripheral circuit region has an LDD (Lightly Doped Drain) structure. By this method, the source region and the drain region can be formed under conditions suitable for the pixel region and the peripheral circuit region. Specifically, since the electric field strength between the channel and the drain region formed under the gate of the peripheral MOS transistor is relaxed, the influence of hot carriers can be reduced. Furthermore, since the MOS transistor in the pixel region is not made into an LDD structure, an etching process for forming a side spacer on the side wall of the gate electrode in the pixel region is unnecessary, thereby reducing the influence of noise such as dark current due to etching damage. It becomes possible to do. Although the drain region of the MOS transistor in the pixel region does not have the LDD structure, since the impurity concentration is low, the influence of hot carriers can be reduced even in the MOS transistor in the pixel region.

JP 2008-041726 A

  In recent years, solid-state imaging devices are required to have finer pixels and higher numbers of pixels while maintaining or improving photoelectric conversion characteristics such as sensitivity and dynamic range. In order to realize this requirement, it is effective to reduce the driving voltage of the elements in the pixel region and to reduce the area other than the photoelectric conversion elements in the pixel region while suppressing the reduction in the area of the photoelectric conversion elements. .

However, by reducing the size of the MOS transistor for reading a signal based on the signal charge of the photoelectric conversion element arranged in the pixel region, the driving capability of the MOS transistor can be reduced. In particular, when the impurity concentration of the source / drain region of the MOS transistor in the pixel region is lowered in order to reduce the influence of hot carriers, the source resistance of the MOS transistor increases. For this reason, the driving capability of the MOS transistor does not increase, which is disadvantageous for a high-speed read operation.
An object of the present invention is to provide a technique advantageous in reducing noise and improving the driving capability of an amplification MOS transistor in a pixel region.

  The solid-state imaging device of the present invention includes a pixel region in which a pixel including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to a column signal line, and driving of the pixel or the A peripheral circuit region including a circuit for processing a signal output to the column signal line is a solid-state imaging device disposed on a semiconductor substrate, and a resistance of a source region of the amplification MOS transistor is a drain of the amplification MOS transistor It is characterized by being lower than the resistance of the region.

  According to the present invention, it is possible to reduce noise and improve the driving capability of the amplification MOS transistor in the pixel region.

1 is a schematic plan view of a solid-state image sensor according to an embodiment of the present invention. It is the top view and sectional drawing of the amplification MOS transistor of the solid-state image sensor of embodiment of this invention. It is the top view and sectional drawing of the amplification MOS transistor of the solid-state image sensor of embodiment of this invention. It is a circuit diagram of a pixel of a solid-state image sensor of an embodiment of the present invention. It is a typical sectional view of the solid-state image sensing device of a 1st embodiment. It is a manufacturing process flowchart of the solid-state image sensor of 1st Embodiment. It is a typical sectional view of the solid-state image sensing device of a 3rd embodiment. It is a typical sectional view of a solid-state image sensing device for explaining an embodiment of the present invention. It is the top view and sectional drawing of the amplification transistor of the solid-state image sensor of 4th Embodiment. It is a block diagram for demonstrating the imaging system using a solid-state image sensor.

Next, exemplary embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In addition, this invention is not limited to each embodiment, It can combine and change in the range which does not exceed the main point of invention. In each embodiment, a specific MOS transistor has been described as an example. However, the structure of each embodiment can be applied to all MOS transistors arranged in each region.
(First embodiment)
FIG. 1 shows a plan layout of a solid-state image sensor. Reference numeral 111 denotes a pixel region. When the solid-state imaging device is configured as a linear sensor, a plurality of pixels are arranged in a pixel area in a one-dimensional manner. Further, when the solid-state imaging device is configured as an image sensor, a plurality of pixels are arranged in a two-dimensional manner, that is, in a plurality of rows and columns. A pixel is a minimum unit of an element assembly including one photoelectric conversion element and an element for outputting a signal from the photoelectric conversion element to a column signal line. Examples of the configuration that can be included in the element assembly include a transfer unit, an amplification unit, and a reset unit. The transfer unit includes a transfer MOS transistor that transfers charges from the photoelectric conversion element to the floating diffusion unit. The amplifying unit includes an amplifying MOS transistor that outputs a signal converted into a voltage by the floating diffusion unit. The reset unit includes a reset MOS transistor that resets the voltage of the floating diffusion unit to a reset voltage. It is possible to share the amplification unit and the reset unit in adjacent pixels, but in this case as well, the pixel is defined as the minimum unit of an element assembly for reading a signal of one photoelectric conversion element.

Reference numeral 112 denotes a signal processing circuit including a circuit that amplifies a signal read from the pixel region 111. In addition to the amplifier circuit, the signal processing circuit 112 may include, for example, a circuit that removes noise generated in the pixels by CDS (Correlated Double Sampling) processing. The signal processing circuit 112 may include a circuit for simply converting signals read in parallel from a plurality of columns into serial signals.
Reference numeral 113 denotes a vertical shift register for driving each pixel arranged in the pixel region 111. Reference numeral 114 denotes a horizontal shift register for driving the signal processing circuit 112. When AD conversion is performed in the solid-state imaging device, an AD conversion circuit may be included in the solid-state imaging device. The signal processing circuit 112, the vertical shift register 113, and the horizontal shift register 114 are circuits arranged in the peripheral circuit area.

  FIG. 4 shows an example of one pixel arranged in the pixel region 111. The pixel includes, for example, a photoelectric conversion element 1, a transfer MOS transistor (transfer unit) 2, a reset MOS transistor (reset unit) 4, and an amplification MOS transistor (amplification unit) 5. The pixel can be selected by the voltage supplied to the drain of the reset MOS transistor 4. This selection is made by a vertical shift register. The photoelectric conversion element 1 is a photodiode, for example, and converts incident light into electric charge by photoelectric conversion and accumulates it. The transfer MOS transistor 2 transfers the charge accumulated in the photoelectric conversion element 1 to a floating diffusion (floating diffusion region: FD) 3 that is an input portion of the amplification MOS transistor. A source follower circuit can be configured by the amplification MOS transistor 5, the constant current source 6, the power supply 7, and the column signal line 8. The amplification MOS transistor 5 can output the potential of the floating diffusion 3 to the column signal line 8 by the source follower operation. Charges are amplified and output by such source follower operation. In this example, the selection operation of the target pixel to be read is performed by the drain voltage of the reset MOS transistor 4, but a selection MOS transistor may be provided to perform selection. The selection MOS transistor is arranged in an electrical path between the source of the amplification MOS transistor 5 and the column signal line 8. Alternatively, the selection MOS transistor is arranged in an electrical path between the drain of the amplification transistor 5 and the power supply 7.

  In order to understand the present invention, a solid-state imaging device will be described in which the impurity concentration in the source region and drain region of the MOS transistor in the pixel region is lower than that in the peripheral circuit region, and the peripheral MOS transistor has an LDD structure. FIG. 8 is a schematic cross-sectional view of a solid-state imaging device. The solid-state imaging device includes a pixel area 101 and a peripheral circuit area 102. The pixel region 101 includes an amplification MOS transistor 909 for reading a signal from the photoelectric conversion element. The peripheral circuit region 102 includes, for example, a MOS transistor 910 that constitutes any one of a signal processing circuit 112, a vertical shift register 113, and a horizontal shift register 114 signal.

  An LDD structure is adopted for the source / drain regions of the peripheral MOS transistor 910. In the LDD structure, a semiconductor region 911 having a high impurity concentration is formed in an intermediate region closer to the channel than the semiconductor region 916 to such an extent that the driving capability of the MOS transistor is not impaired. Further, the semiconductor region 914 has a lower impurity concentration than the semiconductor region 911 and closer to the channel than the intermediate region. The semiconductor region 914 is formed under the side spacer 913 and serves as an electric field relaxation layer for hot carriers. Further, a semiconductor region 916 exhibiting low resistance and ohmic properties is formed under the contact hole 915. The impurity concentration of the semiconductor region 916 is higher than that of the semiconductor region 911. The source region and drain region of the MOS transistor 909 disposed in the pixel region have a single drain structure. The impurity concentration of the source region and drain region of the MOS transistor 909 disposed in the pixel region 101 is lower than the impurity concentration of the semiconductor region 911 of the peripheral MOS transistor 910, and functions as an electric field relaxation layer so as not to cause hot carriers.

In the pixel region where the electric field needs to be relaxed for the purpose of miniaturization or the like, it is necessary to form a wide electric field relaxation layer. In consideration of etching damage when the side spacer is formed on the gate side wall, it is advantageous not to adopt the LDD structure in the pixel region. On the other hand, when the electric field relaxation layer is wide or the impurity concentration is too low, the parasitic resistance (series resistance) of the transistor increases, resulting in a significant loss of the driving capability of the transistor. Therefore, it is desirable that the resistance of the source region of the amplification MOS transistor, in which drive capability is particularly important, be kept low.
In the embodiment of the present invention, the structure of the source region and the drain region of the amplifying MOS transistor is mutually changed in order to achieve both the miniaturization of the solid-state imaging device and the improvement of the driving capability of the amplifying MOS transistor. Specifically, the resistance of the source region of the amplification MOS transistor disposed in the pixel region is set lower than the resistance of the drain region. This can be done, for example, by making the impurity concentration of the source of the amplification MOS transistor higher than the impurity concentration of the drain of the amplification MOS transistor.
The relationship between the impurity concentration of the source region and the drain region of the amplification MOS transistor will be described with reference to FIG. FIG. 2A is a plan view of an amplification MOS transistor arranged in the pixel region, and FIG. 2B is a cross-sectional view taken along line AA ′. The amplification MOS transistor includes a gate electrode 2001, a source region 2002, a drain region 2003, and a contact plug connection region (first region) 2004. A contact plug connection region 2004 is provided corresponding to each of the source region 2002 and the drain region 2003. In some cases, the contact plug connection region 2004 is disposed only in one of the source region 2002 and the drain region 2003. In the contact plug connection region 2004, the contact plug connection regions 2004 corresponding to the source region and the drain region may have the same impurity concentration. The source region 2002 includes a semiconductor region (second region) 2005 disposed between the channel region 2007 and the connection region 2004. The drain region 2003 includes a semiconductor region (third region) 2006 disposed between the channel region 2007 and the connection region 2004. The semiconductor region 2005 has a higher impurity concentration than the semiconductor region 2006. Thus, by making the impurity concentration of the source region higher than the impurity concentration of the drain region, it becomes possible to improve the driving capability of the amplification MOS transistor arranged in the pixel region. In addition, hot carriers of the MOS transistor arranged in the pixel region can be reduced. Further, in the pixel region, the side spacer forming step is not required because the LDD structure is not adopted. As a result, it is not damaged by the etching process for forming the LDD structure.

FIG. 5 is a schematic cross-sectional view of the pixel region 101 and the peripheral region 102 of the solid-state imaging device of the present embodiment. In the pixel region 101 of FIG. 5, cross-sectional structures of the photoelectric conversion element 1, the transfer MOS transistor 2, and the amplification MOS transistor 5 are shown. In the peripheral circuit region 102, MOS transistors constituting any one of the signal processing circuit 112, the vertical shift register 113, and the horizontal shift register 114 are shown. The solid-state imaging device shown in FIG. An n-type or p-type well 39 is formed in the semiconductor substrate 38, and a semiconductor region that becomes the photoelectric conversion element 1 and the MOS transistor is formed in the well 39.
In the pixel region 101 of FIG. 5, the first conductivity type semiconductor region 33 constituting the photoelectric conversion element 1 is n-type when the charge accumulated in the photoelectric conversion element 1 is an electron. The transfer MOS transistor 2 includes a gate electrode 31, a semiconductor region 33 that functions as a source, and a semiconductor region 3 that functions as a drain. The semiconductor region 33 is common to the source region of the transfer MOS transistor 2 and the semiconductor region constituting the photoelectric conversion element 1. The semiconductor region 3 is common to the semiconductor region constituting the source of the reset MOS transistor (not shown) and the floating diffusion (FD) 3. The amplification MOS transistor 5 has a gate electrode 32, a semiconductor region 34a functioning as a drain, and a semiconductor region 34b functioning as a source. A reference voltage for pixel selection can be applied to the semiconductor region 34a. A silicon nitride film 36a and a silicon oxide film 37a are sequentially stacked on the surface of the semiconductor substrate. The silicon nitride film 36a and the silicon oxide film 37a constitute an insulating film. The insulating film composed of the silicon nitride film 36 a and the silicon oxide film 37 a covers all regions except the contact bottom of the pixel region 101. Furthermore, the silicon nitride film 36a and the silicon oxide film 37a can constitute an antireflection film that reduces reflection on the surface of the photoelectric conversion element. This insulating film is not limited to a combination of a silicon nitride film and a silicon oxide film. A conductor such as contact plug 41a is in contact with the semiconductor region. The FD 3 is connected to the gate electrode of the amplification MOS transistor through an electrode (not shown), and the semiconductor region 34a is also connected to an amplification reference voltage wiring (not shown) through the electrode.

In the peripheral circuit region 102 of FIG. 5, the impurity concentration of the semiconductor region 43 that becomes the source region or drain region of the MOS transistor 42 having the LDD structure is higher than that of the semiconductor region 44 that becomes the electric field relaxation layer. A silicon nitride film 36b and a silicon oxide film 37b constituting side spacers are formed on the side surfaces of the gate electrode 42.
By forming the silicon nitride film 36a and the silicon oxide film 37a in the pixel region 101 and the silicon nitride film 36b and the silicon oxide film 37b to be side spacers in the peripheral circuit region 102 in the same process, the manufacturing cost can be kept low. .
Further, the silicon nitride film 36a and the silicon oxide film 37a in the pixel region can be used as a mask when the high impurity concentration semiconductor region 43 in the peripheral circuit region 102 is formed by ion implantation. Since it is not necessary to provide a mask again, the manufacturing cost can be kept low.

In the pixel region 101, the amplification MOS transistor 5 has a single drain structure, and the drain region 34a is formed of a semiconductor region having a lower impurity concentration than the source region 34b. Therefore, deterioration of transistor characteristics due to hot carriers can be suppressed as compared with an LDD structure in which a drain region includes a semiconductor region with a high impurity concentration.
In this manner, in the pixel region 101, the source region 34b of the amplification MOS transistor is formed of a semiconductor region having a higher impurity concentration than the drain region 34a of the amplification MOS transistor, so that the resistance of the source region 34b is lower than that of the drain region 34a. it can. Compared to the drain region side, the source region where a high electric field is not required does not need to consider the influence of hot carriers. The single drain structure is more suitable for miniaturization than the LDD structure in which the side spacer is formed on the gate side wall, and can reduce noise such as dark current due to etching damage when the side spacer is formed.

  In the semiconductor regions 3, 34a, and 34b of the MOS transistor disposed in the pixel region 101, the contact region that contacts the bottom of the contact plug 41a needs to secure an impurity concentration that can be electrically connected by metal wiring. This is preferably achieved by implanting impurities through the contact hole openings.

  Further, the silicon nitride film 36a in the pixel region 101 may be used as an etching stopper at the time of anisotropic dry etching that opens a contact hole in an interlayer insulating film 40 such as BPSG (Boron Phosphorus Silicon Glass). After anisotropic dry etching, anisotropic etching is performed under etching conditions having selectivity with respect to the silicon nitride film 36a and the silicon oxide film 37a to complete a contact hole. According to this method, the contact plug 41a does not come into contact with the element isolation region or the well 39 on the side surface even when the contact hole runs over the element isolation region due to misalignment during the etching of the interlayer insulating film. For this reason, the leakage current between the semiconductor regions 3, 34 a and 34 b and the well 39 can be suppressed. Therefore, the distance between the contact plug and the element isolation region can be shortened, and the element can be miniaturized.

  The silicon nitride films 36a and 36b can be films containing a large amount of hydrogen molecules. In this case, by performing a heat treatment at 350 ° C. or higher after forming the silicon nitride film, hydrogen diffuses into the semiconductor substrate, and a dangling bond termination effect is obtained. Such a silicon nitride film can be obtained by a plasma CVD method.

Next, a method for manufacturing a solid-state imaging device will be described with reference to FIGS.
First, as shown in FIG. 6A, a first conductivity type (n-type) well (not shown) and a second conductivity type (p-type) well 39 are formed on a semiconductor substrate 38 such as silicon. Next, an element isolation region 41 is formed by an STI (Shallow Trench Isolation) method, a selective oxidation method, or the like. 6A to 6F, the pixel region 101 and the peripheral circuit region 102 are drawn adjacent to each other.

  Subsequently, as shown in FIG. 6B, gate electrodes 31, 32, and 42 of the MOS transistor in the pixel region and the MOS transistor in the peripheral region are formed in the well 39 of the semiconductor substrate 38 by polysilicon. After this gate electrode formation step, an n-type impurity is introduced to form an n-type semiconductor region (storage region) 33 of the photodiode that constitutes the photoelectric conversion element. Next, a p-type semiconductor region 35 is formed on the surface of the n-type semiconductor region 33 in order to introduce a p-type impurity to form a buried photodiode. Then, n-type impurities are introduced by ion implantation (first implantation step) using the gate electrodes 31, 32, and 42 as a mask. Semiconductor regions 3, 34a, 34b, and 44 that are source regions and drain regions that are self-aligned with the gate electrode are formed in the source formation region (the source region) and the drain formation region (the drain region) on the side surface of the gate electrode. Form.

  Further, as shown in FIG. 6C, a resist 50 having an opening exposing the source region of the amplification MOS transistor is formed on the pixel region and the peripheral circuit region. Next, n-type impurities are introduced into the source region 34b of the amplification MOS transistor by selective ion implantation (second implantation step) using the gate electrode 32 as a mask. As a result, the impurity concentration of the source region 34b can be made higher than the impurity concentration of the drain region 34a of the amplification MOS transistor 5.

  Then, a thin silicon oxide film 30b is formed on the semiconductor substrate surface layer excluding the element isolation region and the gate electrode. The thin polysilicon oxide film may be formed by leaving the gate oxide film on the surface of the semiconductor substrate formed when anisotropic dry etching is performed to form a polysilicon gate electrode. Alternatively, a thin polysilicon film may be formed by thermal oxidation before depositing the silicon nitride film 36. Alternatively, a thin polysilicon film may be formed by depositing a silicon oxide film. Then, as shown in FIG. 6D, a silicon nitride film 36 is formed on the surface of the semiconductor substrate, and a silicon oxide film 37 is formed thereon. The silicon nitride film 36 and the silicon oxide film 37 are insulating films that cover the pixel region 101 and the peripheral circuit region 102.

  Next, a resist 51 is formed on the pixel region and etched back leaving a part of the silicon nitride film 36 and the silicon oxide film 37 on the side surface of the gate electrode 42 in the peripheral circuit region 102. Thus, as shown in FIG. 6E, side spacers made of the silicon nitride film 36b and the silicon oxide film 37b are formed on the side walls of the gate electrode 42 in the peripheral circuit region 102. Then, n-type impurities are introduced (third implantation step) using the gate electrode 42 and the side spacer in the peripheral circuit region 102 as a mask. As a result, the source region and the drain region that are self-aligned with the side surface of the side spacer can be formed into the semiconductor region 43 having a higher impurity concentration than the semiconductor region 44. At this time, the pixel region 101 may use the silicon nitride film 36 and the silicon oxide film 37 remaining on the entire surface as a mask. In this case, since it is not necessary to mask again, the manufacturing cost can be reduced. Thus, a structure as shown in FIG. 6E is obtained.

  Next, as illustrated in FIG. 6F, an interlayer insulating film 40 such as BPSG is formed so as to cover the entire pixel region 101 and the peripheral circuit region 102. Further, contact holes 41a and 41b are opened in the interlayer insulating film 40 by anisotropic dry etching. At this time, by using the silicon nitride film 36a in the pixel region as an etching stopper, a contact hole in which the contact region in contact with the contact bottom of the pixel region 101 is self-aligned is formed on the semiconductor substrate. Then, a contact plug is formed by filling the contact holes 41a and 41b with a conductor. In this way, the structure shown in FIG. 6F is obtained. In any step after the formation of the silicon oxide film, it is desirable to perform heat treatment at 350 ° C. or higher.

  In the above description, an example using an n-channel MOS transistor formed on a p-type semiconductor substrate has been described. However, when a solid-state imaging device is manufactured by a CMOS process, the p-channel type is similarly changed by changing the conductivity type. MOS transistors can be made. Since the p-channel MOS transistor has lower carrier mobility than the n-channel MOS transistor, it is important to increase the driving capability of the amplification MOS transistor in the pixel region as in this embodiment.

  As described above, in this embodiment, the amplification MOS transistor arranged in the pixel region has a single drain structure in which the source region is made of a semiconductor having a higher impurity concentration than the drain region. The MOS transistor arranged in the peripheral circuit region has an LDD structure. The low impurity concentration region of the drain region of the amplification MOS transistor arranged in the pixel region can be formed in the same process as the low impurity concentration region of the LDD structure of the MOS transistor arranged in the peripheral circuit region. The solid-state imaging device formed by such a process can achieve both suppression of characteristic deterioration due to hot carriers of the amplification MOS transistor in the pixel region and realization of high drive capability of the amplification MOS transistor.

In addition, when the antireflection film is used as an etching stopper, the contact hole in the pixel portion contacts only the surface of the semiconductor substrate in a self-aligning manner, so that leakage current between the source, drain and well of the MOS transistor can be suppressed.
Further, if the insulating film is used as an antireflection film and a contact etching stopper in the pixel region and is used as a side spacer of the MOS transistor in the peripheral circuit portion, the manufacturing cost can be reduced.
Further, when the insulating film is formed of a silicon nitride film containing a large amount of hydrogen molecules, trapping at the transistor interface or the silicon / silicon oxide film interface on the photodiode can be more effectively reduced.
(Second Embodiment)
In the present embodiment, an embodiment in which the resistance of the source of the amplification MOS transistor 5 is lower than the resistance of the drain will be described. 3A is a plan view of the amplification MOS transistor 5 arranged in the pixel region, and FIG. 3B is a cross-sectional view taken along the line AA ′.

The amplification MOS transistor 5 includes a gate electrode 2001, a source region 2002, a drain region 2003, a contact plug connection region 2004 (first region), and a channel region 2007. A contact plug connection region 2004 is provided corresponding to each of the source region 2002 and the drain region 2003. In some cases, the contact plug connection region 2004 is disposed only in one of the source region 2002 and the drain region 2003. Further, the source region of the amplification MOS transistor 5 includes a semiconductor region 2005 (second region) disposed between the channel region 2007 and the first region. The drain region of the amplification MOS transistor 5 includes a semiconductor region 2006 (third region) arranged between the channel region 2007 and the first region. The length in which the second region 2005 and the channel region 2007 are in contact is longer than the length in which the third region 2006 and the channel region 2007 are in contact. In other words, the channel of the amplification MOS transistor has a wider channel width at the source end than at the drain end. Here, the boundary of the channel region is defined by the element isolation part. Examples of the element isolation portion include field oxide film isolation, STI isolation, PN junction isolation, and EDI isolation. Although not shown, the channel region may be defined by the gate electrode. In this case, the channel is formed by making the gate width at the source end of the gate electrode wider than the gate width at the drain end.
The contact area between the source-side contact plug and the semiconductor region may be larger than the contact area between the drain-side contact plug and the semiconductor region. Therefore, the area of the first region corresponding to the source region may be larger than the second area corresponding to the drain region.

With such a structure, the resistance of the source region of the amplification MOS transistor arranged in the pixel region can be reduced, so that the driving capability of the amplification MOS transistor can be improved.
According to the structure in which the channel width on the drain side is smaller than the channel width on the source side of the amplification MOS transistor as shown in FIG. 3, the capacitance between the gate electrode and the drain region can be reduced. As a result, the capacity of the floating diffusion portion electrically connected to the gate electrode can be reduced. For this reason, it is possible to increase the gain for converting the read charge into a voltage. If the charge-voltage conversion gain in the floating diffusion portion is high, the subsequent noise can be relatively reduced. Further, Gm can be increased by keeping the channel width on the source side large. Therefore, it is possible to relatively reduce low frequency noise such as RTS noise even in the same gate area.
(Third embodiment)
In the present embodiment, the contact region of the drain region that is in direct contact with the conductor will be described. Generally, contact between a source and drain forming a MOS transistor and a conductor such as a contact plug that electrically connects a wiring pattern of a wiring layer is required to exhibit low resistance and ohmic characteristics. In a solid-state imaging device sensitive to point scratches caused by metal impurities, there may be a case where the process of forming silicide is not applied. Therefore, in the solid-state imaging device, it is important to make an ohmic contact between the drain region and the conductor.

  When the drain region of the MOS transistor arranged in the pixel region as in each of the above-described embodiments has an electric field relaxation structure, a method for forming a contact exhibiting low resistance and ohmic characteristics is required. The structure and manufacturing method of the solid-state imaging device that satisfies this will be described below. FIG. 7 shows a cross-sectional view of the solid-state imaging device of the present embodiment. Components having the same functions as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Reference numeral 101 denotes a floating diffusion (FD) 3 arranged in the pixel region, that is, a connection portion between the drain region of the transfer MOS transistor (here, n-type) and the conductor. Reference numeral 104 denotes a connection portion between the source region or drain region of the n-type MOS transistor disposed in the peripheral circuit portion and the conductor. Reference numeral 105 denotes a connection portion between the source region or drain region of the p-type MOS transistor disposed in the peripheral circuit region and the conductor.

  As shown at 101, the FD 3 has an n-type high impurity concentration semiconductor region 45 that is in direct contact with the conductor 41a. Similarly, 104 and 105 have n-type and p-type high impurity concentration semiconductor regions 45 and 46 in the source and drain regions. By applying the structure of the present embodiment, low resistance and good ohmic contact characteristics can be obtained in all the contact plugs (41a, 41b, 41c).

Next, a method for manufacturing a solid-state imaging device in the present embodiment will be described.
In the flow described in the first embodiment, the process up to FIG. Here, the impurity concentration of the low impurity concentration semiconductor region can be set to about 1 × 10 ¹⁷ / cm ³ ≦ d1 ≦ 5 × 10 ¹⁸ / cm ³ . Thereafter, contact holes are formed by anisotropic dry etching corresponding to the source region and drain region to be connected to the conductor. Thereafter, n-type impurities typified by phosphorus (P) are applied to the bottom of the contact with respect to the FD 3 disposed in the pixel region using the photomask and the bottom of the contact with respect to the semiconductor region 43 disposed in the peripheral circuit region 102. Introduce. In order to obtain contact with the semiconductor region 3 in the pixel region with low resistance and ohmic characteristics, the impurity concentration d2 of the semiconductor region directly in contact with the contact plug is 5 × 10 ¹⁸ / cm ³ ≦ d2 ≦ 5 × 10 ¹⁹ / cm ^3. It is desirable to set the dose amount to. In consideration of cost reduction, an n-type impurity may be introduced into the entire region without using a photomask.

Next, a p-type impurity typified by boron (B) is introduced into the source region, drain region, and conductor connecting portion 105 of the p-type MOS transistor disposed in the peripheral circuit region using a photomask. A p-type high concentration semiconductor region is formed. At this time, the n-type impurity may be introduced into the p-type semiconductor region by the above-described entire surface ion implantation of the n-type impurity. In this case, a mask pattern is formed so as to cover the entire source region, drain region, and conductor connecting portion 104 of the n-type MOS transistor disposed in the peripheral circuit region. Then, it is necessary to set the p-type impurity ion implantation conditions so as to exceed the concentration of the n-type impurity introduced by the entire surface ion implantation. For example, the dose amount at this time is about 1.0 × 10 ¹⁵ / cm ² so that the impurity concentration d3 of the region in direct contact with the contact plug is 5 × 10 ¹⁸ / cm ³ ≦ d3 ≦ 5 × 10 ¹⁹ / cm ^3. It is desirable to set to.

  The manufacturing method of this embodiment is applicable to the first embodiment and the second embodiment described above. Further, it can be applied to various MOS transistors arranged in the pixel region.

(Fourth embodiment)
The present embodiment is characterized in that the impurity concentration of the source region of the amplification MOS transistor included in the pixel is higher than the impurity concentration of the drain region.

  FIG. 1 shows a plan layout of the solid-state imaging device of the present embodiment. Reference numeral 111 denotes a pixel region. A plurality of pixels are arranged in the pixel region 111. The structure of the pixel region 111 and the structure of the pixel are the same as those of the solid-state imaging device of the first embodiment. Therefore, detailed description is omitted here. However, in this embodiment, the structure of the amplification MOS may be different from that of the solid-state imaging device of the first embodiment.

  Reference numeral 112 denotes a signal processing circuit including a circuit that amplifies a signal read from the pixel region 111. Reference numeral 113 denotes a vertical shift register for driving each pixel arranged in the pixel region 111. Reference numeral 114 denotes a horizontal shift register for driving the signal processing circuit 112. The signal processing circuit 112, the vertical shift register 113, and the horizontal shift register 114 are circuits arranged in the peripheral circuit area. Since these circuits are the same as those of the solid-state imaging device of the first embodiment, detailed description thereof is omitted.

  FIG. 4 shows an example of one pixel arranged in the pixel region 111. The pixel circuit of the solid-state image sensor of this embodiment is the same as the pixel circuit of the solid-state image sensor of the first embodiment. Therefore, detailed description is omitted here.

  In this embodiment, the impurity concentration in the drain region of the MOS transistor in the pixel region is lower than the impurity concentration in the peripheral region, and the MOS transistor in the peripheral circuit region has an LDD structure. FIG. 8 is a schematic cross-sectional view of the solid-state imaging device of the present embodiment. The solid-state imaging device includes a pixel area 101 and a peripheral circuit area 102. The pixel region 101 includes an amplification MOS transistor 909 for reading a signal from the photoelectric conversion element. The peripheral circuit region 102 includes, for example, a MOS transistor 910 that constitutes any one of a signal processing circuit 112, a vertical shift register 113, and a horizontal shift register 114 signal.

  An LDD structure is employed for the source / drain regions of the MOS transistor 910 in the peripheral circuit region. The LDD structure includes a semiconductor region 911 having a high impurity concentration to such an extent that the driving capability of the MOS transistor is not impaired, and a semiconductor region 914 having a lower impurity concentration than the semiconductor region 911. The semiconductor region 914 is formed under the side spacer 913 and serves as an electric field relaxation layer for hot carriers. Further, a semiconductor region 916 exhibiting low resistance and ohmic properties is formed under the contact hole 915. The impurity concentration of the semiconductor region 916 is higher than that of the semiconductor region 911. The drain region of the MOS transistor 909 arranged in the pixel region has a single drain structure. The impurity concentration of the drain region of the MOS transistor 909 disposed in the pixel region 101 is lower than the impurity concentration of the semiconductor region 911 of the MOS transistor 910 disposed in the peripheral region, and acts as an electric field relaxation layer so as not to cause hot carriers. . In the present embodiment, the source region of the MOS transistor 909 disposed in the pixel region 101 may have any structure. For example, the source region of the MOS transistor 909 may have an LDD structure. Further, the impurity concentration of the source region of the MOS transistor 909 may be higher than or similar to the impurity concentration of the source region or the drain region of the MOS transistor 910 disposed in the peripheral region 102.

In the pixel region where the electric field needs to be relaxed for the purpose of miniaturization or the like, it is necessary to form a wide electric field relaxation layer. In consideration of etching damage when the side spacer is formed on the gate side wall, it is advantageous not to adopt the LDD structure in the pixel region. On the other hand, when the electric field relaxation layer is wide or the impurity concentration is too low, the parasitic resistance (series resistance) of the transistor increases, resulting in a significant loss of the driving capability of the transistor. Therefore, it is desirable that the resistance of the source region of the amplification MOS transistor, in which drive capability is particularly important, be kept low.
In the pixel region 101 of FIG. 8, the cross-sectional structures of the photoelectric conversion element 1, the transfer MOS transistor 2, and the amplification MOS transistor 909 are shown. In the peripheral circuit region 102, a MOS transistor 910 constituting any one of the signal processing circuit 112, the vertical shift register 113, and the horizontal shift register 114 is shown. The solid-state imaging device shown in FIG. 8 is configured on a semiconductor substrate. An n-type or p-type well is formed in the semiconductor substrate, and further, a semiconductor region to be the photoelectric conversion element 1 and a MOS transistor is formed in the well.

  In the pixel region 101 of FIG. 8, the first conductivity type semiconductor region 903 constituting the photoelectric conversion element 1 is n-type when the charge accumulated in the photoelectric conversion element 1 is an electron. The transfer MOS transistor 2 includes a gate electrode 901, a semiconductor region 903 that functions as a source, and a semiconductor region 914 that functions as a drain. The semiconductor region 903 is common to the source region of the transfer MOS transistor 2 and the semiconductor region constituting the photoelectric conversion element 1. The semiconductor region 914 is common with the semiconductor region that forms the source of the reset MOS transistor (not shown) and the floating diffusion (FD) portion 3. The amplification MOS transistor 909 includes a gate electrode 902, a semiconductor region 914 that functions as a drain, and a semiconductor region 914 that functions as a source. A power supply voltage can be applied to the drain region 914. A silicon nitride film and a silicon oxide film are sequentially stacked on the surface of the photoelectric conversion element 1. The silicon nitride film and the silicon oxide film constitute an insulating film. The insulating film formed of the silicon nitride film and the silicon oxide film may cover all regions except the contact bottom of the pixel region 101. Furthermore, an antireflection film that reduces reflection on the surface of the photoelectric conversion element can be constituted by the silicon nitride film and the silicon oxide film. This insulating film is not limited to a combination of a silicon nitride film and a silicon oxide film. A conductor such as a contact plug 915 is in contact with the semiconductor region. The FD portion 914 is connected to the gate electrode of the amplification MOS transistor through an electrode (not shown), and the drain region 914 of the amplification MOS transistor 909 is also connected to the power supply voltage wiring (not shown) through the electrode.

  In the peripheral circuit region 102 in FIG. 8, the impurity concentration of the semiconductor region 911 that becomes the source region or drain region of the MOS transistor 910 having the LDD structure is higher than that of the semiconductor region 914 that becomes the electric field relaxation layer. A silicon nitride film and a silicon oxide film that form side spacers are formed on the side surfaces of the gate electrode 912.

  By forming the silicon nitride film and silicon oxide film in the pixel region 101 and the silicon nitride film and silicon oxide film to be the side spacers in the peripheral circuit region 102 in the same process, the manufacturing cost can be kept low.

  In the semiconductor region 914 of the MOS transistor disposed in the pixel region 101 and the semiconductor region 911 of the MOS transistor disposed in the peripheral circuit region 102, the bottom of the contact plug 915 contacts. The contact portion needs to secure an impurity concentration that allows electrical connection by metal wiring. This is preferably achieved by implanting impurities through the contact hole openings.

  Further, the silicon nitride film in the pixel region 101 may be used as an etching stopper. For example, a silicon nitride film can be used as an etching stopper in anisotropic dry etching that opens a contact hole in an interlayer insulating film made of BPSG (Boron Phosphorus Silicon Glass) or the like. After anisotropic dry etching, anisotropic etching is performed under etching conditions having selectivity with respect to the silicon nitride film and the silicon oxide film to complete the contact hole. According to this method, even when the contact hole runs over the element isolation region due to misalignment during the etching of the interlayer insulating film, the contact plug 915 does not contact the element isolation region or the side well. For this reason, the leakage current between the semiconductor region and the well can be suppressed. Therefore, the distance between the contact plug and the element isolation region can be shortened, and the element can be miniaturized.

  Further, as the silicon nitride film, a film containing a large amount of hydrogen molecules can be used. In this case, by performing a heat treatment at 350 ° C. or higher after forming the silicon nitride film, hydrogen diffuses into the semiconductor substrate, and a dangling bond termination effect is obtained. Such a silicon nitride film can be obtained by a plasma CVD method.

  In the embodiment of the present invention, the structure of the source region and the drain region of the amplifying MOS transistor is mutually changed in order to achieve both the miniaturization of the solid-state imaging device and the improvement of the driving capability of the amplifying MOS transistor. Specifically, the impurity concentration in the source region of the amplification MOS transistor is higher than the impurity concentration in the drain region of the amplification MOS transistor. Thereby, the resistance of the source region of the amplification MOS transistor arranged in the pixel region can be made lower than the resistance of the drain region, so that the driving power of the amplification MOS transistor can be increased.

  Such an impurity concentration distribution will be described in detail with reference to FIG. FIG. 9A is a plan view of the amplification MOS transistor arranged in the pixel region, and FIG. 9B is a cross-sectional view taken along line BB ′. FIG. 9C is a cross-sectional view taken along the line BB ′ of the modified example of the present embodiment.

  The amplifying MOS transistor includes a gate electrode 3001, a source region 3002, and a drain region 3003. Furthermore, a source-side contact plug connection region 3004 and a drain-side contact plug connection region 3005 are included. Only one of the connection region 3004 and the connection region 3005 may be arranged, or both may not be arranged. In the case where the source region 3002 or the drain region 3003 also serves as a source region or a drain region of another transistor, a contact plug may not be provided.

  The source region 3002 includes a region 3006 disposed between the contact plug connection region 3004 and the gate electrode 3001. The drain region 3003 includes a region 3007 arranged between the contact plug connection region 3005 and the gate electrode 3001.

  In this embodiment, the relationship between the impurity concentrations of the two regions 3006 and 3007 is a characteristic part. First, in the cross section shown in FIG. 9B, the impurity concentration of the entire region 3006 is higher than the impurity concentration of the region 3007 having the highest impurity concentration. The relationship between the impurity concentrations in the other portions may be anything. For example, the impurity concentration of the drain-side connection region 3005 may be higher than the impurity concentration of the region 3006. In particular, in order to reduce the contact resistance between the contact plug 3005a and the drain region 3003, it is advantageous that the impurity concentration in the connection region 3005 is high. Further, the impurity concentration of the source region 3002 except for the region 3006 may be the same as or different from that of the region 3006. Further, the impurity concentration of the drain region 3003 excluding the region 3007 may be approximately the same as or different from that of the region 3007.

  As described above, the overall impurity concentration of the region 3006 is higher than the impurity concentration of the region 3007 having the highest impurity concentration, whereby the driving capability of the amplification MOS transistor can be improved and hot carriers can be reduced. .

  FIG. 9C shows a cross-sectional view of a modification of the present embodiment. In FIG. 9C, a region 3006 disposed between the contact plug connection region 3004 and the gate electrode 3001 in the source region 3002 includes a region 3006a and a region 3006b having different impurity concentrations. A region 3007 disposed between the contact plug connection region 3005 and the gate electrode 3001 in the drain region 3003 includes a region 3007a and a region 3007b having different impurity concentrations. In FIG. 9C, parts having the same structure as in FIG. 9B are denoted by the same reference numerals as in FIG. 9B.

  The impurity concentration of the region 3006a is higher than the impurity concentration of the region 3006b. The region 3006b is disposed between the region 3006a and the gate electrode 3001. The impurity concentration of the region 3007a is higher than the impurity concentration of the region 3007b. The region 3007b is disposed between the region 3007a and the gate electrode 3001. The impurity concentration of the region 3006a is higher than the impurity concentration of the region 3007a. On the other hand, the region 3006b and the region 3007b have substantially the same impurity concentration. That is, only a part of the region 3006 disposed between the source-side contact plug connection region 3004 and the gate electrode 3001 may have a higher impurity concentration than the region 3007.

  As described above, the impurity concentration of at least a part of the region 3006 is higher than the impurity concentration of the region 3007 having the highest impurity concentration, thereby improving the driving capability of the amplification MOS transistor and reducing hot carriers. It becomes possible.

As described above, the impurity concentration in the source region of the amplification MOS transistor is higher than the impurity concentration in the drain region of the amplification MOS transistor. Thereby, the resistance of the source region of the amplification MOS transistor arranged in the pixel region can be made lower than the resistance of the drain region, so that the driving power of the amplification MOS transistor can be increased.
(Fifth embodiment)
FIG. 10 shows an example of a circuit block when the solid-state imaging device according to the present invention is applied to an imaging system.

The optical system includes a photographic lens 1002, a shutter 1001, and a diaphragm 1003, and forms an image of a subject on the solid-state image sensor 1004.
An output signal from the solid-state imaging device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The output digital signal is further processed by a signal processing unit 1007. The processed digital signal is stored in the memory 1010 or sent to an external device through the external I / F 1013. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008, and the entire system is controlled by an overall control unit / arithmetic unit 1009. In order to record an image on the recording medium 1012, the output digital signal is recorded through a recording medium control I / F unit 1011 controlled by the overall control unit / arithmetic unit.

  1: photoelectric conversion element, 2: transfer MOS transistor, 3: semiconductor region, 5: amplification MOS transistor, 31: gate electrode, 32: gate electrode, 33: semiconductor region, 34a: drain region, 34b: source region, 35: Semiconductor region, 36: silicon nitride film, 37: silicon oxide film, 38: semiconductor substrate, 39: well, 40: interlayer insulating film, 41: contact portion, 101: pixel region, 102: peripheral circuit region

The solid-state imaging device according to the present invention includes a pixel region including a pixel including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to a charge generated in the photoelectric conversion element to a column signal line, and drives the pixel and a peripheral circuit region including a circuit for processing a circuit or a signal output to the column signal lines for, but a solid-state imaging elements arranged on a semiconductor substrate, in the amplifying MOS transistor, the channel region and the source region The length of the portion in contact with the channel region is longer than the length of the portion in contact with the channel region and the drain region, and the peripheral circuit region is provided with a peripheral MOS transistor constituting a part of the circuit, The source region and the drain region of the peripheral MOS transistor have the same structure.

Claims (11)

A pixel region including a pixel including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to a column signal line; and driving the pixel or a signal output to the column signal line A peripheral circuit region including a circuit for processing the solid-state imaging device disposed on the semiconductor substrate,
A solid-state imaging device, wherein a resistance of a source region of the amplification MOS transistor is lower than a resistance of a drain region of the amplification MOS transistor.   2. The solid-state imaging device according to claim 1, wherein an impurity concentration of the source region of the amplification MOS transistor is higher than an impurity concentration of the drain region of the amplification MOS transistor.   The length of a portion where the channel region of the amplification MOS transistor is in contact with the source region is longer than a length of a portion where the channel region of the amplification MOS transistor is in contact with the drain region. The solid-state imaging device according to 1. In the peripheral circuit region, a peripheral MOS transistor constituting a part of the circuit is arranged,
Each of the source region and the drain region of the peripheral MOS transistor includes a contact region in contact with a contact plug, an intermediate region closer to the channel than the contact region, and a region closer to the channel than the intermediate region,
The impurity concentration of the intermediate region is higher than the impurity concentration of the region closer to the channel than the intermediate region,
4. The solid-state imaging device according to claim 1, wherein an impurity concentration of the source region and the drain region of the amplification MOS transistor is lower than an impurity concentration of the intermediate region. 5. In the peripheral circuit region, a peripheral MOS transistor constituting a part of the circuit is arranged,
Each of the source region and the drain region of the peripheral MOS transistor includes a contact region in contact with a contact plug, an intermediate region closer to the channel than the contact region, and a region closer to the channel than the intermediate region,
The impurity concentration of the intermediate region is higher than the impurity concentration of the region closer to the channel than the intermediate region,
4. The solid-state imaging device according to claim 1, wherein an impurity concentration of the drain region of the amplification MOS transistor is lower than an impurity concentration of the intermediate region. 5. A pixel region including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to a column signal line, and a circuit for driving the pixel or the column signal line A peripheral circuit region including a circuit for processing the received signal is a solid-state imaging device disposed on a semiconductor substrate,
A solid-state imaging device, wherein an impurity concentration in a source region of the amplification MOS transistor is higher than an impurity concentration in a drain region of the amplification MOS transistor. A pixel region including a pixel including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to a column signal line; and driving the pixel or a signal output to the column signal line A peripheral circuit region including a circuit for processing the solid-state imaging device disposed on the semiconductor substrate,
The solid-state imaging device, wherein a length of a portion where the channel region and the source region of the amplification MOS transistor are in contact is longer than a length of a portion where the channel region and the drain region of the amplification MOS transistor are in contact. A pixel region including a pixel including a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to the charge of the photoelectric conversion element to a column signal line; and driving the pixel or a signal output to the column signal line A peripheral circuit region including a circuit for processing a solid-state imaging device disposed on a semiconductor substrate,
The manufacturing method includes:
A gate electrode forming step of forming a gate electrode of the amplification MOS transistor;
A first implantation step of implanting impurities into a source formation region where the source of the amplification MOS transistor of the semiconductor substrate and a drain formation region where a drain is to be formed are formed using the gate electrode as a mask;
A second implantation step of selectively injecting impurities into the source formation region of the source MOS formation region and the drain formation region of the amplification MOS transistor;
The manufacturing method of the solid-state image sensor characterized by including. In the gate electrode forming step, a gate electrode of the amplification MOS transistor and a gate electrode of a peripheral MOS transistor included in the peripheral circuit region are formed,
In the first implantation step, impurities are implanted into a source formation region where a source is to be formed and a drain formation region where a drain is to be formed, using the gate electrodes of the amplification MOS transistor and the peripheral MOS transistor as a mask. ,
The manufacturing method includes:
Forming an insulating film in the pixel region and the peripheral circuit region after the second implantation step;
The portions corresponding to the source and drain of the peripheral MOS transistor are removed from the insulating film formed in the peripheral circuit region so that a part of the insulating film remains on the side wall of the gate electrode of the peripheral MOS transistor. A removal step;
9. The method of manufacturing a solid-state imaging device according to claim 8, further comprising a third implantation step of implanting impurities into the semiconductor substrate using the insulating film as a mask after the removing step. Forming an insulating film in the pixel region and the peripheral circuit region;
Opening a contact hole for forming a contact plug in at least one of a region corresponding to a source region and a drain region of the amplification MOS transistor in the insulating film;
Implanting impurities into the semiconductor substrate through the contact holes;
9. The method of manufacturing a solid-state imaging device according to claim 8, further comprising forming a conductor in the contact hole to form the contact plug.   The solid-state imaging device according to claim 1, an optical system that forms an image of light on the solid-state imaging device, and a signal processing circuit that processes an output signal from the solid-state imaging device. An imaging system characterized by the above.

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