JP2015103860A - Power supply switching control circuit and power supply switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a power supply switching control circuit and a power supply switching circuit of low power consumption, with simple circuitry.SOLUTION: A power supply switching control circuit for selecting one of a plurality of power supply voltages and outputting that voltage to an output terminal includes a plurality of input power supply voltage detection circuits 11-1 to 11-n comparing the plurality of power supply voltages, respectively, with the voltage at the output terminal, and outputting the detection signals, respectively, when the values of the plurality of power supply voltages are larger than the voltage at the output terminal by a predetermined value Vth or more, and a control logic circuit 12 outputting the control signals for controlling a plurality of switches Q1-Qn, depending on the detection signals DET(1)-DET(n) outputted from the plurality of input power supply voltage detection circuits, respectively. One of a plurality of power supply voltages is selected by the control signal.

Description

  The present invention relates to a power supply switching control circuit and a power supply switching circuit.

  In recent years, mobile devices and the like can be operated with a plurality of power supplies (for example, a battery, a USB, a button battery, and the like). When a plurality of power supplies are connected in this way, it is necessary to select a desirable power supply as appropriate.

  A mobile device driven by a battery is capable of low power consumption and low voltage operation, which is a necessary element for realizing long-time driving. Therefore, for mobile devices that operate on a battery or the like, it is desired to reduce the power consumption of the battery. Furthermore, for mobile devices, a circuit that can operate properly even when the voltage of the power supply source is low is desired.

  To select the desired power supply from multiple power supplies in a timely manner, compare the voltages of multiple power supplies, turn on the switch connected to the power supply with the highest voltage, and turn off the switch connected to the other power supply (Cut off. In general, the voltages of a plurality of power supplies are constantly compared to detect the power supply with the highest voltage. In order to monitor such a power supply voltage, a detection circuit such as a comparator that constantly consumes current is used. Therefore, power consumption was large.

US Pat. No. 5,187,396

There is also a demand for reduction in power consumption in a power supply switching circuit and a power supply switching control circuit that are mounted on an electronic device and appropriately select a desired power supply from a plurality of power supplies.
The following embodiments describe a power switching control circuit and a power switching circuit with low power consumption.

  The power supply switching control circuit according to the first aspect includes a plurality of input power supply voltage detection circuits and a control logic circuit. The plurality of input power supply voltage detection circuits compares each of the plurality of power supply voltages with the voltage at the output terminal, and outputs a detection signal when each value of the plurality of power supply voltages is greater than the value of the output terminal voltage by a predetermined value or more. To do. The control logic circuit outputs a control signal for controlling the plurality of switches according to the detection signal output from each of the plurality of input power supply voltage detection circuits. The power supply switching control circuit according to the first aspect selects one power supply voltage among a plurality of power supply voltages based on the control signal.

  The power supply switching circuit according to the second aspect includes a plurality of power supply terminals, one output terminal, a plurality of switches, a plurality of input power supply voltage detection circuits, and a control logic circuit. The plurality of switches are respectively connected between the plurality of power supply terminals and the output terminal. The plurality of input power supply voltage detection circuits compare the voltage of the plurality of power supply terminals with the voltage of the output terminal, and each outputs a detection signal when the voltage of each of the plurality of power supply terminals is greater than a predetermined value by the output voltage. The control logic circuit outputs a control signal for controlling the plurality of switches according to the detection signal output from each of the plurality of input power supply voltage detection circuits. The power supply switching circuit according to the second aspect selects a voltage of one of the plurality of power supplies supplied to the plurality of power supply terminals and outputs the selected voltage to the output terminal.

  According to the embodiment, when the voltage of one of the power supplies becomes larger than the output voltage by a predetermined value or more, the corresponding input power supply voltage detection circuit outputs a detection signal, but when the control logic circuit turns on the corresponding switch The output voltage is the same as the switched power supply voltage. As a result, the input power supply voltage detection circuit stops outputting the detection signal, and the input power supply voltage detection circuit does not consume power.

FIG. 1 is a diagram illustrating a configuration of a power supply switching circuit according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a power supply switching circuit according to the second embodiment. FIG. 3 is a time chart showing an operation when power is supplied to the power supply terminal of the power supply switching circuit according to the second embodiment. FIG. 4 is a time chart illustrating an operation when the relationship between the voltages of the power supply terminals changes in the power supply switching circuit of the second embodiment. FIG. 5 is a diagram showing a circuit configuration of a control logic circuit, where (A) shows the overall configuration, (B) shows a circuit example of the delay circuit, and (C) shows the operation of the delay circuit. It is a time chart. FIG. 6 is a time chart showing an operation example of the control logic circuit. 7A and 7B are diagrams showing the configuration of the power supply switching circuit according to the third embodiment. FIG. 7A is a diagram showing the overall configuration, and FIG. 7B is a diagram showing the circuit configuration of the control logic (logic) circuit 12. FIG. 8 is a diagram illustrating an example of a multi-power supply compatible electronic device.

FIG. 1 is a diagram illustrating a configuration of a power supply switching circuit according to the first embodiment.
The power supply switching circuit of the first embodiment includes a plurality (N) of power supply terminals IN1 to INn, one output terminal OUT, a plurality of (power) switches Q1 to Qn, and a plurality of input power supply voltage detection circuits 11−. 1 to 11-n, a control logic circuit 12, and a capacitor C. The plurality of input power supply voltage detection circuits 11-1 to 11-n and the control logic (logic) circuit 12 form a power supply switching control circuit. The power supply switching control circuit controls the plurality of switches Q1 to Qn so that the highest voltage input power supply is selected from the plurality of power supplies input to the plurality of power supply terminals IN1 to INn and is output to the output terminal OUT. The capacitor C is provided to stabilize the output voltage at the output terminal OUT.

  The plurality of switches Q1 to Qn are realized by PMOS transistors, for example, and are connected between the plurality of power supply terminals IN1 to INn and the output terminal OUT, respectively. The plurality of switches Q1 to Qn are controlled by a plurality of control signals G (1) to G (n) output from the control logic circuit 12. Specifically, a plurality of control signals G (1) to G (n) are applied to the gates of a plurality of PMOS transistors forming the plurality of switches Q1 to Qn, respectively.

  The plurality of input power supply voltage detection circuits 11-1 to 11-n compares the voltages of the plurality of power supply terminals IN1 to INn with the voltage of the output terminal OUT. The plurality of input power supply voltage detection circuits 11-1 to 11-n receive the detection signals DET (1) to DET (n) when the voltages of the plurality of power supply terminals IN1 to INn are larger than the voltage of the output OUT by a predetermined value or more. Output. As described later, the predetermined value is, for example, a threshold voltage of a transistor.

  The control logic circuit 12 controls the plurality of switches Q1 to Qn according to the detection signals DET (1) to DET (n) output from the plurality of input power supply voltage detection circuits 11-1 to 11-n. (1) to G (n) are output. Specifically, when the detection signals DET (1) to DET (n) are generated, the control logic circuit 12 turns on (conducts) the switch corresponding to the generated detection signal and turns off (cuts off) the other switches. ) In other words, when the detection signal is generated, the control logic circuit 12 turns off the switch that was on until then, turns on the switch corresponding to the generated detection signal, and maintains the remaining switches in the off state. Therefore, when one of the plurality of power supplies input to the plurality of power supply terminals IN1 to INn becomes higher than the voltage of the output terminal OUT at that time, the switch is switched so that the power supply is immediately selected. In this way, an appropriate power source is selected from a plurality of power sources, and a power source having an appropriate voltage is always output from the output terminal OUT.

  When the input power supply voltage detection circuits 11-1 to 11-n are not outputting the detection signals DET (1) to DET (n), the power consumption is very small and almost zero. The input power supply voltage detection circuit outputs a detection signal when the voltage of the corresponding power supply terminal is larger than the voltage of the output terminal by a predetermined value or more. In response to the detection signal, the control logic circuit 12 turns on the corresponding switch. Therefore, the voltage at the output terminal OUT changes to the voltage at the corresponding power supply terminal. Therefore, the input power supply voltage detection circuit finishes outputting the detection signal in a short time. Therefore, the detection signal is generated for a short time, and power is consumed only during that period, and power is not consumed during other periods. Therefore, the power consumption of the plurality of input power supply voltage detection circuits 11-1 to 11-n is small.

  As described above, the power supply switching circuit according to the first embodiment selects an appropriate power supply (the power supply with the highest voltage) from a plurality of power supplies with a low power consumption and a simple circuit configuration, and connects to the output terminal. To do.

FIG. 2 is a diagram illustrating a configuration of a power supply switching circuit according to the second embodiment.
In the power supply switching circuit of the second embodiment, for simplicity of explanation, two power supply terminals (N = 2) are used, and the input power supply voltage detection circuits 11-1 to 11-2 are realized by transistors and resistors. The circuit is different from the power supply switching circuit of the first embodiment. The power supply switching circuit of the second embodiment automatically selects the power supply having the highest potential among the power supplies input to the two power supply terminals and connects it to the output terminal.

The power supply switching circuit according to the second embodiment includes two power supply terminals IN1 to IN2, one output terminal OUT, four PMOS transistors Q1, Q2, Q11 and Q12, and two resistors R1 and R2. , A control logic circuit 12 and a capacitor C. Two PMOS transistors Q1 and Q2 form a power switch. The PMOS transistor Q11 and the resistor R1 are connected in series between the power supply terminal IN1 and the reference potential source (GND), and the gate of Q11 is connected to the output terminal OUT. PMOS transistor Q11 and resistor R1 form a circuit corresponding to input power supply voltage detection circuit 11-1 in FIG. The PMOS transistor Q12 and the resistor R2 are connected in series between the power supply terminal IN2 and GND, and the gate of Q12 is connected to the output terminal OUT. PMOS transistor Q12 and resistor R2 form a circuit corresponding to input power supply voltage detection circuit 11-2 in FIG.
The power source of the control logic (logic) circuit 12 may be any power source as long as a potential always higher than the voltage of the power source terminals IN1 to IN2 or the output terminal OUT is compensated. You may supply so that conditions may be satisfy | filled.

  Power is input to each of the two power terminals IN1 and IN2. One of the terminals IN1 and IN2 is connected to the output terminal OUT via Q1 and Q2, and one power supply is output. Only one of Q1 and Q2 must be turned on and must not be turned on at the same time. When Q1 and Q2 are turned on at the same time, different power supplies are connected, that is, they are short-circuited.

  The PMOS transistor Q11 has a source terminal connected to the power supply IN1, a gate terminal connected to the output terminal OUT, and a drain terminal connected to the resistor R1. The PMOS transistor Q12 has a source terminal connected to the power supply IN2, a gate terminal connected to the output terminal OUT, and a drain terminal connected to the resistor R2. A detection signal DET (1) is output from the connection node of Q11 and R1, and a detection signal DET (2) is output from the connection node of Q12 and R2, and is input to the control logic (logic) circuit 12. When the detection signal DET (1) (pulse) is input, the control logic (logic) circuit 12 outputs a control signal G (1) for turning on Q1, and a control signal G (2) for turning off Q2. Further, when the detection signal DET (2) (pulse) is input, the control logic (logic) circuit 12 outputs a control signal G (1) for turning off Q1, and a control signal G (2) for turning on Q2.

  First, the operation of the input power supply voltage detection circuit 11-1 formed by Q11 and R1 and the input power supply voltage detection circuit 11-2 formed by Q12 and R2 will be described.

FIG. 3 is a time chart illustrating an operation when power is supplied to the power supply terminals IN1 and IN2 of the power supply switching circuit according to the second embodiment.
FIG. 3 shows a case where the power supply input to IN2 is fixed at 0V and the voltage of the power supply input to IN1 rises. In order to simplify the description, the voltage of the power supply input to IN1 and IN2 may be represented by IN1 and IN2, and the voltage of the output terminal OUT may be represented by OUT, and this is the same in other cases.

  In the stage before IN1 rises, IN1 and IN2 are 0V, and OUT is also 0V. The detection signals DET (1) and DET (2) are at a low level and no detection signal is output. Further, the control signals G (1) and G (2) are at a low level. This is a state in which Q1 and Q2 are turned on as the control signals because Q1 and Q2 are PMOS transistors. However, since IN1 and IN2 are 0V, Q1 and Q2 are off.

  As shown in FIG. 3, when IN1 rises and becomes IN1 = Vth (Q1 threshold), OUT follows IN1 via a body diode that is visible between D (drain) and S (source) on the PMOS structure of Q1. Then begin to rise. When the voltage between IN1 and OUT becomes equal to or higher than Vth, Q11 is turned on and the detection signal DET (1) becomes high level. The logic 12 starts the operation in response to the detection signal DET (1) becoming high level, and after setting both G (1) and G (2) to high level, in response to the detection signal DET (1). , G (1) is kept low and G (2) is kept high. Q1 and Q2 are PMOS transistors. When both G (1) and G (2) become high level, both Q1 and Q2 are once turned off, then Q1 is turned on and Q2 is kept off. .

  As described above, Q1 is turned on, Q2 is turned off, the voltage-increased power supply terminal IN1 is connected to the output terminal OUT, and the power supply terminal IN2 is not connected. This operation is the same when the power supply input to IN1 is fixed at 0V and the voltage of the power supply input to IN2 rises. IN1 and IN2, G (1) and G (2), and DET (1 ) And DET (2) time charts are simply interchanged.

Next, a case where the vertical relationship between the voltages of the power supply terminals IN1 and IN2 changes during operation will be described.
FIG. 4 is a time chart showing an operation when the voltage relationship between the power supply terminals IN1 and IN2 changes in the power supply switching circuit of the second embodiment. FIG. 4A shows a case where IN1 <IN2 and IN1 is constant, In2 descends and changes to IN1> IN2. FIG. 4B shows a case where IN1> IN2 and IN2 is constant, In1 descends and changes to IN1 <IN2. FIG. 4C shows a case where IN1 <IN2, IN2 is constant, In1 rises and changes to IN1> IN2. FIG. 4D shows a case where IN1> IN2 and IN1 is constant, In2 rises and changes to IN1 <IN2.

  As shown in FIG. 4A, since IN2> IN1, G (2) = low level (Q2 = on), G (1) = high level (Q1 = off), and the output terminal OUT Outputs the same voltage as IN2. Q12 is off because Q2 is on and the gate terminal and the source terminal of Q12 are at the same potential. On the other hand, Q11 is OFF because IN1 <OUT (= IN2) and the gate terminal of Q11 is higher than the source terminal (IN1) of Q11. In other words, both Q11 and Q12 are off, and the current consumption for detection is zero.

  When the voltage of IN2 drops from the above state and OUT (= IN2) <In1-Vth (Vth: threshold voltage of Q11, Q12), Q11 is turned on, a current flows through the resistor R1, and DET (1) is Change to high level. The control logic (logic) circuit 12 sets G (2) to a high level by using a change of DET (1) to a high level as a trigger, and Q2 is turned off. After Q2 is turned off, the control logic (logic) circuit 12 sets G (1) to a low level and Q1 is turned on. When Q1 is turned on, the gate voltage and the source voltage of Q11 become the same potential, Q11 is turned off, so that the current flowing through R1 becomes zero, and DET (1) changes to a low level. Therefore, the current flows through R1 for a short time and power consumption is small.

  As shown in FIG. 4B, since IN1> IN2, G (1) = low level (Q1 = on), G (2) = high level (Q2 = off), and the output terminal OUT Outputs the same voltage as IN1. Q11 is off because Q1 is on and the gate terminal and the source terminal of Q11 are at the same potential. On the other hand, Q12 is OFF because IN2 <OUT (= IN1) and the gate terminal of Q12 is higher than the source terminal (IN2) of Q12. In other words, both Q11 and Q12 are off, and the current consumption for detection is zero.

  When the voltage of IN1 drops from the above state and OUT (= IN1) <In2-Vth, Q12 is turned on, a current flows through the resistor R2, and DET (2) changes to a high level. The control logic (logic) circuit 12 sets G (1) to a high level, triggered by a change in DET (2) to a high level, and Q1 is turned off. After Q1 is turned off, the control logic (logic) circuit 12 sets G (2) to a low level and Q2 is turned on. When Q2 is turned on, the gate voltage and the source voltage of Q12 become the same potential, Q12 is turned off, so that the current flowing through R2 becomes zero, and DET (2) changes to a low level. Therefore, the current flows through R2 for a short time and power consumption is small.

  As shown in FIG. 4C, since IN2> IN1, G (2) = low level (Q2 = on), G (1) = high level (Q1 = off), and the output terminal OUT Outputs the same voltage as IN2. Q11 and Q12 are both off.

  When the voltage of IN1 rises from the above state and OUT (= IN2) <In1-Vth, Q11 is turned on, a current flows through the resistor R1, and DET (1) changes to a high level. The control logic (logic) circuit 12 sets G (2) to a high level by using a change of DET (1) to a high level as a trigger, and Q2 is turned off. After Q2 is turned off, the control logic (logic) circuit 12 sets G (1) to a low level and Q1 is turned on. When Q1 is turned on, the gate voltage and the source voltage of Q11 become the same potential, Q11 is turned off, so that the current flowing through R1 becomes zero, and DET (1) changes to a low level. Therefore, the current flows through R1 for a short time and power consumption is small.

  As shown in FIG. 4D, since IN1> IN2, G (1) = low level (Q1 = on), G (2) = high level (Q2 = off), and the output terminal OUT Outputs the same voltage as IN1. Q11 and Q12 are both off.

  When the voltage of IN2 rises from the above state and OUT (= IN1) <In2-Vth, Q12 is turned on, a current flows through the resistor R2, and DET (2) changes to a high level. The control logic (logic) circuit 12 sets G (1) to a high level, triggered by a change in DET (2) to a high level, and Q1 is turned off. After Q1 is turned off, the control logic (logic) circuit 12 sets G (2) to a low level and Q2 is turned on. When Q2 is turned on, the gate voltage and the source voltage of Q12 become the same potential, Q12 is turned off, so that the current flowing through R2 becomes zero, and DET (2) changes to a low level. Therefore, the current flows through R2 for a short time and power consumption is small.

  Since OUT is the voltage of IN1 or IN2, and Q11 and Q12 are turned on by the voltage difference between IN1, IN2, and OUT, DET (1) and DET (2) do not change to a high level at the same time.

  In a steady state where there is no change in the magnitude relationship between IN1 and IN2, even if the drain current of the transistor on which Q1 or Q2 is on changes, the drain end-source end differential voltage (VDS) is Q11 or Q12. Must be smaller than the absolute threshold (| Vth |). When Q1 is on, switching is not performed if (IN1-OUT) (= VDS) <| Vth (Q11) |.

As described above, the power supply switching circuit of the second embodiment has the following advantages.
(1) There is no current consumption of the circuit for monitoring the magnitude relation of the input voltage.
(2) It operates from an input voltage that is about the threshold voltage of Q11 and Q12.
(3) The threshold value of Q11 and Q12 also realizes hysteresis in switching and prevents frequent switching.

Next, the configuration and operation of the control logic circuit 12 that realizes the above control will be described.
FIG. 5 is a diagram showing a circuit configuration of the control logic (logic) circuit 12, (A) shows the overall configuration, (B) shows a circuit example of the delay circuit, and (C) shows the operation of the delay circuit. It is a time chart which shows.

  As shown in FIG. 5A, the control logic circuit 12 includes two detection control units 21-1 and 21-2 corresponding to two detection signals DET (1) and DET (2). 1 common portion 22. The two detection control units 21-1 and 21-2 have the same configuration except that the input is DET (1) or DET (2) and the output is G (1) or G (2). Have. As illustrated, the detection control units 21-1 and 21-2 include two D-type FFs 31, 32, a NAND gate, and a plurality of inverters. Since the configuration of the circuit is clear from the figure, the description is omitted and the operation will be described later.

  As shown in FIG. 5A, the common unit 22 receives signals G (1) and G (2) and outputs from the detection control units 21-1 and 21-2 and generates signals C and D. And it outputs to the detection control parts 21-1 and 21-2 in common. As shown in the figure, the common unit 22 includes one D-type FF 33, a delay circuit 34, and three NAND gates. Since the configuration of the circuit is clear from the figure, the description is omitted and the operation will be described later.

  The delay circuit 34 has the circuit configuration shown in FIG. 5B, and delays the input IN and outputs the output OUT as shown in FIG. 5C. The delay amount is set according to the value of the capacitance connected to the output of the inverter shown in FIG. Since the delay circuit of FIG. 5B is widely known, further explanation is omitted.

  FIG. 6 is a time chart showing an operation example of the control logic circuit 12. FIG. 6 is a time chart when the voltage of IN2 decreases and the detection signal DET (1) is generated from the state where the voltage of IN1 <the voltage of IN2.

  When the voltage of IN2 becomes OUT (= IN2) <IN1 + Vth, DET (1) changes to a high level as described above. Using this as a trigger, D-type FF 31 is set, DET (1) 1 changes to high level, / Q of D-type FF 31 input to common unit 22 changes to low level, and signal A of common unit 22 changes to high level. At the same time, C changes to a low level. At this time, since DET (2) does not change, DET (2) 1 of the detection control unit 21-2 does not change.

  Since the signal C changes to a low level, the D-type FF 32 is reset in the detection control units 21-1 and 21-2, and G (1) and G (2) are at a high level (G (1) is originally High level). As a result, both Q1 and Q2 are turned off. In response to both G (1) and G (2) becoming high level, the signal B1 of the common section 22 changes to low level, and further the signal C becomes high level. (1) Change according to the state of 1 (high level), and G (1) changes to a low level. At this time, in the detection control unit 21-2, since DET (2) 1 is at a low level, G (2) is maintained at a high level. In this way, G (1) and G (2) are determined, Q1 is turned on, and Q2 is turned off.

  On the other hand, since the signal C becomes high level, the D-type FF 33 is in an operating state. When G (1) changes to low level and B1 changes to high level, the signal B2 delayed from B1 becomes high. When the level changes, the output D of the D-type FF 33 changes to a high level. As a result, the D-type FFs 31 of the detection control units 21-1 and 21-2 are in a state where they can accept the next change in DET (1) and DET (2). The reason for limiting the acceptance of changes in DET (1) and DET (2) with the signal D is to prevent erroneous latching due to fluctuations in the potential of DET (1) and DET (2).

  The power supply switching circuit of the second embodiment described above is an example in which there are two input power supplies and two power supply terminals IN1 and IN2, but there are three or more input power supplies and three or more power supplies. Expansion is also possible in the case of the terminals IN1-INn.

  7A and 7B are diagrams showing the configuration of the power supply switching circuit according to the third embodiment. FIG. 7A is a diagram showing the overall configuration, and FIG. 7B is a diagram showing the circuit configuration of the control logic (logic) circuit 12.

  The power supply switching circuit according to the third embodiment switches from n types of input power supplies input to n power supply terminals IN1 and INn so that the power supply terminal to which the highest voltage power supply is input is connected to the output terminal OUT. The power supply switching circuit according to the third embodiment includes n switches / detectors 50-1 to 50-n and one control logic circuit 52.

  The switch / detection unit 50-1 includes a PMOS transistor Q1 that forms a power switch, a PMOS transistor Q11 that forms an input power supply voltage detection circuit, and a resistor R1. Q1 is connected between the power supply terminal IN1 and the output terminal OUT, and its conduction is controlled by a control signal G (1) from the control logic (logic) circuit 12. Q11 and R1 are directly connected between IN1 and GND, the gate terminal is connected to the output terminal OUT, and the detection signal DET (1) is output from the connection node between Q11 and R1. As described above, Q1, Q11, and R1 in FIG. 7 correspond to those in the second embodiment in FIG. The other switches / detectors 50-2 to 50-n have the same configuration.

  The control logic (logic) circuit 52 includes n detection control units 61-1 and 61-n, and one common unit 62. The detection control units 61-1 and 61-n have the same configuration as the detection control unit 21-1 in FIG. The common unit 62 is the same as the common unit 22 in FIG. 5 except that the NAND gate receiving G (1) -G (n) has n inputs. As described above, in the power supply switching circuit of the third embodiment, n sets of PMOS transistors and input power supply voltage detection circuits forming a power switch are provided, and the common portion receives n control signals. And different.

  The detection signals DET (1) -DET (n) do not change to the high level at the same time, and G (1) -G (n) remains from the low level to the high level by one switching. Only one of the switches from high level to low level. Therefore, only the number of detection signals and control signals is increased, and the operation at each switching is the same as in the second embodiment.

As described above, the power supply switching circuits of the first to third embodiments described above are applied to a multi-power supply compatible electronic device that receives a plurality of power supplies from a plurality of power supply terminals and selects and outputs the highest voltage among them.
FIG. 8 is a diagram showing an example of such a multi-power supply compatible electronic device.

  As shown in FIG. 8, the multi-power supply compatible electronic device includes a controller 80, a regulator 81, a micro control unit (MCU) 82, and a PMOS transistor that is a power switch provided between a plurality of power supply terminals and the regulator 81. Q1-Qn. Q1 may be connected to a DC power source (DC Inputs), Q2 may be connected to a USB, Qn may be connected to a storage battery, and there may be a PMOS transistor connected to another power source. The controller 80 is realized by the power supply switching control circuit (input power supply voltage detection circuit + control logic (logic) circuit) of the first to third embodiments, and controls the conduction of Q1-Qn and is connected to the highest voltage power supply. The PMOS transistor to be turned on is turned on. The regulator 81 receives power supply from the selected power supply, generates a predetermined power supply, and supplies it to the inside of the device. The MCU 82 operates by receiving power supply from the regulator 81. For convenience of illustration, only the MCU 82 is shown as a part that receives power supply from the regulator 81. However, the present invention is not limited to this. May be.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

11-1 to 11-n Input power supply voltage detection circuit 12 Control logic (Logic) circuit 21-1, 21-2 Detection control unit 22 Common unit Q1-Qn switch (PMOS transistor)
Q11, Q12 PMOS transistor R1, R2 Resistor INI-INn Power supply terminal OUT Output terminal

Claims (9)

A power supply switching control circuit that selects one power supply voltage from a plurality of power supply voltages and outputs the selected power supply voltage to an output terminal,
A plurality of input power supplies for comparing each of the plurality of power supply voltages with the voltage at the output terminal and outputting a detection signal when each value of the plurality of power supply voltages is greater than a value of the voltage at the output terminal by a predetermined value or more. A voltage detection circuit;
A control logic circuit that outputs a control signal for controlling the plurality of switches according to a detection signal output from each of the plurality of input power supply voltage detection circuits,
A power supply switching control circuit, wherein one power supply voltage among the plurality of power supply voltages is selected based on the control signal. Each of the plurality of input power supply voltage detection circuits includes:
A PMOS transistor and a resistor connected in series between an input terminal to which each of the plurality of power supply voltages is input and a reference potential;
The power supply switching control circuit according to claim 1, wherein a voltage of the output terminal is applied to a gate of the PMOS transistor. The control logic circuit is
When one of the plurality of input power supply voltage detection circuits detects that the power supply voltage corresponding to the input power supply voltage detection circuit is higher than the voltage of the output terminal, it corresponds to the input power supply voltage detection circuit among the plurality of switches. The power supply switching control circuit according to claim 1 or 2, wherein control is performed so that a switch to which a power supply voltage to be supplied is supplied is turned on and another switch is turned off.   4. The power supply switching control circuit according to claim 1, wherein the voltage output to the output terminal is a power supply voltage having the highest voltage among the plurality of power supply voltages. 5. Multiple power terminals,
One output terminal,
A plurality of switches respectively connected between the plurality of power supply terminals and the output terminal;
A plurality of input power supply voltage detection circuits for comparing the voltages of the plurality of power supply terminals with the voltages of the output terminals and outputting detection signals when the voltages of the plurality of power supply terminals are larger than the output voltage by a predetermined value or more. When,
A control logic circuit that outputs a control signal for controlling the plurality of switches according to a detection signal output from each of the plurality of input power supply voltage detection circuits;
A power supply switching circuit, wherein a voltage of one power supply among a plurality of power supplies supplied to the plurality of power supply terminals is selected and output to the output terminal.   The power supply switching circuit according to claim 5, wherein the plurality of switches are PMOS transistors. Each of the plurality of input power supply voltage detection circuits includes:
A PMOS transistor and a resistor connected in series between each of the plurality of voltage supply terminals and a reference potential;
The power supply switching circuit according to claim 5 or 6, wherein a voltage of the output terminal is applied to a gate of the PMOS transistor. The control logic circuit is
When one of the plurality of input power supply voltage detection circuits detects that the voltage of the plurality of power supply terminals corresponding to the input power supply voltage detection circuit is higher than the voltage of the output terminal, the input power supply voltage among the plurality of switches. The power supply switching circuit according to any one of claims 5 to 7, wherein control is performed so that a switch connected to a plurality of power supply terminals corresponding to the detection circuit is turned on and another switch is turned off.   9. The power supply according to claim 5, wherein the voltage output to the output terminal is a voltage of a power supply terminal having the highest voltage among the voltages of the plurality of power supply terminals. 10. Switching circuit.

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