JP2015026724A - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP2015026724A
JP2015026724A JP2013155619A JP2013155619A JP2015026724A JP 2015026724 A JP2015026724 A JP 2015026724A JP 2013155619 A JP2013155619 A JP 2013155619A JP 2013155619 A JP2013155619 A JP 2013155619A JP 2015026724 A JP2015026724 A JP 2015026724A
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lead
out terminal
substrate
semiconductor module
semiconductor
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JP6255771B2 (en
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貴弘 杉村
Takahiro Sugimura
貴弘 杉村
浩史 野津
Hiroshi Nozu
浩史 野津
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module which can inhibit deterioration in reliability of solder connection.SOLUTION: A semiconductor module 101 comprises: semiconductor chips 1, 2; a substrate 3; a housing; first lead-out terminals 21, 24; second lead-out terminals 22, 25; and connection parts 23, 26. The substrate 3 mounts the semiconductor chips 1, 2. The housing stores the substrate 3. The first lead-out terminals 21, 24 are mounted on the substrate 3 and extend in a direction crossing a principal surface of the substrate 3. The second lead-out terminals 22, 25 are provided on the side farther than the first lead-out terminals 21, 24 with respect to the substrate 3 when viewed from the substrate 3 in the above-described direction. The connection parts 23, 26 are provided inside the housing, for electrically connecting the second lead-out terminals 22, 25 with the first lead-out terminals 21, 24, respectively.

Description

この発明は、半導体モジュールに関し、特に、半導体モジュールの基板に搭載される導出端子の構造に関する。   The present invention relates to a semiconductor module, and more particularly to a structure of a lead-out terminal mounted on a substrate of a semiconductor module.

半導体モジュールは、一般的に、基板と、半導体チップと、導出端子と、筐体(ケース)とを備えている。基板は、筐体の底部を構成するベースにはんだ等の導電性接着剤(以下では、代表的に「はんだ」として説明する。)によって固定される。半導体チップおよび導出端子は、基板に搭載され、はんだによって基板に固定される。導出端子は、基板から筐体の外部へ延びる。半導体チップと導出端子とは、ボンディングワイヤによって電気的に接続される。非特許文献1には、このような構成を有する半導体モジュールが記載されている(非特許文献1のp60等参照)。   A semiconductor module generally includes a substrate, a semiconductor chip, lead-out terminals, and a casing (case). The substrate is fixed to a base constituting the bottom of the housing with a conductive adhesive such as solder (hereinafter, typically described as “solder”). The semiconductor chip and the lead-out terminal are mounted on the substrate and fixed to the substrate with solder. The lead-out terminal extends from the substrate to the outside of the housing. The semiconductor chip and the lead-out terminal are electrically connected by a bonding wire. Non-Patent Document 1 describes a semiconductor module having such a configuration (see p60 of Non-Patent Document 1).

高橋良和編、「2010 パワーモジュール組立実装技術 徹底解説」、電子ジャーナル、2010年6月14日、p60Takahashi Yoshikazu, "2010 Power Module Assembly and Mounting Technology Thorough Explanation", Electronic Journal, June 14, 2010, p60

導出端子を基板にはんだ付けした後にボンディングワイヤを形成する場合、基板に設けられた導出端子にボンディングツールが接触し得る。一方、ボンディングワイヤを形成した後に導出端子を基板にはんだ付けする場合、はんだ接続のために昇温する必要がある。そうすると、既設のはんだ(半導体チップを基板に固定しているはんだや、基板をベースに固定しているはんだ等)が再昇温されることとなり、既設のはんだの信頼性が低下する。   When the bonding wire is formed after the lead-out terminal is soldered to the substrate, the bonding tool can come into contact with the lead-out terminal provided on the substrate. On the other hand, when soldering the lead-out terminal to the substrate after forming the bonding wire, it is necessary to raise the temperature for solder connection. If it does so, the existing solder (the solder which fixes the semiconductor chip to the board | substrate, the solder which fixes the board | substrate to the base, etc.) will be heated again, and the reliability of the existing solder will fall.

導出端子用のはんだに既設のはんだよりも低融点のものを採用することも考えられるが、そのような特別なはんだを採用することは、材料コストの増加を招く。また、そのような低融点のはんだを採用したとしても、再昇温による既設のはんだへの影響を完全には排除できない。   Although it is conceivable to use a solder for the lead-out terminal having a lower melting point than that of the existing solder, the use of such a special solder increases the material cost. Moreover, even if such a low melting point solder is employed, the influence on the existing solder due to re-heating cannot be completely eliminated.

それゆえに、本発明の目的は、はんだ接続の信頼性の低下を抑制可能な半導体モジュールを提供することである。   Therefore, an object of the present invention is to provide a semiconductor module capable of suppressing a decrease in reliability of solder connection.

本発明の1つの局面に係る半導体モジュールは、半導体チップと、基板と、筐体と、第1導出端子と、第2導出端子と、接続部とを備える。基板は、半導体チップを搭載する。筐体は、基板を収容する。第1導出端子は、基板に搭載され、基板の主表面と交差する方向に延びる。第2導出端子は、基板から上記の方向に見て基板に対して第1導出端子よりも遠い側に設けられる。接続部は、筐体の内部に設けられ、第2導出端子を第1導出端子と電気的に接続する。   A semiconductor module according to one aspect of the present invention includes a semiconductor chip, a substrate, a housing, a first derivation terminal, a second derivation terminal, and a connection portion. A semiconductor chip is mounted on the substrate. The housing accommodates the substrate. The first lead-out terminal is mounted on the substrate and extends in a direction intersecting with the main surface of the substrate. The second lead-out terminal is provided on the side farther than the first lead-out terminal with respect to the board when viewed from the board in the above direction. The connection portion is provided inside the housing and electrically connects the second lead-out terminal with the first lead-out terminal.

本発明によれば、はんだ接続の信頼性の低下を抑制可能な半導体モジュールを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor module which can suppress the fall of the reliability of solder connection can be provided.

本発明の実施の形態1に係る半導体モジュールのXZ平面に沿った断面図である。It is sectional drawing along the XZ plane of the semiconductor module which concerns on Embodiment 1 of this invention. 図1に示す半導体モジュールの内部を概略的に示した平面図である。FIG. 2 is a plan view schematically showing the inside of the semiconductor module shown in FIG. 1. 図2中のIII−III線に沿った断面図である。It is sectional drawing along the III-III line in FIG. ボンディングワイヤの形成時の様子を示した図である。It is the figure which showed the mode at the time of formation of a bonding wire. 実施の形態2に係る半導体モジュールのXZ平面に沿った断面図である。FIG. 6 is a cross-sectional view taken along the XZ plane of the semiconductor module according to the second embodiment. 実施の形態3に係る半導体モジュールのXZ平面に沿った断面図である。FIG. 6 is a cross-sectional view along the XZ plane of a semiconductor module according to a third embodiment. 第2導出端子の他の構成を示した図である。It is the figure which showed the other structure of the 2nd derivation | leading-out terminal. 第2導出端子のさらに他の構成を示した図である。It is the figure which showed other structure of the 2nd derivation | leading-out terminal.

[本願発明の実施形態の説明]
最初に本発明の実施形態を列記して説明する。
[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described.

(1)本発明の実施形態に係る半導体モジュールは、半導体チップと、基板と、筐体と、第1導出端子と、第2導出端子と、接続部とを備える。基板は、半導体チップを搭載する。筐体は、基板を収容する。第1導出端子は、基板に搭載され、基板の主表面と交差する方向に延びる。第2導出端子は、基板から上記の方向に見て基板に対して第1導出端子よりも遠い側に設けられる。接続部は、筐体の内部に設けられ、第2導出端子を第1導出端子と電気的に接続する。   (1) The semiconductor module which concerns on embodiment of this invention is provided with a semiconductor chip, a board | substrate, a housing | casing, a 1st derivation | leading-out terminal, a 2nd derivation | leading-out terminal, and a connection part. A semiconductor chip is mounted on the substrate. The housing accommodates the substrate. The first lead-out terminal is mounted on the substrate and extends in a direction intersecting with the main surface of the substrate. The second lead-out terminal is provided on the side farther than the first lead-out terminal with respect to the board when viewed from the board in the above direction. The connection portion is provided inside the housing and electrically connects the second lead-out terminal with the first lead-out terminal.

この半導体モジュールにおいては、端子が第1導出端子と第2導出端子とに分けられ、第2導出端子を第1導出端子と電気的に接続するための接続部が筐体内部に設けられる。これにより、ボンディングワイヤの形成時に端子がボンディングツールと接触しないように第1導出端子の長さを決定することができる。   In this semiconductor module, the terminal is divided into a first lead-out terminal and a second lead-out terminal, and a connection portion for electrically connecting the second lead-out terminal to the first lead-out terminal is provided inside the housing. Accordingly, the length of the first lead-out terminal can be determined so that the terminal does not come into contact with the bonding tool when the bonding wire is formed.

そして、このような構成とすることにより、第1導出端子を基板にはんだ付けした後、接続部により第2導出端子を第1導出端子に接続する前にワイヤボンディングを実施することができる。これにより、ワイヤボンディングの実施前に、第1導出端子のはんだ付けを半導体チップのはんだ付けと同時に行なうことができる。したがって、この半導体モジュールによれば、はんだ接続用の昇温を複数回実施することによるはんだ接続の信頼性低下を回避することができる。また、第1導出端子用に低融点のはんだを選定する必要もなく、はんだの材料コストの増加も抑制できる。   And by setting it as such a structure, after soldering a 1st derivation | leading-out terminal to a board | substrate, before connecting a 2nd derivation | leading-out terminal to a 1st derivation | leading-out terminal by a connection part, wire bonding can be implemented. Thus, the soldering of the first lead-out terminal can be performed simultaneously with the soldering of the semiconductor chip before the wire bonding is performed. Therefore, according to this semiconductor module, it is possible to avoid a decrease in the reliability of solder connection caused by performing the temperature increase for solder connection a plurality of times. Further, it is not necessary to select a low melting point solder for the first lead-out terminal, and an increase in solder material cost can be suppressed.

なお、第1導出端子の延びる方向が基板の主表面と交差するとは、基板の主表面に対して第1導出端子の延びる方向が直交または実質的に直交していることを意味する。実質的に直交するとは、直交している状態からたとえば±10°以下の範囲でずれた状態で交差している場合を含む。第1導出端子の延びる方向は、最適には、基板の主表面に対して90°の角度で交差しているとよい。   The direction in which the first lead-out terminal extends intersects the main surface of the substrate means that the direction in which the first lead-out terminal extends is orthogonal or substantially orthogonal to the main surface of the substrate. The term “substantially orthogonal” includes the case of crossing in a state shifted from the orthogonal state within a range of ± 10 ° or less, for example. The extending direction of the first lead-out terminal may optimally intersect with the main surface of the substrate at an angle of 90 °.

接続部が筐体の内部に設けられるとは、接続部が筐体の内側に設けられる場合、および接続部が筐体の壁部と一体的に構成される場合の双方を含む。また、接続部の構成は、特に限定されない。ソケット、ネジ止め、コネクタ、溶接(たとえばレーザー溶接)等、種々の接続形態を採用し得る。   The phrase “the connection portion is provided inside the housing” includes both the case where the connection portion is provided inside the housing and the case where the connection portion is configured integrally with the wall portion of the housing. Moreover, the structure of a connection part is not specifically limited. Various connection forms such as sockets, screwing, connectors, and welding (for example, laser welding) may be employed.

(2)好ましくは、筐体は、基板の主表面と対向する面に開口を有する。半導体モジュールは、開口に設けられる蓋体をさらに備える。第2導出端子は、蓋体と一体的に設けられる。   (2) Preferably, a housing | casing has opening in the surface facing the main surface of a board | substrate. The semiconductor module further includes a lid provided in the opening. The second lead-out terminal is provided integrally with the lid.

このような構成により、第2導出端子の配設を蓋体の開口への取付けと同時に行なうことができる。したがって、この半導体モジュールによれば、第2導出端子の配設が容易になる。   With such a configuration, the second lead-out terminal can be disposed simultaneously with the attachment to the opening of the lid. Therefore, according to this semiconductor module, the arrangement of the second lead-out terminals is facilitated.

(3)さらに好ましくは、接続部は、蓋体と一体的に設けられる。
このような構成により、蓋体と接続部とが一部品として構成される。したがって、この半導体モジュールによれば、部品点数を削減することができる。
(3) More preferably, the connection portion is provided integrally with the lid.
With such a configuration, the lid and the connecting portion are configured as one component. Therefore, according to this semiconductor module, the number of parts can be reduced.

(4)好ましくは、第2導出端子は、前記筐体の外部へ引き出される引出部を含む。基板の主表面と交差する方向に沿って半導体モジュールを平面視した場合に、第2導出端子は、引出部が第1導出端子とずれるように構成される。   (4) Preferably, a 2nd derivation | leading-out terminal contains the drawer part pulled out to the exterior of the said housing | casing. The second lead-out terminal is configured such that the lead-out portion is displaced from the first lead-out terminal when the semiconductor module is viewed in plan along the direction intersecting the main surface of the substrate.

このような構成により、第1導出端子の配置に拘わらず、第2導出端子の筐体外部への引出位置を一定とし得る。あるいは、第1導出端子の配置を変更することなく、第2導出端子の筐体外部への引出位置を変更し得る。したがって、この半導体モジュールによれば、設計の自由度が向上する。   With such a configuration, the drawing position of the second lead-out terminal to the outside of the housing can be made constant regardless of the arrangement of the first lead-out terminal. Alternatively, the drawing position of the second lead-out terminal to the outside of the housing can be changed without changing the arrangement of the first lead-out terminal. Therefore, according to this semiconductor module, the degree of freedom in design is improved.

(5)好ましくは、接続部は、ソケットを含む。
この構成によれば、第2導出端子を第1導出端子と容易に接続することができる。
(5) Preferably, a connection part contains a socket.
According to this configuration, the second lead-out terminal can be easily connected to the first lead-out terminal.

(6)好ましくは、接続部は、第2導出端子に設けられる。
このような構成により、接続部は、半導体チップおよび第1導出端子を基板にはんだ付けするときの昇温(リフロー工程等)の影響を受けない。したがって、この半導体モジュールによれば、接続部の信頼性を確保することができる。
(6) Preferably, a connection part is provided in a 2nd derivation | leading-out terminal.
With such a configuration, the connection portion is not affected by a temperature rise (such as a reflow process) when the semiconductor chip and the first lead-out terminal are soldered to the substrate. Therefore, according to this semiconductor module, the reliability of the connecting portion can be ensured.

(7)好ましくは、半導体チップは、ワイドバンドギャップ半導体を含む。
上述のように、導出端子用のはんだに半導体チップ用のはんだよりも低融点のものを採用することによって、半導体チップを基板にはんだ付けしてボンディングワイヤを形成した後に、導出端子を基板にはんだ付けすることも考えられる。しかしながら、シリコン系の半導体素子に比べて高温使用されるワイドバンドギャップ半導体を用いた半導体モジュールにおいては、使用可能なはんだの種類が限定されるので、そのようなはんだを選定すらできない可能性がある。この半導体モジュールによれば、ワイヤボンディングの実施前に、第1導出端子のはんだ付けを半導体チップのはんだ付けと同時に行なうことができるので、上記のような問題は発生しない。
(7) Preferably, the semiconductor chip includes a wide band gap semiconductor.
As described above, by adopting a solder for the lead-out terminal having a lower melting point than that for the semiconductor chip, the semiconductor chip is soldered to the substrate to form a bonding wire, and then the lead-out terminal is soldered to the substrate. It is also possible to attach it. However, in a semiconductor module using a wide bandgap semiconductor that is used at a higher temperature than a silicon-based semiconductor element, the types of solder that can be used are limited, so it may not be possible to select such solder. . According to this semiconductor module, the soldering of the first lead-out terminal can be performed simultaneously with the soldering of the semiconductor chip before the wire bonding is performed, and thus the above-described problem does not occur.

そして、半導体チップがワイドバンドギャップ半導体を含むことにより、同じ電流駆動能力を有するシリコン系の半導体素子に比べてチップ面積を縮小することができる。したがって、この半導体モジュールによれば、半導体チップの実装面積を削減することにより半導体モジュールを小型化することができる。
[本願発明の実施形態の詳細]
以下、図面を参照しつつ、本発明の実施の形態について説明する。以下に複数の実施の形態について説明するが、各実施の形態で説明された構成を適宜組合わせることは出願当初から予定されている。なお、以下の説明では、同一または対応する要素には同一の符号を付して、それらについての詳細な説明は繰り返さない。
Since the semiconductor chip includes a wide band gap semiconductor, the chip area can be reduced as compared with a silicon-based semiconductor element having the same current driving capability. Therefore, according to this semiconductor module, the semiconductor module can be reduced in size by reducing the mounting area of the semiconductor chip.
[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. A plurality of embodiments will be described below, but it is planned from the beginning of the application to appropriately combine the configurations described in the embodiments. In the following description, the same or corresponding elements are denoted by the same reference numerals, and detailed description thereof will not be repeated.

図面中に示したX軸、Y軸およびZ軸は、互いに直交する軸である。X軸およびY軸によって定まる平面をXY平面と称する。XY平面は、本発明の実施の形態に係る半導体モジュールが設置される面として定義される。1つの例では、XY平面は水平面である。しかしながら、XY平面は水平面に限定されない。たとえば、XY平面は鉛直面であってもよい。   The X axis, the Y axis, and the Z axis shown in the drawings are axes orthogonal to each other. A plane defined by the X axis and the Y axis is referred to as an XY plane. The XY plane is defined as a surface on which the semiconductor module according to the embodiment of the present invention is installed. In one example, the XY plane is a horizontal plane. However, the XY plane is not limited to a horizontal plane. For example, the XY plane may be a vertical plane.

<実施の形態1>
図1から図3を用いて、本発明の実施の形態1に係る半導体モジュールの構成について説明する。図1は、本発明の実施の形態1に係る半導体モジュールのXZ平面に沿った断面図である。図2は、図1に示す半導体モジュールの内部を概略的に示した平面図であり、図3は、図2中のIII−III線に沿った断面図である。図2,図3では、半導体モジュールの蓋体が外された状態が示されている。
<Embodiment 1>
The configuration of the semiconductor module according to the first embodiment of the present invention will be described with reference to FIGS. 1 is a cross-sectional view taken along the XZ plane of a semiconductor module according to Embodiment 1 of the present invention. 2 is a plan view schematically showing the inside of the semiconductor module shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 and 3 show a state where the lid of the semiconductor module is removed.

図1から図3を参照して、実施の形態1に係る半導体モジュール101は、半導体チップ1,2と、基板3と、第1導出端子21,24と、第2導出端子22,25と、接続部23,26と、ワイヤ27,28とを備える。また、半導体モジュール101は、ベース11と、枠体12と、蓋体31と、封止樹脂29とをさらに備える。ベース11、枠体12、および蓋体31は、半導体モジュール101の筐体(ケース)を構成する。   With reference to FIGS. 1 to 3, the semiconductor module 101 according to the first embodiment includes semiconductor chips 1 and 2, a substrate 3, first lead terminals 21 and 24, second lead terminals 22 and 25, Connection portions 23 and 26 and wires 27 and 28 are provided. The semiconductor module 101 further includes a base 11, a frame body 12, a lid body 31, and a sealing resin 29. The base 11, the frame body 12, and the lid body 31 constitute a housing (case) for the semiconductor module 101.

この実施の形態1において、半導体チップ1,2の各々は、ワイドバンドギャップ半導体を含む。ワイドバンドギャップ半導体は、SiC(シリコンカーバイド),GaN(窒化ガリウム)、あるいはダイヤモンド等によって構成される。   In the first embodiment, each of the semiconductor chips 1 and 2 includes a wide band gap semiconductor. The wide band gap semiconductor is composed of SiC (silicon carbide), GaN (gallium nitride), diamond, or the like.

ワイドバンドギャップ半導体素子は、シリコン半導体素子に比べて、高耐圧、低オン抵抗、および高温環境での安定動作等を特徴とする。半導体チップ1,2の各々をワイドバンドギャップ半導体によって構成することにより、同じ電流駆動能力を有するシリコン系の半導体素子に比べてチップ面積を縮小することができ、その結果、半導体モジュール101を小型化することができる。   Wide bandgap semiconductor elements are characterized by high breakdown voltage, low on-resistance, stable operation in a high temperature environment, and the like as compared with silicon semiconductor elements. By configuring each of the semiconductor chips 1 and 2 with a wide band gap semiconductor, the chip area can be reduced as compared with a silicon-based semiconductor element having the same current driving capability, and as a result, the semiconductor module 101 can be downsized. can do.

この実施の形態1では、半導体チップ1,2の各々は、たとえばSiCによって作成されたパワー半導体チップである。1つの実施の形態において、半導体チップ1,2の各々は、パワーMOSFET(Metal Oxide Semiconductor FET)である。SiCによって形成されたMOSFETの場合、MOSFETに内蔵されるダイオードをフリーホイールダイオードとして利用することができるので、筐体に収容される半導体チップの数を削減することができる。   In the first embodiment, each of semiconductor chips 1 and 2 is a power semiconductor chip made of, for example, SiC. In one embodiment, each of the semiconductor chips 1 and 2 is a power MOSFET (Metal Oxide Semiconductor FET). In the case of a MOSFET formed of SiC, a diode built in the MOSFET can be used as a freewheel diode, so that the number of semiconductor chips accommodated in the housing can be reduced.

基板3は、絶縁板4と、電極パターン5a,5bと、銅板6とを含む。電極パターン5a,5bは、絶縁板4の一方の主表面に配置される。銅板6は、絶縁板4の他方の主表面に配置される。   The substrate 3 includes an insulating plate 4, electrode patterns 5 a and 5 b, and a copper plate 6. The electrode patterns 5 a and 5 b are arranged on one main surface of the insulating plate 4. The copper plate 6 is disposed on the other main surface of the insulating plate 4.

基板3は、銅板6がベース11に対向するようにベース11上に配設され、はんだ7によってベース11に固定される。ベース11は、アルミニウム(Al)や銅(Cu)等の金属を含む金属ベースであり得る。ベース11は、半導体チップ1,2が発生させた熱を筐体外部に放出するための放熱板として機能し得る。ベース11は、さらにグラウンド電極としても利用され得る。   The substrate 3 is disposed on the base 11 so that the copper plate 6 faces the base 11, and is fixed to the base 11 with solder 7. The base 11 may be a metal base containing a metal such as aluminum (Al) or copper (Cu). The base 11 can function as a heat radiating plate for releasing the heat generated by the semiconductor chips 1 and 2 to the outside of the housing. The base 11 can also be used as a ground electrode.

半導体チップ1,2は、基板3に搭載され、それぞれはんだ8a,8bによって電極パターン5a上に固定される。半導体チップ1は、ワイヤ27によって電極パターン5bに電気的に接続される。半導体チップ2は、ワイヤ28によって電極パターン5aに電気的に接続される。ワイヤ27,28は、ワイヤボンディング用のボンディングツールを用いて形成される。ワイヤボンディングには、ボールボンディングを用いてもよいし、ウェッジボンディングを用いてもよい。   The semiconductor chips 1 and 2 are mounted on the substrate 3 and fixed on the electrode pattern 5a by solders 8a and 8b, respectively. The semiconductor chip 1 is electrically connected to the electrode pattern 5b by wires 27. The semiconductor chip 2 is electrically connected to the electrode pattern 5a by wires 28. The wires 27 and 28 are formed using a bonding tool for wire bonding. Ball bonding may be used for wire bonding, or wedge bonding may be used.

第1導出端子21は、電極パターン5b上に配設され、はんだ8cによって電極パターン5bに固定される。第1導出端子21は、基板3の主表面と交差する方向(Z軸方向)に延び、接続部23に接続される。   The first lead-out terminal 21 is disposed on the electrode pattern 5b and is fixed to the electrode pattern 5b with solder 8c. The first lead-out terminal 21 extends in the direction intersecting the main surface of the substrate 3 (Z-axis direction) and is connected to the connection portion 23.

第2導出端子22は、基板3から主表面と交差する方向(Z軸方向)に見て基板3に対して第1導出端子21よりも遠い側に設けられる。第2導出端子22は、引出部22aと、延在部22bとを有する。引出部22aの端部には、接続部23が設けられる。引出部22aは、Z軸方向に延び、蓋体31を通じて筐体の内部から外部へ引き出される。延在部22bは、蓋体31の上面30に沿って配設される。延在部22bの上部には、Y軸方向に延びるバスバー51が配設される(図1)。ネジ53を締めることによって、バスバー51と第2導出端子22の延在部22bとが蓋体31の上面30に固定される。   The second lead-out terminal 22 is provided on the side farther than the first lead-out terminal 21 with respect to the board 3 when viewed from the board 3 in the direction intersecting the main surface (Z-axis direction). The second lead-out terminal 22 has a lead portion 22a and an extending portion 22b. A connecting portion 23 is provided at the end of the lead-out portion 22a. The lead-out portion 22a extends in the Z-axis direction and is pulled out from the inside of the housing through the lid body 31. The extending portion 22 b is disposed along the upper surface 30 of the lid body 31. A bus bar 51 extending in the Y-axis direction is disposed on the extension 22b (FIG. 1). By tightening the screw 53, the bus bar 51 and the extending portion 22 b of the second lead-out terminal 22 are fixed to the upper surface 30 of the lid 31.

なお、延在部22bは、蓋体31が取り付けられるまでは、引出部22aと同方向(Z軸方向)に延びている。そして、図示されないネジ等によって蓋体31が枠体12に固定された後、蓋体31の上面30に沿うように第2導出端子22を折り曲げることによって延在部22bが形成される。   In addition, the extension part 22b is extended in the same direction (Z-axis direction) as the drawer | drawing-out part 22a until the cover body 31 is attached. Then, after the lid body 31 is fixed to the frame body 12 with screws or the like (not shown), the extended portion 22 b is formed by bending the second lead-out terminal 22 along the upper surface 30 of the lid body 31.

接続部23は、筐体の内部に設けられ、第2導出端子22を第1導出端子21と電気的に接続する。一例として、接続部23は、第2導出端子22の端部に設けられたソケットであり、ソケット内部の導通部が第2導出端子22と電気的に接続される。第1導出端子21の先端が接続部23のソケット雌部に嵌合することにより、第1導出端子21と第2導出端子22とが電気的に接続される。   The connection portion 23 is provided inside the housing and electrically connects the second lead-out terminal 22 with the first lead-out terminal 21. As an example, the connection portion 23 is a socket provided at an end portion of the second lead-out terminal 22, and a conduction portion inside the socket is electrically connected to the second lead-out terminal 22. The first lead-out terminal 21 and the second lead-out terminal 22 are electrically connected by fitting the tip of the first lead-out terminal 21 into the socket female portion of the connection portion 23.

このように、この実施の形態1では、基板3から筐体の外部へ引き出される外部導出端子が、第1導出端子21と第2導出端子22とに分割される。第2導出端子22は、接続部23によって第1導出端子21に電気的に接続される。すなわち、第2導出端子22は、第1導出端子21とは別体として構成され、はんだ8cによって基板3に固定された第1導出端子21に接続部23を用いて後付けされる。   As described above, in the first embodiment, the external lead-out terminal drawn out from the substrate 3 to the outside of the housing is divided into the first lead-out terminal 21 and the second lead-out terminal 22. The second derivation terminal 22 is electrically connected to the first derivation terminal 21 through the connection portion 23. That is, the second lead-out terminal 22 is configured separately from the first lead-out terminal 21 and is retrofitted using the connection portion 23 to the first lead-out terminal 21 fixed to the substrate 3 with the solder 8c.

第1導出端子21のZ軸方向の長さは、ワイヤ27,28の形成時にボンディングツール(図示せず)が第1導出端子21と接触しないように、ボンディングツールの動作範囲に基づいて決定される。一例として、第1導出端子21のZ軸方向の長さは、20mm以下であることが好ましく、10mm以下であればさらに好ましい。   The length of the first lead-out terminal 21 in the Z-axis direction is determined based on the operating range of the bonding tool so that the bonding tool (not shown) does not contact the first lead-out terminal 21 when forming the wires 27 and 28. The As an example, the length of the first lead-out terminal 21 in the Z-axis direction is preferably 20 mm or less, and more preferably 10 mm or less.

このような構成とすることによって、第1導出端子21を半導体チップ1,2とともに基板上にはんだ付けした後に、ワイヤ27,28を形成するワイヤボンディングを実施することが可能になる(図3)。第2導出端子22は、ワイヤ27,28の形成後に第1導出端子21に接続される。   With such a configuration, it is possible to perform wire bonding for forming the wires 27 and 28 after the first lead-out terminal 21 is soldered onto the substrate together with the semiconductor chips 1 and 2 (FIG. 3). . The second lead terminal 22 is connected to the first lead terminal 21 after the wires 27 and 28 are formed.

第1導出端子24、第2導出端子25、および接続部26の構成も、それぞれ第1導出端子21、第2導出端子22、および接続部23の構成と同様である。第1導出端子24、第2導出端子25、および接続部26の説明は、第1導出端子21、第2導出端子22、および接続部23の説明と重複するので、繰り返さない。   The configurations of the first derivation terminal 24, the second derivation terminal 25, and the connection portion 26 are the same as the configurations of the first derivation terminal 21, the second derivation terminal 22, and the connection portion 23, respectively. Since the description of the first derivation terminal 24, the second derivation terminal 25, and the connection portion 26 overlaps with the description of the first derivation terminal 21, the second derivation terminal 22, and the connection portion 23, it will not be repeated.

枠体12は、絶縁体(たとえば樹脂)により形成される。枠体12は、ベース11を取り囲むように形成されて、半導体モジュール101の筐体の側壁を構成する。枠体12およびベース11は、半導体チップ1,2が実装された基板3を収容する。基板3は、筐体の内部において、封止樹脂29によって封止される(図1)。   The frame body 12 is formed of an insulator (for example, resin). The frame body 12 is formed so as to surround the base 11 and constitutes the side wall of the housing of the semiconductor module 101. The frame 12 and the base 11 accommodate the substrate 3 on which the semiconductor chips 1 and 2 are mounted. The substrate 3 is sealed with a sealing resin 29 inside the housing (FIG. 1).

筐体のベース11と対向する面には、開口部20が形成される。開口部20には、蓋体31が設けられる。蓋体31は、枠体12と同様に絶縁体(たとえば樹脂)により形成される。蓋体31は、図示されないネジ等によって枠体12に固定され、開口部20を閉じる。   An opening 20 is formed on the surface of the housing facing the base 11. A lid 31 is provided in the opening 20. The lid body 31 is formed of an insulator (for example, resin) similarly to the frame body 12. The lid body 31 is fixed to the frame body 12 by screws or the like (not shown) and closes the opening 20.

この実施の形態1では、半導体チップ1,2の基板3へのはんだ付け(ダイボンディング)と、第1導出端子21,24の基板3へのはんだ付けとが、たとえばリフロー炉を用いたリフロー工程において一括して行なわれる。その後、ワイヤボンディング工程において、ボンディングツールを用いてワイヤ27,28が形成される。さらに、ワイヤ27,28の形成後、接続部23,26を用いて第1導出端子21,24に第2導出端子22,25がそれぞれ接続される。   In the first embodiment, the soldering (die bonding) of the semiconductor chips 1 and 2 to the substrate 3 and the soldering of the first lead-out terminals 21 and 24 to the substrate 3 are, for example, a reflow process using a reflow furnace. At once. Thereafter, in the wire bonding step, the wires 27 and 28 are formed using a bonding tool. Further, after the wires 27 and 28 are formed, the second lead-out terminals 22 and 25 are connected to the first lead-out terminals 21 and 24 using the connection portions 23 and 26, respectively.

図4は、ボンディングワイヤの形成時の様子を示した図である。図4を参照して、ワイヤボンディングは、ボンディングツール60を用いて行なわれる。ボンディングツール60が移動するときは、ボンディングツール60は、Z軸方向にある程度引き上げられる。しかしながら、点線で仮想的に示されるように、基板から延びる導出端子が長い場合には、ボンディングツール60が導出端子と接触する。   FIG. 4 is a view showing a state when the bonding wire is formed. Referring to FIG. 4, wire bonding is performed using a bonding tool 60. When the bonding tool 60 moves, the bonding tool 60 is pulled up to some extent in the Z-axis direction. However, as shown in phantom by the dotted line, when the lead terminal extending from the substrate is long, the bonding tool 60 contacts the lead terminal.

ボンディングツール60と導出端子との接触を回避するために、ワイヤボンディング工程の後に導出端子を基板にはんだ付けすることも考えられる。しかしながら、この手法は、導出端子をはんだ付けするために昇温が必要であり、既設のはんだ7,8a,8bの信頼性を低下させる。導出端子用のはんだ8c,8dにはんだ7,8a,8bよりも低融点のものを用いることも考えられるが、そのような特別のはんだを採用することは、材料コストの増加を招き得る。特に、この実施の形態1では、半導体チップ1,2はワイドバンドギャップ半導体を含み、半導体モジュール101が高温で動作する。このために、はんだの選択肢が制約され、上記のような特別のはんだを選定できない可能性がある。   In order to avoid contact between the bonding tool 60 and the lead terminal, it is also conceivable to solder the lead terminal to the substrate after the wire bonding process. However, this method requires a temperature rise in order to solder the lead-out terminal, and reduces the reliability of the existing solders 7, 8a, 8b. Although it is conceivable to use solder having a melting point lower than that of the solders 7, 8a, 8b as the lead terminal solders 8c, 8d, the use of such special solders may increase the material cost. In particular, in the first embodiment, the semiconductor chips 1 and 2 include wide band gap semiconductors, and the semiconductor module 101 operates at a high temperature. For this reason, the choice of solder is restricted, and there is a possibility that the special solder as described above cannot be selected.

そこで、この実施の形態1では、導出端子が第1導出端子21(24)と第2導出端子22(25)とに分割され、接続部23(26)によって第2導出端子22(25)を第1導出端子21(24)に後で接続可能とする。そして、半導体チップ1,2のダイボンディングとともに第1導出端子21(24)のはんだ付けが行なわれ、ワイヤボンディングの実施後に第2導出端子22(25)が接続部23(26)によって第1導出端子21(24)に接続される。   Therefore, in the first embodiment, the lead-out terminal is divided into the first lead-out terminal 21 (24) and the second lead-out terminal 22 (25), and the second lead-out terminal 22 (25) is connected by the connecting portion 23 (26). It is possible to connect to the first lead-out terminal 21 (24) later. Then, the first lead-out terminal 21 (24) is soldered together with the die bonding of the semiconductor chips 1 and 2, and after the wire bonding is performed, the second lead-out terminal 22 (25) is first lead out by the connecting portion 23 (26). Connected to terminal 21 (24).

したがって、この実施の形態1によれば、ワイヤボンディングの実施後に導出端子をはんだ付けするための再昇温工程が不要となり、再昇温による既設のはんだの信頼性低下を回避することができる。   Therefore, according to the first embodiment, a reheating step for soldering the lead-out terminal after the wire bonding is not required, and a decrease in reliability of existing solder due to the reheating can be avoided.

<実施の形態2>
この実施の形態2では、第2導出端子22,25および接続部23,26が蓋体と一体的に設けられる。
<Embodiment 2>
In the second embodiment, the second lead terminals 22 and 25 and the connection parts 23 and 26 are provided integrally with the lid.

図5は、実施の形態2に係る半導体モジュールのXZ平面に沿った断面図である。図5を参照して、この半導体モジュール102は、図1に示した実施の形態1に係る半導体モジュール101と蓋体の構成が異なる。   FIG. 5 is a cross-sectional view taken along the XZ plane of the semiconductor module according to the second embodiment. Referring to FIG. 5, this semiconductor module 102 is different from the semiconductor module 101 according to the first embodiment shown in FIG.

すなわち、この半導体モジュール102では、第2導出端子22,25および接続部23,26が蓋体31と一体的に構成される。接続部23,26は、蓋体31の筐体内部側に設けられる。蓋体31の枠体12への取付けとともに、第1導出端子21,24の先端がそれぞれ接続部23,26に嵌合し、第1導出端子21(24)と第2導出端子22(25)とが電気的に接続される。   In other words, in the semiconductor module 102, the second lead-out terminals 22 and 25 and the connection parts 23 and 26 are configured integrally with the lid 31. The connection parts 23 and 26 are provided on the inside of the housing of the lid 31. As the lid body 31 is attached to the frame body 12, the leading ends of the first lead-out terminals 21 and 24 are fitted into the connection portions 23 and 26, respectively, and the first lead-out terminal 21 (24) and the second lead-out terminal 22 (25). Are electrically connected.

この実施の形態2においても、導出端子が第1導出端子21(24)と第2導出端子22(25)とに分割されており、実施の形態1と同様の効果が得られる。さらに、この実施の形態2によれば、第2導出端子22,25の第1導出端子21,24との接続を、蓋体31の枠体12への取付けと同時に行なうことができる。また、接続部23,26が蓋体31と一体的に設けられるので、部品点数も削減される。   Also in the second embodiment, the lead-out terminal is divided into the first lead-out terminal 21 (24) and the second lead-out terminal 22 (25), and the same effect as in the first embodiment can be obtained. Furthermore, according to the second embodiment, the connection of the second lead-out terminals 22 and 25 to the first lead-out terminals 21 and 24 can be performed simultaneously with the attachment of the lid 31 to the frame body 12. Moreover, since the connection parts 23 and 26 are provided integrally with the cover body 31, the number of parts is also reduced.

なお、上記においては、第2導出端子22,25および接続部23,26が蓋体31と一体的に設けられるものとしたが、接続部23,26は、蓋体31とは別体で構成してもよい。   In the above description, the second lead-out terminals 22 and 25 and the connecting portions 23 and 26 are provided integrally with the lid 31. However, the connecting portions 23 and 26 are configured separately from the lid 31. May be.

<実施の形態3>
第2導出端子22(25)と第1導出端子21(24)との接続方法は、種々の方法を取り得る。たとえば、第1導出端子21(24)と第2導出端子22(25)とをネジ止めによって接続してもよい。
<Embodiment 3>
The connection method of the 2nd derivation | leading-out terminal 22 (25) and the 1st derivation | leading-out terminal 21 (24) can take a various method. For example, the first lead-out terminal 21 (24) and the second lead-out terminal 22 (25) may be connected by screwing.

図6は、実施の形態3に係る半導体モジュールのXZ平面に沿った断面図である。図6を参照して、この半導体モジュール103では、第2導出端子22は、ネジ41によって第1導出端子21と接続される。同様に、第2導出端子25は、ネジ42によって第1導出端子24と接続される。   FIG. 6 is a cross-sectional view along the XZ plane of the semiconductor module according to the third embodiment. With reference to FIG. 6, in this semiconductor module 103, the second lead-out terminal 22 is connected to the first lead-out terminal 21 by a screw 41. Similarly, the second lead terminal 25 is connected to the first lead terminal 24 by a screw 42.

半導体モジュール103のその他の構成は、実施の形態1に係る半導体モジュール101の構成と同じである。   Other configurations of the semiconductor module 103 are the same as those of the semiconductor module 101 according to the first embodiment.

なお、特に図示しないが、第2導出端子22(25)と第1導出端子21(24)との接続方法としては、溶接(たとえばレーザー溶接)を用いてもよいし、第1導出端子21(24)または第2導出端子22(25)の先端にクリップのような構造を設けて他方の導出端子を狭持するようにしてもよい。   Although not particularly illustrated, welding (for example, laser welding) may be used as a method of connecting the second lead terminal 22 (25) and the first lead terminal 21 (24), or the first lead terminal 21 ( 24) or a structure like a clip at the tip of the second lead-out terminal 22 (25), and the other lead-out terminal may be held.

なお、その他の実施の形態として、第2導出端子22(25)の構成について、一例として図7や図8に示されるように、半導体モジュールをZ軸方向から平面視した場合に、第2導出端子22(25)の引出部が第1導出端子21(24)とずれるように第2導出端子22(25)を形成してもよい。   As another embodiment, the configuration of the second lead-out terminal 22 (25) is the second lead-out when the semiconductor module is viewed in a plan view from the Z-axis direction as shown in FIG. 7 and FIG. 8 as an example. The second lead terminal 22 (25) may be formed so that the lead portion of the terminal 22 (25) is displaced from the first lead terminal 21 (24).

このような第2導出端子22(25)によって、たとえば、基板3における第1導出端子21(24)の配置が変更になっても、第2導出端子22(25)の筐体外部への引出位置を一定とすることができる。あるいは反対に、第2導出端子22(25)の筐体外部への引出位置を変更したい場合に、基板3における第1導出端子21(24)の配置を変更することなく、第2導出端子22(25)の引出位置を変更することができる。   With such a second lead-out terminal 22 (25), for example, even if the arrangement of the first lead-out terminal 21 (24) on the substrate 3 is changed, the second lead-out terminal 22 (25) is pulled out of the housing. The position can be constant. Or, conversely, when it is desired to change the position where the second lead-out terminal 22 (25) is pulled out of the housing, the second lead-out terminal 22 is not changed without changing the arrangement of the first lead-out terminal 21 (24) on the substrate 3. The extraction position of (25) can be changed.

なお、上記の各実施の形態においては、ベース11への基板3の固定、ならびに半導体チップ1,2および第1導出端子21,24の基板3への固定には、はんだが用いられるものとしたが、はんだ以外の導電性接着剤を用いてもよい。   In each of the above embodiments, solder is used for fixing the substrate 3 to the base 11 and fixing the semiconductor chips 1 and 2 and the first lead-out terminals 21 and 24 to the substrate 3. However, a conductive adhesive other than solder may be used.

また、上記の各実施の形態で説明した半導体チップの数およびレイアウトは、一例であり、上記で説明したものに限定されない。また、第1導出端子および第2導出端子によって構成される外部導出端子の数(上記の各実施の形態では2つ)およびレイアウトも一例であり、上記で説明したものに限定されるものではない。   In addition, the number and layout of the semiconductor chips described in the above embodiments are examples, and are not limited to those described above. Further, the number of external lead-out terminals (two in each of the above embodiments) and the layout constituted by the first lead-out terminals and the second lead-out terminals are also examples, and are not limited to those described above. .

また、上記の各実施の形態では、接続部23,26は、第2導出端子22,25側に設けられるものとしたが、第1導出端子21,24側に設けてもよい。   Further, in each of the above embodiments, the connection portions 23 and 26 are provided on the second lead-out terminals 22 and 25 side, but may be provided on the first lead-out terminals 21 and 24 side.

今回開示された各実施の形態は、適宜組合わせて実施することも予定されている。そして、今回開示された実施の形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施の形態の説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiments disclosed this time are also scheduled to be implemented in appropriate combinations. The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

1,2 半導体チップ
3 基板
4 絶縁板
5a,5b 電極パターン
6 銅板
7,8a〜8d はんだ
11 ベース
12 枠体
20 開口部
21,24 第1導出端子
22,25 第2導出端子
22a,25a 引出部
22b,25b 延在部
23,26 接続部
27,28 ワイヤ
29 封止樹脂
30 上面
31 筐体
51,52 バスバー
41,42,53,54 ネジ
60 ボンディングツール
101〜103 半導体モジュール
DESCRIPTION OF SYMBOLS 1, 2 Semiconductor chip 3 Board | substrate 4 Insulation board 5a, 5b Electrode pattern 6 Copper plate 7, 8a-8d Solder 11 Base 12 Frame 20 Opening part 21, 24 1st lead-out terminal 22, 25 2nd lead-out terminal 22a, 25a Lead-out part 22b, 25b Extension part 23, 26 Connection part 27, 28 Wire 29 Sealing resin 30 Upper surface 31 Case 51, 52 Bus bar 41, 42, 53, 54 Screw 60 Bonding tool 101-103 Semiconductor module

Claims (7)

半導体チップと、
前記半導体チップを搭載する基板と、
前記基板を収容する筐体と、
前記基板に搭載され、前記基板の主表面と交差する方向に延びる第1導出端子と、
前記基板から前記方向に見て前記基板に対して前記第1導出端子よりも遠い側に設けられる第2導出端子と、
前記筐体の内部に設けられ、前記第2導出端子を前記第1導出端子と電気的に接続するための接続部とを備える、半導体モジュール。
A semiconductor chip;
A substrate on which the semiconductor chip is mounted;
A housing for housing the substrate;
A first lead-out terminal mounted on the substrate and extending in a direction intersecting the main surface of the substrate;
A second lead-out terminal provided on a side farther than the first lead-out terminal with respect to the board when viewed from the board in the direction;
A semiconductor module, comprising: a connection portion provided in the housing for electrically connecting the second lead-out terminal to the first lead-out terminal.
前記筐体は、前記基板の主表面と対向する面に開口を有し、
前記半導体モジュールは、前記開口に設けられる蓋体をさらに備え、
前記第2導出端子は、前記蓋体と一体的に設けられる、請求項1に記載の半導体モジュール。
The housing has an opening on a surface facing the main surface of the substrate,
The semiconductor module further includes a lid provided in the opening,
The semiconductor module according to claim 1, wherein the second lead-out terminal is provided integrally with the lid body.
前記接続部は、前記蓋体と一体的に設けられる、請求項2に記載の半導体モジュール。   The semiconductor module according to claim 2, wherein the connection portion is provided integrally with the lid. 前記第2導出端子は、前記筐体の外部へ引き出される引出部を含み、
前記半導体モジュールを前記方向に沿って平面視した場合に、前記第2導出端子は、前記引出部が前記第1導出端子とずれるように構成される、請求項1から請求項3のいずれか1項に記載の半導体モジュール。
The second lead-out terminal includes a lead-out portion that is pulled out to the outside of the housing,
The said 2nd derivation | leading-out terminal is comprised so that the said drawer | drawing-out part may shift | deviate from the said 1st derivation | leading-out terminal when the said semiconductor module is planarly viewed along the said direction. The semiconductor module according to item.
前記接続部は、ソケットを含む、請求項1から請求項4のいずれか1項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the connection portion includes a socket. 前記接続部は、前記第2導出端子に設けられる、請求項1から請求項5のいずれか1項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the connection portion is provided in the second lead-out terminal. 前記半導体チップは、ワイドバンドギャップ半導体を含む、請求項1から請求項6のいずれか1項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the semiconductor chip includes a wide band gap semiconductor.
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JPH09172116A (en) * 1995-12-21 1997-06-30 Mitsubishi Electric Corp Semiconductor device
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