JP2014191836A - Shift register circuit and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce circuit scale of a driver circuit comprising shift register circuits connected in multiple stages.SOLUTION: A shift register circuit 20 includes a transistor 1 which pulls down the potential of a node 22 in response to rise in the potential of a node 21, and a transistor 2 which pulls down the potential of the node 21 in response to rise in the potential of the node 22. The shift register circuit 20 also includes a transistor 3 which raises the potential of a source thereof when a "CLK" enters, and a transistor 4 which supplies the potential of the source of the transistor 3 to a node 23 in response to rise in the potential of the node 21. The shift register circuit 20 further includes a transistor 5 which outputs "OUT" and a transistor 6 which outputs "OUT" in response to rise in the potential of the node 23.

Description

  The present invention relates to a shift register circuit and an image display device.

  Conventionally, a shift register circuit that transmits a signal output from a preceding circuit to a subsequent circuit is known. Such a shift register circuit is used as a driver circuit for sequentially operating display elements such as an LCD (Liquid Crystal Display) and an organic EL (Electro-Luminescence) display.

  Hereinafter, the operation of the shift register circuit will be described with reference to FIG. FIG. 14 is a circuit diagram illustrating a conventional shift register circuit. For example, the shift register circuit 30 illustrated in FIG. 14 includes a plurality of transistors 31 to 38 and nodes 40 and 41. In the example shown in FIG. 14, the gates (base) and drain (collector) of the transistors 31 and 37 are diode-connected.

  In such a shift register circuit 30, when the signal input from the previous circuit is not output to the next circuit, the potential of the node 40 is in the low state and the potential of the node 41 is in the high state. In the shift register circuit 30, when the signal input from the previous circuit is output to the next circuit, the potential of the node 40 is in a high state and the potential of the node 41 is in a low state.

  Here, when a pulse of “in” that is an input signal is input from the preceding circuit, the shift register circuit 30 inputs a pulse to the node 40 via the transistor 31 that operates as a diode. In such a case, as a result of the potential of the node 40 being in a high state and the transistor 35 being in an on state, the shift register circuit 30 outputs “CLK” that is a clock signal as “OUT” that is an output signal.

  Further, the shift register circuit 30 inputs an “in” pulse to the gate (base) of the transistor 34. In such a case, the transistor 34 is turned on, and the potential of the node 41 drops to “VGL (low potential)”. The shift register circuit 30 inputs a clock signal pulse to the gate of the transistor 38. As a result, the transistor 38 is turned on, the potential of the node 41 is lowered to “VGL”, the transistor 33 is turned off, and the potential of the node 40 is in a high state.

  Further, the shift register circuit 30 inputs “OUT” output from the circuit in the next stage to the gate of the transistor 32. Then, since the transistor 32 is turned on, the potential of the node 40 drops to “VGL”. After the operation of the shift register circuit 30, the transistors 34 and 38 are turned off, the potential of the node 41 is changed from the low state to the high state, and the transistors 33 and 36 are turned on. As a result, the node 40 is turned on. A stable low state is obtained.

JP 2003-046090 A

  However, since the shift register circuit 30 described above can output only one “OUT” for one “in”, there is a problem that the circuit scale of the driver circuit in which the shift register circuits are arranged in multiple stages is increased. .

  For example, when the shift register circuit 30 is applied to a driver circuit that operates a display element such as an LCD or an organic EL display, the shift register circuits 30 must be provided by the number of scanning lines, resulting in an increase in circuit scale. It is not possible to narrow the frame.

  The disclosed technique has been made in view of the above, and an object thereof is to provide a shift register circuit and an image display device capable of reducing the circuit scale of a driver circuit in which shift register circuits are connected in multiple stages. .

  In the shift register circuit and the image display device according to the present invention, the gate is connected to the first conductive path, the drain is connected to the second conductive path, and the source is connected to the low potential terminal. A first transistor that lowers the potential of the second conductive path in response to an increase in the potential of the second conductive path, a gate connected to the second conductive path, and a drain connected to the first conductive path A second transistor having a source connected to a low potential terminal and lowering the potential of the first conductive path in response to an increase in potential of the second conductive path, and a gate and a drain Connected to the input terminal of the first clock signal, the third transistor for raising the potential of the source when the first clock signal is input, and the gate of the first conductive path Connected, the drain is connected to the source of the third transistor and the source is connected to the third conductive path, and the potential of the first transistor rises in response to an increase in potential of the first conductive path. A fourth transistor for supplying a source potential to the third conductive path; a gate connected to the third conductive path; and a drain for delaying the first clock signal by a predetermined amount. The second clock signal is used as the first output signal in response to a rise in the potential of the third conductive path, the source of which is connected to the first output terminal and the source is connected to the first output terminal. A fifth transistor output from one output terminal, a gate connected to the third conductive path, and a drain of a third clock signal obtained by delaying the second clock signal by a predetermined amount. The second clock signal is used as the second output signal in response to an increase in potential of the third conductive path, which is connected to the power terminal and the source is connected to the second output terminal. And a sixth transistor for outputting from the output terminal.

  The shift register circuit and the image display device according to the present invention can reduce the circuit scale of a driver circuit in which shift register circuits are connected in multiple stages.

It is a circuit diagram which shows the shift register circuit of a 1st form. It is a graph explaining the current characteristic of a transistor. It is a figure explaining the signal waveform input into a shift register circuit. It is a figure explaining operation | movement of a shift register circuit. FIG. 10 illustrates a state of a shift register circuit in a period T0. FIG. 10 illustrates a state of a shift register circuit in a period T1. FIG. 10 illustrates a state of a shift register circuit in a period T3. FIG. 10 illustrates a state of a shift register circuit in a period T5. FIG. 10 illustrates a state of a shift register circuit in a period T7. FIG. 10 illustrates a state of a shift register circuit in a period T9. FIG. 10 illustrates a state of a shift register circuit in a period T15. FIG. 11 is a first diagram illustrating an application example of a shift register circuit. It is a 2nd figure explaining the application example of a shift register circuit. It is a circuit diagram explaining the conventional shift register circuit.

  Embodiments of a shift register circuit and an image display device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. And the embodiment illustrated below can be suitably changed and combined in the range which does not contradict a shape.

[First form]
[Structure of shift register circuit]
A first embodiment of the shift register circuit will be described with reference to FIG. FIG. 1 is a circuit diagram showing a shift register circuit according to the first embodiment. As shown in FIG. 1, the shift register circuit 20 includes a shift register unit 25 and an OUT waveform control unit 26. Specifically, the shift register circuit 20 includes a plurality of transistors 1 to 15 and a plurality of nodes 21 to 24. Further, the shift register circuit 20 has input terminals for “in” which is a signal output from the preceding shift register circuit and clock signals “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ” and “CLK ₄ ”. Have.

The shift register circuit 20 has output terminals “OUT ₁ ” and “OUT ₂ ” that are outputs of the shift register circuit 20. That is, the shift register circuit 20 sequentially outputs _two signals “OUT ₁ ” and “OUT ₂ ” for one input signal “in”. For example, when the shift register circuit 20 is applied to a driver circuit of an image display device, signals are sequentially sent from the output terminals of “OUT ₁ ” and “OUT ₂ ” to two continuous gate lines in the image display area. Output.

Further, the shift register circuit 20 has an input terminal to which “OUT ₃ ” is input in order to shift to a standby state after outputting “OUT ₁ ” and “OUT ₂ ”. “OUT ₃ ” is an output signal corresponding to “OUT ₁ ” of the shift register circuit 20 in the shift register circuit at the next stage. In the next stage of the shift register circuit, "CLK _1" of the shift register circuit 20 corresponds to "CLK _4", "CLK _2" corresponds to "CLK _2", "CLK _3" is "CLK ₃ “CLK ₄ ” corresponds to “CLK ₁ ”.

  Further, the shift register circuit 20 includes a high potential terminal in which the potential is maintained at a value “VGH” higher than a predetermined threshold, and a low potential terminal in which the potential is maintained at a value “VGL” lower than the predetermined threshold. And have. In the following description, the value of “VGH” is a value higher than GND (ground), for example, 8 (V) to 20 (V), and the value of “VGL” is a value lower than GND. -5 (V) to -15 (V).

  Each of the transistors 1 to 15 is, for example, an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but the present invention is not limited to this. For example, each of the transistors 1 to 15 may be an NPN type transistor or a field effect transistor (FET) adopting a MIS (Metal Insulator Semiconductor) structure of a type (n type) in which carriers are electrons. Good.

  Each of the transistors 1 to 15 may be a thin film transistor (TFT) that is a kind of FET, that is, an n-MISFET TFT. Alternatively, a circuit that exhibits a function equivalent to that of the shift register circuit 20 may be configured using a PNP transistor, a FET whose carrier is a hole (p-type), a TFT, or the like.

  Here, each of the transistors 1 to 15 has three electrodes of a gate, a source, and a drain, and the source and the drain are defined by the conductivity of the transistor and the relative potential relationship. Therefore, in the following description, it is assumed that each of the transistors 1 to 15 is an n-channel MOSFET, and among the terminals of each of the transistors 1 to 15, the high potential side terminal is the drain, and the low potential side terminal is the source. Describe.

[Connection]
Here, a connection relationship between the transistors 1 to 15 and the nodes 21 to 24 in the shift register circuit 20 illustrated in FIG. 1 will be described.

  The node 21 is a conductive path that connects the transistors 1, 2, 4, 14, and 15. Specifically, the node 21 is connected to the gate of the transistor 1, the drain of the transistor 2, the gate of the transistor 4, the drain of the transistor 14, and the source of the transistor 15.

  The node 22 is a conductive path that connects the transistors 1, 2, 11, 12, and 13. Specifically, the node 22 is connected to the drain of the transistor 1, the gate of the transistor 2, the source of the transistor 11, the gate of the transistor 12, and the gate of the transistor 13.

  The node 23 is a conductive path that connects the transistors 4, 5, 6, 7, 8, and 9. Specifically, the node 23 is connected to the source of the transistor 4, the gate of the transistor 5, the gate of the transistor 6, the drain of the transistor 7, the gate of the transistor 8, and the drain of the transistor 9.

  Node 24 is a conductive path connecting transistors 8, 9, and 10. Specifically, the node 24 is connected to the drain of the transistor 8, the gate of the transistor 9, and the source of the transistor 10.

  The transistor 1 has a gate connected to the node 21, a drain connected to the node 22, and a source connected to the low potential terminal. The transistor 1 is turned on when the potential of the node 21 is higher than a predetermined threshold value. As a result, the potential of the node 22 is lowered to “VGL”.

  The transistor 2 has a gate connected to the node 22, a drain connected to the node 21, and a source connected to the low potential terminal. The transistor 2 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential of the node 21 is lowered to “VGL”.

The transistor 3 has a gate and a drain connected to the input terminal of “CLK ₁ ” and a source connected to the drain of the transistor 4. The transistor 3 is turned on when the potential of “CLK ₁ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the transistor 4.

Transistor 4 has a gate connected to node 21, a drain connected to the source of transistor 3, and a source connected to node 23. The transistor 4 is turned on when the potential of the node 21 is higher than a predetermined threshold value. As a result, when the potential of “CLK ₁ ” is higher than the predetermined threshold and the potential of the node 21 is higher than the predetermined threshold, “VGH” supplied from the transistor 3 is supplied to the node 23, The potential increases.

The transistor 5 has a gate connected to the node 23, a drain connected to the input terminal of “CLK ₂ ”, and a source connected to “OUT ₁ ”. The transistor 5 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, “CLK ₂ ” is output as “OUT ₁ ”.

The transistor 6 has a gate connected to the node 23, a drain connected to the input terminal of “CLK ₃ ”, and a source connected to “OUT ₂ ”. The transistor 6 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, “CLK ₃ ” is output as “OUT ₂ ”.

The transistor 7 has a gate connected to the input terminal of “OUT ₃ ”, a drain connected to the node 23, and a source connected to the low potential terminal. The transistor 7 is turned on when the potential of “OUT ₃ ” is higher than a predetermined threshold value. As a result, the potential of the node 23 is lowered to “VGL”.

  The transistor 8 has a gate connected to the node 23, a drain connected to the node 24, and a source connected to the low potential terminal. The transistor 8 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, the potential of the node 24 is lowered to “VGL”.

  The transistor 9 has a gate connected to the node 24, a drain connected to the node 23, and a source connected to the low potential terminal. The transistor 9 is turned on when the potential of the node 24 is higher than a predetermined threshold value. As a result, the potential of the node 23 is lowered to “VGL”.

The transistor 10 has a gate connected to the input terminal of “CLK ₄ ”, a drain connected to the high potential terminal, and a source connected to the node 24. The transistor 10 is turned on when the potential of “CLK ₄ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 24 and the potential of the node 24 rises.

The transistor 11 has a gate connected to the input terminal of “CLK ₄ ”, a drain connected to the high potential terminal, and a source connected to the node 22. The transistor 11 is turned on when the potential of “CLK ₄ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 22 and the potential of the node 22 rises.

The transistor 12 has a gate connected to the node 22, a drain connected to the source of the transistor 5 and the output terminal of “OUT ₁ ”, and a source connected to the low potential terminal. The transistor 12 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential at the source of the transistor 5, that is, the output terminal of “OUT ₁ ” is lowered to “VGL”.

The transistor 13 has a gate connected to the node 22, a drain connected to the source of the transistor 6 and an output terminal of “OUT ₂ ”, and a source connected to a low potential terminal. The transistor 13 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential at the source of the transistor 6, that is, the output terminal of “OUT ₂ ” is lowered to “VGL”.

The transistor 14 has a gate connected to the input terminal “OUT ₃ ”, a drain connected to the node 21, and a source connected to the low potential terminal. The transistor 14 is turned on when the potential of “OUT ₃ ” is higher than a predetermined threshold value. As a result, the potential of the node 21 is lowered to “VGL”.

  The transistor 15 has a gate connected to the input terminal of the signal “in”, a drain connected to the high potential terminal, and a source connected to the node 21. The transistor 15 is turned on when the potential of the signal “in” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 21 and the potential of the node 21 rises.

As described above, the shift register circuit 20 includes the transistor 1 that decreases the potential of the node 22 as the potential of the node 21 increases, and the transistor 2 that decreases the potential of the node 21 as the potential of the node 22 increases. And have. In addition, the shift register circuit 20 supplies “VGH” to the node 23 when the potential of “CLK ₁ ” is high and the potential of the node 21 is high due to the transistors 3 and 4. At this time, the transistors 2 and 14 for lowering the potential of the node 21 are turned off, and the transistor 15 is also turned off. Therefore, the potential of the node 21 is increased by bootstrap, and the “VGH” Is supplied.

The shift register circuit 20 includes a transistor 5 that outputs “CLK ₂ ” as “OUT ₁ ” and a transistor 6 that outputs “CLK ₃ ” as “OUT ₂ ” as the potential of the node 23 increases. Have. At this time, since the transistors 7 and 9 that lower the potential of the node 23 are turned off, and the transistor 3 is also turned off, the potential of the node 23 is increased by bootstrap, and each OUT is stabilized. Can be output.

  Here, the current flowing between the drain and source of each of the transistors 1 to 15 varies depending on the potential between the gate and source. Therefore, each of the transistors 1 to 15 is completely turned on when the gate potential is sufficiently higher than the predetermined threshold, but is completely turned on when not sufficiently higher than the predetermined threshold. Must not. Each of the transistors 1 to 15 is completely turned off when the gate potential is sufficiently lower than the predetermined threshold value, but is completely turned off when the gate potential is not sufficiently lower than the predetermined threshold value. It is not turned off.

  For example, FIG. 2 is a graph illustrating current characteristics of a transistor. In the graph shown in FIG. 2, the horizontal axis represents the potential Vg (V: Volt) between the gate and source of each transistor 1-15, and the vertical axis represents the current Id (A: Ampere) between the drain and source in logarithm. did. As shown in FIG. 2, when the potential Vg is sufficiently low, each of the transistors 1 to 15 is in an off state in which almost no current Id flows.

  Further, each of the transistors 1 to 15 is in an on (low) state in which the current Id flows when the potential Vg is not sufficiently low. Further, each of the transistors 1 to 15 is in an on (medium) state where the current Id does not flow sufficiently when the potential Vg is not sufficiently high. Further, when the potential Vg is sufficiently high, each of the transistors 1 to 15 is saturated with the current Id and is turned on (high), which is a complete on state.

  Therefore, in the conventional shift register circuit 30 illustrated in FIG. 14, when the potential applied to the gates of the transistors 31 to 38 is not sufficiently higher than a predetermined threshold, the transistors 31 to 38 are turned on ( May not be in a high state and may cause malfunction. Further, the conventional shift register circuit 30 is not turned off and may cause malfunction when the potential applied to the gates of the transistors 31 to 38 is not sufficiently lower than a predetermined threshold value. .

On the other hand, the shift register circuit 20 of the present invention lowers the potential of the node 22 according to the potential of the node 21, not the potential of “OUT ₁ ”. As a result, the shift register circuit 20 can reliably lower the potential of the node 22 when outputting “OUT ₁ ” and “OUT ₂ ”. Furthermore, when the shift register circuit 20 outputs “OUT ₁ ” and “OUT ₂ ”, the potential of the node 23 can be set to “VGH” or more by coupling by bootstrap. As a result, by keeping the potential of the node 23 sufficiently high, a drop in signal output can be prevented.

[Operation Flow of Shift Register Circuit 20]
The operation flow of the shift register circuit 20 will be described. First, a signal input to the shift register circuit 20 will be described with reference to FIG. FIG. 3 is a diagram for explaining a signal waveform input to the shift register circuit. For example, in the example illustrated in FIG. 3, for example, “VST” (vertical scan start signal: Vertical Start Technology) is input to the shift register circuit 20 as “in”, and a plurality of clock signals “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” are input.

  Here, “VST” is a signal that is input to the shift register circuit 20 as “in” when there is no other shift register circuit in the previous stage of the shift register circuit 20. It is a signal which shows the start of the process to transmit.

“CLK ₁ ” is a first clock signal whose potential periodically changes from VGH to VGL, and is a signal indicating a period during which the shift register circuit 20 outputs “OUT ₁ ” and “OUT ₂ ”. is there. This “CLK ₁ ” is an example of the “first clock signal” in the claims.

“CLK ₂ ” is a signal obtained by periodically changing the potential from VGH to VGL and delaying “CLK ₁ ” by a predetermined amount, and indicates the timing at which the shift register circuit 20 outputs “OUT ₁ ”. This is a clock signal. This “CLK ₂ ” is an example of a “second clock signal” recited in the claims.

“CLK ₃ ” is a signal in which the potential changes periodically from VGH to VGL and “CLK ₂ ” is delayed by a predetermined amount, and indicates the timing at which the shift register circuit 20 outputs “OUT ₂ ”. This is a clock signal. This “CLK ₃ ” is an example of a “third clock signal” recited in the claims.

“CLK ₄ ” is a signal whose potential changes periodically from VGH to VGL and rises at the same timing as “CLK ₃ ” by shifting the phase of “CLK ₁ ”. This “CLK ₄ ” is an example of a “fourth clock signal” recited in the claims.

That is, “CLK ₂ ” is input to the shift register circuit 20 in synchronization with “in”. “CLK ₁ ” and “CLK ₄ ” are signals that rise at the same timing as “CLK ₃ ”, but are out of phase and rise alternately at the same timing as “CLK ₃ ”. “CLK ₂ ” is a signal obtained by inverting “CLK ₃ ”, and becomes “VGL” when “CLK ₃ ” is “VGH”.

Next, the operation of the shift register circuit 20 when each signal is input will be described with reference to FIG. FIG. 4 is a diagram for explaining the operation of the shift register circuit. Note that FIG. 4 shows input waveforms of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, “CLK ₄ ”, and “in” input to the shift register circuit 20, and potential changes at the nodes 21 to 24. , “OUT ₁ ”, “OUT ₂ ”, “OUT ₃ ”, “OUT ₄ ” waveforms are shown.

Here, “OUT ₃ ” is a signal output first after the next-stage circuit inputs “in”, and is a signal corresponding to “OUT ₁ ” output from the shift register circuit 20. “OUT ₄ ” is a signal that is output second after the next-stage circuit inputs “in”, and is a signal corresponding to “OUT ₂ ” output by the shift register circuit 20.

  Further, in FIG. 4, the range in which each of the transistors 1 to 15 is in the on (high) state is indicated by shading, the range in which the transistor is in the on (medium) state is indicated by dark stippling, and the range in which the on (low) state is indicated Shown in light stippling. Further, the range in which each of the transistors 1 to 15 is turned off is shown in white. In the state before the period T1 in FIG. 4, the potentials of the nodes 21 and 23 are “VGL”, and the potentials of the nodes 22 and 24 are potentials in the vicinity of “VGH”.

In such a state, the shift register circuit 20 sequentially outputs “OUT ₁ ” and “OUT ₂ ” in response to the input of “in” synchronized with “CLK ₂ ” that periodically changes, A series of flows for stopping output by “OUT ₃ ” input from the shift register circuit at the subsequent stage is shown. Here, the above series of flows will be specifically described using the states of the transistors 1 to 15 in the period shown by T1 to T16 in FIG.

(Period T0) The period T0 is a non-selection period before “in” is input. Specifically, it is a period in which the potentials of “in”, “CLK ₁ ”, “CLK ₂ ”, and “CLK ₄ ” are “VGL” and the potential of “CLK ₃ ” is “VGH”.

  FIG. 5 is a diagram illustrating the state of the shift register circuit in the period T0. 5 to 11, nodes whose potential is higher than VGL are represented by bold lines, and nodes whose potential is VGL are represented by thin lines. As shown in FIG. 5, in the period T0, the node 22 and the node 24 hold “VGH”, and the transistors 2 and 9 are in the on state. Therefore, the node 21 and the node 23 maintain the “VGL” state. doing. As described above, in the period T0, the potentials of the nodes 22 and 24 are maintained at “VGH”, so that the potentials of the nodes 21 and 23 are maintained at “VGL” and the output of each OUT is suppressed. It is an example.

Specifically, as shown in FIG. 4, since the potentials of the nodes 22 and 24 are “VGH”, the transistors 2, 9, 12, and 13 are turned on (high). The node 21 is pulled to “VGL” because “VGH” is not supplied and the transistor 2 is on (high). As a result, the potential of the node 21 becomes “VGL”. The node 23 is pulled to “VGL” because the transistor 9 is in an on (high) state in a state where neither “CLK ₁ ” nor “VGH” is supplied. As a result, the potential of the node 23 becomes “VGL”.

  That is, in the period T0, the transistors 2, 9, 12, and 13 are turned on (high), and the other transistors are turned off. Further, the potential of the node 21 and the node 23 is “VGL”, and the potential of the node 22 and the node 24 is a high potential near “VGH”.

(Period T1) The period T1 is a period in which OUT output from the upper shift register circuit is input to “in” or, in the uppermost stage, a start pulse is input to “in”. Specifically, the potential of “in” is “VGH”, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGH”, and the potential of “CLK ₃ ” is “VGH”. Is a period in which the potential of “CLK ₄ ” becomes “VGL”.

  FIG. 6 is a diagram illustrating the state of the shift register circuit in the period T1. As shown in FIG. 6, when “in” of the shift register circuit 20 is input, “VGH” is supplied to the node 21 and the transistor 1 is turned on, so that “VGH” held at the node 22 is held. Is pulled to “VGL”. Therefore, the potential of the node 22 decreases and the potential of the node 21 increases.

  Specifically, as illustrated in FIG. 4, since the potential of “in” becomes “VGH”, the transistor 15 is turned on (high), and “VGH” starts to be supplied to the node 21. When the potential of the node 21 rises, the transistor 1 and the transistor 4 that input the potential of the node 21 to the gate are turned on (medium).

  Further, since the transistor 1 is turned on (medium), the potential of the node 22 is pulled to “VGL”. Therefore, the potential of the node 22 drops from “VGH” and becomes higher than “VGL” and lower than “GND”. In addition, since the potential of the node 22 input to the gate of the transistors 2, 12, and 13 is lower than “VGH”, the transistors 2, 12, and 13 are turned from an on (high) state to an on (low) state. Therefore, the node 21 is slightly pulled to “VGL” by the transistor 2. As a result, the potential of the node 21 is lower than “VGH” and higher than “GND”. Note that since the potential of the node 24 continues to be “VGH”, the transistor 9 is maintained in an on (high) state.

  That is, in the state of the period T1, the transistors 9 and 15 are turned on (high), the transistors 1 and 4 are turned on (middle), the transistors 2, 12, and 13 are turned on (low), and the other transistors are turned on. Turns off. Further, the potential of the node 21 is lower than “VGH” and higher than “GND”, the potential of the node 22 is lower than “GND”, the potential of the node 23 is “VGL”, and the node 24 Continues to be a high potential in the vicinity of “VGH” from the period T0.

(Period T2) The period T2 is a period in which “in” becomes “VGL”. Specifically, it is a period in which each potential of “in”, “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. Since the period T2 is a period in which “in” becomes “VGL” from the period T1, the transistor 15 is turned off. However, the node 21 is not pulled from any transistor to “VGL”. Therefore, the potential of the node 21 holds the potential of the T1 period.

(Period T3) The period T3 is a period in which the potentials of “CLK ₁ ” and “CLK ₃ ” are “VGH”. Specifically, the potential of “in” becomes “VGL”, the potential of “CLK ₁ ” becomes “VGH”, the potential of “CLK ₂ ” becomes “VGL”, and the potential of “CLK ₃ ” becomes “VGH”. This is a period in which the potential of “CLK ₄ ” is “VGL”.

FIG. 7 is a diagram illustrating a state of the shift register circuit in the period T3. As illustrated in FIG. 7, “VGH” is supplied to the node 23 by “CLK ₁ ”, so that the transistor 8 is turned on and the node 24 is pulled to “VGL”. Then, a bootstrap occurs in the transistor 4, and the node 21 becomes a potential higher than “VGH”. For this reason, the transistor 1 is further turned on, and the node 22 becomes “VGL”. Further, since the node 23 is “VGH”, the pulse of “CLK ₃ ” is output to “OUT ₂ ” via the transistor 6. As a result, the gate of the display area is turned on in the same manner as “OUT ₂ ” in the previous stage, and the potential written in the previous stage pixel is also written in this pixel. However, this serves as a precharge.

Specifically, as shown in FIG. 4, since the potential of “CLK ₁ ” is “VGH”, the transistor 3 is turned on (high), and “VGH” is supplied to the drain of the transistor 4. On the other hand, since the transistors 2 and 14 are in the off state, the node 21 is not pulled to “VGL”. As a result, a bootstrap occurs at the node 21 through the transistor 4, and the potential of the node 21 becomes “VGH” or more by coupling. For example, the potential of the node 21 rises to about 1.3 to 1.5 times “VGH”.

  As the potential of the node 21 rises, the transistor 1 is turned on (high), and the potential of the node 22 is pulled to “VGL”. For this reason, the potential of the node 22 is completely lowered to “VGL”. Thus, since the potential of the node 22 is “VGL”, the transistors 2, 12, and 13 are turned off.

  Further, since the transistors 3 and 4 are turned on, “VGH” is supplied to the node 23 and the potential of the node 23 becomes “VGH”. Since the potential of the node 23 becomes “VGH”, the transistor 8 is turned on (medium), and the potential of the node 24 is pulled to “VGL”. As a result, the potential of the node 24 is higher than “VGL” and lower than “GND”. As the potential of the node 24 drops, the transistor 9 is turned off.

Since the potential of the node 23 is “VGH”, the transistors 5 and 6 are also turned on (medium). Further, since the potential of “CLK ₃ ” is “VGH”, “CLK ₃ ” is output to “OUT ₂ ” via the transistor 6.

That is, in the state of the period T3, the transistors 1, 3, and 4 are turned on (high), the transistors 5, 6, and 8 are turned on (middle), and the other transistors are turned off. In addition, the potential of the node 21 becomes “VGH” or higher, the potential of the node 22 becomes “VGL”, the potential of the node 23 becomes “VGH”, and the potential of the node 24 is higher than “VGL” and lower than “GND”. Become. Furthermore, “OUT ₂ ” is output as precharge.

(Period T4) The period T4 is a period in which “CLK ₁ ” and “CLK ₃ ” change from “VGH” to “VGL”. Specifically, it is a period in which each potential of “in”, “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. In the period T4, since “CLK ₁ ” and “CLK ₃ ” are “VGL”, the transistor 3 is turned off. On the other hand, the potentials of the nodes 21 and 23 hold “VGH”, and the potentials of the nodes 22 and 24 hold “VGL”.

(Period T5) The period T5 is a period in which the pulse of “CLK ₂ ” switches from “VGL” to “VGH”. Specifically, this is a period in which the potential of “CLK ₂ ” becomes “VGH” and the other potentials of “in”, “CLK ₁ ”, “CLK ₃ ”, and “CLK ₄ ” become “VGL”.

FIG. 8 illustrates the state of the shift register circuit in the period T5. As shown in FIG. 8, since the potential of “CLK ₂ ” becomes “VGH”, a bootstrap occurs due to the drain-gate capacitance of the transistor 5, and the node 23 is raised to a potential higher than “VGH”. It is done. Thereby, the pulse of “CLK ₂ ” is output to “OUT ₁ ” without a voltage drop.

Specifically, as shown in FIG. 4, since “CLK ₁ ” is “VGL”, the transistor 3 is turned off, the bootstrap in the transistor 4 is finished, and the potential of the node 21 becomes “VGH”. Become. In addition, since the potential of the node 21 is “VGH”, the transistor 1 continues to be on (high). For this reason, since the node 22 is continuously pulled to “VGL”, it maintains “VGL”. Therefore, the transistors 2, 12, and 13 maintain the off state.

Then, “VGH” is supplied to the node 23 through the transistor 4 from the period T3. Further, since the node 23 is at a high potential, the transistor 8 is turned on (high), and the node 24 maintains “VGL”, so that the transistor 9 also maintains the off state. In this manner, when each transistor that lowers the potential of the node 23 and the transistor 3 are in the OFF state, the potential of “CLK ₂ ” becomes “VGH”, and therefore, a bootstrap occurs at the node 23. As a result, the potential of the node 23 becomes “VGH” or more by coupling. Therefore, the transistor 5 is completely turned on (high), and there is no voltage drop, and “CLK ₂ ” is output from “OUT ₁ ”. Note that the potential of the node 23 rises by about 1.3 to 1.5 times, for example, “VGH”.

That is, in the period T5, the transistors 1, 4, 5, 6, and 8 are turned on (high), and the other transistors are turned off. Further, the potential of the node 21 becomes “VGH”, the potential of the node 22 becomes “VGL”, the potential of the node 23 becomes “VGH” or more, and the potential of the node 24 becomes “VGL”. Further, “CLK ₂ ” is output as “OUT ₁ ”.

(Period T6) The period T6 is a period in which the pulse of “CLK ₂ ” switches from “VGH” to “VGL”. Specifically, it is a period in which each potential of “in”, “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. In the period T6, “OUT ₁ ” is pulled from “VGH” to “VGL” by “CLK ₂ ”. The node 23 is also affected by the coupling and drops to the potential before the bootstrap.

(Period T7) The period T7 is a period in which the pulses of “CLK ₃ ” and “CLK ₄ ” are switched from “VGL” to “VGH”. Specifically, it is a period in which the potentials of “in”, “CLK ₁ ”, and “CLK ₂ ” are “VGL” and the potentials of “CLK ₃ ” and “CLK ₄ ” are “VGH”.

FIG. 9 is a diagram illustrating the state of the shift register circuit in the period T7. As shown in FIG. 9, when “CLK ₃ ” is output to “OUT ₂ ” via the transistor 6, the node 23 is raised to a potential higher than “VGH” due to the bootstrap effect. As a result, a pulse of “CLK ₃ ” is output from “VGH” to “OUT ₂ ” without a potential drop. Further, the potential of “CLK ₄ ” also switches from “VGL” to “VGH”, the transistors 10 and 11 are turned on, and “VGH” is supplied to the node 22 and the node 24. However, since the transistor 1 and the transistor 8 are in the on state, the potentials of the nodes 22 and 24 are not changed from “VGL” and are maintained as they are.

Specifically, as shown in FIG. 4, since the potential of “CLK ₄ ” is “VGH”, the transistors 10 and 11 are turned on (high), and “VGH” is supplied to the nodes 22 and 24. Is done. On the other hand, since the potential of the node 21 is “VGH”, the transistor 1 is turned on (high), and the node 22 is pulled to “VGL”. Therefore, the potential of the node 22 is maintained at “VGL”. Further, since the potential of the node 23 is “VGH”, the transistor 8 is turned on (high), and the node 24 is pulled to “VGL”. Therefore, the potential of the node 24 maintains “VGL”.

Since the node 24 maintains “VGL”, the transistor 9 also maintains the off state. In this way, when each transistor that lowers the potential of the node 23 and the transistor 3 are in the OFF state, the potential of “CLK ₃ ” becomes “VGH”, and thus a bootstrap occurs at the node 23. As a result, the potential of the node 23 becomes “VGH” or more by coupling. Therefore, the transistor 6 is completely turned on (high), there is no voltage drop, and “CLK ₃ ” is output from “OUT ₂ ”.

That is, in the period T7, the transistors 1, 4, 5, 6, 8, 10, and 11 are turned on (high), and the other transistors are turned off. Further, the potential of the node 21 becomes “VGH”, the potential of the node 22 becomes “VGL”, the potential of the node 23 becomes “VGH” or more, and the potential of the node 24 becomes “VGL”. Further, “CLK ₃ ” is output as “OUT ₂ ”. Note that in the period T7, “OUT ₄ ” is output in the shift register circuit in the next stage.

(Period T8) The period T8 is a period in which the pulses of “CLK ₄ ” and “CLK ₃ ” change from “VGH” to “VGL”. Specifically, it is a period in which each potential of “in”, “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. In the period T8, “OUT ₂ ” is pulled from “VGH” to “VGL” by “CLK ₃ ”. The node 23 is also affected by the coupling and drops to the potential before the bootstrap. Further, since the potential of “CLK ₄ ” is changed from “VGH” to “VGL”, the transistors 10 and 11 are turned from the on (high) state to the off state, and the supply of “VGH” to the nodes 22 and 24 is stopped. .

(Period T9) The period T9 is a period in which “OUT ₃ ” of the next stage is output. Specifically, as in the period T5, the potential of “CLK ₂ ” is “VGH”, and the other potentials of “in”, “CLK ₁ ”, “CLK ₃ ”, and “CLK ₄ ” are “VGL”. And a period during which the potential of “OUT ₃ ” is “VGH”.

FIG. 10 is a diagram illustrating the state of the shift register circuit in the period T9. As shown in FIG. 10, the transistors 7 and 14 are turned on by the pulse of “OUT ₃ ”, and the nodes 21 and 23 are pulled to “VGL”. Further, when the potentials of the nodes 21 and 23 drop, the transistors 1, 4, 5, 6, and 8 are turned off.

Specifically, as shown in FIG. 4, since the potential of “OUT ₃ ” is “VGH”, the transistors 7 and 14 are turned on (high). For this reason, the potential of the node 21 is pulled to “VGL” as the transistor 14 is turned on, and thus becomes completely “VGL”. Further, the potential of the node 23 is also pulled to “VGL” as the transistor 7 is turned on, and thus becomes completely “VGL”.

  Since the potential of the node 21 becomes “VGL”, the transistors 1 and 4 are also turned off. Similarly, since the potential of the node 23 becomes “VGL”, the transistors 5, 6, and 8 are also turned off.

  That is, in the state of the period T9, the transistors 7 and 14 are turned on (high), and the other transistors are turned off. Further, the potential of the node 21 drops to “VGL”, the potential of the node 22 maintains “VGL”, the potential of the node 23 drops to “VGL”, and the potential of the node 24 changes to “VGL”. To maintain.

(Period T10) Period T10 is a period in which “CLK ₂ ” switches to “VGL” and “OUT ₃ ” switches to “VGL” from period T9. Specifically, it is a period in which each potential of “in”, “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, “CLK ₄ ”, “OUT ₃ ” is “VGL”.

  This period T10 does not change from the state of the period T9.

(Period T11) The period T11 is a period in which “CLK ₁ ” and “CLK ₃ ” are switched to “VGH” from the period T10, and “OUT ₄ ” is switched to “VGH”. Specifically, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGH”, and the potential of “CLK ₄ ” is “VGL”. Is the period. Note that during this period, “OUT ₄ ” is output from the shift register circuit in the next stage.

As shown in FIG. 4, in the period T11, “CLK ₃ ” becomes “VGH”, but the state of the transistor is not affected. On the other hand, since “CLK ₁ ” becomes “VGH”, the transistor 3 is turned on (high).

(Period T12) The period T12 is a period in which “CLK ₁ ” and “CLK ₃ ” are switched to “VGL” from the period T11. Specifically, it is a period in which each potential of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. Accordingly, the transistor 3 is changed from the on (high) state to the off state.

(Period T13) The period T13 is a period in which “CLK ₂ ” switches to “VGH” from the period T12. Specifically, the potential of “CLK ₁ ” becomes “VGL”, the potential of “CLK ₂ ” becomes “VGH”, the potential of “CLK ₃ ” becomes “VGL”, and the potential of “CLK ₄ ” becomes “VGL”. Is the period. As shown in FIG. 4, in the period T13, “CLK ₂ ” becomes “VGH”, but does not affect the state of the transistor, so the state of each transistor and the state of each node do not change from the state of the period T12. .

(Period T14) The period T14 is a period in which “CLK ₂ ” switches to “VGL” from the period T13. Specifically, it is a period in which each potential of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”. Therefore, the state of each transistor and the state of each node do not change from the state of the period T13.

(Period T15) Period T15 is a period in which “CLK ₄ ” switches from “VGL” to “VGH”. Specifically, it is a period in which the potentials of “CLK ₁ ” and “CLK ₂ ” are “VGL” and the potentials of “CLK ₃ ” and “CLK ₄ ” are “VGH”.

FIG. 11 is a diagram illustrating the state of the shift register circuit in the period T15. As shown in FIG. 11, since “CLK ₄ ” becomes “VGH”, the transistors 10 and 11 are turned on, and “VGH” is supplied to the node 22 and the node 24. Therefore, the transistors 2, 9, 12, and 13 are turned on, and the node 21 and the node 23 are stably “VGL”. Therefore, even if “CLK ₁ ”, “CLK ₂ ”, and “CLK ₃ ” are switched from “VGL” to “VGH”, they are not affected and do not malfunction. Since “CLK ₄ ” is periodically switched from “VGL” to “VGH”, potential supply is also performed periodically. For this reason, the node 22 and the node 24 stably maintain “VGH”.

Specifically, since “CLK ₄ ” becomes “VGH”, the transistors 10 and 11 are turned on (high). Therefore, “VGH” is supplied to the node 22, and “VGH” is supplied to the node 24, so that the node 22 and the node 24 have a high potential near “VGH”. Since the potential of the node 22 becomes high, the transistors 2, 12, and 13 that input the potential of the node 22 to the gate are turned on (high). As a result, the potential of the node 21 is pulled to “VGL” via the transistor 2, so that “VGL” is stably maintained. Further, “OUT ₁ ” and “OUT ₂ ” are also pulled to “VGL” by the transistor 12 and the transistor 13, respectively.

  Since the node 23 is “VGL”, the transistor 8 is in an off state, so that the node 24 maintains the supplied “VGH”. Therefore, the transistor 9 that inputs the potential of the node 24 to the gate is turned on (high), and the node 23 stably maintains “VGL”. Further, since the potential of the node 23 is stabilized at “VGL”, the transistors 5 and 6 also maintain the off state.

  That is, in the period T15, the transistors 2, 9, 10, 11, 12, and 13 are turned on (high), and the other transistors are turned off. Further, the potential of the node 21 and the node 23 becomes “VGL”, and the potential of the node 22 and the node 24 becomes a high potential in the vicinity of “VGH”.

(Period T16) The period T16 is a period in which “CLK ₃ ” and “CLK ₄ ” are switched from “VGH” to “VGL” from the state of the period T15. Specifically, it is a period in which each potential of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” is “VGL”.

As shown in FIG. 4, since “CLK ₄ ” becomes “VGL”, the transistors 10 and 11 are turned off. For this reason, supply of “VGH” to the nodes 22 and 24 is suppressed. However, since both the transistors that drop the node 22 or the node 24 to “VGL” are in the off state, the potentials of the node 22 and the node 24 continue to maintain “VGH” from the period T15.

[Effect of the shift register circuit 20]
As described above, since the shift register circuit 20 can output “OUT ₁ ” and “OUT ₂ ” for one “in”, the circuit scale of the driver circuit including the shift register circuit 20 is reduced. Can be made. For example, when the shift register circuit 20 is applied to a driver circuit that operates a display element, the frame size of the driver circuit can be reduced, resulting in a narrow frame.

In addition, when “CLK ₁ ” is “VGH”, the transistor that pulls the node 21 to “VGL” is turned off, so that a bootstrap occurs at the node 21, and “CLK ₁ ” maintains “VGH” at the node 23. Can be output stably. Further, when “CLK ₂ ” is “VGH”, the transistor that pulls the node 23 to “VGL” can be turned off. Further, at this time, since the transistor 3 is turned off by “CLK ₁ ”, “VGH” of the node 23 can remain in the node 23, so that a bootstrap can be generated in the node 23. Therefore, “OUT ₁ ” can be output stably.

Similarly, when “CLK ₃ ” is “VGH”, the transistor that pulls the node 23 to “VGL” can be turned off. Further, at this time, since the transistor 3 is turned off by “CLK ₁ ”, “VGH” of the node 23 can be kept in the node 23, so that a bootstrap can be generated in the node 23. Therefore, “OUT ₂ ” can be output stably.

In addition, the shift register circuit 20 has a gate connected to the input terminal of “OUT ₃ ”, a drain connected to the node 23, and a source connected to the low potential terminal according to the potential of “OUT ₃ ”. 23 has a transistor 7 for dropping the potential of 23. For this reason, in the non-selection period of the shift register circuit 20, the potential of the node 23 can be lowered, so that signal output can be accurately suppressed.

That is, “CLK ₁ ” becomes “VGL” after outputting “VGH” to the node 23, and the transistor 3 is diode-connected. Therefore, when “CLK ₂ ” is output to “OUT ₁ ”, a bootstrap can be generated by the gate-drain capacitance of the transistor 5, and when “CLK ₃ ” is output to “OUT ₂ ”, the transistor 6 Bootstrap can be generated by the gate-drain capacitance. As a result, the potential of the node 23 becomes higher than “VGH”, “OUT ₁ ” can output the same potential as “CLK ₂ ”, and “OUT ₂ ” outputs the same potential as “CLK ₃ ”. be able to.

  The shift register circuit 20 includes a transistor 8 that lowers the potential of the node 24 according to the potential of the node 23 and a transistor 9 that lowers the potential of the node 23 according to the potential of the node 24. Therefore, when the shift register circuit 20 is in the selection period, that is, when the node 23 is at a high potential such as “VGH”, the potential of the node 24 can be lowered to “VGL”. It can be maintained and can output stably. Further, when the shift register circuit 20 is in a non-selection period, that is, when the node 23 is at a low potential such as “VGL”, the potential of the node 24 can be maintained at “VGH”. It is possible to suppress the output stably.

Further, the shift register circuit 20 includes the transistor 10 that raises the potential of the node 24 in accordance with the input of “CLK ₄ ” whose gate is shifted in phase from “CLK ₁ ” and rises at the same timing as “CLK ₃ ”. Therefore, “VGH” can be stably supplied to the node 24.

The shift register circuit 20 includes the transistor 11 that raises the potential of the node 22 in accordance with the input of “CLK ₄ ”. Therefore, “VGH” can be stably supplied to the node 22. Then, as the potential of the node 22 increases, the transistors 12 and 13 that decrease the potential of “OUT ₁ ” or “OUT ₂ ” to “VGL” are included. Therefore, the shift register circuit 20 can prevent erroneous output of “OUT ₁ ” and “OUT ₂ ” in the off state.

In addition, the shift register circuit 20 includes a transistor 14 that lowers the potential of the node 21 in response to the rise of the potential of “OUT ₃ ” output from the circuit in the next stage. For this reason, the shift register circuit 20 can reliably transit to the non-selected state when the circuit in the subsequent stage outputs a signal. The shift register circuit 20 includes a transistor 15 that raises the potential of the node 21 in response to the rise of the potential of “in”. For this reason, the shift register circuit 20 can increase the potential of the node 21 when “in” is input, and shift to the selected state.

[Scope of application]
For example, the shift register circuit 20 exemplified in the above embodiment is suitably applied to a driver circuit that operates an image display device using a liquid crystal panel or an organic EL (Electro-Luminescence) panel. The shift register circuit 20 can also be applied to circuits other than the driver circuit described above. The shift register circuit 20 can be applied to an arbitrary device such as a sensor device, a light emitting element array, or a thermal head having a plurality of transistors and a driver circuit for sequentially driving each element.

(Application to LCD panel)
In the following description, an example in which the shift register circuit 20 is applied to a driver circuit that operates an image display device using a liquid crystal panel will be described as an application example of the shift register circuit 20.

  FIG. 12 is a first diagram illustrating an application example of the shift register circuit. In the example illustrated in FIG. 12, the image display device 50 includes a control circuit 51 and a panel 52. Note that the image display device 50 includes a light source device such as a backlight, a color filter substrate, a polarizing plate having different polarization directions, and the like. However, in FIG.

  The control circuit 51 is provided on, for example, an FPC (Flexible Printed Circuits) arranged on the panel 52 or on an external circuit board of the panel 52, and receives a control signal for driving the panel 52. Output to the drive circuit 55. In FIG. 12, illustration of the FPC or the external circuit board is omitted.

  In addition, a liquid crystal panel is used for the panel 52, and it is composed of a pair of substrates. For example, the panel 52 is composed of a pair of glass substrates including an array substrate in which a thin film transistor is formed in the active area 57 and a color filter substrate facing the array substrate. A peripheral portion 54 is formed around the array substrate in the active area 57. The peripheral portion 54 is provided with a driving circuit 55 and a scanning line driving circuit 56, and the scanning line driving circuit 56 is formed on the glass of the array substrate. The driving circuit 55 and the scanning line driving circuit 56 are connected by a scanning line control line 53.

  The drive circuit 55 is composed of a semiconductor element for driving, and includes a signal line drive circuit for outputting an image signal to a data line extending on the active area, a scanning line control circuit, a counter potential drive circuit, and the like. The drive circuit 55 is mounted on the peripheral portion 54 of the active area 57 by a COG (Chip On Glass) method.

  In addition, a plurality of circuits that exhibit the same function as the shift register circuit 20 described in the first embodiment are applied to the scanning line driving circuit 56 provided in the peripheral portion 54 of the panel 52. Specifically, the scan line driving circuit 56 is connected in multiple stages to shift register units 25 to 25b that perform the same function as the shift register unit 25. Each shift register unit 25 to 25b includes an OUT waveform control unit. 26 are connected to OUT waveform control units 26 to 26b that perform the same functions as the H.26.

The shift register units 25 to 25b are formed on a scanning line driving circuit 56 that is integrally formed on the array substrate of the panel 52. In addition to the shift register units 25 to 25b and the OUT waveform control units 26 to 26b, the scanning line driving circuit 56 includes a shift register circuit including a plurality of shift register units and an OUT waveform control unit. In FIG. 12, the description is omitted for easy understanding. In addition, two scanning lines extending on the active area 57 are connected to each of the OUT waveform control units 26 to 26b. In the example shown in FIG. 12, the input lines of “CLK ₁ ” to “CLK ₄ ” are omitted for easy understanding.

  The drive circuit 55 is connected to the scan line drive circuit 56 through the scan line control line 53, and outputs a control signal to the first-stage shift register unit 25 through the scan line control line 53.

  The active area 57 has a plurality of pixels 58 arranged in a matrix. Specifically, in the active area 57, a plurality of data lines are extended in the column direction, and a plurality of scanning lines are extended in the row direction. In the active area 57, pixels 58 are formed corresponding to the intersections of the data lines and the scanning lines.

  Here, the pixel 58 includes a thin film transistor 59 that operates as an active element, and a pixel electrode 60. The image display device 50 displays an image by controlling liquid crystal molecules with a voltage applied between a pixel electrode 60 provided on the array substrate and a common electrode (not shown) provided on the color filter substrate. Here, the panel 52 is described in a vertical electric field method in which the pixel electrode 60 is provided on the array substrate and the common electrode is provided on the color filter substrate. Alternatively, a horizontal electric field method in which a pixel electrode 60 and a common electrode are provided may be used.

The scanning line driving circuit 56 is a circuit in which shift register units 25 to 25b similar to the shift register unit 25 according to the first embodiment are connected in multiple stages, and OUT waveform control units 26 to 26b are connected to the shift register units 25 to 25b. Consists of. Here, the scanning line driving circuit 56 sequentially inputs “OUT ₁ ” and “OUT ₂ ” output from the OUT waveform control unit 26 to the scanning lines extending on the active area 57 by the operation of the shift register unit 25 described above. To do.

Further, since the potential of “OUT ₁ ” included in the shift register unit 25 is input as “in” to the shift register unit 25a, the scanning line driving circuit 56 operates the OUT waveform control unit 26a by the operation of the shift register circuit 25a. “OUT ₃ ” and “OUT ₄ ” output from the signal are sequentially input to the scanning lines extending on the active area 57. As described above, the shift register units 25 to 25b installed in multiple stages sequentially shift the signals, and each OUT waveform control unit 26 to 26b sequentially outputs the two signals. For this reason, when a control signal is input from the drive circuit 55 via the scanning line control line 53, the scanning line driving circuit 56 applies voltages to the scanning lines on the active area 57 in order from the top. Apply.

For example, when the scanning line driving circuit 56 receives the control signal, the operation of the shift register unit 25 and the OUT waveform control unit 26 outputs “OUT ₁ ” to the first scanning line, and then outputs “OUT ₂ ”. Is output to the second scanning line. Next, the scanning line driving circuit 56 outputs “OUT ₃ ” to the third-stage scanning line by the operation of the shift register unit 25 a and the OUT waveform control unit 26 a, and then outputs “OUT ₄ ” to the fourth-stage scanning line. Output to scan line. As a result, the scanning line driving circuit 56 sequentially applies a voltage to each scanning line on the active area 57.

  Here, when the scanning line driving circuit 56 is configured using a conventional shift register circuit, the same number of shift register circuits as the scanning lines extended on the active area 57 are connected in multiple stages, and each shift register is connected. A signal is output from the circuit onto each scanning line. However, when the scanning line driving circuit 56 is configured using the shift register circuit 20 including the shift register unit 25 and the OUT waveform control unit 26, a signal is sent from one shift register circuit 20 to two scanning lines. Therefore, the circuit scale of the scanning line driving circuit 56 can be reduced, and the narrowed frame of the image display device 50 can be realized.

  In addition, the shift register circuit 20 can output the output signal without lowering the potential of the signal due to the bootstrap effect, so that the voltage applied to each scanning line by the scanning line driving circuit 56 can be prevented from being lowered. As a result, the image display device 50 can prevent a decrease in the voltage applied to each pixel 58 even when the number of scanning lines increases due to the increase in the size of the active area 57 or the densification of the pixels 58. Can work.

  In the thin film transistor 59, a data line and a source corresponding to the position where the pixel 58 is formed are connected, and a scanning line and a gate corresponding to the position where the pixel 58 is formed are connected. When a voltage is applied to the corresponding scanning line from the scanning line driving circuit 56 and a voltage is applied to the corresponding data line from the driving circuit 55, the voltage applied to the data line is passed through the thin film transistor 59. Applied to the pixel electrode 60.

  Note that FIG. 12 illustrates an example in which the shift register circuit 20 is applied to an image display device using a liquid crystal panel. However, the embodiment is not limited to this. For example, the shift register circuit 20 may be applied to an image display device using an organic EL panel. For example, FIG. 13 is a second diagram illustrating an application example of the shift register circuit 20.

(Application to organic EL)
In the example shown in FIG. 13, the image display device 70 having the scanning register driving circuit 56 having the shift register unit 25 and the OUT waveform control unit 26 and using an organic EL panel is described. In the example shown in FIG. 13, the scanning line driving circuit 56 having the shift register circuit 20 including the shift register unit 25 and the OUT waveform control unit 26 is described for easy understanding. Includes a plurality of circuits similar to the shift register circuit 20. Specifically, the scanning line driving circuit 56 may be configured by connecting, in multiple stages, the same circuits as the shift register circuit 20 by a number that is half the number of scanning lines extending on the active area 57. Note that the shift register circuit 20 is integrally formed on the peripheral portion of the panel 52 on the array substrate, similarly to the image display device 50 using the above-described liquid crystal panel.

  In the example shown in FIG. 13, the pixel 58 includes a light emitting element 80 whose anode is electrically connected to the constant potential supply circuit 71, and a transistor 81 whose one electrode is connected to the cathode of the light emitting element 80. The pixel 58 includes an n-type thin film transistor, and includes a driver element 83 whose drain is connected to the drain of the transistor 82 and whose source is electrically connected to the power supply circuit 72. In addition, the pixel 58 includes a transistor 82 that controls the conduction state between the gate and the drain of the thin film transistor that forms the driver element 83, and a capacitance 84.

  In the example shown in FIG. 13, a constant potential supply circuit 71 that supplies a constant on potential to the anode of the light emitting element 80 provided in each pixel 58, and a transistor 81 provided in the pixel 58 via a control line. And a power supply circuit 72 for supplying an ON potential or a zero potential to the source of the driver element 83.

  The light emitting element 80 has a mechanism for emitting light by current injection, and is formed of, for example, an organic EL element. The organic EL device includes an anode layer and a cathode layer formed of Al, Cu, ITO (Indium Tin Oxide), and the like, and phthalocyanine, trisaluminum complex, benzoquinolinolato, and beryllium complex between the anode layer and the cathode layer. And a light emitting layer formed of an organic material such as an organic material, and has a function of generating light by recombination of holes and electrons injected into the light emitting layer.

  The transistor 81 has a function of controlling conduction between the light emitting element 80 and the driver element 83, and is formed of an n-type thin film transistor in the first embodiment. That is, the drain and the source of the thin film transistor are connected to the light emitting element 80 and the driver element 83, respectively, while the gate is electrically connected to the drive control circuit 73, and supplied from the drive control circuit 73. Based on the potential, the conduction state between the light emitting element 80 and the driver element 83 is controlled.

  The driver element 83 has a function for controlling the current flowing through the light emitting element 80. Specifically, the driver element 83 has a function of controlling a current flowing through the light emitting element 80 in accordance with a potential difference equal to or greater than a threshold value. In the first embodiment, the driver element 83 is formed of an n-type thin film transistor, and controls the light emission luminance of the light emitting element 80 according to the potential difference applied between the gate and the source.

  In such a pixel 58, charges are accumulated in the capacitance 84 by the voltage applied to the signal line by the drive circuit 55. While the drive control circuit 73 applies a voltage to the gate of the transistor 81, a current corresponding to the charge accumulated in the capacitance 84 flows to the light emitting element 80, and the light emitting element 80 emits light.

  As described above, even when each pixel 58 has the light emitting element 80, the scanning line driving circuit 56 includes the shift register unit 25 including the shift register unit 25 and the OUT waveform control unit 26 on two scanning lines. The output signal of each pixel is output. For this reason, the image display device 70 can reduce the circuit scale of the scanning line driving circuit 56 and reduce the frame even when the pixel 58 includes an organic EL panel. Further, since the shift register circuit 20 prevents the potential of the signal output on the scanning line from being lowered, the image display device 70 can be operated normally regardless of the number of pixels on the active area 57.

1 to 15 transistor 20 shift register circuit 21 to 24 node 25, 25a, 25b shift register unit 26, 26a, 26b OUT waveform control unit

Claims (9)

The gate is connected to the first conductive path, the drain is connected to the second conductive path, and the source is connected to the low potential terminal. A first transistor that lowers the potential of the second conductive path;
In response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the drain being connected to the first conductive path and the source being connected to the low potential terminal. A second transistor that lowers the potential of the first conductive path;
A third transistor having a gate and a drain connected to an input terminal of the first clock signal, and raising a potential of the source when the first clock signal is input;
The potential of the first conductive path rises with the gate connected to the first conductive path, the drain connected to the source of the third transistor and the source connected to the third conductive path. And a fourth transistor for supplying a potential of the source of the third transistor to the third conductive path according to
A gate is connected to the third conductive path, a drain is connected to an input terminal of a second clock signal obtained by delaying the first clock signal by a predetermined amount, and a source is connected to the first output terminal. A fifth transistor for outputting the second clock signal as a first output signal from the first output terminal in response to an increase in potential of the third conductive path;
The gate is connected to the third conductive path, the drain is connected to the input terminal of the third clock signal obtained by delaying the second clock signal by a predetermined amount, and the source is connected to the second output terminal. And a sixth transistor for outputting the third clock signal as a second output signal from the second output terminal in response to an increase in potential of the third conductive path. Shift register circuit.   The shift register circuit of the next stage is connected to the output terminal that outputs a signal corresponding to the first output signal, the drain is connected to the third conductive path, and the source is connected to the low potential terminal 2. The shift register circuit according to claim 1, further comprising a seventh transistor that drops the potential of the third conductive path in accordance with the potential of the signal output from the shift register circuit at the next stage. In response to an increase in the potential of the third conductive path, the gate being connected to the third conductive path, the drain being connected to the fourth conductive path and the source being connected to the low potential terminal. An eighth transistor for lowering the potential of the fourth conductive path;
In response to an increase in potential of the fourth conductive path, the gate being connected to the fourth conductive path, the drain being connected to the third conductive path and the source being connected to the low potential terminal. The shift register circuit according to claim 1, further comprising: a ninth transistor that lowers a potential of the third conductive path.   The gate is connected to the input terminal of the fourth clock signal that rises at the same timing as the third clock signal by shifting the phase of the first clock signal, the drain is connected to the high potential terminal, and the source is the above-mentioned The tenth transistor, which is connected to the fourth conductive path, further increases the potential of the fourth conductive path in response to the input of the fourth clock signal. 4. The shift register circuit according to any one of 3.   According to the input of the fourth clock signal, the gate is connected to the input terminal of the fourth clock signal, the drain is connected to the high potential terminal, and the source is connected to the second conductive path. The shift register circuit according to claim 4, further comprising an eleventh transistor that raises a potential of the second conductive path. In response to an increase in potential of the second conductive path having a gate connected to the second conductive path, a drain connected to the first output terminal, and a source connected to a low potential terminal. A twelfth transistor for lowering the potential of the first output terminal;
In response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the drain being connected to the second output terminal and the source being connected to the low potential terminal. The shift register circuit according to claim 1, further comprising a thirteenth transistor that lowers the potential of the second output terminal.   The potential of the first conductive path according to the potential of the input signal, the gate being connected to the input terminal of the input signal, the drain being connected to the high potential terminal and the source being connected to the first conductive path. The shift register circuit according to claim 1, further comprising a fifteenth transistor for raising the voltage. A driver circuit having the shift register circuit according to any one of claims 1 to 7,
An image display device comprising: a display panel that displays an image by a light emitting element that emits light according to a signal output from the driver circuit. A driver circuit having the shift register circuit according to any one of claims 1 to 7,
An image display device comprising: a liquid crystal panel that displays an image according to a signal output from the driver circuit.

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