JP2012220565A - Image display device and control method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for achieving excellent moving picture quality and high definition while avoiding problems of shortage of writing period and trouble in wiring layout, in an active matrix driving type image display device.SOLUTION: Each pixel circuit includes a capacitance, a writing switch for charging the capacitance with charges corresponding to a value of an image signal, a driving transistor for driving an electro-optical element according to a gate voltage corresponding to charges held in the capacitance, and a stop switch that stops light emission of the electro-optical element by discharging the capacitance. At least stop switches of the number corresponding to two lines of pixel circuits are connected to a common stop control line. Each of the electro-optical elements stops light emission in response to a stop control signal given via the common stop control line.

Description

  The present invention relates to an image display device using an active matrix driving method.

  Examples of the flat panel display (FPD) include a liquid crystal display device (LCD), a plasma display device (PDP), an electroluminescence display device (ELD), and a field emission display device (FED). Among them, ELD is excellent in moving image quality because it is self-luminous, has a small viewing angle dependency, and has high-speed response. Further, an active matrix driving type ELD is easy to achieve high definition, and has a long life because the peak current flowing through the display element can be reduced.

  On the other hand, in a hold-type image display device using an active matrix driving method, a phenomenon called so-called hold blur occurs in which a video is blurred when displaying a moving image. Patent Document 1 below discloses an image display apparatus that suppresses hold blur by adjusting a light emission period (hold time).

JP 2001-060076 A

  Patent Document 1 discloses the following three configurations as configurations for adjusting the hold time. (1) A configuration in which light emission is stopped by controlling the potential of a power supply wiring that supplies a power supply potential Vdd to the pixel circuit, (2) a configuration in which a luminance zero (black) signal is written after an image signal is written, and (3) light emission The structure which provides the stop control line for stopping every line. However, these configurations (1) to (3) have the following problems.

  (1) In this configuration, the power supply wiring is electrically separated for each row. Therefore, the light emission current corresponding to one row of pixels connected to the power supply wiring (1920 × 3 = 5760 pixels in the case of full HD) concentrates on one power supply wiring, and a voltage drop due to wiring resistance occurs. To do. If the amount of voltage drop in the power supply wiring is different for each row, the light emission luminance fluctuates and luminance unevenness (so-called crosstalk) may occur in the display image. It is known that this problem can be alleviated by operating the driving transistor in a saturation region like constant current driving. However, it is difficult to make the saturation region characteristic of the transistor completely flat, and it is difficult to sufficiently solve the above problem by this method. In addition, if the wiring resistance is reduced by increasing the wiring width or wiring thickness, the problem of crosstalk can be suppressed. However, if the wiring width is increased, it becomes difficult to achieve high definition due to problems in the wiring layout. Increasing the size causes another problem that the cost increases.

  (2) Since it is necessary to secure a period for writing the luminance zero signal, the image signal writing period is approximately halved. This makes it difficult to achieve high definition due to reasons such as defective writing.

(3) In the configuration in which a dedicated stop control line is provided, it is not necessary to separate the power supply wiring for each row, so the above-described crosstalk does not become a problem, and writing and light emission stop control can be performed independently using the dedicated line. There is no need to reduce the writing period. However, since the number of wirings in the row direction is at least doubled, it is difficult to achieve high definition due to wiring layout problems.

  The present invention has been made in view of such circumstances, and in an active matrix drive type image display device, in order to achieve good moving image quality and high definition while avoiding a shortage of a writing period and a problem of wiring layout. The purpose is to provide the technology.

  According to a first aspect of the present invention, there is provided an active matrix driving type image display apparatus having a plurality of electro-optic elements arranged in a matrix and a plurality of pixel circuits for driving the electro-optic elements. Each pixel circuit includes a capacitor, a write switch for charging the capacitor with a charge corresponding to an image signal value, and the electro-optic element according to a gate voltage based on the charge held in the capacitor. A drive transistor for driving, and a stop switch for stopping the light emission of the electro-optical element by discharging the capacitor, and the stop switches of the pixel circuits for at least two rows are connected to a common stop control line. Provided is an image display device which is connected and stops light emission of each electro-optic element in accordance with a stop control signal given via the common stop control line.

  According to a second aspect of the present invention, there is provided a control method for an active matrix driving type image display apparatus, which includes a plurality of electro-optical elements arranged in a matrix and a plurality of pixel circuits for driving the electro-optical elements. Each pixel circuit includes a capacitor, a driving transistor that drives the electro-optic element according to a gate voltage based on a charge held in the capacitor, and light emission of the electro-optic element by discharging the capacitor. The stop switch of at least the pixel circuit in the first row and the stop switch of the pixel circuit in the second row are connected to a common stop control line, and the control The method starts charging the first row of electro-optic elements by charging the capacitance of the pixel circuit in the first row with a charge corresponding to the value of the image signal, and the pixel circuit in the second row. By charging the capacitor with a charge corresponding to the value of the image signal, starting the light emission of the electro-optic elements of the second row, and applying a stop control signal via the common stop control line, And a step of stopping light emission of the electro-optic elements in the first row and the second row.

  According to the present invention, in an active matrix drive type image display device, it is possible to realize a good moving image quality and high definition while avoiding a shortage of a writing period and a problem of a wiring layout.

1 is a diagram schematically illustrating the overall configuration of an image display device according to a first embodiment. FIG. 3 is an equivalent circuit diagram of the pixel circuit according to the first embodiment. 4 is a timing chart showing the operation of the image display apparatus according to the first embodiment. The figure which shows the mode of light emission of the image display apparatus which concerns on 3rd Embodiment. The equivalent circuit schematic of the pixel circuit which concerns on 4th Embodiment. The figure which shows the mode of light emission of the image display apparatus which concerns on 4th Embodiment. The figure which shows typically the whole structure of the image display apparatus which concerns on 5th Embodiment. FIG. 10 is an equivalent circuit diagram of a pixel circuit according to a fifth embodiment. The figure which shows the mode of light emission of the image display apparatus which concerns on 5th Embodiment.

The present invention relates to an image display device, and more particularly to a configuration for controlling a light emission period (hold time) of each pixel. The present invention is preferably applied to an image display apparatus of an active matrix driving system having a plurality of electro-optical elements (display elements) arranged in a matrix and a plurality of pixel circuits for driving each electro-optical element. it can. Here, the electro-optical element refers to a self-luminous device whose emission intensity (luminance) is controlled by an electric signal (current signal or voltage signal), for example, an organic light emitting diode (OLED), an electron emitting element (cold cathode). Element) and a light emitting element composed of an electron beam excited phosphor.
Hereinafter, an embodiment of the present invention will be described by taking an ELD using an OLED as a light emitting element as an example.

(First embodiment)
FIG. 2 is an equivalent circuit diagram of the pixel circuit PXL corresponding to the upper and lower two pixels. In the figure, Vdd is a power supply voltage, A is an anode, K is a cathode, G is a gate, D is a drain, and S is a source.

  The scanning line Y is a wiring that supplies a selection signal for sequentially selecting the pixel circuits PXL row by row. The data line X is a wiring for supplying a data signal for instructing the light emission luminance of the pixel circuit PXL. The data signal is given as a voltage signal corresponding to the value (gradation information) of the image signal. A pixel circuit PXL is formed at the intersection of the scanning line Y and the data line X. The pixel circuit PXL is a circuit for driving the light emitting element OLED, and includes a write switch TFT1, a drive transistor TFT2, a storage capacitor Cs, and a stop switch TFT3.

  The light emitting element OLED is an electro-optical element whose luminance varies depending on the amount of current supplied. The write switch TFT1 is a transistor controlled by a selection signal supplied via the scanning line Y, and charges the holding capacitor Cs with a charge corresponding to the data signal supplied from the data line X when ON. As a result, gradation information is written in the pixel circuit PXL. The drive transistor TFT2 controls an electrical signal (current amount in this example) supplied to the light emitting element OLED according to the gate voltage based on the electric charge held in the holding capacitor Cs. The gradation information written in the pixel circuit PXL is held in the holding capacitor Cs even after the scanning line Y is not selected, so that the light emitting state of the light emitting element OLED is maintained.

  The stop switch TFT3 is a transistor for stopping driving (light emission) of the light emitting element OLED. The stop switch TFT3 is switched ON / OFF by a stop control signal given to the gate G via the stop control line Z. When the stop switch TFT3 is turned on, the holding capacitor Cs is discharged. As a result, the gate-source voltage Vgs of the driving transistor TFT2 becomes 0V, the driving current flowing through the light emitting element OLED is cut off, and the light emitting element OLED is turned off. In the present embodiment, the gate G of the stop switch TFT3 of the pixel circuits PXL for the upper and lower two rows is connected to the common stop control line Z, and the light emission stop control is performed in units of two rows.

  FIG. 1 schematically shows the overall configuration of the image display apparatus. The above-described circuit diagram of FIG. 2 corresponds to the broken line portion of FIG. The scanning lines Y1, Y2,..., YN are arranged in rows, and the data lines X are arranged in columns. A pixel circuit PXL is formed at each intersection of the scanning line Y and the data line X. Further, stop control lines Z1, Z2,..., ZN / 2 are formed in parallel with the scanning lines Y1, Y2,. One stop control line Z is arranged for each of the two scanning lines Y of the odd-numbered row (first row) and the even-numbered row (second row).

The scanning line Y is connected to the scanning line driving circuit 21. The scanning line driving circuit 21 includes a shift register, and sequentially selects the scanning lines Y1, Y2,..., YN by sequentially transferring the vertical start pulse VSP1 in synchronization with the vertical clock VCK. For example, when the frame frequency is 60 Hz, one scanning cycle is 1/60 second, and each scanning line Y is selected once per scanning cycle. On the other hand, the stop control line Z is connected to the light emission stop control circuit 23. The light emission stop control circuit 23 also includes a shift register. By sequentially transferring the vertical start pulse VSP2 in synchronization with the vertical clock VCK, stop control signals are sequentially supplied to the stop control lines Z1, Z2,..., ZN / 2. Output. The pulse VSP2 is delayed from the pulse VSP1 by a delay circuit 24 by a predetermined time.

  The data line X is connected to the data line driving circuit 22. The data line driving circuit 22 outputs a data signal to each data line X in synchronization with the line sequential scanning of the scanning lines Y. In this case, the data line driving circuit 22 performs so-called line sequential driving, and supplies data signals to all the pixels in the selected row all at once. The image processing circuit 20 performs necessary signal processing (for example, IP conversion, color conversion, gradation conversion, frame frequency conversion, etc.) on the image signal input to the image display device, and converts the converted image signal into data This is a circuit that outputs to the line drive circuit 22. In the data line driving circuit 22, a data signal (voltage signal) corresponding to the value of the image signal is generated based on the image signal given from the image processing circuit 20.

  FIG. 3 is a timing chart showing the operation of the image display apparatus. First, the vertical start pulse VSP 1 is input to the scanning line driving circuit 21 and the delay circuit 24. After receiving the pulse VSP1, the scanning line driving circuit 21 sequentially selects the scanning lines Y1, Y2,..., YN in synchronization with the vertical clock VCK. By supplying a data signal from the data line driving circuit 22 in synchronization with this scanning, gradation information is written to the pixel circuit PXL in units of scanning lines. The light emitting element OLED of each pixel circuit PXL starts light emission at an intensity corresponding to the written gradation information.

  The pulse VSP1 is delayed by the delay circuit 24 and input to the light emission stop control circuit 23 as the pulse VSP2. After receiving the pulse VSP2, the light emission stop control circuit 23 sequentially outputs stop control signals to the stop control lines Z1, Z2,..., ZN / 2 in synchronization with the vertical clock VCK. At this time, the shift register of the light emission stop control circuit 23 shifts the pulse VSP2 every two cycles of the vertical clock VCK. As a result, the light emission is stopped every two rows as in the scanning lines Y1 and Y2, Y3 and Y4,..., YN-1 and YN.

  According to this configuration, the light emission period of each pixel is a period from when the gradation information is written to the pixel circuit PXL until the light emission is stopped by the stop control signal. The length of the light emission period is approximately equal to the length of the delay time set by the delay circuit 24. Assuming that the delay time is t and one scanning cycle (one frame period) is T, the time ratio at which the pixels emit light, that is, the duty is approximately t / T. Strictly speaking, the light emission periods are slightly different between odd-numbered pixels and even-numbered pixels (portion A in FIG. 3), but in this embodiment, a difference in luminance due to this difference A is allowed.

  According to the configuration of the present embodiment described above, by appropriately adjusting the light emission period according to the delay time t of the delay circuit 24, hold blur can be suppressed and the image quality of the moving image can be improved. In addition, since the number of stop control lines Z can be halved as compared with the conventional configuration in which stop control lines are arranged in all rows, high definition is facilitated. Further, since the number of output stages of the light emission stop control circuit 23 may be half the number of scanning lines, the circuit scale can be reduced and the cost can be reduced. Further, since almost no current flows in the stop control line Z other than the current that charges and discharges the parasitic capacitance, image quality deterioration due to crosstalk hardly occurs.

(Second Embodiment)
In the first embodiment, as shown by A in FIG. 3, the light emission period of the odd-numbered pixels is longer than that of the even-numbered pixels by the selection period of one row. This is because the light emission start timing is different for each scanning line, whereas the light emission stop timing is the same for the two scanning lines sharing the stop control line Z. As a result, when the same gradation information is written, the odd-numbered pixels are slightly brighter than the even-numbered pixels.

  If the total number of scanning lines is N, the light emission period (corresponding to the delay time) of odd rows is t, and the scan cycle (one frame period) is T, the difference in light emission period length is T / N, and the same gradation The rate of change in luminance between odd and even lines when information is written is expressed as T / (N × t). Although it depends on the brightness of the image, it is generally said that the limit at which a luminance difference can be detected is approximately 1%. Therefore, when T / (N × t) is larger than about 0.01, that is, when the duty (t / T) is smaller than about 100 / N, uneven luminance may be visually recognized.

Therefore, in the image display apparatus of the present embodiment, the light emission stop timing, that is, the delay time of the delay circuit 24 is determined so that the duty satisfies the following conditional expression.
Duty> 100 / N
N: Number of scanning lines If the duty is too large, hold blur may occur, and the image quality of the moving image may deteriorate. Therefore, the upper limit of the duty may be determined as in the following conditional expression.
Duty <Dmax
Here, Dmax is a duty value that is an allowable limit of hold blur. A specific value of Dmax can be determined by subject experiment or the like. Note that Dmax may be a fixed value or may be changed according to the frame frequency, the brightness of the image, the amount of motion, and the like.
By such light emission period control, it is possible to achieve both suppression of luminance unevenness and hold blur, and display a high-quality moving image.

  The method of the second embodiment described above cannot be used when 100 / N ≧ Dmax. Therefore, in the third embodiment and the fourth embodiment described below, a means for suppressing luminance unevenness due to the difference in the length of the light emission period between a plurality of rows connected to a common stop control line is provided separately.

(Third embodiment)
In the third embodiment, luminance unevenness caused by the difference in the length of the light emission period is suppressed by correcting the image signal (tone value). Hereinafter, differences from the first embodiment will be described in detail.

  FIG. 4 shows the state of light emission in the odd and even rows. The horizontal axis represents time, and the vertical axis represents emission intensity. The control of the light emission start timing and the light emission stop timing is the same as in the first embodiment (see FIG. 3), and the light emission period is longer in the odd-numbered rows as indicated by A. The brightness perceived by humans corresponds to the time integral of the emission intensity, that is, the area of the graph of FIG. Therefore, in order to eliminate the difference in brightness between the odd and even rows, the emission intensity may be adjusted so that the areas of the graph in FIG. 4 are the same.

  In the present embodiment, the image signals in the odd-numbered rows are reduced (light emission intensity is reduced) so that the areas of the portions A and B in FIG. 4 are the same. For example, when the light emission period of the odd-numbered row is longer by 2% than that of the even-numbered row, the odd-numbered image signal may be multiplied by a gain (for example, 0.98) that makes the odd-numbered row image signal 2% smaller. . If the value of the image signal is not proportional to the light emission intensity, the image signal is converted into a linear signal with respect to the light emission intensity and then multiplied by a gain, or the gain considering the nonlinearity of the image signal and the light emission intensity is taken into account. A value may be used. These processes are performed by the image processing circuit 20 of FIG.

  With the above-described configuration, luminance unevenness due to the difference in the length of the light emission period can be suppressed. Furthermore, unlike the second embodiment, since there is no lower limit (constraint) in the duty, the duty can be set to a value of 1 / N or less as required, and hold blur can be reliably suppressed.

In this embodiment, the odd-numbered image signal is corrected. However, the same result can be obtained by correcting the even-numbered image signal or correcting both the odd-numbered and even-numbered image signals. However, as in the present embodiment, it is preferable that an image signal having a longer light emission period is a correction target. The reason for this is that when correcting an image signal with a shorter light emission period, the value of the image signal is increased (for example, multiplied by a gain greater than 1), so that the corrected value does not overflow. This is because it is necessary to add means (for example, a limiter circuit).

(Fourth embodiment)
As described above, when the light emission periods are different between the odd-numbered rows and the even-numbered rows, there is a possibility that jagged edges (jaggy) may be seen at the edge of the object in the video when the fast-moving video is viewed. This is because, due to the afterimage, the picture in the row with the longer light emission period looks wider than the picture in the row with the shorter light emission period. Therefore, in the fourth embodiment, the difference in the light emission period for each row is reduced by providing a difference in the decay rate (for example, time constant) of the light emission intensity when light emission is stopped. Hereinafter, differences from the first embodiment will be described in detail.

  FIG. 5 is an equivalent circuit diagram of the pixel circuit of the fourth embodiment. The difference from the first embodiment (see FIG. 2) is that a resistor R is added to the source side of the stop switch TFT 32 in the pixel circuits PXL in even rows.

  FIG. 6 shows the state of light emission in the odd and even rows. The horizontal axis represents time, and the vertical axis represents emission intensity. The control of the light emission start timing and the light emission stop timing is the same as in the first embodiment (see FIG. 3). When light emission is stopped, a light emission stop signal is simultaneously applied to the gates G of both the odd-numbered stop switch TFT 31 and the even-numbered stop switch TFT 32 by the common stop control line Z. At this time, in the odd-numbered pixel circuit PXL, the charge in the storage capacitor Cs1 is quickly discharged, and light emission stops immediately. On the other hand, in the pixel circuits PXL in the even-numbered rows, the discharge of the storage capacitor Cs2 gradually proceeds due to the action of the resistor R, so that the drive current amount (that is, the emission intensity of the OLED) of the drive transistor TFT22 attenuates with a predetermined time constant. As a result, the difference between the light emission periods of the odd and even rows is reduced.

  The time constant is determined by the storage capacitor Cs2, the resistance R, other parasitic capacitances and parasitic resistances around the discharge path, the gate capacitance of the stop switch TFT 32, and the like. Therefore, the size, structure, characteristics, etc. of each element of the pixel circuit PXL may be set so that the area C in FIG. 6 has the same area as the area A. For example, since the ON resistance of the stop switch TFT 32 can be adjusted by changing the gate width and the gate length, the resistance R can be substantially adjusted. If the decay rate of the light emission intensity (drive current) is adjusted, any element such as the storage capacitor Cs2, the resistor R2, and other parasitic capacitances and parasitic resistances around the discharge path may be changed.

  With the above-described configuration, the difference in the light emission period for each row can be reduced, so that it is possible to suppress jaggedness (jaggy) when a fast-moving video is viewed. Further, by making the areas A and C the same as shown in FIG. 6, luminance unevenness can be suppressed. In addition, unlike the third embodiment, there is no need for a special circuit for correcting the image signal, and it can be performed only by changing the pattern of the exposure mask for creating the display panel substrate. Therefore, there is an advantage that the production cost is hardly increased. .

(Fifth embodiment)
Hereinafter, the configuration of the image display apparatus according to the fifth embodiment will be described in detail with respect to differences from the first embodiment.

FIG. 7 is a diagram schematically illustrating the overall configuration of the image display apparatus according to the fifth embodiment. FIG. 8 is an equivalent circuit diagram of pixel circuits for four rows, corresponding to the broken line portion of FIG. The difference from the first embodiment is that two stop control lines Z are connected to the same output stage of the light emission stop control circuit 23, and the pixel circuits for four rows are controlled by the same stop control signal. The difference is that the decay rate of the drive current is different in the pixel circuits for the rows.

  Specifically, as shown in FIG. 7, one stop control line Z is arranged for every two scanning lines Y, and the two stop control lines Z are bundled together at the take-out portion to stop light emission. It is connected to one output stage of the control circuit 23. As a result, the number of output stages of the light emission stop control circuit 23 is half that of the first embodiment.

  Further, as shown in FIG. 8, resistors R2, R3, and R4 are provided in the stop switches TFT32, TFT33, and TFT34 of the second to fourth pixel circuits PXL in the set of four rows, respectively. By setting the ratio of the values of the resistors R2, R3, and R4 to approximately 1: 2: 3, the decay rate of the drive current when the light emission is stopped can be decreased in order from the first to the fourth. The specific method for forming the resistor is as described in the fourth embodiment.

  FIG. 9 shows how each of the first to fourth pixel circuits emits light. The horizontal axis represents time, and the vertical axis represents emission intensity. The control of the light emission start timing and the light emission stop timing is the same as in the first embodiment (see FIG. 3). Due to the action of the resistors R2 to R4, the lowering of the emission intensity becomes more gradual in the later rows. As a result, the difference between the light emission periods of the four rows is reduced.

  With the configuration described above, in addition to the same effects as those of the above-described embodiment, the circuit scale can be reduced and the cost can be reduced by further reducing the number of output stages of the light emission stop control circuit 23.

  In the present embodiment, two stop control lines Z are connected to the same output stage. However, if more stop control lines Z are connected to the same output stage, the number of output stages of the light emission stop control circuit 23 is further reduced. it can. Further, in this embodiment, luminance unevenness due to the difference in the light emission period is suppressed by the resistors R2 to R3. However, as described in the fourth embodiment, the storage capacitor, the gate capacitor, and the like are adjusted, or described in the third embodiment. The same effect can be obtained by correcting the image signal as described above. In addition, when luminance unevenness is not a problem as in the first and second embodiments, a configuration for suppressing luminance unevenness is not necessary.

  Each embodiment described above is only a specific example of the present invention, and does not limit the scope of the present invention. For example, in the above embodiment, the pixel circuits for two rows are connected to one stop control line, but a configuration in which pixel circuits for three or more rows are connected to a common stop control line may be employed. In addition, the present invention is applicable to other than an ELD as long as it is an active matrix drive type image display device having a plurality of electro-optical elements and a pixel circuit that outputs an electric signal for driving each electro-optical element. it can. For example, the present invention can also be applied to an FED that uses a light-emitting element composed of an electron-emitting element and a phosphor as an electro-optical element. In the pixel circuit in the case of FED, it is preferable to use an electron-emitting device with a voltage signal by a source follower circuit. The present invention can also be applied to an image display device having another pixel circuit (such as various pixel circuits for compensating for characteristic variations of TFTs). In each of the above embodiments, each switch and driving transistor may be a field effect transistor, preferably a thin film transistor.

OLED: Light emitting element (electro-optic element)
PXL: Pixel circuit Cs, Cs1, Cs2: Retention capacitance TFT1, TFT11, TFT12: Write switch TFT2, TFT21, TFT22: Drive transistor TFT3, TFT31, TFT32, TFT33, TFT34: Stop switch Z: Stop control line

Claims (7)

An active matrix drive type image display device having a plurality of electro-optic elements arranged in a matrix and a plurality of pixel circuits for driving each electro-optic element,
Each pixel circuit
Capacity,
A write switch for charging the capacitor with a charge corresponding to the value of the image signal;
A driving transistor for driving the electro-optic element in accordance with a gate voltage based on the charge held in the capacitor;
A stop switch that stops light emission of the electro-optic element by discharging the capacitance;
Have
Stop switches of at least two rows of pixel circuits are connected to a common stop control line, and stop light emission of each electro-optical element in accordance with a stop control signal given through the common stop control line. A characteristic image display device. A duty which is a ratio of a light emission period of the electro-optical element with respect to one scanning cycle,
Duty> 100 / N
2. The image display apparatus according to claim 1, wherein the light emission stop timing of the electro-optic element by the stop control signal is determined so as to satisfy N: the number of scanning lines. The image display apparatus according to claim 1, further comprising means for suppressing luminance unevenness caused by a difference in length of light emission periods between a plurality of rows connected to a common stop control line. The means for suppressing the luminance unevenness performs a correction on the image signal to reduce the value of the image signal in the row having the longer light emission period or to increase the value of the image signal in the row having the shorter light emission period. The image display device according to claim 3, wherein the image display device is a circuit. The means for suppressing the luminance unevenness delays the decay rate of the light emission intensity of the electro-optical element when light emission is stopped by the stop switch in a row having a shorter light emission period than a row having a longer light emission period. The image display device according to claim 3, wherein the image display device is a circuit. A light emission stop control circuit having a plurality of output stages for outputting a stop control signal;
6. The image display device according to claim 1, wherein two or more stop control lines are connected to the same output stage of the light emission stop control circuit. A control method for an active matrix drive type image display apparatus, comprising: a plurality of electro-optical elements arranged in a matrix; and a plurality of pixel circuits for driving each electro-optical element,
Each pixel circuit includes a capacitor, a driving transistor that drives the electro-optic element according to a gate voltage based on a charge held in the capacitor, and a stop that stops light emission of the electro-optic element by discharging the capacitor. A switch, and
At least the stop switch of the pixel circuit in the first row and the stop switch of the pixel circuit in the second row are connected to a common stop control line,
The control method is:
Charging light corresponding to the value of the image signal to the capacitance of the pixel circuit in the first row to start light emission of the electro-optic element in the first row;
Starting the light emission of the electro-optic elements in the second row by charging the capacitance of the pixel circuits in the second row with a charge corresponding to the value of the image signal;
Stopping light emission of the electro-optic elements in the first row and the second row by providing a stop control signal via the common stop control line;
A control method for an image display device.

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