JP2012084786A - Led package - Google Patents
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- JP2012084786A JP2012084786A JP2010231478A JP2010231478A JP2012084786A JP 2012084786 A JP2012084786 A JP 2012084786A JP 2010231478 A JP2010231478 A JP 2010231478A JP 2010231478 A JP2010231478 A JP 2010231478A JP 2012084786 A JP2012084786 A JP 2012084786A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
Description
本発明は優れた放熱性を有するLEDパッケージに関する。 The present invention relates to an LED package having excellent heat dissipation.
従来のLEDパッケージは、素子をリードフレーム、セラミック基板、ガラスエポキシ製プリント基板、BT製プリント基板等の配線基板上に載せ、電極をワイヤボンド、はんだ、高放熱性接着剤等で固定したものが一般的であった。 A conventional LED package has an element mounted on a wiring board such as a lead frame, a ceramic substrate, a glass epoxy printed board, or a BT printed board, and electrodes fixed with wire bond, solder, high heat dissipation adhesive, or the like. It was general.
また、近年の照明や液晶光源の高出力化によりLEDチップ、あるいは各種LEDチップを搭載したパッケージの発熱量が増大する傾向がある。このため、基板あるいは半導体部品においては、良好な放熱性と、熱応力に対する破断強度が求められている。 In addition, with the recent increase in output of illumination and liquid crystal light sources, there is a tendency that the amount of heat generated by the LED chip or a package equipped with various LED chips increases. For this reason, in a board | substrate or a semiconductor component, favorable heat dissipation and the breaking strength with respect to a thermal stress are calculated | required.
LEDパッケージの放熱性を高める手段として、セラミック基板の使用やリードフレームの厚さを厚くすることは一般に行われている。 In general, the use of a ceramic substrate and the increase of the thickness of the lead frame are performed as means for improving the heat dissipation of the LED package.
特許文献1は、セラミック製絶縁基体上に半導体素子搭載部を有し、絶縁基体の下面に外部電気回路基板が接続パッドを介してろう付される配線基板において、接続パッドの外周縁近傍に所定形状の間隙を設けることにより、ろう付部の破断を防止するようにしたものである。 Japanese Patent Laid-Open No. 2004-228688 has a semiconductor element mounting portion on a ceramic insulating base, and a predetermined wiring board is provided in the vicinity of the outer peripheral edge of the connection pad in a wiring board in which an external electric circuit board is brazed to the lower surface of the insulating base via a connection pad. By providing a gap of the shape, the brazing part is prevented from being broken.
特許文献2に記載された配線基板は、絶縁材中に金属放熱体が基板の上下を貫く態様で埋め込んだものであり、金属板の上下両面に順次ハーフエッチング加工を施して両面から凹部を形成し、これらの凹部内に絶縁性樹脂を充填することにより、金属板を上下方向に貫く絶縁層を形成することによって製造される。
The wiring board described in
特許文献3に記載されたLED部品は、セラミック基板に貫通孔を設け、その孔の内部にLEDチップを実装した放熱板をろう付したものである。
The LED component described in
特許文献4に記載された発光素子搭載用基板は、セラミック粉末とバインダを混合したスラリーで薄板上に形成したグリーンシート上に絶縁層を印刷するとともに配線パターンを印刷し、焼結したものである。
The light emitting element mounting substrate described in
しかしながら、特許文献1〜4の技術には、それぞれに基板の材料や形態に起因して以下のような問題点がある。
However, the techniques of
セラミック基板は樹脂基板よりも高い放熱性能を有しているが、金属よりも放熱性能が劣っている。また、セラミック基板の切断加工や孔明け加工は、破断しないように加工するには格別の加工技術が必要であるため、加工コストが高くなる。 The ceramic substrate has higher heat dissipation performance than the resin substrate, but is inferior to metal in terms of heat dissipation performance. Further, the cutting process and drilling process of the ceramic substrate requires a special processing technique to process the ceramic substrate so as not to break, so that the processing cost becomes high.
また、リードフレームでは複雑な加工が必要になる等、手間とコストがかかるという問題がある。しかも絶縁層が樹脂で構成されているため、LEDチップとの熱膨張差が大きく、繰り返し使用による熱履歴によって断線を起こすことがある。 In addition, the lead frame has a problem that it requires labor and cost, such as complicated processing. Moreover, since the insulating layer is made of resin, the difference in thermal expansion from the LED chip is large, and disconnection may occur due to thermal history due to repeated use.
また、金属基板を、特許文献3のような両面基板に加工するには複雑な加工が必要である。しかも絶縁層が樹脂であるために放熱性が不十分である、また、安価な片面基板では発光面の裏面に電極を設けることができないために、チップを表面実装することができず、チップの実装が複雑になる。
Further, in order to process a metal substrate into a double-sided substrate as in
本発明は、上記技術背景に鑑み、放熱性に優れ、LEDチップが基板に表面実装されたLEDパッケージの提供を目的とする。 In view of the above technical background, an object of the present invention is to provide an LED package that is excellent in heat dissipation and has an LED chip surface-mounted on a substrate.
即ち、本発明は下記[1]〜[5]に記載の構成を有する。 That is, this invention has the structure as described in following [1]-[5].
[1]LEDチップを搭載する基板が、金属からなる複数の導電部と、無機物からなりこれらの導電部を電気的に絶縁する絶縁部とを有し、前記導電部および絶縁部がチップ搭載面から垂直方向に積層された状態で一体化されてなり、
前記基板の導電部にLEDチップが接合されていることを特徴とするLEDパッケージ。
[1] A substrate on which the LED chip is mounted has a plurality of conductive parts made of metal and an insulating part made of an inorganic material and electrically insulating these conductive parts, and the conductive part and the insulating part are chip mounting surfaces. Are integrated in a vertically stacked state from
An LED package, wherein an LED chip is bonded to the conductive portion of the substrate.
[2]前記絶縁部を構成する無機物が酸化アルミニウム、窒化アルミニウム、窒化ケイ素、酸化ジルコニウムのうちの少なくとも1種である前項1に記載のLEDパッケージ。 [2] The LED package according to [1], wherein the inorganic material constituting the insulating portion is at least one of aluminum oxide, aluminum nitride, silicon nitride, and zirconium oxide.
[3]前記絶縁部を構成する無機物は、JIS Z8715で規定される白色度が50%以上である前項1または2に記載のLEDパッケージ。
[3] The LED package according to
[4]前記導電部上に、該導電部とは異なる金属層が形成されている前項1〜3のいずれかに記載のLEDパッケージ。 [4] The LED package according to any one of [1] to [3], wherein a metal layer different from the conductive portion is formed on the conductive portion.
[5]前記金属層は電解めっきによって形成されためっき皮膜である前項4に記載のLEDパッケージ。
[5] The LED package according to
上記[1]に記載の発明にかかるLEDパッケージは、LEDチップを搭載する基板が、金属からなる複数の導電部と、無機物からなりこれらの導電部を電気的に絶縁する絶縁部とを有し、前記導電部および絶縁部がチップ搭載面から垂直方向に積層された状態で一体化したものである。かかる基板構造において、前記導電部はチップ搭載面とその対向面との間を貫いているので、基板のチップ搭載面において導電部上にLEDチップを接合すると、対向面においてその導電部に電極を接続することができる。従って、基板にスルーホール等の加工を施すことなく両面基板として使用でき、LEDチップの表面実装が可能である。 In the LED package according to the invention described in [1] above, the substrate on which the LED chip is mounted has a plurality of conductive parts made of metal and an insulating part made of an inorganic material and electrically insulating these conductive parts. The conductive portion and the insulating portion are integrated in a state where they are stacked in the vertical direction from the chip mounting surface. In such a substrate structure, since the conductive portion penetrates between the chip mounting surface and the opposing surface, when an LED chip is bonded on the conductive portion on the chip mounting surface of the substrate, an electrode is formed on the conductive portion on the opposing surface. Can be connected. Accordingly, the substrate can be used as a double-sided substrate without processing through holes or the like, and the surface mounting of the LED chip is possible.
また、前記導電部は金属であり基板の厚さを有していることでヒートシンクとして機能し、導電部に接合されたLEDチップが発生する熱は直接導電部に放熱され、あるいは絶縁部を介して他の導電部にも放熱されるので、優れた放熱性能が得られる。 Further, the conductive part is a metal and has a thickness of the substrate, so that it functions as a heat sink, and heat generated by the LED chip bonded to the conductive part is directly radiated to the conductive part or via an insulating part. Since heat is radiated to other conductive parts, excellent heat radiation performance can be obtained.
さらに、前記絶縁部を構成する無機物は熱膨張係数率が小さいので、大発熱量や発熱と冷却の反復に対しても破線や断線が発生しにくい。 Further, since the inorganic material constituting the insulating portion has a small coefficient of thermal expansion, broken lines and disconnections are less likely to occur even when the amount of heat generation is large or heat and cooling are repeated.
上記[2]に記載のLEDパッケージは、絶縁部が酸化アルミニウム、窒化アルミニウム、窒化ケイ素、酸化ジルコニウムのうちのうちの少なくとも1種で形成されているため、優れた電気絶縁性および放熱性が得られる。また、これらの無機物の熱膨張係数は、LEDチップに用いられているサファイア基板の熱膨張係数に近似しているので、LEDチップの接合部に発生する熱収縮応力が小さく、接合部の破断、切断、剥がれが発生しない、あるいは発生しにくい。 In the LED package described in [2] above, since the insulating portion is formed of at least one of aluminum oxide, aluminum nitride, silicon nitride, and zirconium oxide, excellent electrical insulation and heat dissipation are obtained. It is done. In addition, since the thermal expansion coefficient of these inorganic substances approximates the thermal expansion coefficient of the sapphire substrate used in the LED chip, the thermal contraction stress generated in the joint part of the LED chip is small, the joint part breaks, Cutting or peeling does not occur or is difficult to occur.
上記[3]に記載のLEDパッケージは、絶縁部の白色度が50%以上の無機物で形成されているため、LEDチップが発する光が拡散反射し、光の利用効率が良い。 Since the LED package described in [3] is formed of an inorganic material having a whiteness of the insulating portion of 50% or more, the light emitted from the LED chip is diffusely reflected and the light use efficiency is good.
上記[4]に記載のLEDパッケージは、導電部上に金属層が設けられているので、導電部表面の酸化膜形成が抑制されるとともにLEDチップやボンディングワイヤとのはんだ接合性が向上し、優れた導電性および放熱性が得られる。 In the LED package according to the above [4], since the metal layer is provided on the conductive portion, the formation of an oxide film on the surface of the conductive portion is suppressed and the solder bonding property with the LED chip and the bonding wire is improved. Excellent conductivity and heat dissipation can be obtained.
上記[5]に記載の半導体パッケージは導電部上の金属層を電解めっきで形成したものである。電解めっきは容易に金属層を形成でき、かつ絶縁部に金属層が形成されないのでマスキングが不要である。これらの点で、電解めっきによれば低コストで金属層を形成することができる。 In the semiconductor package described in [5] above, the metal layer on the conductive portion is formed by electrolytic plating. Electrolytic plating can easily form a metal layer and does not require a mask because no metal layer is formed on the insulating portion. In these respects, the electrolytic plating can form a metal layer at low cost.
[LEDパッケージ]
図1および図2は本発明のLEDパッケージに用いる基板(1)(2)を示す斜視図であり、図3A、図3Bおよび図4はこれらの基板を用いたLEDパッケージ(3A)(3B)(4)である。これらの図面において、基板(1)(2)の上面がチップ搭載面(M1)、下面がチップ搭載面(M1)の対向面(M2)であり、チップ搭載面(M1)と対向面(M2)との距離が基板(1)(2)の厚さ(t)を示している。
[LED package]
1 and 2 are perspective views showing substrates (1) and (2) used in the LED package of the present invention, and FIGS. 3A, 3B and 4 show LED packages (3A) and (3B) using these substrates. (4). In these drawings, the upper surfaces of the substrates (1) and (2) are the chip mounting surface (M1), the lower surface is the facing surface (M2) of the chip mounting surface (M1), and the chip mounting surface (M1) and the facing surface (M2). ) Indicates the thickness (t) of the substrates (1) and (2).
基板(1)において、導電部(11a)(11b)および絶縁部(12)は、それぞれがチップ搭載面(M1)と対向面(M2)との間を貫き、チップ搭載面(M1)において導電部(11a)、絶縁部(12)、導電部(11b)の順に並び、これらが一体化されている。従って、導電部(11a)(11b)および絶縁部(12)はチップ搭載面(M1)から垂直方向に積層され、導電部(11a)(11b)および絶縁部(12)の全てがチップ搭載面(M1)および対向面(M2)の両方の面に露出し、(t)なる基板(1)の厚さを有している。また、前記チップ搭載面(M1)の三者の積層方向の寸法は(w)で表され、積層方向における導電部(11a)の寸法が(w1a)、絶縁部(12)の寸法が(w2)、導電部(11b)の寸法が(w1b)で表されている。また、チップ搭載面(M1)の他の一辺の寸法は(d)で表されている。 In the substrate (1), each of the conductive portions (11a) (11b) and the insulating portion (12) penetrates between the chip mounting surface (M1) and the opposing surface (M2), and is electrically conductive on the chip mounting surface (M1). The part (11a), the insulating part (12), and the conductive part (11b) are arranged in this order, and these are integrated. Accordingly, the conductive portions (11a) (11b) and the insulating portion (12) are stacked vertically from the chip mounting surface (M1), and all of the conductive portions (11a) (11b) and the insulating portion (12) are mounted on the chip mounting surface. It is exposed on both the (M1) and the opposing surface (M2), and has a thickness (t) of the substrate (1). The dimension of the chip mounting surface (M1) in the stacking direction of the three members is represented by (w), the dimension of the conductive part (11a) in the stacking direction is (w1a), and the dimension of the insulating part (12) is (w2). ), The dimension of the conductive portion (11b) is represented by (w1b). The dimension of the other side of the chip mounting surface (M1) is represented by (d).
本発明において、基板が複数の導電部を有し、これらの導電部が絶縁部によって電気的に絶縁されている限り、それぞれの数は任意である。図2に示す基板(2)は3つの導電部(11c)(11d)(11e)と2つの絶縁部(12)とが交互に積層したものである。また、各部の寸法も任意に設定することができ、例えば図1の基板(1)は、2つ導電部(11a)(11b)の寸法が異なり、一方の導電部(11a)の寸法(w1a)<他方の導電部(11a)の寸法(w1b)の関係にある。 In the present invention, as long as the substrate has a plurality of conductive portions, and these conductive portions are electrically insulated by the insulating portions, the number of each is arbitrary. The substrate (2) shown in FIG. 2 has three conductive portions (11c) (11d) (11e) and two insulating portions (12) stacked alternately. Moreover, the dimension of each part can also be set arbitrarily, for example, the board | substrate (1) of FIG. 1 differs in the dimension of two electroconductive parts (11a) (11b), and the dimension (w1a) of one electroconductive part (11a). ) <Dimension (w1b) of the other conductive portion (11a).
前記導電部(11a)…(11e)は金属からなる。導電部(11a)…(11e)は配線部であり、かつヒートシンクとしても機能するものであるから、導電性および放熱性の両方が良好な金属を用いることが好ましく、アルミニウムおよび銅を推奨できる。アルミニウムは、純アルミニウム、アルミニウム合金のいずれでも良く、導電率が良く、基板としての強度、硬度を有する組成のものを適宜使用する。銅もまた、圧延銅、電解銅などの種類や合金組成を問わず使用でき、導電性が良く、基板としての強度、硬度を有する組成のものを適宜使用する。 The conductive portions (11a) (11e) are made of metal. Since the conductive portions (11a)... (11e) are wiring portions and also function as heat sinks, it is preferable to use a metal having good conductivity and heat dissipation, and aluminum and copper can be recommended. Aluminum may be either pure aluminum or an aluminum alloy, and a material having good electrical conductivity and strength and hardness as a substrate is appropriately used. Copper can be used regardless of the type and alloy composition of rolled copper, electrolytic copper, etc., and has a good conductivity and a composition having strength and hardness as a substrate.
また、図3A〜図4に示すように、前記導電部(11a)…(11e)上にはLEDチップ(20)やボンディングワイヤ(15)との導電性および接合性を高めるために、導電部(11a)…(11e)とは異なる金属層(13)を設けることも好ましい。導電部(11a)…(11e)として銅を使用した場合は表面酸化が起こりやすく、酸化膜が導電性を低下させる原因となるので、金属層(13)の形成によって導電部(11a)…(11e)の表面酸化を防ぐことができる。また、アルミニウムはもとよりはんだ適応性の良くない金属であるから、アルミニウムの導電部(11a)…(11e)上に金属層(13)を形成するによってはんだ接合特性を高めることができる。前記金属層(13)の金属は、導電部(11a)…(11e)の表面酸化防止、はんだ接合特性の向上という観点より、金、銀、ニッケルが好ましい。これらの金属は熱伝導性が良好であるから、導電部(11a)…(11e)の放熱性を低下させるものではない。 Further, as shown in FIGS. 3A to 4, on the conductive portions (11a)... (11e), in order to improve the conductivity and bonding properties with the LED chip (20) and the bonding wire (15), the conductive portions It is also preferable to provide a metal layer (13) different from (11a) ... (11e). When copper is used as the conductive portion (11a) (11e), surface oxidation is likely to occur, and the oxide film causes a decrease in conductivity. Therefore, the formation of the metal layer (13) causes the conductive portion (11a) ( 11e) surface oxidation can be prevented. In addition, since aluminum is a metal with poor solder adaptability, solder joint characteristics can be improved by forming a metal layer (13) on the conductive portions (11a)... (11e) of aluminum. The metal of the metal layer (13) is preferably gold, silver, or nickel from the viewpoint of preventing surface oxidation of the conductive portions (11a) to (11e) and improving solder joint characteristics. Since these metals have good thermal conductivity, they do not reduce the heat dissipation of the conductive portions (11a) (11e).
前記金属層(13)の形成方法は限定されず、導電部(11a)…(11e)にめっきを施してめっき皮膜を金属層とする方法、蒸着による方法、導電部(11a)…(11e)の材料としてクラッド材を使用し、クラッド材の心材を導電部とし、皮材を金属層とする方法等を例示できる。これらの形成方法の中で電解めっきを推奨できる。電解めっきは金属層(13)の形成が容易であり、また絶縁部(12)には金属層(12)が形成されないのでマスキングが不要である。これらの点で、電解めっきによれば低コストで金属層(13)を形成することができる。 The method of forming the metal layer (13) is not limited, and the method of plating the conductive portions (11a) ... (11e) to form a plating film as a metal layer, the method by vapor deposition, the conductive portions (11a) ... (11e) Examples thereof include a method in which a clad material is used as the material, a core material of the clad material is used as a conductive portion, and a skin material is used as a metal layer. Among these forming methods, electrolytic plating can be recommended. Electroplating makes it easy to form the metal layer (13), and no masking is required because the metal layer (12) is not formed on the insulating portion (12). In these respects, the electroplating can form the metal layer (13) at low cost.
前記金属層(13)は絶縁部(12)上に形成しないことは当然であるが、後述するように絶縁部(12)の寸法(w2)は小さいものであるから、金属層(13)のショートを確実に防止するために、絶縁部(12)上に金属層(13)の厚さと同等またはそれ以上の厚さの絶縁絶層(16)を形成することが好ましい(図3A参照)。この絶縁層(16)は、金属層(13)の形成後に絶縁塗料を塗布する等の簡単な方法で簡単に形成することができる。絶縁塗料の種類は限定されないが、LEDチップ(20)を搭載するので、光による劣化が少なくかつ光反射率の高い絶縁塗料を使用することが好ましい。 Of course, the metal layer (13) is not formed on the insulating portion (12). However, since the dimension (w2) of the insulating portion (12) is small as described later, the metal layer (13) In order to surely prevent a short circuit, it is preferable to form an insulating insulating layer (16) having a thickness equal to or greater than the thickness of the metal layer (13) on the insulating portion (12) (see FIG. 3A). The insulating layer (16) can be easily formed by a simple method such as applying an insulating paint after forming the metal layer (13). The type of the insulating paint is not limited, but since the LED chip (20) is mounted, it is preferable to use an insulating paint with little light degradation and high light reflectance.
また、図示例では導電部(11a)…(11e)のチップ搭載面(M1)側および対向面(M2)側の両面に金属層(13)を形成している。これは、本発明に用いる基板(1)(2)は導電部(11a)…(11e)が両面間を貫く両面基板であり、導電部(11a)…(11e)が対向面側(M2)において電極となされ別の基板等に通電可能に接続されるからである。従って、金属層(13)は導電部(11a)…(11e)の両面に形成することが好ましい。 In the illustrated example, metal layers (13) are formed on both the chip mounting surface (M1) side and the opposing surface (M2) side of the conductive portions (11a)... (11e). This is because the substrates (1) and (2) used in the present invention are double-sided substrates in which the conductive portions (11a)... (11e) penetrate between both surfaces, and the conductive portions (11a). This is because the electrode is connected to another substrate or the like so as to be energized. Therefore, the metal layer (13) is preferably formed on both surfaces of the conductive portions (11a)... (11e).
前記絶縁部(12)は無機物からなる。無機物は樹脂よりも熱伝導性が良く高い放熱性を有する。電気絶縁性と放熱性を兼ね備える無機物として、酸化アルミニウム、窒化アルミニウム、窒化ケイ素、酸化ジルコニウム等のセラミックを推奨できる。搭載するLEDチップ(20)にはサファイア基板(酸化アルミニウム基板)の使用が一般的であり、上述したセラミックの熱膨張係数はサファイア基板の熱膨張係数に近似しているので、LEDチップ(20)の接合部に発生する熱収縮応力が小さく、接合部の破断、切断、剥がれが発生しない、あるいは発生しにくい。 The insulating part (12) is made of an inorganic material. Inorganic substances have better heat conductivity and higher heat dissipation than resins. Ceramics such as aluminum oxide, aluminum nitride, silicon nitride, and zirconium oxide can be recommended as inorganic materials that have both electrical insulation and heat dissipation. As the LED chip (20) to be mounted, a sapphire substrate (aluminum oxide substrate) is generally used, and since the thermal expansion coefficient of the ceramic described above approximates that of the sapphire substrate, the LED chip (20) The heat shrinkage stress generated in the joint is small, and the joint is not broken or cut off or peeled off.
また、基板(1)(2)にはLEDチップ(20)を搭載するので、絶縁部(12)の表面が反射板として作用する。このため、光が拡散反射する白色または白色に近い無機物を使用することが好ましい。光が拡散反射するとLEDチップ(20)が発する光の利用効率が高くなる。白色の程度は、JIS Z 8715で規定される白色度が50%以上であることが好ましく、特に70%以上であることが好ましい。 Moreover, since the LED chip (20) is mounted on the substrates (1) and (2), the surface of the insulating portion (12) acts as a reflector. For this reason, it is preferable to use white or near-white inorganic material that diffusely reflects light. When light is diffusely reflected, the utilization efficiency of light emitted from the LED chip (20) is increased. As for the degree of whiteness, the whiteness specified by JIS Z 8715 is preferably 50% or more, and particularly preferably 70% or more.
また、基板が複数の導電部あるいは複数の絶縁部を有する場合、それらの材料は同一材料であっても良いし異種材料であっても良い。複数の導電部に異種材料を用いる場合、LEDチップを接合する導電部をより熱伝導率の高い材料で作製することによって放熱効率を高めることができる。また、LEDチップを接合する導電部を光反射率の高い材料で作製することにより前方への光の取出し効率を高めることができる。 When the substrate has a plurality of conductive parts or a plurality of insulating parts, these materials may be the same material or different materials. In the case where different materials are used for the plurality of conductive portions, the heat radiation efficiency can be increased by producing the conductive portions for joining the LED chips with a material having higher thermal conductivity. Moreover, the light extraction efficiency to the front can be improved by manufacturing the conductive part for joining the LED chip with a material having high light reflectance.
基板(1)(2)において、導電部(11a)〜(11e)および絶縁部(12)の寸法および厚さは限定されず、LEDチップ(20)の寸法や搭載方法、使用電圧における絶縁性確保に要する寸法、LEDチップ(20)の発熱量等に応じて任意に設定することができる。 In the substrates (1) and (2), the dimensions and thickness of the conductive parts (11a) to (11e) and the insulating part (12) are not limited. The dimensions and mounting method of the LED chip (20), and the insulation at the operating voltage It can be arbitrarily set according to the dimensions required for securing, the heat generation amount of the LED chip (20), and the like.
図3Aは前記基板(1)にLEDチップ(20)を表面実装したLEDパッケージ(3A)の例を示している。2つの導電部(11a)(11b)は積層方向における寸法に大小の差があり、一方の導電部(11b)の寸法(w1b)が他方の導電部(11a)の寸法(w1a)よりも大きく、大きい導電部(11b)にLEDチップ(20)をはんだ、導電性接着剤等の接合層(14)を接合し、小さい導電部(11a)にボンディングワイヤ(15)を接合している。これにより、LEDチップ(20)から発生する熱を大きい導電部(11b)から効率良く放熱することができる。 FIG. 3A shows an example of an LED package (3A) in which an LED chip (20) is surface-mounted on the substrate (1). The two conductive portions (11a) and (11b) have a difference in size in the stacking direction, and the size (w1b) of one conductive portion (11b) is larger than the size (w1a) of the other conductive portion (11a). The LED chip (20) is soldered to the large conductive portion (11b), the bonding layer (14) such as a conductive adhesive is bonded, and the bonding wire (15) is bonded to the small conductive portion (11a). Thereby, the heat generated from the LED chip (20) can be efficiently radiated from the large conductive portion (11b).
本発明において「LEDチップを導電部に接合する」とはその導電部が主な放熱経路となるようにLEDチップが接続されている状態であり、具体的にはLEDチップと導電部との間にはんだや導電性接着剤等の接合に必要な材料のみが介在している状態である。ボンディングワイヤによる電気的接続は、本発明におけるLEDチップを導電部に接合した状態には含まれない。 In the present invention, “joining the LED chip to the conductive part” is a state in which the LED chip is connected so that the conductive part becomes a main heat dissipation path, and specifically, between the LED chip and the conductive part. In this state, only materials necessary for bonding such as solder and conductive adhesive are present. The electrical connection by the bonding wire is not included in the state where the LED chip in the present invention is bonded to the conductive portion.
また、絶縁部(12)は使用電圧下で十分な電気絶縁性が得られる限りその寸法に制限はない。例えば、LEDチップを搭載する場合の電圧は一般に5V以下であるので、図1の基板(1)を参照すると、絶縁部(12)の寸法(w2)は数μmでも導電部(11a)(11b)を絶縁することができる。ただし、LED器具としての安全性を考慮した場合に、1kV以上で電圧下でも絶縁できることが好ましく、絶縁部(12)の寸法(w2)を30μm以上に設定することが好ましい。 Further, the dimensions of the insulating part (12) are not limited as long as sufficient electrical insulation can be obtained under the operating voltage. For example, since the voltage when the LED chip is mounted is generally 5 V or less, referring to the substrate (1) in FIG. 1, even if the dimension (w2) of the insulating part (12) is several μm, the conductive part (11a) (11b ) Can be insulated. However, in consideration of safety as an LED device, it is preferable that insulation can be performed even at a voltage of 1 kV or more, and the dimension (w2) of the insulating portion (12) is preferably set to 30 μm or more.
本発明において、基板(1)の厚さ(t)は、基板としての強度を満足する限り任意に設定することができる。また、基板(1)の厚さ(t)は導電部(11a)(11b)の厚さでもあるので、かかる厚さ(t)を有する導電部(11a)(11b)は熱伝達能力が高くヒートシンクとしての機能を有している。 In the present invention, the thickness (t) of the substrate (1) can be arbitrarily set as long as the strength as the substrate is satisfied. Moreover, since the thickness (t) of the substrate (1) is also the thickness of the conductive portions (11a) and (11b), the conductive portions (11a) and (11b) having such a thickness (t) have high heat transfer capability. It functions as a heat sink.
さらに、LEDチップが少なくとも1つの導電部を主たる放熱経路となるように接合されている限り、LEDチチップを導電部に接続する方法も限定されない。図3AのLEDパッケージ(3A)は一方の導電部(11b)上に接合層(14)を介してLEDチップ(20)を接合し、他方の導電部(11a)にボンディングワイヤ(15)で接続した例であり、一方の導電部(11b)が主たる放熱経路となる。また、図3BのLEDパッケージ(3B)は、LEDチップ(20)を2つの導電部(11a)(11b)にまたがるようにボール形のはんだ(17)で接合した例であり、2つの導電部(11a)(11b)が放熱経路となる。また、図4のLEDパッケージ(4)は、一つの導電部(11d)上に導電性接着剤またははんだ(14)でLEDチップ(20)を接合し、他の2つの導電部(11c)(11e)にボンディングワイヤ(15)で接続した例であり、一つの導電部(11d)が主たる放熱経路となる。 Furthermore, as long as the LED chip is bonded so that at least one conductive part is a main heat dissipation path, the method of connecting the LED chip chip to the conductive part is not limited. In the LED package (3A) of FIG. 3A, the LED chip (20) is bonded on one conductive part (11b) via a bonding layer (14), and connected to the other conductive part (11a) with a bonding wire (15). In this example, one of the conductive portions (11b) is the main heat dissipation path. The LED package (3B) in FIG. 3B is an example in which the LED chip (20) is joined with ball-shaped solder (17) so as to straddle the two conductive parts (11a) and (11b). (11a) and (11b) are heat dissipation paths. In the LED package (4) of FIG. 4, the LED chip (20) is bonded to one conductive portion (11d) with a conductive adhesive or solder (14), and the other two conductive portions (11c) ( 11e) is connected with a bonding wire (15), and one conductive portion (11d) is the main heat dissipation path.
[LEDパッケージを用いたLEDランプ]
図5に、本発明のLEDパッケージ(3)を用いて作製したLEDランプ(5)を示す。
[LED lamp using LED package]
FIG. 5 shows an LED lamp (5) produced using the LED package (3) of the present invention.
LEDパッケージ(3)は、図3AのLEDパッケージ(3A)の基板(1)の外周部に樹脂製外枠(21)を取り付け、基板(1)のチップ搭載面(M1)と外枠(21)の内周面によって形成される凹部に樹脂封止材(22)を充填し、さらに樹脂製レンズ(23)を一体に形成したものである。前記封止材(22)は、LEDチップ(20)への衝撃を緩和するとともに水分の侵入を防止してLEDチップ(20)を保護し、かつハンドリング性を高めている。また、封止材用の樹脂にはランプの色調を調整するために色素を混合することもできる。また、光学性能の向上を目的として、前記外枠(21)の内面にリフレクターを取り付けること、あるいはリフレクター一体型の外枠を使用すること、封止材(22)の上面にレンズ(23)を取り付けることも好ましい。また、このようにLEDチップ(20)を樹脂で覆ったことで、LEDパッケージのハンドリング性が高められている。 In the LED package (3), a resin outer frame (21) is attached to the outer periphery of the substrate (1) of the LED package (3A) of FIG. 3A, and the chip mounting surface (M1) and outer frame (21) of the substrate (1) are attached. ) Is filled with a resin sealing material (22), and a resin lens (23) is integrally formed. The sealing material (22) mitigates the impact on the LED chip (20), prevents the intrusion of moisture, protects the LED chip (20), and improves handling. In addition, a pigment can be mixed with the resin for the sealing material in order to adjust the color tone of the lamp. For the purpose of improving optical performance, a reflector is attached to the inner surface of the outer frame (21) or a reflector-integrated outer frame is used, and a lens (23) is mounted on the upper surface of the sealing material (22). It is also preferable to attach. Moreover, the handling property of the LED package is improved by covering the LED chip (20) with the resin in this way.
前記LEDパッケージ(3)は、LEDチップ(20)を樹脂製の外枠(21)および封止材(22)で覆うことで上記の効果を得ているが、本発明のLEDパッケージはLEDチップを搭載した基板を各種被覆材で覆うことは必須要件ではない。本発明で規定する基板にLEDチップが搭載されているものは被覆材の有無に拘わらず本発明に含まれる。また、LEDチップを搭載した基板を被覆材で覆うと放熱性が低下するので、被覆材を基板の一部が露出するような形状に形成することも好ましい。 The LED package (3) obtains the above effect by covering the LED chip (20) with a resin outer frame (21) and a sealing material (22). However, the LED package of the present invention is an LED chip. It is not an indispensable requirement to cover the substrate on which the substrate is mounted with various coating materials. A substrate in which an LED chip is mounted on a substrate defined by the present invention is included in the present invention regardless of the presence or absence of a coating material. Moreover, since the heat dissipation is reduced when the substrate on which the LED chip is mounted is covered with a covering material, it is also preferable to form the covering material in a shape that exposes part of the substrate.
LEDランプ(5)は、熱伝導性絶縁基板(24)上に形成された銅配線部(25)にLEDパッケージ(3)の基板(1)の導電部(11a)(11b)をはんだ付けしたものである。図中、(26)ははんだを示している。なお、図示例の基板(1)は導電部(11a)(11b)が金属層(13)に被覆されているので、導電部(11a)(11b)は金属層(13)を介して銅配線部(25)にはんだ付けされている。 In the LED lamp (5), the conductive portion (11a) (11b) of the substrate (1) of the LED package (3) is soldered to the copper wiring portion (25) formed on the heat conductive insulating substrate (24). Is. In the figure, (26) indicates solder. In addition, since the conductive portion (11a) (11b) is covered with the metal layer (13), the conductive portion (11a) (11b) is connected to the copper wiring via the metal layer (13). Soldered to the part (25).
前記LEDランプ(5)において、LEDチップ(20)の基板(1)への搭載方法は図3Aと同じであるから、大きい導電部(11b)上に接合層(14)を介してLEDチップ(20)が接合され、LEDチップ(20)はボンディングワイヤ(15)で小さい導電部(11a)に接続されている。よって、LEDチップ(20)から発生する熱は、主としてLEDチップ(20)が接合されている導電部(11b)に直接伝わり、はんだ(26)を介して熱伝導性絶縁基板(24)に放熱される。また、導電部(11a)から絶縁部(12)を介して他方の導電部(11b)にも伝わって熱伝導性絶縁基板(24)に放熱される。LEDチップ(20)から発生する熱は導電部(11a)(11b)が放熱経路となって排熱され、基板(1)の厚さ(t)を有する導電部(11a)(11b)自身がヒートシンクとして作用するので放熱効率が良い。前記導電部(11a)(11b)上の金属層(13)は熱伝導性の良い金属であるから、放熱経路上の金属層(13)もヒートシンクの一部として機能し、放熱効率を高めることになる。 In the LED lamp (5), the mounting method of the LED chip (20) on the substrate (1) is the same as that in FIG. 3A. Therefore, the LED chip (20) is interposed on the large conductive portion (11b) via the bonding layer (14). 20) is joined, and the LED chip (20) is connected to the small conductive portion (11a) by a bonding wire (15). Therefore, the heat generated from the LED chip (20) is mainly transferred directly to the conductive part (11b) to which the LED chip (20) is bonded, and is radiated to the heat conductive insulating substrate (24) via the solder (26). Is done. Further, the heat is transmitted from the conductive portion (11a) to the other conductive portion (11b) through the insulating portion (12) and is radiated to the thermally conductive insulating substrate (24). The heat generated from the LED chip (20) is exhausted through the conductive portions (11a) and (11b) as a heat dissipation path, and the conductive portions (11a) and (11b) themselves having the thickness (t) of the substrate (1) Since it acts as a heat sink, heat dissipation efficiency is good. Since the metal layer (13) on the conductive part (11a) (11b) is a metal having good thermal conductivity, the metal layer (13) on the heat dissipation path also functions as a part of the heat sink, thereby improving the heat dissipation efficiency. become.
また、前記導電部(11a)(11b)は基板(1)の両面に露出しているので、チップ搭載面(M1)の対向面(M2)に電極を形成できる。このため、スルーホールを設けるといった電極形成のための加工をすることなく、そのまま両面基板として用いることができ、表面実装型の半導体パッケージを製作することができる。なお、前記導電部(11a)(11b)は基板(1)の側面にも露出しているので側面に電極を形成することもできる。 Further, since the conductive portions (11a) and (11b) are exposed on both surfaces of the substrate (1), electrodes can be formed on the opposing surface (M2) of the chip mounting surface (M1). Therefore, it can be used as a double-sided substrate as it is without processing for electrode formation such as providing a through hole, and a surface-mount type semiconductor package can be manufactured. Since the conductive portions (11a) and (11b) are also exposed on the side surface of the substrate (1), an electrode can be formed on the side surface.
また、前記絶縁部(12)を構成する無機物は熱膨張係数率が小さいので、大発熱量や発熱と冷却の反復に対しても破線や断線が発生しにくい。また、絶縁部(12)の線膨張係数はLEDチップ(20)の線膨張係数に近似しているために、BGA(Ball Grid Array)基板のようにチップの底面にはんだ付けをする場合でも断線しにくい。 In addition, since the inorganic material constituting the insulating portion (12) has a low coefficient of thermal expansion, broken lines and disconnections are less likely to occur even when the amount of heat generation is large or heat and cooling are repeated. In addition, since the linear expansion coefficient of the insulating part (12) approximates the linear expansion coefficient of the LED chip (20), the wire breaks even when soldering to the bottom of the chip like a BGA (Ball Grid Array) board. Hard to do.
[基板の製造方法]
本発明のLEDパッケージに用いる基板は導電部を構成する金属と絶縁部を構成する無機物とを一体化したものであり、その一体化のための手段は限定されず、接着剤による接合、圧接、ろう付、放電プラズマ接合等を例示できる。ただし、有機接着剤は、高温下で劣化しやすく、また光によっても劣化するので、金属と無機物とを直接または無機物を介して接合することが好ましい。
[Substrate manufacturing method]
The substrate used in the LED package of the present invention is an integration of the metal constituting the conductive part and the inorganic substance constituting the insulating part, and the means for the integration is not limited, bonding with an adhesive, pressure welding, Examples thereof include brazing and discharge plasma bonding. However, since the organic adhesive is easily deteriorated at high temperatures and is also deteriorated by light, it is preferable to join the metal and the inorganic material directly or via the inorganic material.
また、陽極酸化処理の手法を用いてアルミニウム中に絶縁部を形成することによっても基板を製造することができる。 Moreover, a board | substrate can be manufactured also by forming an insulating part in aluminum using the technique of an anodizing process.
以下に、図1の基板(1)の製造を例に挙げて、積層材から基板を製造する方法および陽極酸化処理によって基板を製造する方法について詳述する。 In the following, taking the production of the substrate (1) of FIG. 1 as an example, a method for producing a substrate from a laminate and a method for producing a substrate by anodization will be described in detail.
(1)積層材から基板を製造する方法
図6に示すように、積層材(30)は2枚の金属板(31a)(31b)の間に絶縁板(32)を挟んだ状態で一体に接合された3層平板である。前記積層材(30)を積層方向に沿った任意の面で切断すると、その切断面は金属板(31a)、絶縁板(32)、金属板(31b)が積層順に、それぞれの板厚(W1A)、(W2)、(W1B)の寸法で積層している。従って、前記積層材(30)を積層方向に沿った面で切断して直方体を切り出すと、切り出した直方体のそれぞれが基板(1)となる。そして、積層材(30)における金属板(31a)(31b)、絶縁板(32)基板(1)における導電部(11a)(11b)、絶縁部(12)となる。また、直方体を切り出した際の任意の切断面(積層材の側面を含む)とその対向面との間に金属板(31a)(31b)および絶縁板(32)が貫通しているので、任意の切断面を基板(1)のチップ搭載面(M1)とすることができる。
(1) Method of manufacturing a substrate from a laminated material As shown in FIG. 6, the laminated material (30) is integrated with an insulating plate (32) sandwiched between two metal plates (31a) and (31b). It is a joined three-layer flat plate. When the laminated material (30) is cut along an arbitrary surface along the laminating direction, the cut surfaces of the metal plate (31a), the insulating plate (32), and the metal plate (31b) are respectively stacked in the order of lamination (W1A). ), (W2), and (W1B). Therefore, when the laminated material (30) is cut along a plane along the lamination direction to cut out a rectangular parallelepiped, each of the cut out rectangular parallelepipeds becomes a substrate (1). Then, the metal plates (31a) and (31b) in the laminated material (30), the conductive portions (11a) and (11b), and the insulating portion (12) in the insulating plate (32) substrate (1). In addition, since the metal plates (31a) (31b) and the insulating plate (32) penetrate between the arbitrary cut surface (including the side surface of the laminated material) and the facing surface when the rectangular parallelepiped is cut out, any This cut surface can be the chip mounting surface (M1) of the substrate (1).
前記金属板(31a)(31b)および絶縁板(32)の板厚(W1A)(W1B)(W2)が基板(1)のチップ搭載面(M1)の三者の積層方向における導電部(11a)(11b)および絶縁部(12)の寸法(w1b)(w1b)(w2)となるので、基板(1)の導電部(11a)(11b)および絶縁部(12)の寸法(w1b)(w1b)(w2)は積層材(30)の製造時に金属板(31a)(31b)および絶縁板(32)の板厚(W1A)(W1B)(W2)によって任意に設定することができ、積層材(30)の厚さ(W)が基板(1)のチップ搭載面(M1)における積層方向の寸法(w)となる。また、前記積層材(30)における切断寸法の一つ(TA)が基板(1)の厚さ(t)となり、他の寸法(DA)が基板(1)のチップ搭載面(M1)の他の一辺の寸法(d)となるので、基板(1)の厚さ(t)および他の一辺の寸法(d)は積層材(30)の切断寸法(TA)(DA)によって任意に設定することができる。 The thicknesses (W1A), (W1B), and (W2) of the metal plates (31a) and (31b) and the insulating plate (32) are the conductive portions (11a) in the three layers of the chip mounting surface (M1) of the substrate (1). ) (11b) and the dimension (w1b) (w1b) (w2) of the insulating part (12), so that the dimension (w1b) (the conductive part (11a) (11b) and the insulating part (12) of the substrate (1) w1b) (w2) can be arbitrarily set by the thickness (W1A) (W1B) (W2) of the metal plates (31a) (31b) and the insulating plate (32) during the production of the laminate (30). The thickness (W) of the material (30) is the dimension (w) in the stacking direction on the chip mounting surface (M1) of the substrate (1). Further, one of the cut dimensions (TA) in the laminate (30) is the thickness (t) of the substrate (1), and the other dimension (DA) is other than the chip mounting surface (M1) of the substrate (1). Therefore, the thickness (t) of the substrate (1) and the dimension (d) of the other side are arbitrarily set according to the cut dimensions (TA) (DA) of the laminated material (30). be able to.
以上より、積層材(30)を製作し、積層材(30)を切断することにより多数の基板(1)を効率良く製造できる。 As described above, a large number of substrates (1) can be efficiently manufactured by manufacturing the laminated material (30) and cutting the laminated material (30).
前記積層材(30)は、金属板と絶縁板と直接、または間接的に接合一体化する周知の積層一体化技術によって製造することができる。 The laminate (30) can be manufactured by a well-known laminate integration technique in which a metal plate and an insulating plate are joined or integrated directly or indirectly.
(1−1)直接接合
直接接合による積層材の製造例として、図7に示すように、金属板(31a)(31b)と絶縁板(32)とを所要の順序に重ね、両側をパンチ(40)で挟んで加圧しながら加熱する方法がある。この製造工程は、DBC基板(Direct Bonding Copper 基板)と呼ばれる銅貼りセラミック基板の製造工程を利用でき、Cu中に含まれる微量な酸化物を利用してセラミックとの共晶を生成させて銅(金属板)とセラミック基板(絶縁板)とが直接接合した積層材を製造できる。
(1-1) Direct bonding As an example of manufacturing a laminated material by direct bonding, as shown in FIG. 7, metal plates (31a) (31b) and an insulating plate (32) are stacked in a required order, and both sides are punched ( There is a method of heating while pressing between 40). This manufacturing process can use a manufacturing process of a copper-clad ceramic substrate called a DBC substrate (Direct Bonding Copper substrate), and generates a eutectic with a ceramic by using a trace amount of oxide contained in Cu (copper ( A laminated material in which a metal plate) and a ceramic substrate (insulating plate) are directly bonded can be manufactured.
(1−2)間接接合
間接接合による積層材の製造例として、図8に示すように、金属板(31a)(31b)と絶縁板(32)との間にシート状のろう材または活性金属ろう材(33)(33)を介在させて重ね合わせ、両側をパンチ(40)で挟んで加圧しながら加熱する方法がある。この製造工程は、DBA基板(Direct Brazed Aluminum 基板)と呼ばれるアルミニウム貼りセラミック基板の製造工程や、AMC基板(Active Metal Brazed Copper 基板)と呼ばれる銅貼りセラミック基板の製造工程を利用できる。DBA基板はセラミック基板(絶縁板)にアルミニウム板(金属板)をろう付した基板である。また、AMC基板は、Ti、Zr等の活性金属を添加したろう材でセラミック基板(絶縁板)に銅板(金属板)をろう付した基板である。これらの製造方法によれば、導電部と絶縁部とが間接的に接合された基板を製作することができる。
(1-2) Indirect joining As an example of manufacturing a laminated material by indirect joining, as shown in FIG. 8, a sheet-like brazing material or active metal between the metal plates (31a) (31b) and the insulating plate (32). There is a method in which the brazing materials (33) and (33) are overlapped with each other, and both sides are sandwiched by punches (40) and heated while being pressurized. For this manufacturing process, a manufacturing process of an aluminum-clad ceramic substrate called a DBA substrate (Direct Brazed Aluminum substrate) or a manufacturing process of a copper-clad ceramic substrate called an AMC substrate (Active Metal Brazed Copper substrate) can be used. The DBA substrate is a substrate obtained by brazing an aluminum plate (metal plate) to a ceramic substrate (insulating plate). The AMC substrate is a substrate obtained by brazing a copper plate (metal plate) to a ceramic substrate (insulating plate) with a brazing material to which an active metal such as Ti or Zr is added. According to these manufacturing methods, it is possible to manufacture a substrate in which the conductive portion and the insulating portion are indirectly joined.
(1−3)放電プラズマ接合
金属板と絶縁板を直接接合する他の方法として放電プラズマ接合方法を挙げることができる。放電プラズマ接合方法とは、放電プラズマ焼結法(Spark Plasma Sintering:SPS)の焼結機構を粉体の焼結ではなく板の接合に適用した公知の接合方法である。なお、この「放電プラズマ接合法」は、「SPS接合法」、「パルス通電圧接法(Pulsed Current Hot Pressing:PCHP)」等とも呼ばれている。
(1-3) Discharge plasma bonding As another method of directly bonding a metal plate and an insulating plate, a discharge plasma bonding method can be given. The discharge plasma bonding method is a known bonding method in which a spark plasma sintering (SPS) sintering mechanism is applied to plate bonding rather than powder sintering. The “discharge plasma bonding method” is also called “SPS bonding method”, “Pulsed Current Hot Pressing (PCHP)”, or the like.
具体的には、図9に示すように、黒鉛製ダイ(41)内に金属板(31a)(31b)と絶縁板(32)を重ねて配置し、積層方向の上下を黒鉛製パンチ(42)で挟んで両パンチ(42)に電極(43)(44)を接続し、積層物にパルス通電することによって金属板(31a)(31b)と絶縁板(32)とを接合する。この方法によれば、導電部と絶縁部とが直接接合された基板を製作することができる。 Specifically, as shown in FIG. 9, metal plates (31a) (31b) and an insulating plate (32) are placed in a graphite die (41) so as to overlap each other, and a graphite punch (42 ), The electrodes (43) and (44) are connected to both the punches (42), and the metal plate (31a) (31b) and the insulating plate (32) are joined by applying pulse current to the laminate. According to this method, a substrate in which the conductive portion and the insulating portion are directly bonded can be manufactured.
なお、放電プラズマ焼結法により、ダイ内に絶縁板および金属粉末を配置し、放電プラズマによって金属粉末を焼結して金属の固形化と絶縁板との接合とを同時に行って積層材を製造することも可能である。 In addition, an insulating plate and metal powder are placed in a die by a discharge plasma sintering method, and the metal powder is sintered by discharge plasma to simultaneously solidify the metal and join the insulating plate to produce a laminated material. It is also possible to do.
上記の工程によれば、積層材の切断によって多数個の基板を効率良く製造することができる。なお、図示例の積層材(30)は3層であるが、金属板および絶縁板の積層数は任意に設定することができる。 According to said process, many board | substrates can be manufactured efficiently by the cutting | disconnection of a laminated material. In addition, although the laminated material (30) of the example of illustration is three layers, the number of lamination | stacking of a metal plate and an insulating board can be set arbitrarily.
積層材の製造方法は上述の方法に限定されるものではなく、他の接合方法として拡散接合法、絶縁板上に溶融アルミニウムを流し込み、アルミニウムを凝固させるともに絶縁板に接合する溶湯接触法、絶縁板にめっき、DLC(ダイヤモンドライクカーボン)等の蒸着によって金属層(導電部)を形成する方法、絶縁板に金属粉を印刷付着させ焼結して金属層(導電部)を形成する方法等を例示できる。 The manufacturing method of the laminated material is not limited to the above-mentioned method. As another bonding method, diffusion bonding method, molten aluminum is poured onto an insulating plate, the molten aluminum is solidified and the molten metal contact method is bonded to the insulating plate, insulation. A method of forming a metal layer (conductive part) by plating, vapor deposition such as DLC (diamond-like carbon) on a plate, a method of forming a metal layer (conductive part) by printing metal powder on an insulating plate and sintering. It can be illustrated.
(2)陽極酸化処理による基板の製造
導電部がアルミニウムの場合は、アルミニウム板の陽極酸化処理によって絶縁部を形成して基板を製造することができる。
(2) Manufacture of substrate by anodizing treatment When the conductive portion is aluminum, the substrate can be manufactured by forming the insulating portion by anodizing the aluminum plate.
図10に示す板状の素材(50)は陽極酸化処理品であり、アルミニウム板の幅方向の中間に長手方向に沿った絶縁部(54)が形成され、この絶縁部(54)によってアルミニウムが2つの導電部(51a)(51b)に分断されたものである。2つの導電部(51a)(51b)および絶縁部(54)は、それぞれ、素材(50)の板厚方向の一方の面と他方の面との間を貫く方向に積層している。この素材(50)を所要寸法(DB)に切断したものがそれぞれ基板(1)となる。前記素材(10)の導電部(51a)(51b)および絶縁部(54)が基板(1)の導電部(11a)(11b)および絶縁部(12)に対応する。 The plate-like material (50) shown in FIG. 10 is an anodized product, and an insulating portion (54) along the longitudinal direction is formed in the middle of the width direction of the aluminum plate, and aluminum is formed by this insulating portion (54). It is divided into two conductive portions (51a) and (51b). The two conductive portions (51a) (51b) and the insulating portion (54) are stacked in a direction penetrating between one surface and the other surface in the plate thickness direction of the material (50). The material (50) cut into the required dimension (DB) is the substrate (1). The conductive portions (51a) (51b) and the insulating portion (54) of the material (10) correspond to the conductive portions (11a) (11b) and the insulating portion (12) of the substrate (1).
図11はアルミニウム板(55)から前記素材(50)を製作する工程(S1〜S4)を模式的に示したものである。以下に、図11を参照しつつ素材(50)の製造方法について説明する。 FIG. 11 schematically shows steps (S1 to S4) for producing the material (50) from the aluminum plate (55). Below, the manufacturing method of a raw material (50) is demonstrated, referring FIG.
(S1)アルミニウム板(55)は、その板厚(TB)が基板(1)の厚さとなるので、アルミニウム板(55)は所期する基板(1)の厚さ(t)のものを使用する。このアルミニウム板(55)において、導電部(51a)(51b)となる部分の両面にレジスト(52)を塗布する。レジスト(52)を塗布しない部分はアルミニウムが露出し、アルミニウム露出部分(53)は絶縁部(12)が形成される部分である。図示例では、アルミニウム板(55)の上下両面に各1箇所のアルミニウム露出部分(53)がある。 (S1) Since the plate thickness (TB) of the aluminum plate (55) is the thickness of the substrate (1), the aluminum plate (55) having the thickness (t) of the intended substrate (1) is used. To do. In this aluminum plate (55), a resist (52) is applied to both surfaces of the portions to be the conductive portions (51a) and (51b). The portion where the resist (52) is not applied exposes aluminum, and the aluminum exposed portion (53) is a portion where the insulating portion (12) is formed. In the illustrated example, there are one exposed aluminum portion (53) on each of the upper and lower surfaces of the aluminum plate (55).
(S2)レジスト(52)を塗布したアルミニウム板(55)を処理液に漬けて陽極酸化処理を施す。上下のアルミニウム露出部分(53)に陽極酸化皮膜(54)が生成し、皮膜(54)はアルミニウム板(55)の板厚方向に成長していく。 (S2) The aluminum plate (55) to which the resist (52) is applied is immersed in a treatment solution and anodized. An anodized film (54) is formed on the upper and lower exposed aluminum parts (53), and the film (54) grows in the thickness direction of the aluminum plate (55).
(S3)アルミニウム板(55)の両面から成長した陽極酸化皮膜(54)は板厚方向の中間で繋がり、陽極酸化皮膜(54)がアルミニウム板(55)を板厚方向に貫いてアルミニウム板(55)を幅方向に分断した状態となり、2つの導電部(51a)(51b)と1つの絶縁部(54)が形成される。 (S3) The anodized film (54) grown from both sides of the aluminum plate (55) is connected in the middle of the plate thickness direction, and the anodized film (54) penetrates the aluminum plate (55) in the plate thickness direction and the aluminum plate ( 55) is divided in the width direction, and two conductive portions (51a) (51b) and one insulating portion (54) are formed.
(S4)レジスト(51)おおびアルミニウム板(55)の外側に成長した陽極酸化皮膜(54a)を表面研磨等によって除去すると、図10に示した素材(50)となる。 (S4) When the anodized film (54a) grown on the outside of the resist (51) and the aluminum plate (55) is removed by surface polishing or the like, the material (50) shown in FIG. 10 is obtained.
以上の工程により素材(50)が製造される。そして、前記素材(10)を所要寸法(DB)に切断すると、導電部(11a)(11b)および絶縁部(12)がチップ搭載面(M1)とその対向面(M2)との間を貫く方向に積層した基板(1)となる。チップ搭載面(M1)において三者の積層方向における絶縁部(12)の寸法(w2)は、アルミニウム露出部分(53)の寸法に対応する。また、導電部(11a)(11b)の寸法(w1a)(w1b)は、使用するアルミニウム板(55)の寸法とアルミニウム露出部分(53)の寸法とによって設定され、あるいは陽極酸化処理後のアルミニウム板の切断によって設定される。 The material (50) is manufactured by the above process. When the material (10) is cut to the required dimension (DB), the conductive portions (11a) (11b) and the insulating portion (12) penetrate between the chip mounting surface (M1) and the facing surface (M2). The substrate (1) is laminated in the direction. On the chip mounting surface (M1), the dimension (w2) of the insulating part (12) in the three stacking directions corresponds to the dimension of the aluminum exposed part (53). Further, the dimensions (w1a) and (w1b) of the conductive portions (11a) and (11b) are set according to the dimensions of the aluminum plate (55) to be used and the dimensions of the exposed aluminum part (53), or aluminum after anodizing treatment. Set by cutting the board.
また、前記絶縁部(54)はアルミニウム板(55)の任意の箇所に形成することができるので、1枚のアルミニウム板(55)の複数箇所に絶縁部(54)を形成すれば、1回の陽極酸化処理で図示例の素材(50)を複数個製造することができる。 Moreover, since the said insulation part (54) can be formed in the arbitrary places of an aluminum plate (55), if an insulation part (54) is formed in the several places of one aluminum plate (55), it will be 1 time. A plurality of materials (50) in the illustrated example can be manufactured by the anodizing treatment.
また、図3A等に参照されるように、導電部(11a)(11b)をめっき皮膜による金属層(13)で被覆する場合は、前記素材(50)にめっき処理を施し、その後所要の寸法に切断する。また、陽極酸化処理に供するアルミニウム板としてアルミニウム心材に金属層(皮材)をクラッドしたクラッド材を使用すれば、工程を追加することなく金属層を形成することができる。 In addition, as shown in FIG. 3A and the like, when the conductive portions (11a) and (11b) are covered with the metal layer (13) by the plating film, the material (50) is plated, and then the required dimensions are obtained. Disconnect. Further, if a clad material obtained by clad a metal layer (skin material) on an aluminum core is used as an aluminum plate to be subjected to anodizing treatment, the metal layer can be formed without adding a process.
なお、図11はアルミニウム板(55)の側面については、レジスト塗布の有無について説明を省略しているが、側面にレジストを塗布しなければ陽極酸化皮膜が形成され、レジストを塗布すれば陽極酸化皮膜は形成されない。側面に陽極酸化皮膜を形成するかどうかは、LEDパッケージの形態に応じて任意に設定することができる。例えば、図5に示したLEDパッケージ(3)においては基板(1)の外周部に樹脂製外枠(21)を取り付けるが、導電部(11a)(11b)と外枠(21)との接合性を高めるために陽極酸化皮膜を形成することがある。 Note that FIG. 11 omits the description of whether or not the resist is applied to the side surface of the aluminum plate (55). However, if the resist is not applied to the side surface, an anodized film is formed. A film is not formed. Whether or not the anodized film is formed on the side surface can be arbitrarily set according to the form of the LED package. For example, in the LED package (3) shown in FIG. 5, a resin outer frame (21) is attached to the outer periphery of the substrate (1), but the conductive portions (11a) (11b) and the outer frame (21) are joined. An anodic oxide film may be formed to improve the properties.
陽極酸化処理による基板の製造方法は上記工程に限定されるものではなく、種々の変更が可能である。 The method for manufacturing the substrate by the anodizing treatment is not limited to the above steps, and various modifications can be made.
アルミニウム露出部分(53)は、アルミニウム板(55)の一方の面にのみ設け、陽極酸化皮膜(54)を他方の面に達するように成長させて絶縁部を形成することもできる。しかし、上記工程のように両面から皮膜を成長させる方が処理時間を短縮できる。また、陽極酸化皮膜(54)は膜厚が200μm程度まで成長するとそれ以上は殆ど成長しないので、アルミニウム板(55)の板厚(TB)が皮膜の成長限度を超える場合は、両面にアルミニウム露出部分(53)を設けて両面から陽極酸化皮膜(54)を形成することが必要となる。なお、陽極酸化皮膜の成長限度は陽極酸化処理条件やアルミニウム板の化学組成等によって異なり、上記の200μmは成長限度の一例にすぎない。 The aluminum exposed portion (53) can be provided only on one surface of the aluminum plate (55), and the anodized film (54) can be grown to reach the other surface to form an insulating portion. However, the processing time can be shortened by growing the film from both sides as in the above process. Further, since the anodized film (54) grows to a thickness of about 200 μm, it hardly grows further. Therefore, when the thickness (TB) of the aluminum plate (55) exceeds the growth limit of the film, aluminum is exposed on both sides. It is necessary to provide the part (53) and form the anodized film (54) from both sides. The growth limit of the anodized film varies depending on the anodizing conditions, the chemical composition of the aluminum plate, etc., and the above 200 μm is only an example of the growth limit.
さらに、図12に示すように、アルミニウム板(55)のアルミニウム露出部分(53)に凹部(56)を形成して陽極酸化皮膜(54)の形成を促進することも好ましい。アルミニウム板(55)の板厚(TB)が陽極酸化皮膜の成長限度の2倍を超えるとレジスト(52)を塗らない部分を設けただけではアルミニウム板(55)を貫通させることができないので、凹部(56)を形成することによって使用可能なアルミニウム板(55)の板厚(TB)の範囲を拡大することができる。アルミニウム板(55)の板厚(TB)は基板(1)の厚さ(t)に対応しているので、素材(50)の製作時に凹部(56)を入れることによって製造可能な基板(1)の厚さ(t)の範囲を拡大することができる。また、板厚(TB)が陽極酸化皮膜(54)の成長限度の2倍以下のアルミニウム板においても、凹部(56)を形成することによって処理時間の短縮、処理条件を緩和できる、といった効果が得られる。 Furthermore, as shown in FIG. 12, it is also preferable to promote the formation of the anodic oxide film (54) by forming a recess (56) in the aluminum exposed portion (53) of the aluminum plate (55). If the plate thickness (TB) of the aluminum plate (55) exceeds twice the growth limit of the anodized film, the aluminum plate (55) cannot be penetrated simply by providing a portion where the resist (52) is not applied. By forming the recess (56), the range of the plate thickness (TB) of the usable aluminum plate (55) can be expanded. Since the plate thickness (TB) of the aluminum plate (55) corresponds to the thickness (t) of the substrate (1), the substrate (1 that can be manufactured by inserting the recess (56) when the material (50) is manufactured. ) Thickness (t) can be expanded. In addition, even in an aluminum plate having a plate thickness (TB) that is not more than twice the growth limit of the anodized film (54), the formation of the recess (56) reduces the processing time and reduces the processing conditions. can get.
上述した陽極酸化処理による素材(50)の製造は、レジスト(52)を塗布しないアルミニウム露出部分(53)にアルミニウム板(55)を貫く陽極酸化皮膜を形成させ、これを絶縁部(54)としたものである。レジスト(52)はアルミニウム板(55)上の所望の部分に塗布できるので、アルミニウム板(55)の所望の部分に所望形状の絶縁部(54)を形成することができる。従って、複数の導電部とこれらを絶縁する絶縁部とが複雑に積層した基板を製造することができる。例えば、レジストを環形に塗布すれば環形の絶縁部が形成され、環形の絶縁部の内部と外部に導電部を形成することができる。また、1枚のアルミニウム板から複数の前記素材(50)を製造すること、1枚のアルミニウム板から積層形態の異なる複数の基板を製造することもできる。また、基板(1)の厚さ(t)は素材(50)の製造時に使用するアルミニウム板(55)の板厚(TB)で決まるが、導電部(11a)(11b)の寸法(w1a、w1b)は素材製造後に素材(50)の切断位置で任意に設定することができる。 In the production of the material (50) by the above-described anodizing treatment, an anodized film that penetrates the aluminum plate (55) is formed on the aluminum exposed portion (53) where the resist (52) is not applied, and this is formed as an insulating portion (54). It is a thing. Since the resist (52) can be applied to a desired portion on the aluminum plate (55), an insulating portion (54) having a desired shape can be formed on the desired portion of the aluminum plate (55). Therefore, it is possible to manufacture a substrate in which a plurality of conductive portions and insulating portions that insulate them are complicatedly stacked. For example, if a resist is applied in a ring shape, a ring-shaped insulating portion is formed, and a conductive portion can be formed inside and outside the ring-shaped insulating portion. Moreover, the said raw material (50) can be manufactured from one aluminum plate, and the several board | substrate from which a lamination | stacking form differs can also be manufactured from one aluminum plate. The thickness (t) of the substrate (1) is determined by the plate thickness (TB) of the aluminum plate (55) used when the material (50) is manufactured, but the dimensions (w1a, w1b) can be arbitrarily set at the cutting position of the material (50) after the material is manufactured.
一方、図6の積層材(30)から製造される基板は、チップ搭載面(M1)における導電部(11a)(11b)および絶縁部(12)の積層方向の寸法(w1a、w1b、w2)は積層材(30)の材料板(31a)(31b)(32)の板厚(W1A、W1B、W2)によって決まるので、積層材(30)の製作後に導電部(11a)(11b)および絶縁部(12)の寸法(w1a、w1b、w2)を変更することはできない。しかし、基板(1)の厚さ(t)およびチップ搭載面(M1)における他の一辺の寸法(d)は、積層材製造後に積層材(30)の切断位置によって任意に設定することができる。 On the other hand, the substrate manufactured from the laminated material (30) in FIG. 6 has dimensions (w1a, w1b, w2) in the stacking direction of the conductive portions (11a) (11b) and the insulating portion (12) on the chip mounting surface (M1). Is determined by the plate thickness (W1A, W1B, W2) of the material plates (31a), (31b), (32) of the laminated material (30), so that the conductive portions (11a), (11b) and the insulation are manufactured after the laminated material (30) is manufactured. The dimensions (w1a, w1b, w2) of the part (12) cannot be changed. However, the thickness (t) of the substrate (1) and the dimension (d) of the other side of the chip mounting surface (M1) can be arbitrarily set according to the cutting position of the laminated material (30) after the laminated material is manufactured. .
本発明は、基板の導電部がヒートシンクとして機能して放熱性に優れているので、発熱量の大きいLEDを搭載するLEDパッケージとして好適に利用できる。 Since the conductive portion of the substrate functions as a heat sink and is excellent in heat dissipation, the present invention can be suitably used as an LED package on which an LED with a large amount of heat generation is mounted.
1、2…基板
3、3A、3B、4…LEDパッケージ
11a、11b、11c、11d、11e…導電部
12…絶縁部
13…金属層
14…接着層
15…ボンディングワイヤ
16…絶縁層
17…ボール形のはんだ
20…LEDチップ
21…外枠
22…封止材
23…レンズ
30…積層材
31a、31b…金属板
32…絶縁板
50…素材
55…アルミニウム板
51a、51b…アルミニウム(導電部)
52…レジスト
53…アルミニウム露出部分
54…陽極酸化皮膜(絶縁部)
M1…チップ搭載面
M2…対向面
1, 2 ... PCB
3, 3A, 3B, 4 ... LED package
11a, 11b, 11c, 11d, 11e ... conductive part
12… Insulation part
13 ... Metal layer
14… Adhesive layer
15 ... Bonding wire
16… Insulating layer
17 ... Ball solder
20 ... LED chip
21 ... Outer frame
22 ... Sealant
23 ... Lens
30 ... Laminate
31a, 31b ... metal plate
32… Insulating plate
50 ... Material
55 ... Aluminum plate
51a, 51b ... Aluminum (conductive part)
52 ... Resist
53… Aluminum exposed part
54… Anodized film (insulating part)
M1 ... chip mounting surface M2 ... opposite surface
Claims (5)
前記基板の導電部にLEDチップが接合されていることを特徴とするLEDパッケージ。 The substrate on which the LED chip is mounted has a plurality of conductive parts made of metal and an insulating part made of an inorganic material to electrically insulate these conductive parts, and the conductive part and the insulating part are perpendicular to the chip mounting surface. It is integrated in a stacked state,
An LED package, wherein an LED chip is bonded to the conductive portion of the substrate.
The LED package according to claim 4, wherein the metal layer is a plating film formed by electrolytic plating.
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Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20141202 |