JP2012069812A - Capacitor, method of manufacturing the same, and multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor component of low floating inductance which can be manufactured at a low cost with ease, and a method of manufacturing the same, and to provide the capacitor component of low profile and a multilayer wiring board incorporating the low profile capacitor.SOLUTION: The capacitor, in which a monomolecular film of organic material is dielectric body, is characterized in that at least one of electrodes for the capacitor is formed by electroless plating which is started with the catalyst material carried by a dielectric monomolecular. By forming the capacitor on a support base material, a thin film capacitor can be handled as a component. The height of the component can be decreased by grinding the support base material to be thinner.

Description

  The present invention relates to a capacitor, and more particularly to a structure and a manufacturing method of a low-inductance and thin capacitor using an organic thin film as a dielectric, and a multilayer wiring board.

As a major cause of radiation noise generated from a multilayer wiring board, power supply voltage fluctuations between a ground layer where a reference voltage is formed and a power supply layer that supplies a power supply voltage to electrical components such as semiconductor elements are considered. . In particular, when a system composed of a power supply layer and a ground layer resonates, a high level of electromagnetic radiation is generated.
In order to suppress radiation caused by such power supply voltage fluctuation, a capacitor that connects a power supply layer and a ground layer is mounted on a general multilayer wiring board. This capacitor is also called a “bypass capacitor” and bypasses instantaneous voltage fluctuations occurring in the power supply voltage to the ground layer. Thereby, resonance at a frequency at which the system of the power supply layer and the ground layer should resonate can be prevented, and as a result, radiation noise can be suppressed.

  However, the bypass capacitor does not suppress the resonance at the frequency where the system of the power supply layer and the ground layer should resonate. generate. Similar to the resonance of the system itself, this parallel resonance causes radiation noise, but the parallel resonance frequency is higher than the resonance frequency of the system itself, so the influence of radiation noise due to the parallel resonance is relatively minor. It was treated as something.

However, in recent years, with the improvement of the operating frequency of semiconductor elements, the influence of noise due to parallel resonance is becoming ignorable. In response to this problem, a technique has been developed that suppresses inductance that increases with the addition of a bypass capacitor and shifts the parallel resonance frequency to a higher frequency range.
The inductance that increases with the addition of the bypass capacitor can be classified into the floating inductance of the capacitor itself and the inductance of the capacitor mounting structure (mounting pad, wiring, via, etc.).

An example of a technique developed by paying attention to the stray inductance of the capacitor itself is Patent Document 1. In the present invention, it is proposed to use a thin film forming process for manufacturing a capacitor. Capacitors using a thin film formation process can reduce stray inductance when realizing the same capacity as compared to discrete component capacitors that are generally used as bypass capacitors.
On the other hand, Patent Document 2 and Patent Document 3 are examples of development of a technique for incorporating a capacitor in a multilayer wiring board. The inductance of the capacitor mounting structure can be reduced by shortening the wiring connecting the power supply layer or the ground layer and the capacitor by incorporating the capacitor.

JP 2008-294008 A Japanese Patent No. 4279090 JP 2006-93493 A

However, there is a problem to be improved in the technology relating to the inductance reduction of the bypass capacitor disclosed in the above-mentioned documents.
For example, the thin film capacitor component of Patent Document 1 has a problem of high manufacturing cost. Since the metal electrode forming the capacitor structure is formed by a thin film process requiring a high vacuum, the cost for the manufacturing process is increased compared to that of the discrete component.

On the other hand, the obstacle in the component built-in multilayer wiring board exemplified in Patent Document 2 or Patent Document 3 is the dimension in the substrate thickness direction of the component to be built. In most multilayer wiring boards with built-in components, the built-in components are not exposed on the substrate surface, and the components are completely embedded in the multilayer wiring board. This is to ensure as much as possible the area of the substrate surface where components can be mounted. However, in this case, the multilayer wiring board containing the component cannot be made smaller than the dimension of the component in the substrate thickness direction.
The present invention has been made in view of the above problems, and an object of the present invention is to supply capacitors having a small stray inductance and a multilayer wiring board incorporating these capacitors.

In order to solve the above-mentioned problem, the invention described in claim 1 is characterized in that a dielectric monomolecular film composed of at least a monomolecular film of an organic material is supported on the surface of a supporting base material and supported on the dielectric monomolecular film. The present invention provides a capacitor comprising an electroless plating catalyst and a capacitor electrode comprising an electroless plating layer on the dielectric monomolecular film.
Next, the invention described in claim 2 is characterized in that a second dielectric layer having a thickness of 50 nm or more is provided on at least a surface of the outermost layer of the support base material on which the dielectric monomolecular film is formed. And

Next, the invention described in claim 3 is characterized in that the specific resistivity of the second dielectric layer is 1.0 × 10 ⁵ (Ω · cm) or more.
Next, the invention described in claim 4 is characterized in that the support base material is a semiconductor material.
Next, the invention described in claim 5 is characterized in that the thickness of the support base is 50 μm or less.
Next, the invention described in claim 6 is characterized in that the specific resistivity of the semiconductor material constituting the support base is 1.0 (Ω · cm) or less.

Next, the invention described in claim 7 is characterized in that the dielectric monomolecular film forms a chemical bond with the second dielectric layer on the outermost surface of the support substrate.
Next, the invention described in claim 8 is characterized in that the organic material forming the dielectric monomolecular film is either an organic silane compound or an organic titanium compound.
Next, the invention described in claim 9 is characterized in that the organic material has at least one substituent having a complex forming ability with the electroless plating catalyst.
Next, the invention described in claim 10 is characterized in that the organic material has an aliphatic straight chain having 2 to 20 carbon atoms, and the substituent is bonded to the aliphatic straight chain.

Next, the invention described in claim 11 is characterized in that one or more of the substituents form part of the aliphatic straight chain.
Next, the invention described in claim 12 is characterized in that the electroless plating catalyst is palladium.
Next, the invention described in claim 13 is characterized in that the capacitor electrode is made of any one of Ni, Ni-B, Ni-P, Cu, or a combination thereof.
Next, an invention described in claim 14 provides a multilayer wiring board characterized in that the capacitor according to any one of claims 1 to 13 is incorporated therein.

Next, the invention described in claim 15 is the method of manufacturing a capacitor according to any one of claims 1 to 13,
Forming a plurality of monomolecular dielectric films on the surface of the support substrate;
Supporting the electroless plating catalyst on the plurality of monomolecular dielectric films;
Forming the capacitor electrode by electroless plating on the plurality of monomolecular dielectric films to form a plurality of capacitors on the support substrate;
Separating the plurality of capacitors together with the support base;
A method for manufacturing a capacitor is provided.

Next, in the invention described in claim 16, the step of forming the capacitor electrode on the support substrate by forming the capacitor electrode on the plurality of monomolecular dielectric films by electroless plating,
Forming the capacitor electrode on the plurality of monomolecular dielectric films by electroless plating, grinding the support substrate from a surface opposite to the surface on which the capacitor is formed, A step of forming a capacitor.

According to the present invention, by forming a thin film capacitor using an organic material capable of supporting a plating catalyst as a dielectric, it is possible to reduce the number of vacuum processes for forming the capacitor structure. Therefore, a thin film capacitor can be obtained at low cost.
In addition, when a support base material is used for forming a capacitor, it is natural that handling properties during manufacture of the thin film capacitor are improved, and there is a merit when used as an electronic component. By dividing the completed thin film capacitor according to the standard, it becomes a thin film capacitor component that can be handled like a discrete component.

  If the support substrate having a second dielectric layer having a high specific resistivity on the surface is used, an effect of improving the withstand voltage of the thin film capacitor can be expected. Further, if an organic material for forming the monomolecular dielectric layer is selected in accordance with the material of the second dielectric layer, an effect of improving the adhesion with the supporting substrate can be obtained. As a material for forming the second dielectric layer, an insulator containing Si such as silicon dioxide or silicon nitride, or a compound semiconductor such as gallium nitride or silicon-germanium alloy is preferable.

When the thin film capacitor electrode facing the plating electrode is formed by the support base material having a small specific resistivity, the stray inductance of the capacitor can be further reduced by processing the support base material thinly.
Moreover, since the supporting substrate is thin, the height of the completed thin film capacitor can be kept low. This is an advantage when the thin film capacitor is built in the component built-in multilayer wiring board. Since the height of the built-in component that has limited the thinning of the component built-in multilayer wiring board can be suppressed, the thickness of the entire multilayer wiring board can be reduced.

  The material of the support base material does not impair the effects of the present invention at all. Any material can be used, including semiconductors. However, in order to maximize the above effects, it is desirable to use a semiconductor, particularly single crystal silicon, as the supporting base material. This is because the individualization / thinning process is established, the wafer on which the second dielectric layer is formed is commercially available, and the specific resistivity can be easily reduced.

It is a conceptual diagram of the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the capacitor | condenser which concerns on embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the multilayer wiring board with a built-in capacitor based on Embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the multilayer wiring board with a built-in capacitor based on Embodiment based on this invention. It is sectional drawing explaining the process of manufacturing the multilayer wiring board with a built-in capacitor based on Embodiment based on this invention. It is an outline figure about a part of multilayer wiring board with a built-in capacitor concerning an embodiment based on the present invention.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
The embodiment described below is taken up for convenience in order to explain the concept of the invention, and does not limit the embodiment of the invention.
(Capacitor manufacturing method)
FIG. 1 schematically shows the structure of the capacitor of this embodiment.
Prior to capacitor formation, first, a support substrate 2 for forming the thin film capacitor structure 1 is prepared.

As the support substrate 2, a semiconductor material in which the second dielectric layer 200 has been formed on the surface layer is suitable. The second dielectric layer 200 preferably has a thickness of 50 nm or more. The specific resistivity of the second dielectric layer 200 is preferably 1.0 × 10 ⁵ (Ω · cm) or more. Further, the specific resistivity of the semiconductor material is preferably 1.0 (Ω · cm) or less.
Subsequently, the dielectric monomolecular film 3 of the thin film capacitor structure 1 is formed. Since the capacitor of this embodiment is assumed to be mounted very close to the radiation noise source by utilizing the feature that the stray inductance is reduced, it is not necessary to secure a large capacitance. Therefore, it is not necessary to place special restrictions on the configuration and characteristics of the monomolecular film, and a known film forming method such as an LB film or a self-assembled monomolecular film can be freely selected.

However, it is desirable to use a method for forming an organic film with an organic silane compound or an organic titanium compound for the semiconductor material on which the second dielectric layer has been formed. This is because the second dielectric layer on the outermost surface of the supporting substrate and these organic materials form a chemical bond, so that the adhesion between the supporting substrate, the dielectric monomolecular film, and the capacitor electrode is improved.
In addition, when the organic material used as the raw material for the monomolecular film has a functional group capable of complexing with the electroless plating catalyst, the amount of catalyst supported increases in the plating catalyst supporting process described later, so that good results are obtained. Is obtained.

In addition, the organic material preferably has at least one substituent having a complex forming ability with the electroless plating catalyst. The organic material preferably includes an aliphatic straight chain having 2 to 20 carbon atoms, and the substituent is bonded to the aliphatic straight chain. Furthermore, it is preferable that at least one of the substituents forms part of the aliphatic straight chain.
Next, the electroless plating catalyst is supported on the monomolecular film. An object on which a dielectric monomolecular film is formed is immersed in a solution of a compound containing a known electroless plating catalyst such as palladium, and the plating catalyst is supported on the dielectric monomolecular film. In addition, when using palladium as an electroless plating catalyst, it is preferable to use a substance provided with one or more electron-donating functional groups that form a complex with palladium in the pre-organic material. Examples of electron donating atomic groups include amino groups, carboxyl groups, pyrrole groups, imidazole groups, and pyridine groups.

Thereafter, the electrode 4 for the capacitor is formed by electroless plating from the supported plating catalyst. For the formation of the electrode 4, known electroless plating such as Ni, Ni—B, Ni—P, and Cu may be used alone or in combination.
Finally, the periphery of the thin film capacitor structure is sealed with an insulator 5 to complete the capacitor. Silicon dioxide and silicon nitride thin films by CVD can be used as the insulator for sealing, but the conductive part of the electrode 4 can be easily exposed by applying thermosetting resin or sealing with photosensitive resin. This is desirable because it can be done.

On the other hand, separately from the above-described thin film capacitor structure forming step, a step of forming the electrode 6 facing the thin film capacitor structure is performed. In forming the electrode 6, various methods using existing techniques can be used. For example, if a semiconductor material is used for the support base 2, a method for increasing the conductivity of the wafer itself by a method such as using highly doped silicon or performing additional doping after the thin film capacitor structure is formed can be considered. Thereafter, the support substrate 2 itself is used as the electrode 6 by grinding the support substrate from the back surface of the thin film capacitor structure.
The completed capacitor may be separated into pieces as needed. A thin film capacitor that can be handled like a discrete component can be realized by dicing the supporting substrate with a laser or a diamond saw.

In this embodiment, a manufacturing process of a capacitor using a single crystal silicon wafer as a support base 2 will be described. 2 to 11 are diagrams for explaining the manufacturing process of the capacitor.
First, a pretreatment of the support base material 2 for forming a thin film capacitor structure was performed. First, a 6-inch N + type silicon wafer 2 in which a silicon nitride layer having a thickness of 50 nm was formed was prepared (see FIG. 2). The resistivity of the wafer itself before forming the nitride film was 0.25 (Ω · cm). This wafer was cleaned by SPM treatment (H ₂ SO ₄ : H ₂ O ₂ = 4: 1 (volume ratio)).

Next, the process of forming the dielectric monomolecular film 3 on the support base 2 was performed. A dry film resist 7 having acid resistance was laminated on the silicon wafer 2 (see FIG. 3). Subsequently, as shown in FIG. 4, a portion of the photoresist layer 7 where the thin film capacitor structure is to be formed was opened by an exposure and development process. The shape of the opening was a rectangle having a long side of 0.5 mm and a short side of 0.2 mm. The pitch of the openings was 0.65 millimeters in the long side direction and 0.35 millimeters in the short side direction.
The silicon wafer 2 thus treated was immersed in an organic silane compound ethanol solution having the composition shown in Table 1 at 50 ° C. for 4 hours. Next, the wafer was placed in an ethanol bath, subjected to ultrasonic cleaning, and then heated in an oven in a nitrogen atmosphere at 90 ° C. for 60 minutes to fix the dielectric monomolecular film 3 on the wafer surface. (See FIG. 5).

  Subsequently, a process of supporting palladium as a catalyst on the dielectric monomolecular film 3 was performed. The silicon wafer 2 on which the dielectric monomolecular film 3 was formed by the above process was immersed in an aqueous solution of a palladium compound having the composition shown in Table 2 at 25 ° C. for 30 minutes. Thereafter, the silicon wafer 2 was washed in a pure water bath, transferred to another pure water bath, and stored until the next step.

  The silicon wafer 2 after the catalyst supporting step was sequentially put into an electrode forming step by electroless nickel plating. The electroless nickel plating on the dielectric monomolecular film was performed using a plating solution having the composition shown in Table 3. The wafer carrying palladium was immersed in the above plating solution bath at 60 ° C. for 70 minutes to form an electrode 4 for capacitor structure as shown in FIG.

Thereafter, the photoresist 7 was peeled off from the silicon wafer 2 on which the electrodes were formed. Through the steps so far, a thin film capacitor structure 1 having a desired shape is completed on the silicon wafer 2 (see FIG. 7).
As a subsequent process, an insulator for protecting the thin film capacitor structure was formed. The thermosetting underfill material 5 is applied as shown in FIG. 8 using a dispenser. Thereafter, the silicon wafer 2 was placed in an oven and heated at 70 ° C. for 1 hour in a nitrogen atmosphere to cure the underfill material.
Then, the process of forming the other electrode 6 which opposes the electrode 4 made from nickel plating already formed was implemented.

First, a silicon wafer on which a thin film capacitor structure was formed was bonded to a support substrate 8 made of soda glass. As shown in FIG. 9, the silicon wafer was attached so that the surface on which the thin film capacitor structure was formed was opposed to the support substrate 8.
Next, the silicon wafer 2 was thinned. As a first step of thinning, the wafer 2 was ground to 50 μm by a BG (Back Grind) process. Next, as a second step of thinning, the wafer was polished to 30 μm using a CMP (Chemical Mechanical Polishing) process. Through this step, the counter electrode 6 that also serves as a supporting base was completed (see FIG. 10).

Finally, the completed capacitor was singulated as shown in FIG. After the thinned silicon wafer 2 is attached to the dicing tape (not shown) together with the support substrate, the support substrate 8 and the adhesive 9 are removed, and then the silicon wafer 2 and the underfill material 5 are made of the underfill material. The capacitor was cut into pieces of 0603 size by cutting at the portion.
Table 4 shows the results of evaluating the characteristics of the separated capacitors. The capacitance was calculated in accordance with 4.7 of JIS C 5101-1-1998, and the stray inductance was calculated using the above-described capacitance based on the resonance frequency obtained as a result of measuring the impedance of the capacitor.

In this example, a manufacturing process of a capacitor using a single crystal silicon carbide wafer as a supporting substrate will be described. Since the outline of the process is the same as that of the first embodiment, FIGS. 2 to 11 are used for the description of the process.
First, the support substrate was pretreated. As a first step of the pretreatment, a single-crystal silicon carbide wafer 2 having a diameter of 4 inches, a thickness of 0.33 mm, and a specific resistivity of 0.1 (Ω · cm) is subjected to a thermal oxidation process, and a second dielectric layer and A silicon dioxide layer 200 having a thickness of 100 nm (average value) was formed on the outermost surface of the wafer. (Figure 2)
As the second step of the pretreatment, when the wafer was cooled to 90 ° C., water vapor was blown onto the wafer surface to promote the generation of silanol groups on the outermost surface of the silicon dioxide layer 200. Finally, as a pretreatment third step, the wafer was cleaned by SPM treatment (H ₂ SO ₄ : H ₂ O ₂ = 4: 1 (volume ratio)).

  Next, the process of forming the dielectric monomolecular film 3 on the support substrate was performed. The single crystal silicon carbide wafer 2 was spin-coated with a negative photoresist solution having acid resistance. Thereafter, the silicon wafer coated with the photoresist was heated on a hot plate at 100 ° C. for 120 seconds to fix the photoresist layer 7 as shown in FIG. At this time, the thickness of the resist layer was about 2 μm.

Subsequently, as shown in FIG. 4, a portion of the photoresist layer 7 where the thin film capacitor structure is to be formed was opened by an exposure and development process. The shape of the opening was a rectangle having a long side of 0.5 mm and a short side of 0.2 mm. The pitch of the openings was 0.65 millimeters in the long side direction and 0.35 millimeters in the short side direction.
The single crystal silicon carbide wafer 2 thus treated was immersed in an organic titanium compound ethanol solution having the composition shown in Table 5 at 50 ° C. for 4 hours. Subsequently, this wafer was placed in an ethanol bath, subjected to ultrasonic cleaning, and then heated in an oven in a nitrogen atmosphere at 120 ° C. for 45 minutes to fix the dielectric monomolecular film 3 on the wafer surface (FIG. 5). reference).

  Subsequently, a process of supporting palladium as a catalyst on the dielectric monomolecular film was performed. The single crystal silicon carbide wafer 21 on which the dielectric monomolecular film 3 was formed by the above process was immersed in an aqueous solution of a palladium compound having the composition shown in Table 6 at 25 ° C. for 30 minutes. Thereafter, the wafer was put into a pure water bath and washed, and then transferred to another pure water bath and stored until the next step.

  The single crystal silicon carbide wafer 2 that has finished the catalyst supporting step was sequentially put into an electrode forming step by electroless copper plating. The electroless copper plating on the dielectric monomolecular film 3 was performed using a plating solution having the composition shown in Table 7. The quartz glass plate 22 carrying palladium was immersed in the plating solution bath at 60 ° C. for 70 minutes to form an electrode 4 for capacitor structure as shown in FIG.

Thereafter, the photoresist 7 was peeled off from the wafer on which the electrodes were formed. Through the steps so far, the thin film capacitor structure 1 having a desired shape is completed on the support substrate. (Fig. 7)
As a subsequent process, an insulator for protecting the thin film capacitor structure was formed. The thermosetting underfill material 5 is applied as shown in FIG. 8 using a dispenser. Thereafter, the single crystal silicon carbide wafer 2 was placed in an oven and heated at 70 ° C. for 1 hour in a nitrogen atmosphere to cure the underfill material.
Then, the process of forming the other electrode 6 which opposes the electrode 4 made from copper plating already formed was implemented.

First, the single crystal silicon carbide wafer 2 on which the thin film capacitor structure had been formed was bonded to a support substrate 8 made of soda glass. As shown in FIG. 9, the silicon wafer was attached so that the surface on which the thin film capacitor structure was formed was opposed to the support substrate 8.
Next, the silicon wafer 2 was thinned. As a first step of thinning, the wafer was ground to 100 μm by a BG (Back Grind) process. Next, as a second step of thinning, the wafer was polished to 50 μm using a CMP (Chemical Mechanical Polishing) process. By this step, the counter electrode 61 that also serves as a support base was completed (see FIG. 10).

Finally, the completed capacitor was singulated as shown in FIG. After the thinned silicon wafer 21 is attached to the dicing tape (not shown) together with the support substrate, the support substrate 81 and the adhesive are removed, and then the wafer and the underfill material 5 are cut at the portion of the underfill material. As a result, the capacitors were separated into 0603 sizes.
Table 8 shows the results of evaluating the characteristics of the separated capacitors. The capacitance was calculated in accordance with 4.7 of JIS C 5101-1-1998, and the stray inductance was calculated using the above-described capacitance based on the resonance frequency obtained as a result of measuring the impedance of the capacitor.

  Furthermore, a multilayer wiring board with built-in components using the completed capacitor was manufactured. Based on a general multilayer wiring board process, a multilayer wiring board 11 having four wiring layers shown in FIG. 12 was manufactured. Here, a rectangular conductor pattern 13 having a long side of 0.6 mm and a short side of 0.3 mm was appropriately provided in the wiring layer 123 arranged on the outermost side in the multilayer wiring board 11. All of these patterns were designed to be connected to the ground layer.

  Subsequently, a component mounting process was performed on the component built-in multilayer wiring board. A lead-free solder paste was supplied to the rectangular conductor pattern 13 by screen printing, and the separated capacitors were mounted using a chip mounter. Finally, the multilayer wiring board on which the capacitor was mounted was passed through a reflow apparatus having a maximum temperature of 260 ° C., and the capacitor was mounted on the multilayer wiring board as shown in FIG.

Thereafter, 0.04 mm thick prepregs and 0.015 mm thick conductor layers were alternately laminated on both surfaces of the multilayer wiring board 11 to completely embed the built-in capacitors. At this time, a hole corresponding to the position of the capacitor was provided in the prepreg or copper foil laminated on the capacitor mounting surface to ensure flatness after lamination.
The conduction between the built-in capacitor and the power supply pattern of the wiring layer 121 was ensured by a via. First, via holes were drilled with a UV-YAG laser on the multilayer wiring board 11 on which the prepreg was laminated to expose the capacitor electrodes. Next, via filling and wiring formation were performed by a semi-additive process, and as shown in FIG. 14, the wiring layer 121 and the via connecting the built-in capacitor and the wiring layer 131 were completed. FIG. 15 shows a schematic diagram of a cross-sectional structure around the built-in capacitor at this time.

DESCRIPTION OF SYMBOLS 1 ... Thin film capacitor structure 2 ... Support base material 200 ... Outermost surface 201 of a support base material ... Second dielectric layer 3 ... Dielectric monomolecular film 4 ... Electrode for capacitor 5 formed by electroless plating ... Insulator 6 ... Capacitor Electrode 7 ... Photoresist 8 ... Support substrate 9 ... Adhesive 11 for supporting substrate adhesion ... Multilayer wiring substrate 121-128 ... Conductor layer 13 of multilayer wiring substrate ... Built-in capacitor mounting pad 14 ... Solder 15 ... Multi-layer wiring substrate with built-in components

Claims (16)

  A dielectric monomolecular film made of at least a monomolecular film of an organic material, an electroless plating catalyst supported on the dielectric monomolecular film, and an electroless plating on the dielectric monomolecular film on the surface of the support substrate A capacitor electrode comprising a layer.   2. The capacitor according to claim 1, further comprising a second dielectric layer having a thickness of 50 nm or more on at least a surface on which the dielectric monomolecular film is formed of the outermost layer of the support base material. 3. The capacitor according to claim 2, wherein the specific resistivity of the second dielectric layer is 1.0 × 10 ⁵ (Ω · cm) or more.   The said support base material is a semiconductor material, The capacitor | condenser of any one of Claims 1-3 characterized by the above-mentioned.   The capacitor according to claim 4, wherein the support base has a thickness of 50 μm or less.   6. The capacitor according to claim 4, wherein the specific resistivity of the semiconductor material constituting the support base is 1.0 (Ω · cm) or less.   The said dielectric monomolecular film makes a chemical bond with said 2nd dielectric material layer in the outermost surface of the said support base material, The any one of Claims 2-6 characterized by the above-mentioned. Capacitor.   The capacitor according to any one of claims 1 to 7, wherein the organic material forming the dielectric monomolecular film is any one of an organic silane compound and an organic titanium compound.   The capacitor according to claim 1, wherein the organic material has at least one substituent having a complex forming ability with the electroless plating catalyst.   10. The capacitor according to claim 9, wherein the organic material includes an aliphatic straight chain having 2 to 20 carbon atoms, and the substituent is bonded to the aliphatic straight chain.   The capacitor according to claim 10, wherein at least one of the substituents forms part of the aliphatic straight chain.   The capacitor according to any one of claims 1 to 11, wherein the electroless plating catalyst is palladium.   The capacitor according to any one of claims 1 to 12, wherein the capacitor electrode is made of any one of Ni, Ni-B, Ni-P, and Cu, or a combination thereof.   14. A multilayer wiring board comprising the capacitor according to claim 1 incorporated therein. It is a manufacturing method of the capacitor given in any 1 paragraph of Claims 1-13,
Forming a plurality of monomolecular dielectric films on the surface of the support substrate;
Supporting the electroless plating catalyst on the plurality of monomolecular dielectric films;
Forming the capacitor electrode by electroless plating on the plurality of monomolecular dielectric films to form a plurality of capacitors on the support substrate;
Separating the plurality of capacitors together with the support base;
A method for producing a capacitor, comprising: The step of forming the capacitor electrode by electroless plating on the plurality of monomolecular dielectric films to form a plurality of capacitors on the support substrate,
Forming the capacitor electrode on the plurality of monomolecular dielectric films by electroless plating, grinding the support substrate from a surface opposite to the surface on which the capacitor is formed, The method for manufacturing a capacitor according to claim 15, wherein the method is a step of forming a capacitor.

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