JP2011188361A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit in which a malfunction does not occur. <P>SOLUTION: This invention relates to a power-on reset circuit which is initialized by generating a reset signal on an initial stage of powering-on or in the case of power supply voltage drop, including: a first comparison voltage generating unit for generating a first comparison voltage by dividing a voltage corresponding to a power supply voltage; a reference voltage generating unit for outputting a first voltage corresponding to the power supply voltage; a depression type first transistor which is connected between a power supply voltage terminal and a first node and inputs the first voltage to a control terminal; and an enhancement type second transistor which is connected between the first node and a ground terminal and in which the control terminal is connected to the first node. The power-on reset circuit further has: a second comparison voltage generating unit for generating a voltage corresponding to a potential of the first node as a second comparison voltage; and a comparator which outputs the reset signal in accordance with a comparison result of the first and second comparison voltages. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power-on reset circuit.

  When the power supply of the circuit system is turned on, the circuit system may malfunction if the power supply voltage is at a low voltage value. In order to prevent this, a function for starting the operation of the circuit system after confirming that the power supply voltage has become a certain value or more is required. This function is called power-on reset (POR).

  A general configuration for realizing the power-on reset function is a configuration in which a comparator compares a voltage value that increases in proportion to the power supply voltage with a reference voltage value. If the value of the reference voltage fluctuates with respect to temperature and process variations, an accurate power-on reset function cannot be realized. For this reason, there is a need for a technique for reducing the fluctuation of the reference voltage value with respect to temperature and process variations and realizing a stable and accurate power-on reset function.

  Patent document 1 is disclosed as an example of such a technique. Patent Document 1 discloses a power-on reset circuit 1 as shown in FIG. As shown in FIG. 9, the power-on reset circuit 1 includes reference voltage generation units 11 and 12 and a comparator CMP11.

  The reference voltage generation unit 11 includes a PMOS transistor MP11, resistors R11 and R12, and a capacitor C11. The reference voltage generation unit 12 includes PMOS transistors MP12 to MP14, NMOS transistors MN11 and MN12, a diode D11, and resistors R13 and R14.

  The PMOS transistor MP11 has a source connected to the power supply terminal VDD, a drain connected to the node N11, and a gate connected to the node N14. The PMOS transistor MP12 has a source connected to the power supply terminal VDD, a drain connected to the node N13, and a gate connected to the node N11. The PMOS transistor MP13 has a source connected to the power supply terminal VDD, a drain connected to the node N13, and a gate connected to the node N14. The PMOS transistor MP14 has a source connected to the power supply terminal VDD and a drain and gate connected to the node N14. The PMOS transistor MP15 has a source connected to the power supply terminal VDD, a drain connected to the node N16, and a gate connected to the node N14.

  The NMOS transistor MN11 has a drain and a gate connected to the node N13 and a source connected to the ground terminal GND. The NMOS transistor MN12 has a drain connected to the node N14, a source connected to the node N15, and a gate connected to the node N13.

  The resistor R11 has one end connected to the node N11 and the other end connected to the node N12. The resistor R12 has one end connected to the node N12 and the other end connected to the ground terminal GND. The resistor R13 has one end connected to the node N15 and the other end connected to the ground terminal GND. The resistor R14 has one end connected to the node N16 and the other end connected to the node N17.

  The capacitor C11 has one end connected to the node N11 and the other end connected to the ground terminal GND. The diode D11 has an anode connected to the node N17 and a cathode connected to the ground terminal GND. The comparator CMP11 compares the voltage Vref of the node N16 and the voltage VA of N12 and outputs the comparison result to the output terminal OUT.

  Here, the start-up unit 13 is configured by the PMOS transistor MP12 and the capacitor C11. The PMOS transistors MP13 to MP15, NMOS transistors MN11 and MN12, resistors R13 and R14, and a diode D11 constitute a BGR circuit 14.

  The start-up unit 13 and the power-on reset circuit 1 perform the following operations. First, the capacitor C11 before charging transmits the ground voltage GND to the node N11. Therefore, the PMOS transistor MP12 is turned on and transmits the power supply voltage VDD to the node N13. For this reason, even in the initial power-on state, the reference current is caused to flow through the NMOS transistors MN11 and MN12, and the reference voltage generator 12 is forcibly activated.

  The comparator CMP11 compares the voltage VA generated at the node N12 with the voltage Vref generated at the node N16 by the current flowing according to the reference current. Using this comparison result, a power-on reset of the circuit is realized. Here, since the voltage Vref of the node N16 is generated by the BGR circuit included in the reference voltage generation unit 12, it is hardly affected by variations in elements and temperature dependence. For this reason, the power-on reset circuit 1 can perform a stable power-on reset operation.

  FIG. 10 shows operation waveforms of the power-on reset circuit 1. As shown in FIG. 10, the power is turned on at time t0, and the power supply voltage VDD gradually increases. Since the BGR circuit is not operating immediately after the power supply voltage is turned on, both the voltages Vref and VA are low. Then, the potential inside the BGR circuit starts to rise, the potential of the voltage Vref rises and settles to a predetermined reference voltage. On the other hand, the voltage VA continues to rise together with the power supply voltage VDD and becomes higher than the reference voltage Vref at time t2. For this reason, as a comparison result of the comparator CMP11, the power-on reset signal output from the output terminal OUT becomes a low level after time t2.

JP-A-8-186484

  However, as shown in FIG. 10, at the time t0 to t1 immediately after the power supply voltage is turned on, the operating current of the BGR circuit is not sufficient, so the voltage VA may be higher than Vref. For this reason, if a high level power-on reset signal should be output as a comparison result of the comparator CMP11, a low level signal may be output to the output terminal OUT. Thus, the power-on reset circuit 1 has a problem of outputting an incorrect output value immediately after the power supply voltage is turned on.

  As means for solving such a problem, the configuration of a power-on reset circuit 2 is described in Patent Document 1. FIG. 11 shows the configuration of the power-on reset circuit 2. As shown in FIG. 11, the power-on reset circuit 2 includes reference voltage generation units 21 and 22, comparators CMP11 and CMP12, and an OR circuit OR11. The reference voltage generation unit 22 has a BGR circuit 23.

  The reference voltage generation unit 21 includes a PMOS transistor MP11, resistors R11 to R15, and a capacitor C11. The reference voltage generation unit 22 includes PMOS transistors MP12 to MP14, NMOS transistors MN11 and MN12, and diodes D11 to D13.

  The power-on reset circuit 2 has a configuration in which a resistor R15, diodes D12 and D13, a comparator CMP12, and an OR circuit OR11 are newly added to the power-on reset circuit 1. In order to solve the problem of the power-on reset circuit 1, the power-on reset circuit 2 has a comparator CMP12 that compares the voltage VB at the node N18 and the voltage VC at the node N13. The comparison result of the comparator CMP12 and the comparison result of the comparator CMP11 are summed by the OR circuit OR11. The result of this sum operation is used as a power-on reset signal.

  FIG. 12 shows operation waveforms of the power-on reset circuit 2. As shown in FIG. 12, the voltage VC of the node N13 increases following the power supply voltage VDD, and settles to a voltage value at which the BGR circuit operates stably. The voltage VB at the node N18 rises with a larger slope than the voltage VA at the node N12. For this reason, as shown in FIG. 12, the voltage VB and the voltage VC intersect at a time t2 earlier than the time t3 when the voltage VA and the voltage Vref intersect. Therefore, by taking the sum operation of the outputs of the comparators CMP11 and CMP12, the problem that the power-on reset circuit 1 outputs an incorrect value immediately after the power supply voltage is turned on is solved.

  However, the power-on reset circuit 2 has the following problems. When the rising speed of the power supply voltage VDD is fast, the voltage VC of the node N13 cannot follow the power supply voltage VDD as shown in FIG. At this time, there is a period Td1 in which the magnitude of the voltage value is uncertain for the time that the rise of the voltage is delayed, and the output of the comparator CMP12 may output an incorrect value at time t0 to t1 in FIG. There is sex. For this reason, when the rise of the power supply voltage VDD is more sudden than expected, there is a problem that the power-on reset signal output from the power-on reset circuit 2 also outputs an incorrect output value immediately after the power supply voltage is turned on.

  Thus, there is a need for a power-on reset circuit that can accurately generate a power-on reset signal even in the initial power-on state.

  The present invention provides a power-on reset circuit that generates a reset signal at the start of supply of a power supply voltage of a semiconductor device or when the power supply voltage drops, and initializes an internal circuit of the semiconductor device. A first comparison voltage generation unit that generates a first comparison voltage divided at a predetermined ratio; a reference voltage generation unit that outputs a first voltage corresponding to the power supply voltage; and a power supply that supplies the power supply voltage A depletion-type first transistor that is connected between the voltage terminal and the first node and inputs the first voltage to the control terminal, and is connected between the first node and the ground terminal. And a second comparison voltage generation unit that generates, as a second comparison voltage, a voltage corresponding to the potential of the first node, the enhancement-type second transistor having a terminal connected to the first node The first compares the second comparison voltage, a power-on reset circuit having a comparator for outputting the reset signal in response to the comparison result.

  The power-on reset circuit according to the present invention includes a second comparison voltage generation unit including a depletion-type first transistor and an enhancement-type second transistor connected in series between a power supply voltage terminal and a ground terminal. The depletion-type first transistor and the enhancement-type second transistor are connected at a first node, and the control terminal of the second transistor is connected to the first node. For this reason, in the initial state where the power is turned on, the voltage at the first node rises by following substantially the same potential when the power supply voltage rises.

  The voltage at the first node becomes a constant voltage when the power supply voltage becomes higher than a predetermined voltage. For this reason, the second comparison voltage corresponding to the first node and the first comparison voltage obtained by dividing the voltage corresponding to the power supply voltage by a predetermined ratio are large or small even in the initial state of power-on. It is possible to prevent the reset signal output from the comparator from becoming an incorrect value without causing the relationship to be uncertain.

  The power-on reset circuit according to the present invention can prevent the reset signal from having an incorrect value.

3 is a configuration of a power-on reset circuit according to the first embodiment. 4 is an operation waveform of the power-on reset circuit according to the first embodiment. 3 is a configuration of a power-on reset circuit according to the second embodiment. 6 is an operation waveform of the power-on reset circuit according to the second embodiment. 4 is a configuration of a power-on reset circuit according to a third embodiment. It is an operation | movement waveform for demonstrating the problem of the conventional power-on reset circuit. This is a configuration of a power-on reset circuit according to another embodiment. This is a configuration of a power-on reset circuit according to another embodiment. This is a configuration of a conventional power-on reset circuit. It is an operation | movement waveform for demonstrating the problem of the conventional power-on reset circuit. This is a configuration of a conventional power-on reset circuit. It is an operation | movement waveform of the conventional power-on reset circuit. It is an operation | movement waveform for demonstrating the problem of the conventional power-on reset circuit.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a power-on reset circuit 100 according to the first embodiment. As shown in FIG. 1, the power-on reset circuit 100 includes a reference voltage generation circuit 110, comparison voltage generation units 120 and 130, and a comparator (comparator) CMP150.

  The reference voltage generation circuit 110 generates a predetermined reference voltage using the power supply voltage VDD from the power supply terminal VDD as a power source. For example, a configuration such as the BGR circuit 14 of the reference voltage generation unit 12 of FIG. 9 or the BGR circuit 23 of the reference voltage generation unit 22 of FIG. When the power supply voltage VDD at the time of power-on is low, the reference voltage generation circuit 110 does not have a sufficient drive current for the internal circuit and cannot be activated. For this reason, even if the power supply voltage VDD increases, the output reference voltage Vref cannot follow the power supply voltage VDD and becomes a low potential.

  The comparison voltage generation unit 120 includes resistors R11 and R12. The resistor R11 has one end connected to the power supply terminal VDD and the other end connected to the node N12. The resistor R12 has one end connected to the node N12 and the other end connected to the ground terminal GND. Note that a voltage appearing at the node N12 is referred to as a comparison voltage VA. As can be seen from the connection configuration of the circuit, the comparison voltage VA follows the same manner as the power supply voltage VDD increases.

  The comparison voltage generation unit 130 includes NMOS transistors DPMN101 and MN101. Here, the NMOS transistor DPMN101 is a depletion type transistor. The NMOS transistor MN101 is an enhancement type transistor.

  The NMOS transistor DPMN101 has a drain connected to the power supply terminal VDD and a source connected to the node N101. The reference voltage Vref from the reference voltage generation circuit 110 is input to the gate of the NMOS transistor DPMN101. The NMOS transistor MN101 has a drain and a gate connected to the node N101 and a source connected to the ground terminal GND. Note that a voltage appearing at the node N101 is referred to as a comparison voltage VD.

  Here, the NMOS transistor DPMN101 which is a depletion type transistor has a negative threshold voltage. Therefore, even when the gate voltage is 0 V, that is, the ground voltage GND, the drain current flows by applying the drain voltage. Further, the NMOS transistor MN101, which is an enhancement type transistor, is turned on when the voltage applied to the gate becomes larger than the threshold voltage, and allows a drain current to flow.

  The comparator CMP150 has one input terminal connected to the node N101, the other input terminal connected to the node N12, and an output terminal connected to the power-on reset output terminal OUT. That is, the comparator CMP150 compares the voltage values of the comparison voltages VA and VD and outputs the comparison result as a power-on reset signal. Note that the voltage of the signal output to the power-on reset output terminal OUT is VOUT.

  The operation of the power-on reset circuit 100 configured as above will be described. FIG. 2 shows operation waveforms of the power-on reset circuit 100. As in the prior art (for example, the power-on reset circuit 1 in FIG. 9), the voltage waveform of the power-on reset signal when the power-on reset signal is generated by the reference voltage Vref from the reference voltage generation circuit using the BGR circuit. Is described as VOUTP.

  As shown in FIG. 2, the comparison voltage generator 120 outputs a comparison voltage VA that is a voltage obtained by resistance-dividing the power supply voltage VDD. Therefore, after time t0 when the power is turned on, the comparison voltage VA also increases with a slope corresponding to the resistance ratio of the resistors R11 and R12 following the increase of the power supply voltage VDD.

  Here, since the driving current of the internal circuit does not sufficiently flow and the reference voltage generation circuit 110 is not in an active state unlike the power-on reset circuit 1, the reference voltage generation circuit 110 does not enter an active state from time t0 to time t1 as shown in FIG. The reference voltage Vref having a low potential is output. When the power supply voltage VDD further increases, the reference voltage generation circuit 110 becomes active. Thereby, the reference voltage Vref rises following the power supply voltage VDD until it reaches a predetermined voltage value.

  Therefore, when the comparator generates the power-on reset signal using the reference voltage Vref and the comparison voltage VA of the reference voltage generation circuit 110, the power-on is continued until the reference voltage Vref and the comparison voltage VA intersect at time t2. The reset signal VOUTP becomes low level. In this case, similarly to the power-on reset circuits 1 and 2 of the prior art, a low-level power-on reset signal is generated at the beginning of power-on, and an incorrect output value is output immediately after power-on.

  However, in the first embodiment, the NMOS transistor DPMN101 of the comparison voltage generation unit 130 is a depletion type transistor, and the threshold voltage takes a negative value. Therefore, even when the reference voltage Vref input to the gate is low and near the ground voltage GND, the NMOS transistor DPMN101 is in the on state. Therefore, when the power supply voltage VDD rises, the NMOS transistor DPMN101 causes a drain current to flow in accordance with the rise of the power supply voltage VDD, and raises the comparison voltage VD that is the voltage of the node N101.

  On the other hand, the NMOS transistor MN101 of the comparison voltage generation unit 130 is an enhancement type transistor, and is not turned on below the threshold voltage. For this reason, when the power supply voltage VDD is low and the comparison voltage VD is equal to or lower than the threshold voltage, the NMOS transistor MN101 is not turned on. For this reason, when the power supply voltage VDD is low immediately after the power supply voltage is turned on at time t0, the NMOS transistor MN101 makes the node N101 and the ground terminal GND nonconductive. Therefore, as shown in FIG. 2, the comparison voltage VD, which is the voltage of the node N101, is output from the comparison voltage generator 130 while maintaining substantially the same voltage value as the power supply voltage VDD.

  Thereafter, the power supply voltage VDD further rises, and the comparison voltage VD that is the voltage of the node N101 also rises. Further, at time t1, the reference voltage generation circuit 110 becomes active, and the reference voltage Vref also increases. The NMOS transistor DPMN101 causes a drain current corresponding to the reference voltage Vref to flow to the node N101. For this reason, the comparison voltage VD further rises and eventually exceeds the threshold voltage of the NMOS transistor MN101. For this reason, the NMOS transistor MN101 is turned on and starts to flow a drain current. That is, the ground terminal GND and the node N101 gradually become conductive.

  For this reason, the comparison voltage VD does not follow the power supply voltage VDD, and becomes constant at a predetermined voltage value determined by the transistor sizes of the NMOS transistors DPMN101 and MN101. At time t3, the comparison voltages VA and VD are reversed, and a low-level power-on reset signal is output from the comparator CMP150. For this reason, it is possible to prevent an erroneous output value from being output immediately after the power supply voltage is turned on.

Here, the comparison voltage VD that becomes constant at a predetermined voltage value will be described. First, the drain current of the NMOS transistor MN101 is expressed as the following formula (1), with the gate-source voltage Vgs being VD. Further, the comparison voltage VD is expressed as Expression (2) from Expression (1). However, β _MN101 and β _{DPMN 101} are values (μ × Cox × W / L) determined by the product of the mobility μ of the NMOS transistors MN101 and DPMN 101, the oxide film capacitance Cox, and the W / L ratio of the transistors, respectively.

Next, the drain current of the NMOS transistor DPMN101 has a gate-source voltage Vgs of Vref−VD, and is expressed as the following equation (3).

By substituting equation (3) into equation (2), equation (4) is obtained.

However, “A” in Expression (4) can be expressed by Expression (5). Note that the mobility μ of the NMOS transistors MN101 and DPMN101 is substantially the same, and the oxide film capacitance Cox is the same. Therefore, the value of A results in a value determined by the transistor size ratio of the NMOS transistors MN101 and DPMN101.

以上、式（６）からわかるように、比較電圧ＶＤは、電源電圧ＶＤＤによらず、基準電圧ＶｒｅｆとＮＭＯＳトランジスタＭＮ１０１、ＤＰＭＮ１０１のトランジスタサイズ比で決まる電圧値で一定（図２のＶｃｎｔ）となる。また、この式（６）から、ＮＭＯＳトランジスタＤＰＭＮ１０１のゲートに入力される電圧Ｖｒｅｆの条件は、ＮＭＯＳトランジスタＭＮ１０１が飽和領域で動作することから、以下の式（７）を満たす必要がある。

When the expression (4) is summarized by VD, the following expression (6) is obtained.

As can be seen from the equation (6), the comparison voltage VD is constant (Vcnt in FIG. 2) at a voltage value determined by the reference voltage Vref and the transistor size ratio of the NMOS transistors MN101 and DPMN101, regardless of the power supply voltage VDD. . Further, from this equation (6), the condition of the voltage Vref input to the gate of the NMOS transistor DPMN101 needs to satisfy the following equation (7) because the NMOS transistor MN101 operates in the saturation region.

Here, the threshold voltage _{Vth DPMN101} of NMOS transistor DPMN101, since a negative value close to 0 degree or 0 as long Vref also about _{Vth MN 101.}

  As described above, in the first embodiment, the comparator CMP150 compares the comparison voltage VA output from the comparison voltage generation unit 120 and the comparison voltage VD output from the comparison voltage generation unit 130, thereby generating a power-on reset signal. ing. The comparison voltage VA resistance-divides the power supply voltage VDD and follows the power supply voltage VDD linearly.

  On the other hand, the comparison voltage VD is substantially the same as the power supply voltage VDD as the potential of the intermediate node (node N101) between the depletion type NMOS transistor DPMN101 in the on state and the enhancement type NMOS transistor MN101 in the off state in the initial stage of power-on. It rises following the voltage value. When the power supply voltage VDD rises to some extent, the voltage value determined by the reference voltage Vref and the transistor size ratio of the NMOS transistors MN101 and DPMN101 becomes constant regardless of the power supply voltage VDD.

  This operation is the same regardless of the rising speed of the power supply voltage VDD. In other words, even if the rising speed of the power supply voltage VDD is fast or slow, the same voltage as the power supply voltage VDD is kept in the initial stage of power-on. Therefore, unlike the power-on reset circuits 1 and 2 of the prior art, it is possible to solve the problem of outputting an incorrect output value without generating a low-level power-on reset signal in the initial stage of power-on. it can.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 3 shows the configuration of the power-on reset circuit 200 according to the second embodiment. As illustrated in FIG. 3, the power-on reset circuit 200 includes a reference voltage generation circuit 210, comparison voltage generation units 220 and 130, and a comparator (comparator) CMP 150.

  The reference voltage generation circuit 210 includes a band gap reference (BGR) circuit 211 and a startup unit 212.

  The BGR circuit 211 includes PMOS transistors MP13 to MP15, NMOS transistors MN11 and MN12, diodes D11 to D13, and resistors R13 and R14.

  The PMOS transistor MP13 has a source connected to the power supply terminal VDD, a drain connected to the node N13, and a gate connected to the node N14. The PMOS transistor MP14 has a source connected to the power supply terminal VDD and a drain and gate connected to the node N14. The PMOS transistor MP15 has a source connected to the power supply terminal VDD, a drain connected to the node N16, and a gate connected to the node N14.

  The NMOS transistor MN11 has a drain and a gate connected to the node N13 and a source connected to the node N19. The NMOS transistor MN12 has a drain connected to the node N14, a source connected to the node N15, and a gate connected to the node N13. The resistor R13 has one end connected to the node N15 and the other end connected to the node N20. The resistor R14 has one end connected to the node N16 and the other end connected to the node N17.

  The diode D11 has an anode connected to the node N17 and a cathode connected to the ground terminal GND. The diode D12 has an anode connected to the node N20 and a cathode connected to the ground terminal GND. The diode D13 has an anode connected to the node N19 and a cathode connected to the ground terminal GND.

  The BGR circuit 211 operates in the same manner as the BGR circuit of the power-on reset circuit 2 in FIG. That is, when the power supply voltage VDD rises and exceeds a certain value, a predetermined reference voltage Vref is generated at the node N16. Here, in the second embodiment, the voltage generated at the node N13 is VC.

  The comparison voltage generation unit 220 includes a PMOS transistor MP11 and resistors R11 and R12. The PMOS transistor MP11 has a source connected to the power supply terminal VDD, a drain connected to the node N11, and a gate connected to the node N14. The resistor R11 has one end connected to the node N11 and the other end connected to the node N12. The resistor R12 has one end connected to the node N12 and the other end connected to the ground terminal GND. Note that a voltage appearing at the node N12 is referred to as a comparison voltage VA.

  The PMOS transistor MP11 forms a current mirror with the PMOS transistor MP14 of the BGR circuit 211. Therefore, when the BGR circuit 211 becomes active and a current flows through the PMOS transistor MP14, the PMOS transistor MP11 also flows a drain current corresponding to the current, and the comparison voltage generation unit 220 becomes active.

  The comparison voltage generation unit 130 includes NMOS transistors DPMN101 and MN101 as in the first embodiment. As in the first embodiment, the NMOS transistor DPMN101 is a depletion type transistor. The NMOS transistor DPMN101 has a drain connected to the power supply terminal VDD, a source connected to the node N101, and a gate connected to the node N13. The NMOS transistor MN101 has a drain and a gate connected to the node N101 and a source connected to the ground terminal GND. Note that a voltage appearing at the node N101 is referred to as a comparison voltage VD.

  The startup unit 212 includes a PMOS transistor MP12 and a capacitor C11. The PMOS transistor MP12 has a source connected to the power supply terminal VDD, a drain connected to the node N13, and a gate connected to the node N11. The capacitor C11 has one end connected to the node N11 and the other end connected to the ground terminal GND.

  The start-up unit 212 has a function of making the BGR circuit (the BGR circuit 211 of the second embodiment) active in a short time from when the power is turned on, like the conventional power-on reset circuits 1 and 2. In this initial state of power-on, the ground voltage GND is transmitted to the node N11 via the capacitor C11, thereby turning on the PMOS transistor MP12 whose gate is connected to the node N11. The PMOS transistor MP12 in the on state transmits the power supply voltage VDD to the node N13, forcing the BGR circuit 211 into an active state.

  Note that when the BGR circuit 211 is activated, the comparison voltage generation unit 220 is also activated, a current flows through the node N11, and the capacitor C11 is charged. When the capacitor C11 is charged, the voltage applied to the gate of the PMOS transistor MP12 becomes high level, and the PMOS transistor MP12 is turned off. Therefore, the start-up unit 212 is turned off after a predetermined period after the BGR circuit 211 becomes active.

  Here, the PMOS transistors MP11 to MP15 and the NMOS transistors MN11 and MN12 are assumed to be enhancement type transistors.

  The comparator CMP150 has one input terminal connected to the node N101, the other input terminal connected to the node N12, and an output terminal connected to the power-on reset output terminal OUT. That is, the comparator CMP150 compares the voltage values of the comparison voltages VA and VD as in the first embodiment, and outputs the comparison result as a power-on reset signal. Note that the voltage of the signal output to the power-on reset output terminal OUT is VOUT.

  Next, the operation of the power-on reset circuit 200 according to the second embodiment will be described. FIG. 4 shows operation waveforms of the power-on reset circuit 200. Here, consider a case where the power supply voltage VDD rises faster than expected, as has been a problem in the conventional power-on reset circuit 2. Further, the basic operations of the BGR circuit 211 and the start-up unit 212 are the same as those of the conventional power-on reset circuit 2, and therefore the description thereof is omitted unless particularly necessary.

  As shown in FIG. 4, the power is turned on at time t0, and the power supply voltage VDD gradually increases. Since the BGR circuit 211 is not active at times t0 to t1 immediately after the power is turned on, both the comparison voltage VA and the reference voltage Vref are as low as the ground voltage GND. When the power supply voltage VDD further rises, the PMOS transistor MP12 is turned on by the function of the startup unit 212, and a drain current flows through the node N13. For this reason, the voltage VC of the node N13 starts to rise, and the BGR circuit 211 becomes active.

  Further, when the BGR circuit 211 becomes active and a current flows through the PMOS transistor MP14, a current also flows through the PMOS transistor MP11 of the comparison voltage generation unit 220 that is current-mirror connected to the PMOS transistor MP14. For this reason, the potential of the comparison voltage VA that is the voltage of the node N12 also starts to rise. When the power supply voltage VDD further rises, the reference voltage Vref and the voltage VC at the node N13 will eventually become constant at a predetermined voltage value.

  Here, in the conventional power-on reset circuit 2, when the rising speed of the power supply voltage VDD is faster than expected, the voltage VC of the node N13 cannot follow the power supply voltage VDD, and the rise of the voltage may be delayed. For this reason, the magnitudes of the voltage values of the comparison voltage VB output from the reference voltage generation unit 21 and the comparison voltage VC output from the comparison voltage generation unit 22 are shown in FIG. It was indeterminate in the period Td1 between times t0 and t1. Therefore, there is a possibility that the output of the comparator CMP12 may output an incorrect value, and the power-on reset signal output from the power-on reset circuit 2 also outputs an incorrect output value immediately after turning on the power supply voltage. there were.

  However, in the second embodiment, as in the first embodiment, the NMOS transistor DPMN101 of the comparison voltage generation unit 130 is a depletion type transistor, and the threshold voltage takes a negative value. Therefore, even when the voltage VC input to the gate of the NMOS transistor DPMN101 is low and near the ground voltage GND, the NMOS transistor DPMN101 is in the on state. Therefore, when the power supply voltage VDD rises, the NMOS transistor DPMN101 causes a drain current to flow in accordance with the rise of the power supply voltage VDD, and raises the comparison voltage VD that is the voltage of the node N101.

  On the other hand, the NMOS transistor MN101 of the comparison voltage generation unit 130 is an enhancement type transistor as in the first embodiment, and is not turned on below the threshold voltage. For this reason, when the power supply voltage VDD is low and the comparison voltage VD is equal to or lower than the threshold voltage, the NMOS transistor MN101 is not turned on. For this reason, when the power supply voltage VDD is low immediately after the power supply voltage is turned on at time t0, the NMOS transistor MN101 makes the node N101 and the ground terminal GND nonconductive. Therefore, as shown in FIG. 4, the comparison voltage VD, which is the voltage at the node N101, is output from the comparison voltage generator 130 while maintaining substantially the same voltage value as the power supply voltage VDD.

  Thereafter, the power supply voltage VDD further rises, and the comparison voltage VD that is the voltage of the node N101 also rises. Further, at time t1, the BGR circuit 211 becomes active and the voltage VC increases. The NMOS transistor DPMN101 passes a drain current corresponding to the voltage VC to the node N101. For this reason, the comparison voltage VD further rises and eventually exceeds the threshold voltage of the NMOS transistor MN101. For this reason, the NMOS transistor MN101 is turned on and starts to flow a drain current. That is, the ground terminal GND and the node N101 gradually become conductive.

  For this reason, the comparison voltage VD does not follow the power supply voltage VDD, and becomes constant at a predetermined voltage value determined by the transistor sizes of the NMOS transistors DPMN101 and MN101. At time t5, the comparison voltages VA and VD are reversed, and a low-level power-on reset signal is output from the comparator CMP150. For this reason, it is possible to prevent an erroneous output value from being output immediately after the power supply voltage is turned on.

  For comparison with the operation waveform of the second embodiment, FIG. 4 shows the resistance-divided voltage (here, the comparison voltage VA) and the voltage VC at the node N13 as in the conventional power-on reset circuit 2. The voltage waveform of the signal generated by comparison is shown as VOUTP. Similarly to FIG. 13, the signal VOUTP is also at a low level as shown in FIG. 4 because the magnitudes of the voltages VC and VA are uncertain during the period of time t0 to t1. For this reason, the power-on reset signal using the signal VOUTP may output an incorrect output value immediately after the power supply voltage is turned on.

  However, as described above, since the power-on reset circuit 200 according to the second embodiment compares the comparison voltage VD generated by the comparison voltage generation unit 130 with the comparison voltage VA, such a problem does not occur.

  Here, the comparison voltage VD that becomes constant at a predetermined voltage value will be described. As in the first embodiment, the drain current of the NMOS transistor MN101 is expressed as Expression (1), and the comparison voltage VD is expressed as Expression (2).

Next, the drain current of the NMOS transistor DPMN101 has a gate-source voltage Vgs of VC−VD, and is expressed as the following equation (8).

By substituting equation (8) into equation (2), equation (9) is obtained.

  Note that “A” in Expression (9) can be expressed by Expression (5) as in Embodiment 1, and the value of A is a value determined by the transistor size ratio of the NMOS transistors MN101 and DPMN101.

以上、式（１０）からわかるように、比較電圧ＶＤは、電源電圧ＶＤＤによらず、ノードＮ１３の電圧ＶＣとＮＭＯＳトランジスタＭＮ１０１、ＤＰＭＮ１０１のトランジスタサイズ比で決まる電圧値で一定（図４のＶｃｎｔ）となる。また、この式（１０）から、ＮＭＯＳトランジスタＤＰＭＮ１０１のゲートに入力される電圧ＶＣの条件は、ＮＭＯＳトランジスタＭＮ１０１が飽和領域で動作することから、以下の式（１１）を満たす必要がある。

When the formula (9) is summarized by VD, the following formula (10) is obtained.

As can be seen from the equation (10), the comparison voltage VD is constant at a voltage value determined by the voltage size of the node N13 and the transistor size ratio of the NMOS transistors MN101 and DPMN101 regardless of the power supply voltage VDD (Vcnt in FIG. 4). It becomes. Further, from this equation (10), the condition of the voltage VC input to the gate of the NMOS transistor DPMN101 needs to satisfy the following equation (11) because the NMOS transistor MN101 operates in the saturation region.

Here, the threshold voltage _{Vth DPMN101} of NMOS transistor DPMN101, since a negative value close to 0 degree or 0 as long VC also about _{Vth MN 101.}

  As described above, in the second embodiment, the comparator CMP150 compares the comparison voltage VA output from the comparison voltage generation unit 220 with the comparison voltage VD output from the comparison voltage generation unit 130, thereby generating a power-on reset signal. ing.

  As described above, the comparison voltage VA is not in the active state of the comparison voltage generation unit 220 before the BGR circuit 211 is in the active state, and is about the ground voltage GND. Then, after the BGR circuit 211 becomes active, the power supply voltage VDD is resistance-divided and linearly follows the power supply voltage VDD.

  On the other hand, the comparison voltage VD is substantially the same as the power supply voltage VDD as the potential of the intermediate node (node N101) between the depletion type NMOS transistor DPMN101 in the on state and the enhancement type NMOS transistor MN101 in the off state in the initial stage of power-on. It rises following the voltage value. When the power supply voltage VDD rises to some extent, the voltage value determined by the voltage VC of the node N13 of the BGR circuit 211 and the transistor size ratio of the NMOS transistors MN101 and DPMN101 becomes constant regardless of the power supply voltage VDD.

  This operation is the same regardless of the rising speed of the power supply voltage VDD. That is, the comparison voltage VD keeps substantially the same voltage as the power supply voltage VDD at the beginning of power-on, whether the rising speed of the power supply voltage VDD is fast or slow. Therefore, unlike the power-on reset circuits 1 and 2 of the prior art, it is possible to solve the problem of outputting an incorrect output value without generating a low-level power-on reset signal in the initial stage of power-on. it can.

  Embodiment 3 of the Invention

  Hereinafter, a specific third embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 5 shows a configuration of a power-on reset circuit 300 according to the third embodiment. As shown in FIG. 5, the power-on reset circuit 300 includes a reference voltage generation circuit 210, comparison voltage generation units 220 and 330, and a comparator (comparator) CMP 150. The reference voltage generation circuit 210 includes a band gap reference (BGR) circuit 211 and a startup unit 212.

  In addition, the structure which attached | subjected the code | symbol same as FIG. 3 among the code | symbols shown in FIG. 5 has shown the same or similar structure as FIG. The difference from the second embodiment is the configuration of the comparison voltage generation unit 330. In the third embodiment, these different parts will be described with emphasis, and description of other parts similar to those of the second embodiment will be omitted.

  The comparison voltage generation unit 330 includes NMOS transistors DPMN101, DPMN102, MN101, and MN102. The NMOS transistors DPMN101 and DPMN102 are depletion type transistors.

  The NMOS transistor DPMN101 has a drain connected to the power supply terminal VDD, a source connected to the node N101, and a gate connected to the node N13. The NMOS transistor MN101 has a drain and a gate connected to the node N101 and a source connected to the ground terminal GND. Note that a voltage appearing at the node N101 is referred to as a comparison voltage VD.

  The NMOS transistor DPMN102 has a drain connected to the power supply terminal VDD, a source connected to the node N102, and a gate connected to the node N101. The NMOS transistor MN102 has a drain and a gate connected to the node N102 and a source connected to the ground terminal GND. Note that a voltage appearing at the node N102 is referred to as a comparison voltage VE.

  The comparator CMP150 has one input terminal connected to the node N102, the other input terminal connected to the node N12, and an output terminal connected to the power-on reset output terminal OUT. That is, the comparator CMP150 compares the voltage values of the comparison voltages VA and VE and outputs the comparison result as a power-on reset signal. Note that the voltage of the signal output to the power-on reset output terminal OUT is VOUT.

  As can be seen from the configuration of FIG. 5, the comparison voltage generation unit 330 has a configuration in which the circuit of the comparison voltage generation unit 130 of the first and second embodiments is connected in two stages in series between the node N13 and the comparator CMP150. It has become. For this reason, the basic operation is almost the same, and a description thereof is omitted here. Hereinafter, a comparison voltage VE that is an output voltage of the comparison voltage generation unit 330 is obtained.

Here, the comparison voltage VD that becomes constant at a predetermined voltage value will be described. First, the drain current of the NMOS transistor MN102 is expressed as the following formula (12), where the gate-source voltage Vgs becomes VE. Further, the comparison voltage VE is expressed as Expression (13) from Expression (12). However, β _MN101 , β _MN102 , β _DPMN101 , and β _DPMN102 are values determined by the products of the mobility μ of the NMOS transistors MN101, MN102, DPMN101, and DPMN 102, the oxide film capacitance Cox, and the W / L ratio of the transistors ( μ × Cox × W / L).

Next, the drain current of the NMOS transistor DPMN102 has a gate-source voltage Vgs of VD−VE, and is expressed as the following equation (14).

Substituting equation (14) into equation (13), equation (15) is obtained.

However, “B” in Expression (15) can be expressed by the following Expression (16). Note that the mobility μ of the NMOS transistors MN102 and DPMN102 is substantially the same, and the oxide film capacitance Cox is the same. Therefore, the value of B results in a value determined by the transistor size ratio of the NMOS transistors MN102 and DPMN102.

次に、ノードＮ１０１の電圧ＶＤの温度依存性を考える。電圧ＶＤの温度依存性は、式（１０）から以下の式（１８）として求めることができる。

同様に、ノードＮ１０２の電圧である比較電圧ＶＥの温度依存性を考える。電圧ＶＥの温度依存性は、式（１８）から以下の式（１９）として求めることができる。

ここで、電圧ＶＤの温度依存性を排除するには、上記式（１８）のＡの値を非常に小さい値（Ａ≒０）に設定する。例えば、ＮＭＯＳトランジスタＤＰＭＮ１０１のゲート幅Ｗ_{ＤＰＭＮ１０１}をＮＭＯＳトランジスタＭＮ１０１のゲート幅Ｗ_{ＭＮ１０１}と比較して十分小さく、もしくは、ＮＭＯＳトランジスタＤＰＭＮ１０１のゲート長Ｌ_{ＤＰＭＮ１０１}をＮＭＯＳトランジスタＭＮ１０１のゲート長Ｌ_{ＭＮ１０１}と比較して十分大きくする。具体的な数値としては、Ｗ_{ＤＰＭＮ１０１}をＷ_{ＭＮ１０１}の約１０分の１以下、もしくは、Ｌ_{ＤＰＭＮ１０１}をＬ_{ＭＮ１０１}の約１０倍以上とし、Ａの値が約０．３以下となるようにする。また、ＮＭＯＳトランジスタＤＰＭＮ１０１のトランジスタサイズ比（Ｗ_{ＤＰＭＮ１０１}／Ｌ_{ＤＰＭＮ１０１}）及びＮＭＯＳトランジスタＭＮ１０１のトランジスタサイズ比（Ｗ_{ＭＮ１０１}／Ｌ_{ＭＮ１０１}）を調整して、結果的にＡの値が約０．３以下となるようにしてもよい。この場合、電圧ＶＤの温度依存性は、ＮＭＯＳトランジスタＭＮ１０１のスレッショルド電圧Ｖｔｈ_{ＭＮ１０１}の温度依存性となる。 When the expression (16) is summarized by VE, the following expression (17) is obtained.

Next, consider the temperature dependence of the voltage VD of the node N101. The temperature dependence of the voltage VD can be obtained from the equation (10) as the following equation (18).

Similarly, consider the temperature dependence of the comparison voltage VE, which is the voltage at the node N102. The temperature dependence of the voltage VE can be obtained from the equation (18) as the following equation (19).

Here, in order to eliminate the temperature dependency of the voltage VD, the value of A in the above equation (18) is set to a very small value (A≈0). For example, sufficiently small compared to the gate width _{W DPMN101} of NMOS transistor DPMN101 the gate width _{W MN101} of NMOS transistors MN101, or sufficient to compare the gate length _{L DPMN101} of NMOS transistor DPMN101 the gate length _{L MN101} of NMOS transistors MN101 Enlarge. Specific numerical _values, the following 1 to about 10 minutes of _{W MN 101} to _{W DPMN101, or} the _{L DPMN101} to about 10 times or more the _{L MN 101,} so that the value of A is about 0.3 or less. Further, by adjusting the transistor size ratio of the NMOS transistor _{DPMN101 (W} DPMN101 _{/ L} DPMN101) and the transistor size ratio of the NMOS transistor _{MN101 (W MN101 / L MN101)} , the resulting value to A of about 0.3 or less You may do it. In this case, the temperature dependency of the voltage VD is the temperature dependency of the threshold voltage Vth _MN101 of the NMOS transistor MN101.

Further, by substituting equation (18) in which the A ≒ 0 in formula (19), the temperature dependency of the threshold voltage _{Vth DPMN102} temperature dependence and NMOS transistor DPMN102 threshold voltage _{Vth MN101} of the NMOS transistor MN101 are the same from, the temperature dependence of the threshold voltage _{Vth DPMN102} of the temperature dependence and the NMOS transistor DPMN102 of the threshold voltage _{Vth MN101} of the NMOS transistor MN101 cancel each other out.

Therefore, as a result, the temperature dependence of the voltage VE is a value obtained by dividing the temperature dependence of the threshold voltage Vth _MN102 of the NMOS transistor MN102 by (1 + B). Therefore, by setting the NMOS transistors DPMN102 and MN102 so as to increase the value of B, the temperature dependence of the voltage VE can be greatly reduced. Note that increasing the value of B, for example, enough larger than the gate width _{W DPMN102} of NMOS transistor DPMN102 the gate width _{W MN 102} of the NMOS transistor MN 102, or the gate length _{L DPMN102} of NMOS transistor DPMN101 NMOS transistor The gate length L of the MN 101 is made sufficiently smaller than the _MN102 . As specific numerical values, the W _{DPMN 102} is set to about 10 times or more of the W _{MN 102} , or the L _{DPMN 101} is set to about _1/10 or _less of the L _{MN 101} , and the value of B is set to about 3 or more. Further, the transistor size ratio (W _DPMN102 / L _DPMN102 ) of the NMOS transistor _DPMN102 and the transistor size ratio (W _MN102 / L _MN102 ) of the NMOS transistor MN102 are adjusted so that the value of B becomes about 3 or more as a result. May be.

Further, as described above, since it has been decided to decrease the value of A and increase the value of B, assuming that _A≈0 and B >> 1, VD = Vth _MN101 , VE = VD−Vth _DPMN102 and Can be approximated. Therefore, VE = Vth _MN101 −Vth _DPMN102 . Here, assuming that the transistors forming the comparison voltage generation unit 330 have variations in manufacturing process in the same direction, the process variations in the comparison voltage VE are also canceled.

  Here, in the conventional power-on reset circuit 2, the voltage value of the voltage VC at the node N13 varies due to the influence of temperature and the influence of process variations. For this reason, as shown in FIG. 6, depending on the design, even if the malfunction immediately after turning on the power supply voltage can be eliminated, the detection time may be delayed by the period Td2.

  However, in the power-on reset circuit 300 of the third embodiment, the temperature dependency and process dependency of the comparison voltage VE can be canceled by setting A and B with the values as described above. For this reason, the comparison voltage generator 330 can output a stable comparison voltage VE regardless of temperature and process variations. As a result, the power-on reset circuit 300 according to the third embodiment generates the same power-on reset signal that has the same effect as the second embodiment and is stable against temperature and process variations. Is possible.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, like the power-on reset circuit 400 shown in FIG. 7, the comparison voltage generation unit 330 of the third embodiment may be replaced with the comparison voltage generation unit 130 of the first embodiment. In this case, the power-on reset circuit 400 can generate a highly accurate power-on reset signal that is stable against temperature and process variations while having the same effect as the first embodiment.

  Further, in the power-on reset circuit 200 according to the second embodiment, the comparator CMP150 generates the power-on reset signal VOUT by comparing the comparison voltages VD and VA. However, as shown in FIG. The power-on reset signal VOUT2 may be generated by comparing the reference voltage Vref generated by the circuit 211 and the comparison voltage VA. Further, whether to transmit the comparison voltage VA to the comparator CMP150 or CMP151 may be selected by the switch SW501.

  By doing so, it is possible to generate a power-on reset signal based on the comparison voltage VD generated by the comparison voltage generator 130, or to generate a power-on reset signal based on the reference voltage Vref generated by the BGR circuit 211. It is also possible to do. This configuration can also be applied to the power-on reset circuit 300 of the third embodiment.

100-500 Power-on reset circuit 110, 210 Reference voltage generation circuit 211 BGR circuit 212 Start-up unit 120, 130 Comparison voltage generation unit CMP150, CMP151 Comparator MN11, MN12, MN101, MN102 Enhancement type NMOS transistor MP11-MP15 Enhancement type PMOS transistor DPMN101 , DPMN102 Depletion type NMOS transistor R11, R12 Resistor C11 Capacitance D11-D13 Diode

Claims (9)

A power-on reset circuit that generates a reset signal at the start of power supply voltage supply of a semiconductor device or at the time of power supply voltage drop, and initializes an internal circuit of the semiconductor device,
A first comparison voltage generation unit that generates a first comparison voltage obtained by dividing a voltage corresponding to the power supply voltage at a predetermined ratio;
A reference voltage generation unit that outputs a first voltage according to the power supply voltage;
A depletion-type first transistor connected between a power supply voltage terminal for supplying the power supply voltage and a first node and inputting the first voltage to a control terminal;
An enhancement-type second transistor connected between the first node and a ground terminal and having a control terminal connected to the first node;
A second comparison voltage generation unit that generates a voltage according to the potential of the first node as a second comparison voltage;
A power-on reset circuit comprising: a comparator that compares the first and second comparison voltages and outputs the reset signal according to the comparison result. 2. The first reference voltage is output from an output node of the reference voltage generation unit and is a first reference voltage that has a constant voltage value when the power supply voltage is equal to or higher than a predetermined voltage. Power-on reset circuit. The reference voltage generation unit is activated when an operating current corresponding to a voltage applied to an internal second node flows, and generates a first control voltage when the active current is activated. A band gap reference circuit that generates a constant reference voltage according to the first control voltage when the power supply voltage is equal to or higher than a predetermined voltage;
The power-on reset circuit according to claim 1, wherein the first voltage is the first control voltage. The power-on reset circuit according to claim 3, wherein the first comparison voltage generation unit is activated in accordance with the first control voltage. The power-on reset circuit according to claim 4, further comprising a start-up unit that transmits the power supply voltage to the first node for a predetermined period from the start of supply of the power supply voltage. The second comparison voltage generation unit further includes a depletion type third transistor and an enhancement type fourth transistor,
The third transistor is connected between a power supply voltage terminal for supplying the power supply voltage and a third node, a control terminal is connected to the first node,
The fourth transistor is connected between the third node and a ground terminal, a control terminal is connected to the third node,
The power-on reset circuit according to any one of claims 1 to 5, wherein the potential of the third node is generated as a second comparison voltage. The ratio of the gate width of at least the second transistor is at least large with respect to the first transistor, or the ratio of the gate length is small.
The power-on reset circuit according to claim 6, wherein at least a ratio of a gate width of the fourth transistor is small or a ratio of a gate length is large with respect to the third transistor. The reference voltage generation circuit includes enhancement type fifth to ninth transistors, first to third diodes, and first and second resistors.
The fifth transistor is connected between the power supply voltage terminal and the second node that generates the first control signal, and a control terminal is connected to a fourth node;
The sixth transistor is connected between the power supply voltage terminal and the fourth node, a control terminal is connected to the fourth node,
The seventh transistor is connected between the power supply voltage terminal and a fifth node that is an output node of the reference voltage generation circuit, and a control terminal is connected to the fourth node.
The eighth transistor is connected between the second node and the sixth node, a control terminal is connected to the second node,
The ninth transistor is connected between the fourth node and the seventh node, and a control terminal is connected to the second node,
The first resistor is connected between the seventh node and an eighth node;
The second resistor is connected between the fifth node and a ninth node;
The first diode is connected between the sixth node and the ground terminal;
The second diode is connected between the eighth node and the ground terminal;
The third diode is connected between the ninth node and the ground terminal;
The comparison voltage generation unit includes a tenth transistor, third and fourth resistors,
The tenth transistor is connected between the power supply voltage terminal and the tenth node, a control terminal is connected to the fourth node,
The third resistor is connected between the tenth node and an eleventh node that generates the first comparison voltage;
The power-on reset circuit according to any one of claims 3 to 7, wherein the fourth resistor is connected between the eleventh node and the ground terminal. The startup unit includes an eleventh transistor and a first capacitor,
The eleventh transistor is connected between the power supply voltage terminal and the second node, a control terminal is connected to the tenth node,
The power-on reset circuit according to claim 8, wherein the first capacitor is connected between the tenth node and a ground terminal.

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