JP2011186554A - Memory management device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently access a memory connected via a network. <P>SOLUTION: A memory management device 32A manages arrangement hint information 14 that is generated based on a property of data stored in at least one of a first semiconductor memory and a nonvolatile second semiconductor memory which has limitations in the number of permitted accesses smaller than the first semiconductor memory and gives a hint for determining an arrangement area of the data. The memory management device 32A includes a management part 20 determining a write area from memory areas of the first semiconductor memory and the second semiconductor memory for data to be written, based on the arrangement hint information 14, memory use information 11, and memory peculiar information 12. A network address conversion part 34 converts a processor logical address issued from a processor into a network logical address which is longer than the processor logical address and which specifies the memory area on a network system. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory management apparatus and method for managing access to a memory.

  In a conventional information processing apparatus, a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory) is used as a main memory (main memory) of a processor. Further, in the conventional information processing apparatus, a nonvolatile semiconductor memory is used as a secondary storage device in combination with a volatile semiconductor memory.

  Japanese Unexamined Patent Application Publication No. 2008-242944 (Patent Document 1) proposes an integrated memory management device. In this integrated memory management device, a NAND flash memory is used as a main memory for the MPU. Furthermore, in Patent Document 1, the MPU primary cache memory, secondary cache memory, and NAND flash memory as the main memory are handled in the same memory hierarchy. The cache controller of the integrated memory management device executes memory management for the main memory in addition to memory management for the primary cache memory and the secondary cache memory.

  Japanese Patent Application Laid-Open No. 7-146820 (Patent Document 2) discloses a technology that employs a flash memory as a main storage device of an information processing apparatus. In Patent Document 2, a flash memory is connected to a memory bus of a system via a cache memory that is a volatile memory. The cache memory is provided with an address array for recording information such as an address or access history of data stored in the cache memory. The controller refers to the access destination address, supplies the data of the cache memory or the flash memory to the memory bus, or stores the data of the memory bus.

  Japanese Patent Application Laid-Open No. 2001-266580 (Patent Document 3) discloses an invention that allows different types of semiconductor memory devices to be connected to a common bus.

  The semiconductor memory device of Patent Document 3 includes a random access memory chip and a package including the random access memory chip. The package includes a plurality of pins that electrically connect the random access memory chip to an external device. The plurality of pins provide a memory function in common to the random access memory and the electrically erasable and programmable nonvolatile semiconductor memory. Each of the plurality of pins is arranged at a corresponding pin position of the nonvolatile semiconductor memory.

  In general, the number of times that a nonvolatile semiconductor memory can be normally accessed is smaller than that of a volatile semiconductor memory.

JP 2008-242944 A Japanese Patent Laid-Open No. 7-146820 JP 2001-266580 A

  It is an object of the present invention to provide a memory management apparatus and method for efficiently accessing a memory connected via a network.

  A memory management device according to one embodiment of the present invention stores data in at least one of a first semiconductor memory and a non-volatile second semiconductor memory having a lower accessible upper limit count than the first semiconductor memory. A first storage unit that stores generation hint information that is generated based on characteristics of each data to be used and serves as a hint for determining an arrangement area of each data; the first semiconductor memory; and the second semiconductor memory A second storage unit that stores memory-specific information indicating memory-specific characteristics for each of the first and second semiconductor memories, and a memory usage that indicates a use state of each memory area included in the first semiconductor memory and the second semiconductor memory A third storage unit for storing information and a processor logical address issued by the processor longer than the processor logical address; A network address conversion unit that converts the upper memory area into a network logical address that identifies the memory area, and the placement hint information for data to be written to at least one of the first semiconductor memory and the second semiconductor memory. A second management unit configured to update the memory use information for the accessed memory area when an access to at least one of the first management unit and the first semiconductor memory and the second semiconductor memory occurs; Based on the management unit, the placement hint information, the memory use information, and the memory unique information, the memory area of the first semiconductor memory and the second semiconductor memory for the write target data is selected. A third management unit for determining a write area and the network of the write target data Based on the fourth management unit that stores the address conversion information that associates the logical address with the physical address of the write area in the fourth storage unit, the network logical address of the read target data and the address conversion information, A fifth management unit for reading the data to be read from either the first semiconductor memory or the second semiconductor memory;

  The above aspect is expressed as a memory management device. However, the present invention is not limited to this, and the above aspect may be expressed by a memory management method, an information processing apparatus, a network system, or the like.

  In the present invention, it is possible to efficiently access a memory connected via a network.

1 is a block diagram showing an example of the configuration of a memory management device and an information processing device according to a first embodiment of the present invention. 1 is a block diagram showing an example of the configuration of a memory management device and an information processing device according to a first embodiment. FIG. 3 is a diagram showing an example of a memory map of the hybrid main memory according to the first embodiment. The figure which shows an example of the address translation information which concerns on 1st Embodiment. The figure which shows an example of the coloring table which concerns on 1st Embodiment. FIG. 6 is a diagram for explaining an example of static color information according to the first embodiment. 6 is a flowchart illustrating an example of data arrangement processing according to the first embodiment. The figure which shows an example of a structure of the coloring table which concerns on 1st Embodiment. The figure which shows the 1st example of the setting of the static color information with respect to various data. The figure which shows the 2nd example of the setting of the static color information with respect to various data. 6 is a flowchart illustrating an example of a coloring table generation process according to the first embodiment. 6 is a flowchart illustrating an example of a creation process of a coloring table entry according to the first embodiment. The figure which shows the 1st example of alignment of the entry of a coloring table. The figure which shows the 2nd example of alignment of the entry of a coloring table. The figure which shows an example of the method of calculating the dynamic writing frequency DW_color and the dynamic reading frequency DR_color based on dynamic color information and static color information. 6 is a flowchart illustrating an example of data read processing according to the first embodiment. 6 is a flowchart illustrating an example of a data read method determination process according to the first embodiment. 5 is a flowchart illustrating an example of a data writing process according to the first embodiment. 6 is a flowchart showing an example of data write destination area determination processing according to the first embodiment; The figure for demonstrating the determination process of the writing object block with respect to the data which concerns on 1st Embodiment. The graph which shows an example of transition of the frequency | count of erasing in the arbitrary block area | regions of a nonvolatile semiconductor memory. The graph which shows an example of the change at the time of setting the threshold value with respect to the difference in the frequency | count of deletion in wear leveling small. The graph which shows an example of grouping of the block area | region according to the frequency | count of erasing. The figure showing the criteria of grouping of the block area according to the number of times of erasure. The figure which shows an example of the search of the block area | region in wear leveling. The block diagram which shows an example of the memory management apparatus provided with the cache memory. The block diagram which shows the example of mounting of a memory management apparatus, a hybrid main memory, and a processor. The block diagram which shows an example of another structure aspect of the memory management apparatus and information processing apparatus which concern on 1st Embodiment. The perspective view which shows an example of several memory management apparatuses which manage several non-volatile semiconductor memory. The block diagram which shows an example of the network system which concerns on the 2nd Embodiment of this invention. The block diagram which shows an example of a structure of the memory management apparatus which concerns on 2nd Embodiment. The block diagram which shows the 1st relationship between the processor logical address and network logical address which concern on 2nd Embodiment. The block diagram which shows the 2nd relationship between the processor logical address and network logical address which concern on 2nd Embodiment. FIG. 10 is a block diagram showing a third relationship between a processor logical address and a network logical address according to the second embodiment. FIG. 9 is a block diagram showing a fourth relationship between a processor logical address and a network logical address according to the second embodiment. FIG. 10 is a block diagram showing a fifth relationship between a processor logical address and a network logical address according to the second embodiment. The block diagram which shows an example of the virtual address space of the network system which concerns on 2nd Embodiment. The block diagram which shows the 1st example of a structure of the processor logical address and network logical address which concern on 2nd Embodiment. The block diagram which shows the 2nd example of a structure of the processor logical address and network logical address which concern on 2nd Embodiment. The block diagram which shows the 3rd example of a structure of the processor logical address and network logical address which concern on 2nd Embodiment. The figure which shows an example of the calculation which estimates the bit number of the address required in order to access the data memorize | stored in many apparatuses connected to a network.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, substantially the same or substantially the same functions and components are denoted by the same reference numerals and will be described as necessary.

(First embodiment)
A memory management device 1 and an information processing device 100 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating an example of a configuration of a memory management device and an information processing device according to this embodiment.

  The information processing apparatus 100 includes a memory management device 1, a hybrid main memory 2, and processors 3a, 3b, and 3c.

  The processors 3a, 3b, and 3c are, for example, MPU (Micro Processor Unit) or GPU (Graphic Processor Unit). Each of the processors 3a, 3b, and 3c includes primary cache memories 4a, 4b, and 4c, and secondary cache memories 5a, 5b, and 5c. The processors 3a, 3b, and 3c execute processes 6a, 6b, and 6c, respectively, and process various data. The processors 3a, 3b, and 3c specify data by virtual addresses when executing the processes 6a, 6b, and 6c.

  The processors 3a, 3b, and 3c generate a write request when writing data (data to be written) to the hybrid main memory 2. The processors 3a, 3b, and 3c generate a read request when reading data (read target data) from the hybrid main memory 2.

  Each of the processors 3a, 3b, and 3c includes a page table (not shown) that converts a virtual address into a physical address of MPU or GPU (logical address for the hybrid main memory 2). When writing data to the primary cache memories 4a, 4b, 4c, the secondary cache memories 5a, 5b, 5c, or the hybrid main memory 2, the processors 3a, 3b, 3c use the page table as a virtual address. Convert and specify the data to be written by logical address. Similarly, when reading data from the primary cache memories 4a, 4b, 4c, the secondary cache memories 5a, 5b, 5c, or the hybrid main memory 2, the processors 3a, 3b, 3c use the page table to set virtual addresses. The data is converted into a logical address, and the data to be read is designated by the logical address.

  Hereinafter, writing to and reading from the primary cache memories 4a, 4b, 4c, the secondary cache memories 5a, 5b, 5c, or the hybrid main memory 2 are collectively referred to as “access”.

  The memory management device 1 manages access (write, read) to the hybrid main memory 2 of the processors 3a, 3b, 3c. The memory management device 1 includes a processing unit 15, a work memory 16, and an information storage unit 17. The memory management device 1 stores memory usage information 11, memory specific information 12, address conversion information 13, and a coloring table 14 described later in the information storage unit 17. The coloring table 14 stored in the information storage unit 17 of the memory management device 1 may be a part of the coloring table 14 stored in the nonvolatile semiconductor memories 9 and 10. For example, data of the frequently used coloring table 14 among the coloring tables 14 stored in the nonvolatile semiconductor memories 9 and 10 may be stored in the information storage unit 17 of the memory management device 1. The memory management device 1 refers to the coloring table 14 and manages access to the hybrid main memory 2 by the processors 3a, 3b, and 3c. Details will be described later.

  The hybrid main memory 2 includes a first memory, a second memory, and a third memory. The first memory has a higher accessible upper limit than the second memory. The second memory has a higher accessible upper limit than the third memory. Here, it should be noted that the upper limit number of accessible times is an expected value that is statistically expected, and does not always mean that this relationship is guaranteed.

  In the present embodiment, it is assumed that the first memory is a volatile semiconductor memory 8. As the volatile semiconductor memory 8, for example, a memory used as a main memory in a general computer, such as a DRAM (Dynamic Random Access Memory), FPM-DRAM, EDO-DRAM, or SDRAM is used. In addition, if random access is possible at high speeds such as DRAM, and there is no practical limit to the upper limit of accessible times, non-volatile random access memories such as MRAM (Magnetoresistive Random Access Memory) and FeRAM (Ferroelectric Random Access Memory) May be adopted.

  Assume that the second memory is a nonvolatile semiconductor memory 9. As the nonvolatile semiconductor memory 9, for example, an SLC (Single Level Cell) type NAND flash memory is used. SLC is faster in reading and writing and more reliable than MLC (Multi Level Cell). However, SLC has a higher bit cost than MLC and is not suitable for increasing the capacity.

  Assume that the third memory is a nonvolatile semiconductor memory 10. As the nonvolatile semiconductor memory 10, for example, an MLC type NAND flash memory is used. MLC is slower in reading and writing and less reliable than SLC. However, the MLC has a lower bit cost than the SLC and is suitable for increasing the capacity.

  In the present embodiment, the nonvolatile semiconductor memory 9 is an SLC type NAND flash memory and the nonvolatile semiconductor memory 10 is an MLC type NAND flash memory. For example, the nonvolatile semiconductor memory 9 is 2 bits / bit. It may be a Cell MLC type NAND flash memory, and the nonvolatile semiconductor memory 10 may be a 3 bit / Cell MLC type NAND flash memory.

  Reliability means the degree of difficulty (durability) of data loss when reading data from a storage device. The durability of SLC is higher than that of MLC. Here, high durability means that the accessible upper limit number is large, and low durability means that the accessible upper limit number is small.

  The SLC can store 1-bit information in one memory cell. On the other hand, the MLC can store information of 2 bits or more in one memory cell. That is, the hybrid main memory 2 according to this embodiment has high durability in the order of the volatile memory 8, the second, the non-volatile semiconductor memory 9, and the third, the non-volatile semiconductor memory 10.

  Compared with the volatile semiconductor memory 8, the nonvolatile semiconductor memories 9, 10 such as NAND flash memory can be inexpensive and have a large capacity. As the nonvolatile semiconductor memories 9 and 10, other types of flash memory such as NOR flash memory, PRAM (Phase change memory), and ReRAM (Resistive Random access memory) are used instead of the NAND flash memory. You can also.

  Note that MLC may be employed as the third memory, and MLC capable of using a pseudo SLC mode in which data writing is performed using only the lower page of the MLC may be employed as the second memory. In this case, the second memory and the third memory can be configured by only a common chip, which is advantageous in terms of manufacturing cost.

  When the case where the nonvolatile semiconductor memories 9 and 10 are used as the main memory and the case where the nonvolatile semiconductor memories 9 and 10 are used as the secondary storage device are compared, the nonvolatile semiconductor memories 9 and 10 are used as the main memory. In this case, the access frequency to the nonvolatile semiconductor memories 9 and 10 is increased. In the present embodiment, an information processing apparatus including a hybrid main memory 2 in which a volatile semiconductor memory 8, an SLC nonvolatile semiconductor memory 9, and an MLC nonvolatile semiconductor memory 10 are combined to form a main memory is realized. Yes. The hybrid main memory 2 is a heterogeneous mixed type main storage device, and the data management is managed by the memory management device 1.

  Memory usage information 11, memory specific information 12, address conversion information 13, and a coloring table 14 are stored in predetermined areas of the nonvolatile semiconductor memories 9 and 10.

  The memory usage information 11 includes the number of times of writing and reading of each page area of the nonvolatile semiconductor memories 9 and 10, the number of times of erasing of each block area, and the size of the area in use.

  The memory specific information 12 includes the memory size of the volatile semiconductor memory 8, the memory sizes of the nonvolatile semiconductors 9 and 10, the page size and block size of the nonvolatile semiconductor memories 9 and 10, and the upper limit number of times that each area can be accessed ( The upper limit number of times of writing, the upper limit number of times of reading, and the upper limit number of times of erasable). Here, the page size is a unit of data size for writing and reading in the nonvolatile semiconductor memories 9 and 10. The block size is a unit of data erase size of the nonvolatile semiconductor memories 9 and 10. In the nonvolatile semiconductor memories 9 and 10, the block size is larger than the page size.

  The address conversion information 13 is information for converting a logical address given from the processors 3a, 3b, and 3c into a physical address corresponding to the logical address. Details of the address translation information 13 will be described later.

  The coloring table 14 is a table that holds coloring information for each data. The coloring information includes static color information and dynamic color information. Details will be described later.

  Next, the memory management device and the operating system according to the present embodiment will be further described with reference to FIG. FIG. 2 is a block diagram illustrating an example of the configuration of the memory management device 1 and the information processing device 100 according to the present embodiment. In FIG. 2, the processor 3b of the processors 3a, 3b, and 3c of FIG. 1 will be described as a representative, but the same applies to the other processors 3a and 3c.

  The operating system 27 is executed by the processor 3b. The operating system 27 is executed by the processor 3 b and has the authority to access the coloring table 14 stored in the information storage unit 17.

  The processing unit 15 of the memory management device 1 includes an address management unit 18, a read management unit 19, a write management unit 20, a coloring information management unit 21, a memory usage information management unit 22, and a relocation unit 23. Further, the coloring information management unit 21 includes an access frequency calculation unit 24 and a dynamic color information management unit 25.

  The processing unit 15 executes various processes using the work memory 16 based on the information stored in the information storage unit 17.

  The work memory 16 is used as a buffer, for example, and is used as a work area for various data conversions.

  The functional block provided in the processing unit 15 can be realized as one of hardware and software (for example, the operating system 27, firmware, or the like), or a combination of both. Whether these functional blocks are realized as hardware or software depends on a specific embodiment or design constraints imposed on the entire information processing apparatus 100. Those skilled in the art can implement these functions in various ways for each specific embodiment, and determining such implementation is within the scope of the present invention. The same applies to functional blocks used in the following description.

  The address management unit 18 assigns a physical address to the logical address and stores it in the address conversion information 13. As a result, the processing unit 15 can obtain the physical address corresponding to the logical address by referring to the address conversion information 13.

  When the processors 3a, 3b, and 3c generate read requests, the read management unit 19 manages the read processing of the read target data with respect to the hybrid main memory 2.

  The write management unit 20 manages the process of writing the write target data to the hybrid main memory 2 when the processors 3a, 3b, 3c generate a write request.

  The coloring information management unit 21 manages the coloring table 14.

  The memory usage information management unit 22 manages the memory usage information 11 of the hybrid main memory 2.

  The relocation unit 23 re-synchronizes data arranged at a physical address corresponding to an arbitrary logical address based on the coloring information included in the coloring table 14 asynchronously with the operation of the processors 3a, 3b, and 3c. Perform placement. For example, based on dynamic color information described later, the rearrangement unit 23 periodically re-sends data with high read frequency and high write frequency among the data included in the non-volatile semiconductor memory 10 to the non-volatile semiconductor memory 9. Deploy. Further, the rearrangement unit 23 periodically re-sends data with low read frequency and write frequency among the data included in the nonvolatile semiconductor memory 9 to the nonvolatile semiconductor memory 10 based on the dynamic color information. Deploy. Similarly, the rearrangement unit 23 can rearrange data between the volatile semiconductor memory 8 and the nonvolatile semiconductor memories 9 and 10. Write processing by the write management unit 20 to be described later performs rearrangement by performing a write destination memory area determination process and a write destination block area determination process each time data is updated. In contrast, the rearrangement unit 23 periodically rearranges data. When the rearrangement unit 23 rearranges data, the write management unit 20 and the read management unit 19 do not operate until the rearrangement is completed. The trigger for starting the operation of the rearrangement unit 23 may be a cycle set by the developer or a cycle settable by the user interface. In addition, the rearrangement unit 23 may operate when the information processing apparatus 100 enters a dormant state.

  The access frequency calculation unit 24 calculates data access frequency information (dynamic write frequency DW_color, dynamic read frequency DR_color) based on the coloring information included in the coloring table 14.

  The dynamic color information management unit 25 manages the dynamic color information included in the coloring table 14.

  Next, the hybrid main memory according to the present embodiment will be described with reference to FIG. FIG. 3 is a diagram showing an example of a memory map of the hybrid main memory 2 according to the present embodiment.

  The hybrid main memory 2 includes a volatile semiconductor memory 8 (DRAM area), a nonvolatile semiconductor memory 9 (SLC area), and a nonvolatile semiconductor memory 10 (2 bit / Cell area, 3 bit / Cell area, 4 bit / Cell area), Is provided. The 2bit / Cell area, the 3bit / Cell area, and the 4bit / Cell area constitute an MLC area. The DRAM area, SLC area, 2bit / Cell area, 3bit / Cell area, and 4bit / Cell area are collectively referred to as a memory area.

  The volatile semiconductor memory 8 is composed of, for example, a 128 MByte DRAM area.

  The nonvolatile semiconductor memory 9 includes, for example, a 2 GByte B area, a 128 MByte B redundant block area, a 2 GByte C area, and a 128 MByte C redundant block area. Each memory area of the nonvolatile semiconductor memory 9 is an SLC type NAND flash memory.

  The non-volatile semiconductor memory 10 includes, for example, a 2 Gbit / Cell area composed of a 4 GByte A area and a 128 MByte A redundant block area, a 3 Gbit / Cell composed of a 4 GByte D area and a 128 MByte D redundant block area, It is composed of a 4 GByte E area and a 4 Mbit / Cell area composed of a 128 MByte E redundant block area. Each memory area of the nonvolatile semiconductor memory 10 is an MLC type NAND flash memory. As shown in FIG. 3, a physical address is assigned to the memory area.

  When the hybrid main memory 2 has the above configuration, the memory specific information 12 includes 1) the memory size of the volatile semiconductor memory 8 (DRAM area) in the memory space of the hybrid main memory 2, and 2) the hybrid main memory 2 The memory size of the nonvolatile semiconductor memories 9 and 10 in the memory space, 3) the block size and page size of the NAND flash memory constituting the memory space of the hybrid main memory 2, and 4) the SLC area in the nonvolatile semiconductor memory 9 ( Memory space information allocated as a binary area (including the maximum number of erasables, the maximum number of readable data, and the maximum number of writable data) 5) Memory space information allocated to the 2bit / Cell area (the maximum number of erasable data, reading) 6) Memory space information allocated to the 3bit / Cell area (can be deleted) Comprising upper limit number, readable upper limit number of times, including writable upper limit number), 7) the memory space information allocated to 4bit / Cell region (erasable upper limit number of times, including readable upper limit number of times).

  Next, the address conversion information (address conversion table) 13 according to the present embodiment will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of the address translation information 13 according to the present embodiment.

  In the address conversion information 13, a logical address, a physical address of the volatile semiconductor memory 8, a physical address of the nonvolatile semiconductor memories 9 and 10, and a valid / invalid flag are managed in a table format.

  Each entry of the address translation information 13 includes a logical address, at least one of a physical address of the volatile semiconductor memory 8 and a physical address of the nonvolatile semiconductor memories 9 and 10 corresponding to the logical address, a valid / invalid flag. Is registered.

  The valid / invalid flag is information indicating whether each entry is valid. The valid / invalid flag indicates valid when 1 and invalid when 0. The initial value of the valid / invalid flag of the entry is 0. An entry whose valid / invalid flag is 0 is an entry in which a logical address is not mapped, or an entry in which a logical address is mapped but deleted. A logical address is mapped to an entry whose valid / invalid flag is 1, and a physical address corresponding to the logical address exists in at least one of the volatile semiconductor memory 8 and the nonvolatile semiconductor memories 9 and 10. .

  In the example of the address translation information 13 shown in FIG. 4, the logical address, the physical address of the volatile semiconductor memory 8, and the physical address of the nonvolatile semiconductor memories 9 and 10 are managed by one entry of the address translation information 13. For example, in the address conversion information 13, the logical address and the physical address of the nonvolatile semiconductor memory 8 may be managed, and the logical address and the physical address of the volatile semiconductor memories 9 and 10 may be managed by another tag RAM. In this case, when converting from a logical address to a physical address, the tag RAM is first referred to, and the address conversion information 13 is referred to when the tag RAM does not have a physical address corresponding to the logical address.

  Next, the coloring table 14 according to the present embodiment will be described with reference to FIG. FIG. 5 is a diagram illustrating an example of the coloring table 14 according to the present embodiment.

  In the present embodiment, coloring information is assigned to each data. The data size unit of the data to which the coloring information is added is, for example, the minimum unit for reading and writing. For example, the minimum unit for reading and writing is the page size of the NAND flash memory. The coloring table 14 associates coloring information for each data, and stores the coloring information for each entry. Each entry in the coloring table 14 is indexed. An index is a value generated based on a logical address. The read management unit 19, write management unit 20, coloring information management unit 21, relocation unit 23, etc. of the memory management device 1 are managed by an index corresponding to the logical address when given a logical address designating data. The data coloring information is obtained by referring to the existing entry.

  The coloring information includes static color information and dynamic color information. The static color information is information generated based on the characteristics of the data to which coloring information is added, and is information that serves as a hint for determining the arrangement (writing) area of the data on the mixed main memory 2. . The dynamic color information is information including at least one of the number and frequency of data reading and writing.

  Next, static color information will be described with reference to FIG. FIG. 6 is a diagram for explaining an example of static color information according to the present embodiment.

  The static color information includes at least one information of “importance”, “reading frequency, writing frequency”, and “data life” of the data. The read frequency described in FIG. 6 corresponds to a static read frequency, which will be described later, and the write frequency corresponds to the static write frequency.

  The “importance” is a value set by estimating the importance of the data based on the type of data.

  The “reading frequency and writing frequency” are values set by estimating the frequency of reading or writing the data based on the type of data.

  The “data lifetime” is a value set by estimating the period (data lifetime) in which the data is used without being erased based on the type of data.

  The “importance”, “read frequency, write frequency (read / write frequency)”, and “data lifetime” are estimated based on, for example, the characteristics of the file held in the file system or the characteristics of the area primarily used in the program. The

  The characteristic of the file held in the file system is a characteristic determined by the data attribute added to the file of the file data including the data to which the coloring information is added. The data attributes added to the file include file header information, file name, file position, file management data (information held in inodd), and the like. For example, if the file is located in the trash of the file system, the characteristics of the data contained in the file are less important, the frequency of reading, the frequency of writing, It can be predicted that the lifetime is short. Based on this characteristic, it is presumed that the coloring information of the data has a low writing frequency, a low reading frequency, and a short data life.

  The characteristics of the area temporarily used in the program include the characteristics determined based on the data type at the time of program execution of the program that handles the data to which coloring information is assigned, and the data type at the time of program file generation. And characteristics determined based on this.

  The data type at the time of program execution is, for example, a data type classified based on whether the data is mapped to a stack area, a heap area, or a text area at the time of program execution. For example, the characteristics of data mapped to the stack area and the heap area are predicted to be high in write frequency, high in read frequency, high in importance, and short in data life. Based on this characteristic, it is presumed that the static coloring information of the data has a high writing frequency, a high reading frequency, a high importance level, and a short data life. For example, since the data mapped to the text area is read-only data, the frequency of writing is low, the frequency of reading is high, the importance is high, and the life of the data is predicted to be long. Based on this characteristic, it is presumed that the static coloring information of the data has high writing frequency, high read frequency, high importance, and long data life.

  Data type prediction when generating a program file means estimating the importance, read / write frequency, and data life of data handled by the program at the time of program generation.

  The static color information may be set directly by the user through the user interface.

  Next, an example of a data writing process based on the coloring information will be described with reference to FIG. FIG. 7 is a flowchart illustrating an example of data arrangement processing.

  As described above, in the present embodiment, the hybrid main memory 2 includes the volatile semiconductor memory 8 and the nonvolatile semiconductor memories 9 and 10. When data is arranged in the hybrid main memory 2, one of the volatile semiconductor memory 8 and the non-volatile semiconductor memories 9 and 10 is determined as the arrangement destination based on the coloring information.

  First, when a write request for data (write target data) occurs, the write management unit 20 refers to the coloring information given to the write target data (step S1).

  Next, the write management unit 20 refers to the “data life” of the coloring information and determines the data life of the write target data (step S2).

When it is determined that the data life of the write target data is short (step S3), the write management unit 20 selects the volatile semiconductor memory 8 as a memory area in which the write target data is arranged (step S4) The memory area in which the target data is arranged is determined as the volatile semiconductor memory 8 (step S12).
When it is determined that the data life of the write target data is long (step S3), the write management unit 20 refers to the “importance” of the coloring information of the write target data to determine the importance of the write target data. (Step S5).

  When it is determined that the importance of the write target data is high (step S6), the write management unit 20 uses the nonvolatile main memory 9 having high durability (reliability) as a memory area in which the write target data is arranged. Select (step S7). Further, the write management unit 20 determines whether or not the write target data is cached in the volatile semiconductor memory 8 based on the coloring information of the write target data (cache method based on the coloring information) (step S8). The memory area in which the write target data is arranged is determined as the nonvolatile semiconductor memory 9 (step S12).

  When it is determined that the importance of the write target data is low (step S6), the write management unit 20 selects the nonvolatile semiconductor memory 10 having low durability as the memory area in which the write target data is arranged (step S6). S9). Further, the write management unit 20 determines the read frequency and write frequency of the write target data based on the coloring information (dynamic color information, static color information) of the write target data (step S10).

  When it is determined that the read frequency and the write frequency of the write target data are high (step S11), the write management unit 20 selects the nonvolatile semiconductor memory 9 as a memory area in which the write target data is arranged (step S7). ). Further, the write management unit 20 determines whether or not the write target data is cached in the volatile semiconductor memory 8 based on the coloring information of the write target data (cache method based on the coloring information) (step S8). The memory area in which the write target data is arranged is determined as the nonvolatile semiconductor memory 9 (step S12).

  When it is determined that the read frequency and the write frequency of the write target data are low (step S11), the write management unit 20 caches the write target data in the nonvolatile main memory 8 based on the coloring information of the write target data. Whether or not to perform (a cache method based on coloring information) is determined (step S8), and a memory area in which data to be written is arranged is determined as the nonvolatile semiconductor memory 10 (step S12).

  Next, a configuration example of the coloring table 14 according to the present embodiment will be described with reference to FIG. FIG. 8 is a diagram showing an example of the configuration of the coloring table 14 according to the present embodiment. In the coloring table 14 shown in FIG. 8, the case where the reading frequency, the writing frequency, and the data lifetime are used as the coloring information among the coloring information shown in FIGS. 5 and 6 will be described.

  As coloring information, any one of “importance”, “reading frequency, writing frequency”, and “data lifetime” may be used, or any two may be used in combination. , Or all may be used in combination. Furthermore, other coloring information not shown in FIG. 6 can be separately defined and used.

  The coloring table 14 is a table that associates coloring information for each data and holds them in units of entries. The data size of the data associated with the coloring information by the coloring table 14 is, for example, the minimum data size to be read and written. For example, the minimum data size to be read and written is the page size of the NAND flash memory. In the following description, it is assumed that the data size of the data associated with the coloring information by the coloring table 14 is the page size, but the present invention is not limited to this.

  Each entry in the coloring table 14 is indexed.

  The coloring information held in the coloring table 14 includes static color information and dynamic color information.

  An index is a value generated based on a logical address. The read management unit 19, write management unit 20, coloring information management unit 21, relocation unit 23, etc. of the memory management device 1 are managed by an index corresponding to the logical address when given a logical address designating data. The data coloring information is acquired by referring to the entry.

  The static color information includes a value SW_color indicating a static writing frequency, SR_color indicating a static reading frequency, a data life SL_color, and a data generation time ST_color.

  Here, the static writing frequency SW_color is a value set by estimating the frequency of writing the data based on the type of data. The static reading frequency SR_color is a value set by estimating the frequency of reading the data based on the type of data. For example, the static writing frequency SW_color is set to a higher value for data estimated to have a higher writing frequency. For example, the static reading frequency SR_color is set to a higher value for data estimated to have a higher reading frequency.

  The data life SL_color is a value set by estimating a period (data life) in which the data is used as data without being erased based on the type of data.

  The static color information is a value that is statically predetermined by a program (process) that generates data. Further, the operating system 27 executed by the information processing apparatus 100 may predict the static color information based on the file extension or file header of the data.

  The dynamic color information includes a data write count DWC_color and a data read count DRC_color. Here, the data write count DWC_color is the number of times the data is written to the hybrid main memory 2. The data read count DRC_color is the number of times the data is read from the hybrid main memory 2. The dynamic color information management unit 25 manages, for each data, the number of times that the data has been written to the hybrid main memory 2 based on the number of times of data writing DWC_color. The dynamic color information management unit 25 manages, for each data, the number of times that the data has been read from the hybrid main memory 2 based on the data read number DRC_color. As described above, the hybrid main memory 2 is used as a main memory. Therefore, data processed by the processors 3 a, 3 b, and 3 c is written into the mixed main memory 2 and read from the mixed main memory 2. The dynamic color information management unit 25 increments the data write count DWC_color each time data is written. The dynamic color information management unit 25 increments the data read count DRC_color every time data is read.

  As will be described later, the access frequency calculation unit 24 calculates the dynamic write frequency DW_color from the data write count DWC_color. The access frequency calculation unit 24 calculates the dynamic read frequency DR_color from the data read count DRC_color.

  The dynamic writing frequency DW_color is a value indicating the frequency at which the data is written to the hybrid main memory 2. The dynamic read frequency DR_color is a value indicating the frequency at which the data is read from the hybrid main memory 2. A method for calculating the dynamic writing frequency DW_color and the dynamic reading frequency DR_color will be described later.

  As will be described later, when a write request or a read request is generated from the processors 3a, 3b, and 3c to the hybrid main memory 2, the memory management device 1 refers to the coloring information to determine the write area, the read method, and the like. decide.

  Next, static color information according to the present embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing a first example of setting static color information (static writing frequency SW_color, static reading frequency SR_color, data life SL_color) for various data. FIG. 10 is a diagram illustrating a second example of setting static color information (static writing frequency SW_color, static reading frequency SR_color, data lifetime SL_color) for various data.

  The text area of the kernel is usually read frequently and written frequently. The operating system 27 sets 5 for the static reading frequency SR_color and 1 for the static writing frequency SW_color of the text area in which it operates. Further, the operating system 27 predicts that the data life SL_color of the kernel text area is long (LONG).

  On the other hand, in the kernel data area, both reading frequency and writing frequency are usually high. Therefore, the operating system 27 sets the static read frequency SR_color to 5 and the static write frequency SW_color to 5 for the kernel data area.

  Since the data area dynamically secured in the kernel is deleted when data is no longer needed, the data life SL_color is short (SHORT).

  The text area of the user program is usually read less frequently than the kernel that is reentrantly called from all processes. However, when the process is active, the frequency of reading is high as in the kernel. For this reason, the static writing frequency SW_color is set to 1 and the static reading frequency SR_color is set to 4 in the text area of the user program. For the text area of the user program, the data life SL_color is generally a period until the program is uninstalled, and thus generally increases. Therefore, the data life SL_color is set to be long (LONG) for the text area of the user program.

  There are roughly two types of areas that are dynamically secured in the program. One is data (including the stack area) that is discarded when the execution of the program ends. These data have a short data life SL_color, and are frequently read and written. Therefore, the static read frequency SR_color is set to 4 and the static write frequency SW_color is set to 4 for the data to be discarded upon completion of the program execution. The area dynamically reserved for another program is an area generated by the program for a new file. Data generated by the program has a long data life SL_color, and the frequency of reading and writing depends on the type of file to be generated.

  For data handled as a file referenced by a process, the data life SL_color of the file is set to be long.

  For example, a case where a system file whose file extension is indicated by SYS, dll, DRV or the like is read will be described. Data having such an extension is a file that is read when the operating system 27 executes various processes. When the operating system 27 is installed on the hybrid main memory 2, the data having such an extension is hardly updated after being written once. A file having these extensions has a relatively high access frequency among files, but is expected to have a low access frequency compared to a text area of a program (kernel). Therefore, the operating system 27 sets the static writing frequency SW_color of data having these extensions to 1 and sets the static reading frequency SR_color to 3. This setting indicates that the frequency of writing predicted from data is extremely low and the frequency of reading predicted is high. In other words, data having these extensions can be rewritten several times when the operating system 27 is updated or another program is installed, and it is predicted that the data will be handled almost as read-only.

  Few users use programs that edit audio files. Therefore, for example, it is considered that the frequency of writing music data compressed by MP3 or the like is low. It is considered that the frequency of reading music data is higher than the frequency of writing. Therefore, the static writing frequency SW_color of music data compressed by MP3 or the like is set to 1, and the static reading frequency SW_color is set to 2.

  Few users use video editing programs. For this reason, for example, it is considered that the frequency of writing moving image data compressed by MPEG or the like is low. It is considered that the frequency of reading moving image data is higher than the frequency of writing. Therefore, the static writing frequency SW_color of moving image data compressed by MP3 or the like is set to 1 and the static reading frequency SW_color is set to 2.

  Many users use text data editing programs. For this reason, for example, the writing frequency and reading frequency of the text file are considered to be high. Accordingly, the static writing frequency SW_color of the text file is set to 3, and the static reading frequency SW_color is set to 3.

  Many users use web browsers. For this reason, it is considered that the browser cache file is read and written more frequently than media files such as music data and moving image data. Therefore, the static writing frequency SW_color of the browser cache file is set to 1, and the static reading frequency SW_color is set to 3.

  For example, the static writing frequency SW_color of a file arranged in a directory with low access frequency such as a trash box is set to 1, and the static reading frequency SW_color is set to 1.

  Photo data whose extension is represented by JPEG and movie data whose extension is represented by MOV are rarely written again once written. Such photo data and movie data are expected to be accessed less frequently from the program. Accordingly, the operating system 27 sets small values for the static writing frequency SW_color and the static reading frequency SR_color of the photo data and movie data.

  Next, the generation process of the coloring table 14 according to the present embodiment will be described with reference to FIG. FIG. 11 is a flowchart illustrating an example of the generation process of the coloring table 14. The coloring table 14 is generated at the initial startup of the system. The coloring table 14 is arranged in an arbitrary area on the nonvolatile semiconductor memories 9 and 10. The address where the coloring table 14 is arranged may be determined by the implementation of the memory management device 1.

  In step T1, the information processing apparatus 100 is turned on and activated.

  In step T2, the coloring information management unit 21 converts the base address of the coloring table 14 into a logical address, and generates an index for each data.

  In step T <b> 3, the coloring information management unit 21 sets the base address of the coloring table 14 in the information storage unit 17. The information storage unit 17 is configured by a register, for example. The base address of the coloring table 14 is set in a coloring table register, for example.

  Next, an entry generation process of the coloring table 14 according to the present embodiment will be described with reference to FIG. FIG. 12 is a flowchart illustrating an example of an entry generation process of the coloring table 14.

  The processors 3a, 3b, and 3c reserve areas in the logical address space used for executing the processes 6a, 6b, and 6c. At the stage of securing the area in the logical address space, 0 is set in the valid / invalid flag of the address translation information 13 of the secured logical address. The physical address is assigned to the logical address when the processes 6a, 6b, and 6c access (read and write) the logical address within the reserved logical address space. When the physical address is assigned to the logical address, the static color information for the data corresponding to the logical address is registered in the coloring table 14, and the valid / invalid flag of the address conversion information 13 of the logical address is set to 1. Is set.

First, the processes 6a, 6b, and 6c executed by the processors 3a, 3b, and 3c issue a request for securing an area in the logical address space for arranging new data (step U1). An unused area in the logical address space is managed by the operating system 27, and the logical address is determined by the operating system 27. (Step U2)
Next, when new data is generated by the processes 6a, 6b, and 6c, the operating system 27 generates static color information based on the type of the newly generated data and the like (step U3). Static color information is generated for each page size of the generated data. For example, if the data size of the generated data is larger than the page size, the data is divided into page sizes, and static color information is generated for each divided page size. In the following description, it is assumed that the data size of the write target data is the page size, but the present invention is not limited to this.

  Next, the operating system 27 refers to the coloring table 14 based on the base address set in the information storage unit 17 (step U4).

  Next, the operating system 27 registers the generated static color information in an entry of the coloring table 14 to which an index corresponding to the reserved logical address is attached (Step U5).

  The processes 6a, 6b, and 6c executed by the processors 3a, 3b, and 3c issue a read request or a write request to the secured logical address space after the logical address space is successfully secured by the operating system 27. . At this time, the address management unit 18 determines a physical address for the logical address where writing has occurred, and this processing will be described later.

  Through the above processing, when the processors 3a, 3b, and 3c execute the processes 6a, 6b, and 6c, new data is generated, and new data is generated when the new data is written to the hybrid main memory 2. Coloring information is generated for the data and registered in a new entry in the coloring table 14. As a result, new data can be written to the hybrid main memory 2.

  Next, the alignment of entries in the coloring table 14 will be described with reference to FIGS. FIG. 13 is a diagram illustrating a first example of the alignment of entries in the coloring table 14. FIG. 14 is a diagram illustrating a second example of the alignment of entries in the coloring table 14.

  The entry of the coloring table 14 corresponds to the minimum read / write size of data (for example, the page size of the NAND flash memory). However, when the processes 6a, 6b, and 6c map data to the logical address space, the data You are not obligated to map to the minimum read / write size. For this reason, a plurality of data may correspond to one entry of the coloring table 14.

  In such a case, as shown in FIG. 13, the operating system 27 represents data predicted to have the highest read frequency and write frequency among a plurality of data corresponding to one entry.

  Alternatively, as shown in FIG. 14, the operating system 27 sets the weighted average value of the static writing frequency SW_color and the static reading frequency SR_color of each data, with the size of the data occupying one entry as a weight.

  The static writing frequency SW_color and the static reading frequency SR_color shown by the coloring table 14 are embedded in the source code such as the operating system 27 by the program developer or predicted by the operating system 27. However, files and photo data may be used for purposes other than those intended by the program developer. In general, most data access such as photo data is read, and the content of photo data is rarely rewritten. However, when a program for processing photo data handles specific photo data, the photo data being processed may be frequently rewritten. In such a case, if the user can rewrite the static writing frequency SW_color and the static reading frequency SR_color of the coloring table 14, the specific file can be moved to an area where the rewriting frequency can be increased at a higher speed. It becomes possible.

  In order to realize such an operation, it is preferable to design the file system of the operating system 27 so that the coloring information of each data is rewritten on the software of the operating system 27. For example, the information processing apparatus 100 is designed so that the attributes corresponding to the coloring table 14 can be viewed on the GUI screen when the file properties are opened by a general browser, and the initial data is displayed on the GUI by the user. It is preferable to design the operating system 27 so that it can be changed.

  Next, a method for calculating the dynamic writing frequency DW_color and the dynamic reading frequency DR_color based on the dynamic color information and the static color information will be described with reference to FIG. FIG. 15 is a diagram illustrating an example of a method for calculating the dynamic writing frequency DW_color and the dynamic reading frequency DR_color based on the dynamic color information and the static color information. In FIG. 15, the horizontal axis represents time, and the vertical axis represents the number of accesses (reading number DWC_color or writing number DRC_color).

  When new data is generated at the data generation time, coloring information (including the data generation time) is generated for the newly generated data and registered in a new entry in the coloring table 14. The data is written into the hybrid main memory 12. Since access (reading and writing) to this data occurs after the data generation time, the access count (the write count DWC_color and the read count DRC_color) increases with the passage of time. The increase in the number of accesses is performed by the dynamic color information management unit 25. The access frequency calculation unit 24 of the memory management device 1 calculates the dynamic write frequency DW_color and the dynamic read frequency DR_color from the access count.

  The data write count DWC_color and data read count DRC_color at the current time can be obtained by referring to the coloring table 14. The dynamic writing frequency DW_color at the current time is obtained from the time average (average change rate α) of the number of writings DWC_color from the data generation time ST_color to the current time. Further, the dynamic read frequency DR_color at the current time is obtained from the time average (average change rate α) of the read count DRC_color from the data generation time ST_color to the current time. As a result, the dynamic writing frequency DW_color and the dynamic reading frequency DR_color of the data are calculated from the dynamic color information (the writing count DWC_color and the reading count DRC_color).

  Next, based on the calculated dynamic writing frequency DW_color and the dynamic reading frequency DR_color, it is determined whether the frequency of access to the data is high or low. The determination of whether the access frequency is high or low is made based on, for example, the memory specific information 11 of the hybrid main memory 2 in which the data is written, the calculated dynamic write frequency DW_color, and the dynamic read frequency DR_color.

  In FIG. 15, first, “accessible upper limit number × weight 1 / data life” is set as the slope of equation A, and “accessible upper limit number × weight 2 / data life” is set as the slope of equation B. Here, weight 1> weight 2. The weights 1 and 2 can be arbitrarily set according to the hybrid main memory 2 to which the data for calculating the dynamic writing frequency DW_color and the dynamic reading frequency DR_color is written.

  When the average rate of change α <the slope of Expression A holds, it is determined that the dynamic access frequency of this data is high.

  If the slope of formula B <average change rate α ≦ the slope of formula A holds, the dynamic access frequency of this data is determined to be medium.

  If the average rate of change α ≦ the slope of formula B holds, it is determined that the dynamic access frequency of this data is low.

  Next, a process of reading data from the hybrid main memory 2 will be described with reference to FIG. FIG. 16 is a flowchart illustrating an example of data read processing.

  First, the processes 6a, 6b, and 6c executed by the processors 3a, 3b, and 3c generate a data (read target data) read request (step W1).

  Next, a virtual address designating read target data is converted into a logical address by a page table (not shown) provided in the processors 3a, 3b, 3c (step W2).

  Next, the read management unit 19 refers to the valid / invalid flag of the entry of the logical address corresponding to the read target data of the address conversion information 13 (step W3).

    When the valid / invalid flag of the address conversion information 13 is 0 (step W3a), data is undefined because writing to the logical address has never occurred. In this case, the read management unit 19 behaves as if 0 data corresponding to the read request size has been read (step W8), and the process proceeds to step W10.

  When the valid / invalid flag of the address translation information 13 is 1 (step W3a), data writing to the logical address has occurred at least once. In this case, the read management unit 19 refers to the address conversion information 13 and determines whether data corresponding to the logical address is stored in the volatile semiconductor memory 8 (step W4).

  When it is determined that the data corresponding to the logical address is stored in the volatile semiconductor memory 8 (step W4a), the read management unit 19 reads from the volatile semiconductor memory 8, and thus the process proceeds to step W10. .

  When it is determined that the data corresponding to the logical address is not stored in the volatile semiconductor memory 8 (Step W4a), the read management unit 19 refers to the coloring table 14 and reads from the nonvolatile semiconductor memories 9 and 10. The read method of the read target data is determined (step W5). The reading method determination process will be described later.

  Next, the read management unit 19 refers to the memory specific information 11 and the memory usage information 12 of the nonvolatile semiconductor memories 9 and 10 in which the read target data is stored, and needs to move (rewrite) the read target data. Judgment is made (step W6).

  If it is determined that the data to be read does not need to be moved (step W6a), the read management unit 19 proceeds to step W9.

  When it is determined that the read target data needs to be moved (step W6a), the read management unit 19 moves the read target data to another area of the nonvolatile semiconductor memories 9 and 10 (step W7). Thereafter, the process proceeds to step W9.

  In step W9, the memory usage information management unit 22 increments the number of times the memory usage information 11 is read when reading from the nonvolatile memory area. In step W10, the dynamic color information management unit 25 increments the data read count DRC_color of the coloring table 14 when the data is read. In step W11, the read management unit 19 reads data based on the physical address obtained from the logical address and the address conversion information 13.

  Next, with reference to FIG. 17, the data read method determination process will be described. FIG. 17 is a flowchart illustrating an example of a data read method determination process. The reading method determination process is a process for determining whether or not to use the memory area of the volatile semiconductor memory 8 as a cache when data is read from the memory area of the nonvolatile semiconductor memories 9 and 10. This process corresponds to Step W5 in FIG.

  As described above, the hybrid main memory 2 includes the volatile semiconductor memory 8 and the nonvolatile semiconductor memories 9 and 10. In the present embodiment, a part of the volatile semiconductor memory 8 can be used as a cache memory. When data is read from the nonvolatile semiconductor memories 9 and 10 of the hybrid main memory 2, data that is read frequently is cached in the volatile semiconductor memory 8 and then read. On the other hand, data that is read infrequently is not directly cached in the volatile semiconductor memory 8 but directly read from the nonvolatile semiconductor memories 9 and 10.

  First, the read management unit 19 refers to the static reading frequency SR_color of the data to be read by referring to the coloring table 14 (step V1). When the static read frequency SR_color is large (for example, SR_color = 5) (step V1a), the read target data is cached from the volatile semiconductor memories 9 and 10 to the volatile main memory 8 (DRAM area). Move on to step V4.

  When the static read frequency SR_color of the read target data is small (for example, SR_color <= 4) (step V1a), the read management unit 19 refers to the address conversion information 13 to write the read target data. The access frequency calculation unit 24 calculates the dynamic read frequency DR_color of the read target data (step V3).

  When “SR_color ≧ 3 or DR_color is high” holds for the static read frequency SR_color and the dynamic read frequency DR_color of the read target data (step V3a), the read management unit 19 sets the volatile semiconductor memory 8 ( It is confirmed whether or not there is an empty area in which data to be read is written in (DRAM area) (step V4). When there is an empty area in the volatile semiconductor memory 8 (step V4a), the read management unit 19 caches the read target data from the volatile semiconductor memories 9 and 10 to the volatile semiconductor memory 8 (DRAM area) ( Step V5). When there is no free area in the volatile memory 8 (step V4a), the read management unit 19 writes back the data stored in the volatile semiconductor memory 8 to the nonvolatile semiconductor memories 9 and 10, and the volatile memory By erasing the data stored in the semiconductor memory 8, a free area is secured (step V6). After the write-back process, the read management unit 19 confirms again the free area of the volatile semiconductor memory 8 (Step V7). If there is an empty area in the volatile semiconductor memory 8 (step V7a), the process proceeds to step V5, and if not (step V7a), the process proceeds to step V8.

  In the case where “SR_color ≧ 3 or DR_color is high” does not hold for the static read frequency SR_color and the dynamic read frequency DR_color of the read target data (Step V3a), the read management unit 19 sets the read target data to The data is read directly from the nonvolatile semiconductor memories 9 and 10 without being cached in the volatile semiconductor memory 8 (step V8).

  As described above, the reading method is determined by referring to the static reading frequency SR_color and the dynamic reading frequency DR_color.

  In FIG. 17, the data lifetime SL_color is not determined. The reason for this will be described. As will be described later, data having a short data life SL_color is arranged in the volatile semiconductor memory 8 at the time of writing. Therefore, data indicating that the valid / invalid flag is 1 and the data life SL_color is short is stored in the volatile semiconductor memory 8. As a result, in FIG. 17, the determination based on the data life SL_color becomes unnecessary.

  Next, a method for reading out data shown in FIGS. 9 and 10 will be described in detail. The data shown in FIG. 9 and FIG. 10 is determined as follows by following the flowchart of the data read method determination process described in FIG.

  First, it is presumed that the kernel text area in which the static read frequency SR_color is set to 5 and the static write frequency SW_color is set to 1 has a high read frequency and a low write frequency. Since the first data in the text area of the kernel is read when the operating system 27 performs various processes, the number of times of reading is increased, and the first data needs to be read at a higher speed.

  The memory management device 1 writes the first data read from the non-volatile semiconductor memories 9 and 10 to the secondary cache memory 5b or the primary cache memory 4b of the processor 3b, and in parallel, The read first data is also transferred to the memory area of the volatile semiconductor memory 8 in the memory 2.

  When the same first data is read again, from the secondary cache memory 5b or the primary cache memory 4b of the processor 3b, or from the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 when no cache hit occurs. The first data is read out. The first data stored in the memory area of the volatile semiconductor memory 8 on the hybrid main memory 2 is stored on the volatile semiconductor memory 8 until the power is turned off unless the memory area of the volatile semiconductor memory 8 is depleted. Retained.

  Next, the kernel data area in which the static read frequency SR_color is set to 5 and the static write frequency SW_color is set to 5 is newly generated and initialized every time the system (information processing apparatus 100) is started. It is an area. For this reason, it is presumed that the second data life SL_color in the kernel data area is short. The memory management device 1 first refers to the lifetime SL_color of the second data. Unless the memory area of the volatile semiconductor memory 8 is depleted, the second data exists on the volatile semiconductor memory 8 and is erased from the volatile semiconductor memory 8 when the power is turned off.

  Next, the user program area in which the static read frequency SR_color is set to 4 and the static write frequency SW_color is set to 1 has a lower read frequency than the kernel that is reentrantly called from all processes. The third data in the user program area is arranged in the memory area of the volatile semiconductor memory 8, but when the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 is filled with FULL, the third data is stored on the volatile semiconductor memory 8. To the memory area of the nonvolatile semiconductor memories 9 and 10. The order of the third data to be written back is determined based on the information in the coloring table 14. In the case of writing back, the third data is transferred from the volatile semiconductor memory 8 to the nonvolatile semiconductor memories 9 and 10 in ascending order of reading.

  Of the fourth data in the area dynamically reserved by the program, in which the static writing frequency SR_color is 4 and the static reading frequency SW_color is 4, the fourth data life SL_color is designated as short Similar to the kernel data area, data exists on the volatile semiconductor memory 8 and is erased from the volatile semiconductor memory 8 when the power is turned off unless the memory area of the volatile semiconductor memory 8 is depleted.

  On the other hand, the fourth data set with a long data life SL_color is arranged in the memory area of the volatile semiconductor memory 8, but the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 is filled with FULL. In this case, it becomes a write-back target from the volatile semiconductor memory 8 to the memory areas of the nonvolatile semiconductor memories 9 and 10.

  Next, data handled as a file referenced by the process will be described. In FIG. 10, the data life SL_color of data handled as a file referred to by the process is set to be long.

  The fifth data included in the files whose static write frequency SW_color is set to 1 and static read frequency SR_color is set to 3 has a very low write frequency and a high expected read frequency. 27. At this time, the memory management device 1 places the fifth data in the memory area of the volatile semiconductor memory 8, but if the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 is filled with FULL, the volatile semiconductor This is a write-back target from the memory 8 to the memory areas of the nonvolatile semiconductor memories 9 and 10.

  The sixth data included in the files with the static writing frequency SW_color set to 1 and the static reading frequency SR_color set to 2 has a very low static writing frequency SW_color and a low predicted static reading frequency SR_color. Is presumed by the operating system 27. As described above, when it is not determined that the static read frequency SR_color is high, the memory management device 1 directly accesses the nonvolatile semiconductor memories 9 and 10 without using the cache of the volatile semiconductor memory 8 at the time of reading.

  The seventh data included in the files with the static writing frequency SW_color set to 1 and the static reading frequency SR_color set to 1 has a very low static writing frequency SW_color and a very high predicted static reading frequency SR_color. Low is speculated by the operating system 27. As described above, when it is not determined that the static read frequency is high, the memory management device 1 directly accesses the nonvolatile semiconductor memories 9 and 10 without using the cache of the volatile semiconductor memory 8 at the time of reading.

  As described above, the reading method of the read target data is determined based on the coloring information of the read target data. As a result, it is possible to use a reading method that matches the characteristics of the data to be read (static reading frequency SR_color, static writing frequency SW_color, data life SL_color), and the data reading efficiency can be improved.

  Next, a data writing process to the hybrid main memory 2 will be described with reference to FIG. FIG. 18 is a flowchart illustrating an example of a data writing process.

  First, the processes 6a, 6b, and 6c executed by the processors 3a, 3b, and 3c generate data (write target data) write requests (step X1).

  Next, a virtual address designating data to be written is converted into a logical address by a page table (not shown) provided in the processors 3a, 3b, 3c (step X2).

  Next, the write management unit 20 refers to the coloring table 14 to determine a memory area to be written in the hybrid main memory 2 (step X3). Selection of the write target memory area will be described later.

  The write management unit 20 determines whether or not the write target memory selected in step X3 is the volatile semiconductor memory 8 (step X4). As a result of the determination, when the selected write target memory is the volatile semiconductor memory 8 (step X4a), the process of step X7 is executed, and when the write target memory is a nonvolatile memory (step X4a), the process of step X5 is performed. Executed.

  In step X <b> 5, the write management unit 20 refers to the memory usage information 11 and the coloring table 14 and determines a write target block area in the memory areas of the nonvolatile semiconductor memories 9 and 10. In step X6, the address management unit 18 updates the address conversion information 13 based on the physical address of the page in the write target block. When the nonvolatile semiconductor memories 9 and 10 are NAND flash memories, the same physical address is not overwritten, so that the physical address must be updated with writing.

  After the write destination physical address is determined, the write management unit 20 performs a data write process (step X7). Subsequently, the address management unit 18 sets the valid / invalid flag of the address translation information 13 to 1 (step X8). The dynamic color information management unit 25 increments the write count DWC_color of the coloring table 14 (step X9), and the memory use information management unit 22 increments the write count of the memory use information 11 (step X10).

  Next, with reference to FIG. 19, a process for determining a memory area into which data is to be written will be described. FIG. 19 is a flowchart illustrating an example of a data write destination area determination process.

  In step Y1, the write management unit 20 refers to the data life SL_color of the write target data.

  In step Y2, the writing management unit 20 determines whether the data life SL_color is longer or shorter than a predetermined value. If the data life SL_color is greater than or equal to the predetermined value, the process proceeds to step Y9.

  If the data life is shorter than the predetermined value, in step Y3, the write management unit 20 checks the free area of the DRAM area, and in step Y4, the write management unit 20 determines whether there is a free area in the DRAM area. To do.

  If there is an empty area in the DRAM area, in step Y5, the write management unit 20 writes the write target data in the DRAM area.

  If there is no free space in the DRAM area, in step Y6, the write management unit 20 executes a write-back process from the DRAM area to another nonvolatile semiconductor memory. In step Y7, the write management unit 20 confirms a free area in the DRAM area. In step Y8, the write management unit 20 determines whether there is a free area in the DRAM area.

  If there is an empty area in the DRAM area, the process proceeds to step Y5, and the write management unit 20 writes the write target data in the DRAM area.

  If there is no empty area in the DRAM area, the process proceeds to step Y9.

  In step Y9, the write management unit 20 refers to the static write frequency SW_color of the write target data managed in the coloring table 14.

  In step Y10, the writing management unit 20 determines whether 5 is set in the static writing frequency SW_color (whether the static writing frequency SW_color of the write target data is high).

  If 5 is set in the static writing frequency SW_color, the process proceeds to Y13, and the writing management unit 20 selects the B area as the writing destination of the writing target data.

  When a value other than 5 (a value less than 5) is set in the static writing frequency SW_color, in step Y11, the memory management device 1 uses the static reading frequency of the write target data managed in the coloring table 14. Refers to SR_color.

  In step Y12, the writing management unit 20 determines which value of 1 to 5 is set in the static reading frequency SR_color.

  When 5 is set to the static read frequency SR_color in step Y12, in step Y13, the write management unit 20 selects area B as the write destination of the write target data.

  If the static read frequency SR_color is set to 4 in step Y12, in step Y14, the write management unit 20 selects the area A as the write destination of the write target data.

  If the static read frequency SR_color is set to 3 in step Y12, the write management unit 20 calculates the dynamic data write frequency DW_color based on the data coloring information in step Y15. Next, in step Y16, the write management unit 20 refers to the static write frequency SW_color of the write target data managed in the coloring table 14.

  In step Y <b> 17, the writing management unit 20 determines whether or not “the static writing frequency SW_color is 3 or more or the data dynamic writing frequency DW_color is at a high level” is satisfied.

  If “SW_color is 3 or higher, or the data dynamic writing frequency DW_color is high” does not hold in step Y17, the process proceeds to step Y14, and the writing management unit 20 selects the A area. To do.

  If “SW_color is 3 or more or the data dynamic writing frequency DW_color is at a high level” holds in step Y17, the process proceeds to step Y18, and the writing management unit 20 selects the C area.

  If the static read frequency SR_color is set to 2 in step Y12, in step Y19, the write management unit 20 calculates the dynamic data write frequency DW_color based on the data coloring information.

  In step Y20, the write management unit 20 refers to the static write frequency SW_color of the write target data managed in the coloring table 14.

  In step Y21, the writing management unit 20 determines whether or not “SW_color is 3 or more or the calculated dynamic writing frequency DW_color is at a high level” is satisfied.

  If “SW_color is 3 or more or the calculated dynamic writing frequency DW_color is at a high level” holds in this step Y21, the process moves to step Y18, and the writing management unit 20 selects the C area. To do.

  If “SW_color is 3 or more or the calculated dynamic writing frequency DW_color is at a high level” does not hold in step Y21, the process proceeds to step Y22.

  In step Y22, the writing management unit 20 determines whether or not “SW_color is 2 or more or the calculated dynamic writing frequency DW_color is at a medium level” is satisfied.

  If “SW_color is 2 or more or the calculated dynamic writing frequency DW_color is at a medium level” holds in step Y22, the process proceeds to step Y23, and the writing management unit 20 selects the D area. To do.

  If “SW_color is 2 or more or the calculated dynamic writing frequency DW_color is at a medium level” does not hold in step Y22, the process moves to step Y24, and the writing management unit 20 selects the E area. To do.

  When the static read frequency SR_color is set to 1 in step Y12, in step Y25, the write management unit 20 calculates the dynamic data write frequency DW_color based on the data coloring information.

  In step Y <b> 26, the write management unit 20 refers to the static read frequency SW_color of the write target data managed in the coloring table 14. Thereafter, the process proceeds to step Y21.

  For example, the developer of the operating system 27 performs the settings shown in FIGS. 9 and 10 for the implementation of the data read method of the read management unit 19 and the data write method of the write management unit 20.

  For example, it is presumed that the first data in the text area of the kernel in which SR_color is set to 5 and SW_color is set to 1 is read many times and written. The first data is transferred to and read from the volatile semiconductor memory 8 during system operation based on the read mode determination operation shown in FIG. For this reason, the frequency with which the first data is actually written into the nonvolatile semiconductor memories 9 and 10 is low. However, since the importance of the first data is high, in FIG. 19, the write management unit 20 writes the first data in the B area of the nonvolatile semiconductor memory 9 that is the SLC.

  Next, since the kernel data area in which SR_color is set to 5 and SW_color is set to 5 is newly created and initialized every time the information processing apparatus 100 is started, the second data in the kernel data area is stored. It is estimated that the data life of is short. The writing management unit 20 first refers to the data life SL_color of the second data. The second data always exists on the volatile semiconductor memory 8 during operation of the information processing apparatus 100, and is erased from the volatile semiconductor memory 8 when the power is turned off. Therefore, the second data is not written in the memory area of the nonvolatile semiconductor memories 9 and 10.

  Next, the user program area in which SR_color is set to 4 and SW_color is set to 1 has a lower read frequency than the kernel called reentrant from all processes. The third data in the user program area is written into the memory area of the nonvolatile semiconductor memories 9 and 10 only when it is not accessed for a long time by the reading method shown in FIG. Therefore, the frequency at which the third data is written into the nonvolatile semiconductor memories 9 and 10 is low. Since the third data is less important than the data in the text area of the kernel, the third data is written in the A area which is the MLC area in FIG.

  Of the fourth data in the area dynamically secured in the program in which SR_color is set to 4 and SW_color is set to 4, the fourth data set with a short data life SL_color is the kernel data area. Similarly, it always exists on the volatile semiconductor memory 8 during the operation of the information processing apparatus 100. The writing management unit 20 first refers to the data life SL_color. The fourth data always exists on the volatile semiconductor memory 8 during system operation, and is erased from the volatile semiconductor memory 8 when the power is turned off, so that the fourth data is written in the memory areas of the nonvolatile semiconductor memories 9 and 10. Absent.

  On the other hand, the fourth data set with a long data life SL_color is arranged in the memory area of the volatile semiconductor memory 8, but the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 is filled with FULL. In this case, it becomes a write-back target from the volatile semiconductor memory 8 to the memory areas of the nonvolatile semiconductor memories 9 and 10. Since the text area of the program has a high importance of data, the data in the text area of the program is written in the C area which is the SLC.

  Next, data handled as a file referred to by the process will be described. In FIG. 10, the data life SL_color of the files referred to by the process is all set to be long.

  It is estimated by the operating system 27 that the fifth data in the system files whose SW_color is set to 1 and SR_color is set to 3 has a very low writing frequency and a high predicted reading frequency. At this time, the write management unit 20 arranges the fifth data in the memory area of the volatile semiconductor memory 8, but if the memory area of the volatile semiconductor memory 8 of the hybrid main memory 2 is filled with FULL, Data is to be written back from the volatile semiconductor memory 8 to the memory areas of the nonvolatile semiconductor memories 9 and 10. Since it is determined that the writing frequency of the fifth data is low, the writing management unit 20 places the fifth data in the MLC area.

  It is estimated by the operating system 27 that files having SW_color set to 3 and SR_color set to 3 have extremely high writing frequency and high predicted reading frequency. Therefore, the write management unit 20 arranges data in files having 3 in SW_color and 3 in SR_color in the SLC area.

  It is presumed by the operating system 27 that the sixth data included in the files whose SW_color is 1 and SR_color is 2 has a very low writing frequency and a low predicted reading frequency. Since it is determined that the sixth data has a low importance as a file, the write management unit 20 places the sixth data in the MLC area.

  It is estimated by the operating system 27 that the seventh data included in the files whose SW_color is set to 1 and SR_color is set to 1 has a very low writing frequency and a very low predicted reading frequency. Since it is determined that the importance of the seventh data as a file is low, the write management unit 20 places the seventh data in the MLC area.

  When the write target memory area is determined by the above processing, the write management unit 20 determines the physical address of the write destination. In this case, the write management unit 20 refers to the coloring table 14 and appropriately selects a write destination physical address to suppress wear leveling and reduce unnecessary erasure processing.

  Here, wear leveling means, for example, that data is exchanged (exchanged) between blocks so that the difference in the number of erases between the block with the largest number of erases and the block with the smallest number of erases falls within a predetermined threshold. Means to do. For example, since data can not be overwritten without erasure processing in a NAND flash memory, the data movement destination needs to be an unused block, and erasure processing of a block that originally stored data occurs.

  Next, with reference to FIG. 20, a process for determining a write target block for data will be described. FIG. 20 is a diagram for explaining a process of determining a write target block for data.

  The nonvolatile semiconductor memories 9 and 10 are erased in units of blocks. The erase count EC for each block area of the nonvolatile semiconductor memories 9 and 10 can be obtained by referring to the memory usage information 11. The ratio of the number of times of erasing EC to the upper limit of the number of times of erasing the block area (the upper limit number of erasable) is defined as a consumption rate.

  When the erase count EC of a block area reaches the maximum erasable count of the block area, the consumption rate is 100%. When the consumption rate is 100%, data is not written to the block area.

  When the erase count EC of the block area is close to the upper limit value of the erase count of the block area (for example, 90%), data writing to the block area is reduced. The writing management unit 20 refers to the coloring table 14 to write data to be written with a low writing frequency (static writing frequency SW_color, dynamic writing frequency DW_color) (for example, SW_color is 1, DW_color is “medium”). Write to a block area with a high consumption rate (for example, less than 90% consumption rate).

  On the other hand, when the erase count EC of the block area is lower than the upper limit value of the erase count of the block area (for example, the consumption rate is 10%), the data write to the block area may be large. The writing management unit 20 refers to the coloring table 14 and stores writing target data (for example, SW_color is 5 and DW_color is “high”) having a high writing frequency (static writing frequency SW_color, dynamic writing frequency DW_color). Write to a block area with a low consumption rate (for example, a consumption rate of less than 10).

  As described above, the block area into which the write target data is written is determined based on the coloring information of the write target data and the consumption rate of the block area. As a result, it is possible to select a write target block area that matches the characteristics (write frequency) of the write target data, and to improve data reliability. Further, as will be described below, it is possible to extend the life of the hybrid main memory.

  Next, referring to FIG. 21 to FIG. 25, details and effects of processing for determining a block area into which write target data is written based on coloring information, memory usage information 11 and memory specific information 12 of the write target data. Will be described.

  FIG. 21 is a graph showing an example of the transition of the number of erasures in an arbitrary block area of the nonvolatile semiconductor memories 9 and 10. In FIG. 21, the vertical axis represents the number of erasures and the horizontal axis represents time.

  The ideal number of erasures in each block area varies with time. For example, in the information processing apparatus 1 that uses nonvolatile semiconductor memories 9 and 10 such as NAND flash memory, the nonvolatile semiconductor memories 9 and 10 will deteriorate in the future, and the nonvolatile semiconductor memories 9 and 10 need to be replaced. . In order to use a large number of block areas of the nonvolatile semiconductor memories 9 and 10 before the memory replacement period, it is necessary to equalize the number of erases by wear leveling. FIG. 21 shows the transition of the number of erasures in an arbitrary block area of the nonvolatile semiconductor memories 9 and 10. It is preferable that the number of times of erasing the block area reaches the upper limit number of erasable when the expected life for the block area is reached.

  For example, in order for all block areas to follow the transition of the erase count shown in FIG. 21, it is possible to set a small threshold for the difference in the erase count of each block area in wear leveling.

  FIG. 22 is a graph showing an example of a change when the threshold for the difference in the number of erasures is set small in wear leveling.

  The broken lines in FIG. 22 indicate the range of variation in the number of erases in each block area. As shown in FIG. 22, by reducing the threshold value, the variation in the number of erasures in each block area is reduced, but the number of occurrences of erasure processing for wear leveling is increased. As a result, the nonvolatile semiconductor memory 9, The lifetime of the entire 10 may be shortened.

  The write management unit 20 is based on the memory usage information 11, the memory specific information 12, and the coloring table 14 when writing data in order to reduce the distribution of the number of erasures and to suppress the number of times erasure processing occurs due to wear leveling. The erase block area is selected.

  FIG. 23 is a graph showing an example of grouping block areas according to the number of erasures.

  FIG. 24 is a diagram showing a criterion for grouping block areas according to the number of erasures.

  In the present embodiment, grouping by the number of erasures is performed for each block area. Information indicating the result of grouping the block areas is stored as memory usage information 11. Note that the information indicating the result of grouping the block areas may be stored as the memory specific information 12.

  The thick line in FIG. 23 shows the transition of the minimum number of erasures, and the broken line represents the wear leveling threshold. As shown in FIG. 23, each block area is classified into a group of the number of times of erasing within the range of the wear leveling threshold (within the range of variation).

  When the data in a certain block area is erased and becomes writable again, the memory usage information management unit 22 determines to which group this block area belongs based on the determination table as shown in FIG. Store in usage information 11.

  In the determination table of FIG. 24, a value obtained by adding the minimum number of times of erasing of all the block areas, and the minimum number of times of erasing and a threshold value for determining whether or not wear leveling is performed. The space is divided by the number of groups. The groups are set as h, g, f, e, d, c, b, a from the bottom to the top of the divided range. In the determination table, an upper limit erase count and a lower limit erase count for each group are set.

  FIG. 25 is a diagram illustrating an example of a block area search in wear leveling.

  Based on the information in the coloring table 14, the write management unit 20 determines a group serving as a reference for searching for a block area of write target data. For example, when the access frequency of the write target data is high, a group with a small erase count is determined, and when the access frequency of the write target data is low, a group with a high erase count is determined. In the following description, it is assumed that the group c is determined for the write target data.

  When the group c of the write target data serving as the search criterion is determined, as shown in FIG. 25, the write management unit 20 uses the memory usage information 11 to determine the block area belonging to the determined group c of the write target data. Search for.

  When there is a block area belonging to the determined group c of the write target data, this block area is determined as a write destination of the write target data.

  On the other hand, when there is no block area belonging to the group c of the determined write target data, the write management unit 20 searches for a block area belonging to the group b near the group c of the determined write target data. .

  When there is a block area belonging to the neighboring group b of the determined write target data, the block area belonging to the neighboring group b is selected as a write destination of the write target data.

  If there is no block area belonging to the neighborhood group b of the determined write target data, similarly, until the block area is determined, further search for another neighborhood group d for the group c of the write target data is executed. . When the physical address of the block area to which data is written is determined by such search processing, the write management unit 20 writes data, and the address management unit 18 updates the address conversion information 13.

  Note that the write management unit 20 may determine a write destination address using another block area search method. For example, the write management unit 20 manages a block area (erased) that can be written in a tree structure (B-Tree B + Tree RB-Tree, etc.) having the erase count as a key and an erase block area as a node. It is stored in the memory specific information 12 or the memory usage information 11. The write management unit 20 searches the tree using the reference erase count as a key, and extracts a block area having the closest erase count.

  When data is erased by any process 3b, the operating system 27 erases the contents of the coloring table 14 for this data. When the contents of the coloring table 14 are erased, the address management unit 18 erases the physical address corresponding to the logical address of the data to be erased in the address conversion information 13.

  When the data exists on the volatile semiconductor memory 8, the data on the volatile semiconductor memory 8 is erased.

  Next, a configuration in which the memory management device 1 according to the present embodiment includes a cache memory will be described with reference to FIG. FIG. 26 is a block diagram illustrating an example of a memory management device that further includes a cache memory in the memory management device 1 according to the present embodiment. In FIG. 26, the processor 3b is described as a representative of the processors 3a, 3b, and 3c, but the same applies to the other processors 3a and 3c.

  The memory management device 1 further includes a cache memory 28.

  The processor 3b can directly access the cache memory 28 in addition to the primary cache memory 4b and the secondary cache memory 5b.

  The memory management device 28 accesses the hybrid main memory 2 when page-in or page-out occurs in any of the primary cache memory 4b, the secondary cache memory 5b, and the cache memory 28.

  An implementation example of the memory management device 1, the hybrid main memory 2, and the processor 3a will be described based on the example of FIG.

  FIG. 27A is a block diagram illustrating a first implementation example of the memory management device 1, the hybrid main memory 2, and the processor 3a. In FIG. 27A, the case where the volatile semiconductor memory 8 is a DRAM and the nonvolatile semiconductor memories 9 and 10 are NAND flash memories is described, but the present invention is not limited to this.

  The processor 3a includes a memory controller (MMU) 3ma, a primary cache memory 4a, and a secondary cache memory 4b. The memory management device 1 includes a DRAM controller. The processor 3a and the memory management device 1 are formed on the same substrate (for example, SoC).

  The volatile semiconductor memory 8 is controlled by a DRAM controller provided in the memory management device 1. The nonvolatile semiconductor memories 9 and 10 are controlled by the memory management device 1. In the mounting example of FIG. 27A, the memory module in which the volatile semiconductor memory 8 is mounted and the memory module in which the nonvolatile semiconductor memories 9 and 10 are mounted are different modules.

  FIG. 27B is a block diagram illustrating a first implementation example of the memory management device 1, the hybrid main memory 2, and the processor 3a. In FIG. 27B, the case where the volatile semiconductor memory 8 is a DRAM and the nonvolatile semiconductor memories 9 and 10 are NAND flash memories will be described, but the present invention is not limited to this. Description of the structure similar to that in FIG.

  In the example of FIG. 27B, the memory management device 1 is electrically connected to the chip on which the processor 3a is mounted from the outside. In addition, a volatile semiconductor memory 8 is connected to the memory management device 1. The memory management device 1 includes a DRAM controller (not shown).

  Next, another configuration aspect of the memory management device 1 and the information processing device 100 according to the present embodiment will be described with reference to FIG. In the memory management device 1 and the information processing device 100 shown in FIG. 1, the count (increment) of the write count DWC_color and the read count RWC_color for data is managed by the dynamic color information management unit 22 of the memory management device 1. On the other hand, in the memory management device 1 and the information processing device 100 shown in FIG. 28, the counts of the data write count DWC_color and the read count RWC_color are the memory controllers (MMU) 3ma, 3mb, 3mb, 3c provided in the processors 3a, 3b, 3c. Perform at 3 mc. In the following description, the memory controller 3ma will be described as a representative of the memory controllers 3ma, 3mb, and 3mc, but the same applies to the other memory controllers 3mb and 3mc.

  The memory controller 3ma provided in the processor 3a includes a counter cta that counts the number of write times DWC_color and the number of read times DRC_color for data. Further, the memory controller 3ma includes count information cia for managing the write count DWC_color and the read count DRC_color for data.

  For example, when the processor 3a generates a load instruction for data, the counter cta counts (increments) the read count DRC_color for the data and updates the count information cia. For example, when the processor 3a generates a store instruction for data, the counter cta counts (increments) the number of write times DWC_color for the data and updates the count information cia.

  The write count DWC_color and read count DRC_color for data managed by the count information cia are periodically reflected in the write count DWC_color and read count DRC_color of the coloring table 14 of the memory management device 1 for the data.

  In the configuration mode of FIG. 28, the following effects are obtained. That is, when the operating frequency of the processor 3a is on the order of GHz while the operating frequency of the memory management device 1 is on the order of MHz, the memory management device 1 can count writing and reading that occur in the processor 3a. It may be difficult. On the other hand, in the configuration mode of FIG. 28, the counter cta of the processor 3a counts writing and reading, so that it is possible to count the number of readings and the number of writings at a high operating frequency.

  Next, a configuration for managing a plurality of nonvolatile semiconductor memories by a plurality of memory management devices 1 will be described with reference to FIG. FIG. 29 is a perspective view showing an example of a plurality of memory management devices that manage a plurality of nonvolatile semiconductor memories.

  In FIG. 29, one memory management device 1 and a plurality of NAND flash memories 29 form one memory module 30. In the example of FIG. 29, three memory modules 30 are formed.

  The plurality of nonvolatile semiconductor memories 29 are, for example, NAND flash memories, and are used as the nonvolatile semiconductor memories 9 and 10 described above.

  The memory management device 1 manages access to a plurality of nonvolatile semiconductor memories 29 belonging to the same memory module 30.

  Further, the plurality of memory management devices 1 provided in the plurality of memory modules 30 operate as one memory management device in cooperation with each other.

  The memory management device 1 of the memory module 30 includes an ECC function and a RAID function for a plurality of nonvolatile semiconductor memories 29 in the memory module 30, and performs mirroring and striping.

  Each nonvolatile semiconductor memory 29 can be hot swapped (replaced) even when the memory module 30 is energized (operating). A button 31 is associated with each of the plurality of nonvolatile semiconductor memories 29.

  The button 31 includes a warning output unit (for example, an LED). For example, when the warning output unit is the first color (green), it indicates a normal state, and when it is the second color (red), it indicates a state that needs to be replaced.

  When the button 31 is pressed, a notification is sent to the processes 6a, 6b, 6c and the operating system 27, and when it is safe to remove when no access occurs, the button 31 becomes the third color (blue) The nonvolatile semiconductor memory 29 corresponding to the button 31 can be hot swapped.

  When the hot swap is executed, after the button 31 for requesting hot swap is pressed, when the write back is completed, a lamp indicating that the replacement is possible is turned on, and the nonvolatile semiconductor memory 29 is replaced.

  The processing unit 15 of the memory management device 1 refers to the memory usage information 11 and the memory specific information 12 stored in the information storage unit 17, and the number of rewrites or read of each nonvolatile semiconductor memory 29 is the memory specific information. It is determined whether or not a predetermined ratio of the upper limit number of accessible times described in 12 has been reached. Then, when the number of times of writing or the number of times of reading has reached a predetermined ratio of the upper limit number of times of writing or the upper limit number of times of reading, the processing unit 15 notifies or warns of the memory replacement.

  In the present embodiment, when the page size or block size of the nonvolatile semiconductor memory 29 is large, preloading is effective.

  When preloading is performed, the processing unit 15 of the memory management device 1 refers to coloring information corresponding to data stored in the nonvolatile semiconductor memory 29 and stores data that is likely to be frequently accessed in advance. Preloaded into the cache memory 28.

  Alternatively, the processing unit 15 preloads data having periodicity and highly likely to be accessed at a predetermined time before the predetermined time.

  In the present embodiment, the data arrangement is determined based on the durability of each memory of the hybrid main memory 2, and the life of the hybrid main memory 2 can be extended. Further, high-speed access to the hybrid main memory 2 can be realized.

  In the present embodiment, since data is arranged based on the durability of each memory of the hybrid main memory 2, fatal data loss in the hybrid main memory 2 can be prevented.

  By using the memory management device 1 and the hybrid main memory 2 according to this embodiment, swapping can be eliminated.

  In the present embodiment, the nonvolatile semiconductor memories 9 and 10 are used as the main memory. As a result, the storage capacity of the main memory can be increased, and a secondary storage device using a hard disk or SSD (Solid State Disk) need not be used.

  In this embodiment, since the nonvolatile semiconductor memories 9 and 10 are used as the main memory, instant-on can be speeded up.

(Second Embodiment)
The present embodiment is a modification of the first embodiment. In the present embodiment, a memory management device that accesses a memory connected via a network will be described.

  FIG. 30 is a block diagram illustrating an example of a network system according to the present embodiment.

  The network system 37 includes an information processing device 37A and an information processing device 37B. The information processing device 37A and the information processing device 37B are connected via a network 38. Since the information processing device 37A and the information processing device 37B have equivalent functions, the information processing device 37A will be described in detail below. The network system 37 may include three or more information processing apparatuses.

  The information processing device 37A includes a processor 3A, a memory management device 32A, a volatile semiconductor memory 8A, a nonvolatile semiconductor memory 9A, and a network interface device 39A.

  The processor 3A is connected to the volatile semiconductor memory 8A, the nonvolatile semiconductor memory 9A, and the network interface device 39A via the memory management device 32A.

  The processor 3A may include a cache memory inside, but the description is omitted in FIG. The information processing apparatus 37A may include a plurality of processors 3A.

  The volatile semiconductor memory 8A is the same as the volatile semiconductor memory 8 of the first embodiment. The nonvolatile semiconductor memory 9A is the same as the nonvolatile semiconductor memory 9 or the nonvolatile semiconductor memory 10 of the first embodiment.

  In the present embodiment, the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A are used as the main memory of the information processing apparatus 37A. However, the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A store information that is frequently accessed or highly important for the information processing device 37A among other data processing devices 37B. It functions as a cache memory in the device 37A. In this case, the volatile semiconductor memory 8A is used as a primary cache memory in the information processing apparatus 37A, and the nonvolatile semiconductor memory 9A is used as a secondary cache memory in the information processing apparatus 37A.

  The network interface device 39A transmits and receives network logical addresses or data to and from the network interface device 39A of the other information processing device 37B via the network 38.

  The memory management device 32A according to this embodiment will be described. FIG. 31 is a block diagram showing an example of the configuration of the memory management device 32A according to the present embodiment.

  The processing unit 33A of the memory management device 32A includes a network address conversion in addition to the address management unit 18, the read management unit 19, the write management unit 20, the coloring information management unit 21, the memory usage information management unit 22, and the relocation unit 23. Unit 34 and communication unit 35.

  The network address conversion unit 34 converts a short address length logical address (hereinafter referred to as a “processor logical address”) used in the processor 3A into a long address length used in a plurality of information processing apparatuses connected via the network. It is converted into a logical address (hereinafter referred to as “network logical address”). For example, a hash function is used in this address conversion. The processor logical address is a pointer stored in a register.

  The work memory 16 stores an address length conversion table AT. The network address conversion unit 34 refers to the address length conversion table AT and converts the processor logical address into a network logical address.

  The address length conversion table AT is stored in the work memory 16, but may be stored in the information storage unit 17.

  The communication unit 35 transmits and receives the network logical address and the data specified by the network logical address via the network 38 using the network interface device 39A.

  In the present embodiment, the memory usage information 11 is the entire network system 37 (in the example of FIG. 31, the memory usage information 11 is the volatile semiconductor memory 8A, the nonvolatile semiconductor memory 9A, the volatile semiconductor memory 8B, the nonvolatile memory It represents the usage state of the memory area of the semiconductor memory 9B).

  Similarly, the memory unique information 12 represents unique information of the memory area of the entire network system 37.

  The address translation information 13 indicates the relationship between network logical addresses and physical addresses used in the entire network system 37.

  The coloring table 14 includes coloring information of each data in the entire network system 37.

  In the network system 37, a unique address is assigned to all data. When a common network logical address space is used in the entire network system 37, the required number of bits of the address becomes large, for example, 128 bits. However, in this network system 37, the registers of the processors 3A and 3B are 32 bits or 64 bits. In this case, it is necessary to convert the processor logical address of the number of bits of the register into the number of bits of the network logical address. The network address conversion unit 34 provided in the memory management devices 32A and 32B executes this conversion process.

  Data reading via the network 38 by the network system 37 will be described.

  The memory management device 32A receives the processor logical address from the processor 3A and converts the processor logical address into a network logical address. Then, the memory management device 32A determines that the data corresponding to the network logical address is not stored in any of the memories (the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A in FIG. 31) of the information processing device 37A. The network logical address is sent to the other information processing apparatus 37B via the network interface apparatus 39A and the network 38.

  The memory management device 32B of the information processing device 37B receives data corresponding to the network logical address from the information processing device 37A via the network 38 and the network interface device 39B.

  The memory management device 32B is based on the address conversion information 13 when the received network logical address is stored in the memory (the volatile semiconductor memory 8B or the non-volatile semiconductor memory 9B in FIG. 31) of the information processing device 37B. Then, the network logical address is converted into a physical address, and the data is read out.

  The memory management device 32B sends the read data to the information processing device 37A via the network interface device 39A and the network 38.

  The memory management device 32A of the information processing device 37A receives the read data from the information processing device 37B via the network 38 and the network interface device 39A.

  The memory management device 32A returns the read data to the processor 3A.

  Further, the memory management device 32A refers to the coloring table 14, and when the access frequency or importance of the read data is equal to or higher than a predetermined value, this data is stored in the volatile semiconductor memory 8A or the nonvolatile semiconductor memory 9A. Write and update the address translation information 13. In this writing, a writing destination is determined by the same method as in the first embodiment.

  Data writing via the network 38 by the network system 37 will be described.

  The memory management device 32A receives the processor logical address and the write target data from the processor 3A, and converts the processor logical address into a network logical address. Then, when the network logical address indicates the other information processing apparatus 37B, the memory management apparatus 32A sends the network logical address and the write target data to the other information processing apparatus 37B via the network interface apparatus 39A and the network 38.

  The memory management device 32B of the information processing device 37B receives the network logical address and the write target data from the information processing device 37A via the network 38 and the network interface device 39B.

  The memory management device 32B converts the network logical address into a physical address based on the address conversion information 13, and writes the write target data in the memory area indicated by the physical address.

  A copy of the data D1 in the network system 37 shown in FIG. 30 will be described.

  The memory management device 32A of the information processing device 37A manages the volatile semiconductor memory 8A, the nonvolatile semiconductor memory 9A, the memory usage information 11 and the memory specific information 12 for the volatile semiconductor memory 8B and the nonvolatile semiconductor memory 9B.

  Further, the memory management device 32A displays the coloring information of each data stored in the volatile semiconductor memory 8A, the nonvolatile semiconductor memory 9A, the volatile semiconductor memory 8B, and the nonvolatile semiconductor memory 9B as the coloring table 14. Manage with.

  The memory management device 32A is based on the memory usage information 11, the memory specific information 12, and the coloring table 14, and in addition to the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A, the volatile semiconductor connected via the network 38. Also for the memory 8B and the nonvolatile semiconductor memory 9B, the write destination is determined so as to extend the lifetime of the nonvolatile semiconductor memories 9A and 9B.

  Here, the memory management device 32A of the information processing device 37A uses the volatile semiconductor memory 8A or the volatile semiconductor memory 8A of the information processing device 37A as the main body data D1 that is frequently accessed from the information processing device 37A to the other information processing device 37B. The data is copied to the nonvolatile semiconductor memory 9A and stored as data D1c. For example, the memory management device 32A refers to the coloring table 14, and stores the data D1 stored in the other information processing device 37B and having an access frequency of a predetermined level or higher as the volatile semiconductor memory 8A or the nonvolatile memory of the information processing device 37A. And stored as data D1c copied to the conductive semiconductor memory 9A.

  When the access frequency for the data D1c copied to the information processing device 37A is greater than or equal to a predetermined level than the access frequency for the data D1 in the other information processing device 37B, the memory management devices 32A and 32B The data D1c copied to is managed as a main body.

  Further, when writing to the copied data D1c occurs in the information processing device 37A, the memory management devices 32A and 32B manage the data D1c of the information processing device 37A as a main body.

  As described above, when the data D1c copied to the information processing apparatus 37A is managed as the main body, the data D1 of the information processing apparatus 37B is maintained as it is, and different addresses (ID) are assigned to the data D1 and D1c. Good. Another address may be assigned to the original data D1 or may be assigned to the copied data D1c.

  Further, when the data D1c is managed as a main body, the original data D1 may be deleted.

  In order to prevent the data D1 and D1c from colliding with the memory management devices 32A and 32B, for example, when writing to the data D1c used as a cache occurs, management such as updating the data D1 of the main body I do.

  FIG. 32 is a block diagram showing a first relationship between the processor logical address and the network logical address according to the present embodiment.

  For example, the upper address P1u of the processor address P1 is 32 bits, and the lower address P1d is 32 bits.

  For example, the combination of the upper address N1u and the middle address N1m of the network logical address N1 is 128 bits, and the lower address N1d is 32 bits.

  The upper address N1u of the network logical address N1 indicates, for example, an operator, and the middle address N1m of the network logical address N1 is, for example, a value unique to the processor. The high-order address N1u and the middle-order address N1m of the network logical address N1 are addresses related to the network, and are, for example, IP addresses, IPv4, and the like.

  A combination of the upper address N1u and the middle address N1m of the network logical address N1 is converted by the hash function 40. By this conversion, the upper address P1u of the processor logical address P1 having a smaller number of bits than the upper address N1u and the middle address N1m of the network logical address N1 is obtained. The upper address P1u of the processor logical address P1 is used as a key in the conversion from the processor logical address P1 to the network logical address N1.

  The lower address N1d of the network logical address N1u is used as it is as the lower address P1d of the processor logical address P1.

  The upper address N1u and the middle address N1m of the network logical address N1 are stored at the position indicated by the upper address P1u of the processor logical address P1 in the address length conversion table AT1.

  When converting the processor logical address P1 to the network logical address N1, the network address conversion unit 34 refers to the position indicated by the higher address P1u of the processor logical address P1 in the address length conversion table AT1, and stores the network stored at this position. An upper address N1u and a middle address N1m of the logical address N1 are obtained.

  Then, the network address conversion unit 34 obtains the network logical address N1 by combining the upper address N1u and the middle address N1m of the obtained network logical address N1 with the lower address P1d of the processor logical address P1.

  In the address length conversion table AT1, an address length conversion flag indicating whether or not each entry is valid is attached.

  The network address conversion unit 34 refers to a registration destination address length conversion flag when registering an entry in the address length conversion table AT1. If the address length conversion flag is invalid, the network address conversion unit 34 registers the entry as it is. The network address conversion unit 34 executes exception processing when the address length conversion flag is valid. This can prevent duplicate registration in the entry.

  FIG. 33 is a block diagram showing a second relationship between the processor logical address P2 and the network logical address N2 according to the present embodiment.

  The middle address N2m of the network logical address N2 is used as the upper address P2u of the processor logical address P2. The upper address P2u of the processor logical address P2 is used as a key in the conversion from the processor logical address P2 to the network logical address N2.

  The lower address N2d of the network logical address N2 is used as it is as the lower address P2d of the processor logical address P2.

  The upper address N2u and the middle address N2m of the network logical address N2 are stored at the position indicated by the upper address P2u of the processor logical address P2 in the address length conversion table AT2.

  When converting the processor logical address P2 to the network logical address N2, the network address conversion unit 34 refers to the position indicated by the higher address P2u of the processor logical address P2 in the address length conversion table AT2, and stores the network stored at this position. The upper address N2u and the middle address N2m of the logical address N2 are obtained.

  Then, the network address conversion unit 34 obtains the network logical address N2 by combining the upper address N2u and middle address N2m of the obtained network logical address N2 with the lower address P2d of the processor logical address P2.

  FIG. 34 is a block diagram showing a third relationship between the processor logical address and the network logical address according to the present embodiment.

  The middle address N3m and the lower address N3d of the network logical address N3 are used as the upper address P3u and the lower address P3d of the processor logical address P3. The upper address P3u of the processor logical address P3 is used as a key in the conversion from the processor logical address P3 to the network logical address N3.

  The upper address N3u of the network logical address N3 is stored at a position indicated by the upper address P3u of the processor logical address P3 in the address length conversion table AT3.

  When converting the processor logical address P3 to the network logical address N3, the network address conversion unit 34 refers to the position indicated by the upper address P3u of the processor logical address P3 in the address length conversion table AT3, and stores the network stored at this position. The upper address N3u of the logical address N3 is obtained.

  Then, the network address conversion unit 34 obtains the network logical address N3 by combining the upper address N3u of the obtained network logical address N3 with the upper address P3u and the lower address P3d of the processor logical address P3.

  FIG. 35 is a block diagram showing a fourth relationship between the processor logical address and the network logical address according to the present embodiment.

  The network address conversion unit 34 extracts a value at an interval of n bits from the combination of the upper address N4u and the middle address N4m of the network logical address N4, and uses the extracted value as the upper address P4u of the processor logical address P4. . By this conversion, the upper address P4u of the processor logical address P4 having a smaller number of bits than the upper address N4u and the middle address N4m of the network logical address N1 is obtained. The upper address P4u of the processor logical address P4 is used as a key in the conversion from the processor logical address P4 to the network logical address N4.

  The other relationship between the network logical address N4 and the processor logical address P4 and the conversion from the processor logical address P4 to the network logical address N4 are the same as in the case of FIG.

  FIG. 36 is a block diagram showing a fifth relationship between the processor logical address and the network logical address according to the present embodiment.

  The network address conversion unit 34 sets the remainder obtained by dividing the combination of the upper address N5u and the middle address N5m of the network logical address N5 by the value P (for example, a prime number) as the upper address P5u of the processor logical address P5. By this conversion, an upper address P5u of the processor logical address P5 having a smaller number of bits than the upper address N5u and the middle address N5m of the network logical address N5 is obtained. The upper address P5u of the processor logical address P5 is used as a key in the conversion from the processor logical address P5 to the network logical address N5.

  The other relationship between the network logical address N5 and the processor logical address P5 and the conversion from the processor logical address P5 to the network logical address N5 are the same as those in FIG.

  The network address conversion unit 34 converts a part of the network logical addresses N1 to N5 into a part of the processor logical addresses P1 to P5 using a conversion table instead of the hash function 40, and the processor logical addresses P1 to P5. A part of P5 may be used as a key for address length conversion.

  The network address conversion unit 34 creates a table for registering part or all of the network logical addresses N1 to N5, and converts the addresses of this table from the processor logical addresses P1 to P5 to the network logical addresses N1 to N5. It may be used as a key. In this conversion method, each of the plurality of information processing devices 37A and 37B may manage the table. More preferably, a table is shared between a plurality of information processing devices 37A and 37B connected to the network 38, and each of the information processing devices 37A and 37B stores a copy of the table locally in a cache memory or the like. Also good.

  In the above address conversion, the lower addresses N1d to N5d of the network logical addresses N1 to N5 and the lower addresses P1d to P5d of the processor logical addresses P1 to P5 are used without being converted, but this network logical address N1 The lower addresses N1d to N5d of .about.N5 and the lower addresses P1d to P5d of the processor logical addresses P1 to P5 may be converted.

  FIG. 37 is a block diagram showing an example of a virtual address space of the network system 37 according to the present embodiment.

  In the present embodiment, since a unique network logical address is assigned to all data in the network system 37, a virtual address space 41 common to the information processing apparatuses 37A and 37B can be formed.

  FIG. 38 is a block diagram showing a first example of the configuration of the processor logical address and the network logical address according to the present embodiment.

  The processor logical address 42 includes a conversion key, a file address, and an offset.

  The network address conversion unit 34 converts the processor logical address 42 into the network logical address 43.

  The network logical address 43 includes processor identification information (for example, identification information of an operator and an information processing device), a file address, and an offset.

  The memory management device 32A transmits the network logical address 42 to the memory management device 32B via the network 38. Then, the memory management device 32B reads out the data specified by the file address and offset of the network logical address 43 and returns it to the memory management device 32A.

  FIG. 39 is a block diagram showing a second example of the configuration of the processor logical address and the network logical address according to the present embodiment.

  The processor logical address 44 includes a translation key and an offset.

  The network address conversion unit 34 converts the processor logical address 44 into a network logical address 45.

  The network logical address 45 includes processor identification information, a file address, and an offset.

  The memory management device 32A transmits the network logical address 45 to the memory management device 32B via the network 38. Then, the memory management device 32B reads the data specified by the file address and offset of the network logical address 45 and returns it to the memory management device 32A.

  FIG. 40 is a block diagram showing a third example of the configuration of the processor logical address and the network logical address according to the present embodiment.

  The processor logical address 46 includes a conversion key and a file address.

  The network address conversion unit 34 converts the processor logical address 46 into a network logical address 47.

  The network logical address 46 includes processor identification information and a file address.

  The memory management device 32A transmits the network logical address 47 to the memory management device 32B via the network 38. Then, the memory management device 32B reads the file data designated by the file address of the network logical address 47 and returns it to the memory management device 32A.

  The technical significance of the address translation as described above will be described below.

  For example, an 8-bit CPU (Central Processing Unit) is generally used as the processor 3A. The number of bits of the 8-bit CPU includes an 8-bit register. Further, in a commonly used 8-bit CPU, the number of bits of the address is 16 bits.

  For example, a 16-bit CPU includes a 16-bit register. In a commonly used 16-bit CPU, the number of bits of an address is 20 bits.

  Both the numerical value and the address are stored in the general register. Therefore, it is desirable that the number of bits in the numerical value and the number of bits in the address match. However, as described above, the number of bits of the register may not match the number of bits of the address.

  Currently, 64-bit CPUs are becoming popular. A 64-bit CPU can provide sufficient computational accuracy. For this reason, the necessity that the number of bits of the register exceeds 64 bits is low. In addition, from the viewpoint of carry processing of the CPU adder, it is considered difficult to provide the CPU with a register exceeding 64 bits.

  On the other hand, it is considered highly necessary to increase the number of bits of the address. As an example, Single Level Store (SLS) will be described.

  In SLS, virtual addresses are assigned to various storage devices including secondary storage devices. In recent years, local storage devices that are not connected via a network are in the Tbyte order, so the size of the virtual address is insufficient with 32 bits, and 64 bits are sufficient.

  However, when a storage device such as (NAS) used in a network environment is used, or when an address is assigned to a large number of storage devices connected to the network, the size of the virtual address is set to, for example, It needs to be as large as 128 bits.

  FIG. 41 is a diagram illustrating an example of calculation for estimating the number of bits of an address necessary for accessing data stored in a large number of devices connected to a network.

  As shown in FIG. 41, assuming that humans around the world store a certain amount of data, these data can be accessed using an 82-bit network logical address.

  Therefore, as described above, in the network system 37, it is significant to obtain a network logical address for a network having a larger number of bits from the same processor logical address as the number of bits of the registers of the processors 3A and 3B.

  For example, in this embodiment, by setting the network logical address to 128 bits, the address can be assigned to all data in the network system.

  In the present embodiment described above, addresses can be assigned to all data used in the network system 37.

  In the present embodiment, for example, address conversion and writing are performed between the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A provided in the network system 37, and the volatile semiconductor memory 8B and the nonvolatile semiconductor memory 9B. Basic memory management and memory access, such as pre-determining, can be performed by a common method. That is, each of the information processing devices 37A and 37B according to the present embodiment has a memory provided in its own device and a memory connected via the network 38 in managing the access method, the number of accesses, the access frequency, and the like. And do not have to be distinguished.

  In the present embodiment, data that is frequently accessed by the information processing devices 37A and 37B is stored in the device, so that an access delay due to transmission / reception via the network 38 and an access failure due to network disconnection are prevented. Can be prevented.

  In the present embodiment, the volatile semiconductor memory 8A and the nonvolatile semiconductor memory 9A, the volatile semiconductor memory 8B, and the nonvolatile semiconductor memory 9B on the network system 38 can be used as the main memory. Furthermore, each of the information processing apparatuses 37A and 37B according to the present embodiment can use the memory in the own apparatus as a cache memory for storing data stored in other apparatuses.

  In the present embodiment, an address having a larger number of bits than the number of bits of the registers of the processors 3A and 3B can be used, and a vast memory space can be used.

  In general, access that is not performed via the network is performed by reading and writing to the storage device, and access that is performed via the network is performed by socket communication. Access methods differ between read and write and socket communication. For Web access via a network, for example, a special access method using a URL or the like is used. On the other hand, in the present embodiment, the storage device is accessed based on the network logical address regardless of whether the access is made via the network, and the same access method is used.

  In the present embodiment, an address length conversion flag is attached to the address length conversion tables AT, AT1 to AT5, thereby preventing duplicate registration.

  The components described in the above embodiments can be freely combined and can be freely divided.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention when it is practiced. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.

  DESCRIPTION OF SYMBOLS 1 ... Memory management apparatus, 2 ... Hybrid main memory, 3a-3b ... Processor, 4a-4c ... Primary cache memory, 5a-5c ... Secondary cache memory, 6a-6c ... Process, 7 ... Bus, 8 ... Volatile Semiconductor memory 9, 10, 29 ... Nonvolatile semiconductor memory, 11 ... Memory usage information, 12 ... Memory specific information, 13 ... Address conversion information, 14 ... Coloring table, 15 ... Processing unit, 16 ... Working memory, 17 ... Information storage unit, 18 ... Address management unit, 19 ... Read management unit, 20 ... Write management unit, 21 ... Coloring information management unit, 22 ... Memory usage information management unit, 23 ... Relocation unit, 24 ... Access frequency calculation unit 25 ... Dynamic color information management unit, 27 ... Operating system, 28 ... Cache memory, 3ma-3mc ... Memory management unit, cta ctc ... counter, cia-cic ... count information, 30 ... memory module, 31 ... button, 3A, 3B ... processor, 8A, 8B ... volatile semiconductor memory, 9A, 9B ... nonvolatile semiconductor memory, 32A, 32B ... memory management Device, 33A ... processing unit, 34 ... network address conversion unit, 35 ... communication unit, 37 ... network system, 37A, 37B ... information processing device, 38 ... network, 39A, 39B ... network interface device, AT, AT1-AT5 ... Address length conversion table.

Claims (6)

Generated based on characteristics of each data stored in at least one of the first semiconductor memory and the non-volatile second semiconductor memory having a lower accessible upper limit than the first semiconductor memory, A first storage unit that stores arrangement hint information serving as a hint for determining the arrangement area of each data;
A second storage unit for storing memory specific information indicating memory specific characteristics for each of the first semiconductor memory and the second semiconductor memory;
A third storage unit for storing memory use information indicating a use state of each memory area included in the first semiconductor memory and the second semiconductor memory;
A network address conversion unit that converts a processor logical address issued by a processor to a network logical address that is longer than the processor logical address and identifies a memory area on the network system;
A first management unit that generates the placement hint information for data to be written to at least one of the first semiconductor memory and the second semiconductor memory;
A second management unit that updates the memory use information for the accessed memory area when access to at least one of the first semiconductor memory and the second semiconductor memory occurs;
Based on the placement hint information, the memory use information, and the memory specific information, a write area is selected from the memory areas of the first semiconductor memory and the second semiconductor memory for the write target data. A third manager to determine;
A fourth management unit that stores, in a fourth storage unit, address conversion information that associates the network logical address of the write target data with the physical address of the write area;
A fifth management unit that reads the read target data from either the first semiconductor memory or the second semiconductor memory based on the network logical address of the read target data and the address conversion information; A memory management device comprising:   The memory management device according to claim 1, further comprising a communication unit that transmits and receives the network logical address to another device via the network. The memory specific information indicates memory specific characteristics for each of the first semiconductor memory and the second semiconductor memory on the network system,
The first management unit manages the placement hint information of each data on the network system,
The second management unit manages memory use information for each memory area of the first semiconductor memory and the second semiconductor memory on the network system. The memory management device described. The processor logical address includes a first processor address portion serving as a conversion key for an address length, and a second processor address portion that is the same as a part of the network logical address.
The network logical address is converted based on the conversion key, and includes a first network address portion having a larger number of bits than the conversion key, and a second network address portion that is the same as the second processor address. ,
The network address conversion unit refers to an address length conversion table in which the first processor address unit and the first network address unit are associated, and the first network address unit, the second processor address unit, 4. The memory management device according to claim 1, wherein the network logical address is generated in combination.   5. The memory management device according to claim 4, wherein a flag indicating validity or invalidity is attached to each entry of the address length conversion table. Generated based on characteristics of each data stored in at least one of the first semiconductor memory and the non-volatile second semiconductor memory having a lower accessible upper limit number than the first semiconductor memory, Generating placement hint information that serves as a hint for determining the placement area of each data;
Managing memory usage information indicating a usage state of each memory area included in the first semiconductor memory and the second semiconductor memory;
Converting a processor logical address issued by a processor into a network logical address that is longer than the processor logical address and identifies a memory area on the network system;
Based on the placement hint information, the memory usage information, and memory specific information indicating memory specific characteristics for each of the first semiconductor memory and the second semiconductor memory, Determining a write area from memory areas of the first semiconductor memory and the second semiconductor memory;
Storing address translation information that associates the network logical address of the write target data with the physical address of the write area;
A memory management method including reading the read target data from either the first semiconductor memory or the second semiconductor memory based on the network logical address of the read target data and the address conversion information .

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