JP2010287603A - Compound semiconductor element, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor element enabling high-speed operation and having high ESD resistance, and to provide a method of manufacturing the same. <P>SOLUTION: This compound semiconductor element includes a transistor portion composed of field effect transistors or heterojunction bipolar transistors, and an ESD protecting portion 114 parallel-connected to the transistor portion. The ESD protecting portion 114 includes a first and second semiconductor layers 109, 113, and a third semiconductor layer 111 formed between the first and second semiconductor layers 109, 113 while having a forbidden band width wider than the forbidden band widths of the first and second semiconductor layers 109, 113, and having impurity concentration of not more than 1×10<SP>17</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof, and for example, relates to a compound semiconductor device used in the fields of optical communication, wireless communication, radar, and the like and a manufacturing method thereof.

  Since compound semiconductor elements can operate at high speed, they have been widely used as front-end devices for wireless communication and optical communication. Further, higher speeds and higher functions are required for mobile phones, radar applications, and 100 Gb / s optical communication applications.

  Compound semiconductor devices include field effect transistors (FETs) and heterojunction bipolar transistors (HBTs). These compound semiconductor devices have been widely used for amplifiers having high electron mobility, high-speed operation, and low noise.

  On the other hand, with the increase in speed and performance of compound semiconductor devices, the device size has been reduced, and electrostatic discharge (ESD) resistance has deteriorated. ESD occurs in handling, machines, and devices, and may cause destruction or irreparable damage to the compound semiconductor element. ESD resistance is an important characteristic that affects the reliability of a compound semiconductor element, and is required to be sufficiently increased to ensure more stable operation.

  The FETs that are particularly susceptible to damage from ESD are the high-frequency signal input / output FETs. In general, it is considered that a large current flows to the interface between the electrode metal and the semiconductor due to ESD, resulting in thermal damage. In many cases, the gate of the FET is the input part of the high frequency signal, and the base of the HBT is the input part. In this case, since the resistance is particularly high and the element size is small, it is easily affected by ESD.

  FIG. 6 is an example of an ESD protection circuit. For the input terminal IN, ESD protection diodes D1 and D2 are inserted in parallel with the FET to be protected between the power supply Vcc and the ground GND. With such a configuration, when a positive electrostatic charge is applied to the input terminal, it is discharged to the power source Vcc, and when a negative electrostatic charge is applied to the input terminal, it is discharged to the ground GND. Patent Document 1 proposes a technique of adding a PN-inverted element in order to improve ESD resistance of a surface emitting laser.

JP 2006-216846 A

  The circuit configuration of FIG. 6 requires two diodes D1 and D2, and the capacitance of the input section increases accordingly, which is disadvantageous for high-speed operation. High-speed compound semiconductor elements are required to have a low capacity and to withstand forward and reverse static electricity.

  It is also conceivable to mount an ESD protection element such as a Zener diode or a varistor in order to improve the ESD tolerance of the semiconductor optical element. These elements have a sufficient ESD protection effect and are widely put into practical use as protective elements for semiconductor integrated circuits (ICs) and the like. However, zener diodes and varistors have a very large parasitic capacitance.

  The present invention has been made under such a background, and an object of the present invention is to provide a compound semiconductor device capable of high-speed operation and having high ESD resistance, and a method for manufacturing the same.

The compound semiconductor device according to the present invention is
A transistor portion comprising a field effect transistor or a heterojunction bipolar transistor;
An ESD protection unit connected in parallel with the transistor unit,
The ESD protection unit is
First and second semiconductor layers containing impurities of a first conductivity type;
Formed between the first and second semiconductor layers, having a forbidden band wider than the forbidden band of the first and second semiconductor layers, and having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less. A third semiconductor layer.

A method for producing a compound semiconductor device according to the present invention includes:
Forming a transistor portion comprising a field effect transistor or a heterojunction bipolar transistor;
Forming an ESD protection part connected in parallel with the transistor part,
The step of forming the ESD protection part includes:
Forming a first semiconductor layer containing an impurity of a first conductivity type;
Forming a second semiconductor layer containing an impurity of the first conductivity type;
Located between the first and second semiconductor layers, the forbidden band width is wider than the forbidden band widths of the first and second semiconductor layers, and the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less. Forming a third semiconductor layer.

  According to the present invention, it is possible to provide a compound semiconductor device capable of high-speed operation and having high ESD resistance and a method for manufacturing the same.

It is a circuit structure figure concerning an embodiment of the invention. It is sectional drawing which shows the structure of the field effect transistor which concerns on Example 1 of this invention. It is a graph of the analysis result which shows the effect of the antistatic element which concerns on Example 1 of this invention. It is a graph of the analysis result which shows the effect of the antistatic element which concerns on Example 1 of this invention. It is a graph of the analysis result which shows the effect of the antistatic element which concerns on Example 1 of this invention. It is a figure which shows the manufacturing method of the field effect transistor which concerns on Example 1 of this invention. It is a figure which shows the manufacturing method of the field effect transistor which concerns on Example 1 of this invention. It is a figure which shows the manufacturing method of the field effect transistor which concerns on Example 1 of this invention. It is sectional drawing which shows the structure of the heterojunction transistor in Example 2 of this invention. It is a figure which shows an example of an ESD protection circuit.

  The compound semiconductor element of the present invention is an FET or HBT used for an input part or an output part of a high-frequency circuit, and is characterized by including an ESD protection element integrated in parallel. An ESD protection element is required to minimize an increase in element capacity and not hinder high-speed operation.

  This ESD protection element is characterized in that an undoped layer (i layer) having a wide forbidden band is sandwiched between conductive layers having a narrow forbidden band. The conductive layer of the ESD protection element may be n-type or p-type. That is, it becomes a nin structure or a pip structure. In this ESD protection element, since there is a discontinuity in the conduction band or valence band between the conductive layer and the i layer, almost no current flows when a bias that can overcome the offset is not applied. Absent.

  In general, the driving voltage of a compound semiconductor element for a high-frequency circuit is often 3.3 V, and even a high-power element is used at 10 V or less. Here, AC coupling (the DC component is cut) may be used to set the common mode voltage (average voltage) to 0 V, and the common mode voltage is not set to 0 V, such as LVDS (Low voltage differential signal) or CML (current mode logic). It may be a value of

  When the ESD protection element according to the present invention has a nin structure, for example, the interface between the n-type conductive layer and the i layer on the side to which a positive voltage is applied is depleted, so that the effective capacity of the element is reduced. become. The element capacitance is proportional to dielectric constant × area ÷ insulating layer thickness. Therefore, an effect equivalent to that of increasing the thickness of the insulating layer can be obtained by increasing the thickness of the depletion layer without carriers. That is, when a bias voltage is applied to the ESD protection element, the capacitance of the ESD protection element can be reduced.

  Therefore, it is necessary to apply a bias voltage to the ESD protection element during the operation of the compound semiconductor element and to connect the ESD protection element in parallel to the input or output terminal of the compound semiconductor element. In the case of AC coupling, the average voltage of the input or output terminal becomes the same as that of GND. Therefore, as shown in FIG. 1, the input or output terminal (input terminal IN in FIG. 1) and the ESD protection element are connected to GND. Instead of being connected in parallel with the compound semiconductor element FET, it is connected in parallel with the power supply Vcc. On the other hand, in the case of LVDS, CML, etc. to which a predetermined common mode voltage is applied instead of AC coupling, one end of the ESD protection element may be connected to GND.

  When static electricity is applied to the ESD protection element, carriers overcome the discontinuity between the i layer and the conductive layer, resulting in avalanche breakdown. Therefore, a current flows to the ESD protection element side. The ESD protection element according to the present invention has a nin structure or a pip structure and is a symmetric structure. Therefore, even when positive or negative static electricity is applied to the input / output terminal of the high-frequency element, the ESD protection effect is achieved. It can be demonstrated. The same effect can be obtained with either the nin structure or the pip structure. However, the nin structure is generally preferable because it has a higher carrier mobility and can lower the device resistance.

It is desirable that no impurities be mixed into the i layer, but it is impossible to completely eliminate impurities during the actual manufacturing process. The unintended background impurity concentration is preferably opposite to the conductivity type of the impurity in the conductive layer, and the concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less. This is because if the conductivity type of the impurity in the conductive layer and the impurity in the i layer are the same, a leak current is generated even at a low voltage at which the compound semiconductor element operates. The higher the impurity concentration of the conductive layer, the lower the resistance in the on state, that is, the breakdown state, and the more easily the current due to static electricity flows. Therefore, the highest possible concentration is desirable. When it is at least 1 × 10 ¹⁸ cm ⁻³ or more, the resistance of the conductive layer can be sufficiently lowered.

In addition, between the conductive layer and the i layer, the forbidden band width is a composition between the conductive layer and the i layer and the impurities are used to deplete the compound semiconductor element operating voltage and reduce the leakage current. Is the same conductivity type as the conductive layer, and a low concentration layer having a concentration of 1 × 10 ¹⁷ cm ⁻³ or less is formed. The low-concentration layer tends to be depleted and thus contributes to a reduction in capacitance. Further, when a bias is applied, it becomes difficult for a current to flow, which contributes to a reduction in leakage current.

  Further, the thickness of the i layer is preferably between 0.1 and 1.0 μm. The reason is that if the thickness is less than 0.1 μm, a leak current is generated at a low voltage, and the capacity increases, so that the high-speed characteristics of the compound semiconductor element deteriorate. On the other hand, when the thickness is 1.0 μm or more, the capacitance can be reduced, but it is not desirable because the voltage applied to this element becomes too high and the element resistance becomes too high. In addition, the composition of the i layer requires that the energy difference between the conduction band and the conductive layer be 0.3 eV or more when the conductive layer is n-type. This is because if the energy difference is small, a leak current flows even with a voltage of about the bias of the compound semiconductor element. On the other hand, when the conductive layer is p-type, the energy difference between the conductive band and the conductive layer needs to be 0.2 eV or more for the same reason.

  Such a compound semiconductor element for a high-frequency circuit is often manufactured on a GaA substrate that is inexpensive and easy to manufacture. In that case, it is desirable that the conductive layer and the i layer of the ESD protection element are substantially lattice-matched with GaAs. For example, GaAs can be used for the conductive layer. On the other hand, for the i layer, for example, an AlGaAs layer, InGaP, or InAlGaP can be used.

  On the other hand, when particularly high performance characteristics are required, it may be fabricated on an InP substrate. It is desirable that the conductive layer and the i layer of the ESD protection element are lattice-matched with the InP substrate, respectively. For example, InGaAsP or the like can be used for the conductive layer. At this time, for example, InP, InAlAs, or the like can be used for the i layer.

  The ESD protection element can be manufactured by regrowth with respect to the transistor, or can be manufactured by crystal growth at the same time as the transistor.

  Since the ESD protection element is integrated in parallel in the compound semiconductor element according to the present invention, a current flows through the ESD protection element when static electricity is applied to the compound semiconductor element. Therefore, the compound semiconductor element can be protected from static electricity. In addition, since the increase in capacitance can be minimized, the compound semiconductor element can be operated at high speed.

  Next, the structure of the compound semiconductor device according to Example 1 of the present invention will be described below with reference to FIG. Here, an example in which the present invention is applied to a high-frequency circuit formed on a GaAs substrate will be described. In this compound semiconductor element, an FET of an input part of a high frequency circuit used for a high frequency analog circuit or a radio and an ESD protection element are integrated.

  In the compound semiconductor device 1 shown in FIG. 2, an n-type buffer layer 102, an n-type channel layer 103 made of GaAs, a Schottky layer 104 made of AlGaAs, an n-type contact layer 105, a source on a semi-insulating substrate 101 made of GaAs. An FET portion including an electrode 106, a drain electrode 107, and a gate electrode 108 is formed.

  In other regions on the semi-insulating substrate 101, an n-type conductive layer 109 made of GaAs, an n-type low concentration layer 110 made of GaAs, an undoped layer 111 made of AlGaAs or InAlGaP, and an n-type low concentration layer made of GaAs. 112, an ESD protection unit 114 including an n-type conductive layer 113 made of GaAs is formed. A dielectric protective film 115 is formed on the side surface of each mesa. Electrodes 116 and 117 are formed on the ESD protection unit 114. Here, the electrode 117 is connected to the power supply Vcc, and the electrode 116 is connected to the gate electrode 108 of the FET portion.

  In the compound semiconductor device 1, FETs whose drain / source current is controlled by applying a voltage to the gate electrode 108 are integrated. As an ESD countermeasure, an ESD protection element having a nin structure in which an undoped layer 111 is sandwiched between two n-type conductive layers 109 and 113 is integrated in parallel with the FET between the gate of the FET and the power supply.

  Next, the operation of the FET unit according to the first embodiment will be described based on the calculation results of FIGS. As the high-frequency signal, a differential signal such as LVDS is often used. The differential signal has an effect that noise can be removed during transmission. In addition, in order to remove common mode noise from the ground, a predetermined common mode voltage other than 0 V is often applied. That is, a differential signal with a common mode voltage of 0 V may be input to the gate electrode 108, or a differential signal with a common mode voltage of 0 V may be input.

  Here, the FET section is often used with a power supply voltage of 3.3V. Further, it is about 10 V when used in a higher output amplifier or the like. When the power supply voltage is 3.3V, the maximum voltage between the gate of the FET section and the power supply or ground is 3.3V. If the input signal is AC coupled, the common mode voltage of the input unit is 0 V, and a voltage of 3.3 V is applied between the gate of the FET unit and the power supply during operation. At the same time, 3.3 V is also applied between the electrodes 116 and 117 of the ESD protection unit 114 connected in parallel.

  The operation of the ESD protection unit 114 will be described. When no bias voltage is applied between the electrodes 116 and 117, such as when the power is turned off or before mounting, the undoped layer 111 contains a small amount of impurities and hardly has a built-in electric field. So it is hardly depleted. For this reason, the capacitance is theoretically larger than the capacity calculated from the thickness of the undoped layer 111.

  In addition, when a static electricity is applied, unlike a human body model, a machine model used in a static electricity application test (model used when contacting a machine charged with static electricity) has almost no contact resistance. When a voltage is applied, the rising of the applied voltage is as fast as nanoseconds and thus has a high frequency component.

  On the other hand, the gate electrode 108 of the FET is Schottky connected, and the gate current hardly flows. Therefore, when ESD is applied, a certain amount of charge is further applied after the gate voltage rises. In this case, the ESD protection unit 114 side first undergoes avalanche breakdown, and a current flows through the ESD protection unit 114. Therefore, a high voltage is not applied to the FET portion. Since the ESD protection unit 114 is structurally symmetrical in the vertical direction, it can cope with either forward or reverse static electricity.

  In this embodiment, n-type low concentration layers 110 and 112 are introduced between the undoped layer 111 and the two n-type conductive layers 109 and 113. Since the n-type low concentration layers 110 and 112 are depleted even at a low bias, it contributes to a reduction in capacitance. In this embodiment, since the n-type low concentration layers 110 and 112 are 0.3 μm and 0.8 μm is depleted together with the undoped layer 111, the capacity can be significantly reduced.

  On the other hand, it is necessary to prevent current (leakage current) from flowing through the ESD protection unit 114 when the bias voltage of the compound semiconductor element 1 is applied. Therefore, it is desirable that current does not flow through the ESD protection unit 114 below the bias voltage, and current flows when a certain voltage is exceeded.

  FIG. 3A shows the result of analyzing the layer thickness dependence of the undoped layer 111 of the leakage current. The horizontal axis is the bias voltage, and the vertical axis is the leakage current. The value inside the graph is the layer thickness (unit: μm) of the AlGaAs undoped layer 111. As shown in this analysis result, even if the undoped layer 111 is as thin as 0.1 μm, the leakage current can be sufficiently reduced. Although the calculation result in FIG. 3A is for the case where the composition of the undoped layer 111 is InGaAsP, the important point is the discontinuous potential between the bands of the conduction band. That is, the same effect can be expected because a barrier with the same potential can be made even in the InP system.

  FIG. 3B shows the Al composition dependence of the undoped layer 111 of the leakage current in the nin structure. When the Al composition of the AlGaAs undoped layer 111 is 0.4 or more, the leakage current can be greatly reduced. Here, since the Al composition is changed from direct transition to indirect transition between 0.4 and 0.5, the leakage current is smaller when the Al composition is 0.4 than when 0.5. When the Al composition is 0.5 or more, the higher the Al composition, the smaller the leakage current.

  FIG. 3C similarly shows the Al composition dependency of the undoped layer 111 of the leakage current in the pip structure. In the case of AlGaAs (undoped layer) and GaAs (conductive layer), the discontinuity of the conduction band becomes smaller. Therefore, in the case of the pip structure, it is necessary to increase the Al composition. Specifically, the Al composition needs to be 0.5 or more.

  The first embodiment has a nin structure formed on a semi-insulating substrate 101 made of GaAs. In the case of n-type, a sufficient effect can be obtained when the energy difference of the conduction band depending on the composition is 0.3 eV or more. If a material having this energy difference is selected, the undoped layer 111 is not limited to AlGaAs but may have other compositions that lattice match with GaAs. For example, InAlP and InGaP can be exemplified.

In addition, since impurities cannot be eliminated completely, there are actually background impurities in the undoped layer 111 of AlGaAs. In the nin structure, if the background impurity of the undoped layer (i layer) 111 is n-type, leakage current is likely to occur. Therefore, it is desirable that the background impurity of the undoped layer 111 is low concentration and p-type. However, if the background impurity of the undoped layer 111 is high, breakdown is difficult to occur and the breakdown voltage becomes high. This is because the semiconductor laser cannot be protected from static electricity. Specifically, the concentration of the p-type impurity in the undoped layer 111 is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

Next, a method for manufacturing the compound semiconductor device 1 according to Example 1 will be described. First, as shown in FIG. 4A, on a semi-insulating substrate 101 made of GaAs, an n-type buffer layer 102, an n-type channel layer 103 made of GaAs, a Schottky layer 104 made of AlGaAs, and a thickness 0. 5 μm n-type contact layer 105 and n-type conductive layer 109 (doping concentration 1 × 10 ¹⁸ cm ⁻³ ), 0.3 μm thick n-type low concentration layer 110 (doping concentration 1 × 10 ¹⁷ cm ⁻³⁾ ), An undoped layer 111 made of AlGaAs having a thickness of 0.5 μm, an n-type low concentration layer 112 made of GaAs having a thickness of 0.3 μm (doping concentration 1 × 10 ¹⁷ cm ⁻³ ), and a thickness of 0.5 μm made of GaAs. N-type conductive layer 113 (doping concentration 1 × 10 ¹⁸ cm ⁻³ ) of metal organic chemical vapor deposition (MOCVD) (Sequence 1).

  Next, as shown in FIG. 4B, the region from which the ESD protection portion 114 is formed is left, and the portions from the n-type conductive layer 113 to the n-type low concentration layer 110 are removed by etching (step 2). At this time, the n-type contact layer 105 and the n-type conductive layer 109 may be partially etched. Next, leaving the regions for forming the ESD protection part 114, the source electrode 106, and the drain electrode 107, the n-type contact layer 105 and the n-type conductive layer 109 are removed by wet etching to form a recess (step 2).

Next, as shown in FIG. 4C, after depositing a dielectric protective film 115 made of SiO ₂ on the entire surface, the dielectric protective film 115 in the region where the gate electrode 108 is to be formed is removed by dry etching. Subsequently, after the Schottky layer 104 is etched by about 5 nm using the dielectric protective film 115 as a mask, WSi and Au are sputter-deposited, and unnecessary portions are removed by ion milling to form the gate electrode 108 (step 3). ).

Then, after depositing a SiO ₂ layer (not shown) again entirely, the SiO ₂ layer of each electrode forming region is removed by etching.

  Subsequently, the source electrode 106, the drain electrode 107 of the FET portion, and the electrodes 116, 117 of the ESD protection portion 114 are formed. AuGe, Ni, and Au are deposited as ohmic electrodes for the n-type contact layer 105 made of GaAs. Finally, the electrode 117 of the ESD protection unit 114 and the gate electrode 108 of the FET unit, and the ESD protection unit 114 and the power supply unit are wired and connected by TiAu.

  The compound semiconductor device 1 shown in FIG. 2 can be manufactured through the above steps. The compound semiconductor device 1 includes a nin type ESD protection unit 114, but can also be manufactured in a pip type. In this case, current flows due to movement of holes. Therefore, unlike the nin structure, the valence band structure is important. Since the effective mass of holes is larger than that of electrons, a sufficient effect can be obtained even if the energy difference in the valence band is small. In this case, an energy difference of 0.3 eV required for the n-type may be 0.2 eV for the p-type. As long as this energy difference is obtained, not only the combination of GaAs and AlGaAs, but also a combination of compositions that lattice-match with other GaAs may be used. For example, a combination of InAlP and InGaP can be exemplified.

  Note that the entire high-frequency circuit is composed of a plurality of FETs, and each FET is designed and wired according to a desired circuit configuration. FIG. 2 shows only the ESD protection element (ESD protection unit 114) and the FET connected thereto. Actually, an ESD protection element may be provided in each FET of the input part or output part of the high-frequency signal in the same high-frequency circuit.

  Next, the structure of the compound semiconductor device according to Example 2 of the present invention will be described with reference to FIG. Here, an example in which the present invention is applied to a high-frequency circuit formed on a GaAs substrate will be described. In this compound semiconductor element, an HBT having a heterojunction of GaAs / InGaP between an emitter and a base formed on a GaAs substrate and an ESD protection element are integrated.

  The compound semiconductor device 2 shown in FIG. 5 includes an n-type subcollector layer 202 made of GaAs, an n-type collector layer 203 made of GaAs, a p-type base layer 204 made of GaAs, and an InGaP on a semi-insulating substrate 201 made of GaAs. An n-type sub-emitter layer 205 made of GaAs, an n-type emitter layer 206 made of GaAs, an n-type contact layer 207 made of InGaAs, an emitter electrode 208, a base electrode 209, and a collector electrode 210.

  Similarly to the first embodiment, the ESD protection unit 216 includes an n-type conductive layer 211 made of GaAs, an n-type low concentration layer 212 made of GaAs, an undoped layer 213 made of AlGaAs, and an n-type low concentration layer 214 made of IGaAs. And an n-type conductive layer 215 made of GaAs.

  Next, the operation of the HBT according to the second embodiment will be described. It has a structure in which a diffusion current is made at the heterojunction between the emitter and the base, and operates in the same manner as a general Si-based npn bipolar transistor. In this HBT, the thickness of the p-type base layer 204 and the p-type impurity concentration are important for high-speed operation, and are different from FETs that require fine processing. Therefore, it is appropriately selected and used according to the use and cost. In DHBT or the like oriented to high-speed operation, the base layer needs to be thin, and the breakdown voltage between the collector and the emitter cannot be increased. Therefore, 3.3V is often used as the power supply voltage, and the circuit design is made so that no voltage is applied between the collector and the emitter.

  The ESD protection unit 216 of the second embodiment has the same nin structure as that of the first embodiment. Also in this example, n-type low concentration layers 212 and 214 are introduced between the undoped layer 213 and the two n-type conductive layers 211 and 215, respectively. Since the n-type low concentration layers 211 and 215 are depleted even at a low bias, it contributes to a reduction in capacitance. In this embodiment, since the n-type low concentration layers 212 and 214 are 0.3 μm and 0.8 μm is depleted together with the undoped layer 213, the capacitance can be greatly reduced.

  Next, a method for manufacturing the compound semiconductor element 2 according to Example 2 will be described. First, similarly to Example 1, the n-type subcollector layer 202 to the n-type contact layer 207 are sequentially stacked on the semi-insulating substrate 201 made of GaAs by MOCVD method or MBE (Molecular Beam Epitaxy) method. Silicon was used as the n-type dopant, and carbon was used as the p-type dopant.

  Next, the region for forming the HBT portion is left and removed by dry etching or wet etching. Next, the ESD protection part is formed by regrowth. This process is almost the same as in the first embodiment.

The n-type doping concentration of the two n-type low concentration layers 212 and 214 of the ESD protection unit 216 is 1 × 10 ¹⁷ cm ^−3, and the n-type doping concentration of the two n-type conductive layers 211 and 215 is 1 × 10 ¹⁸ cm. ^-3 .

  Next, a resist mask is formed on the ESD protection part 216 and the HBT part by a photolithography technique, and then an element isolation groove is formed. Thereafter, each region of the HBT portion and the ESD protection portion 216 is formed by etching. Next, after forming the dielectric protective film 217 on the entire surface, each electrode is formed. Finally, it is completed through wiring processes such as connection between the base electrode 209 and the electrode 219 of the ESD protection unit 216 and connection between the electrode 218 of the ESD protection unit 216 and the power supply Vcc.

  Through the above steps, the compound semiconductor element 2 shown in FIG. 5 can be manufactured. The entire high frequency circuit is composed of a plurality of HBTs, and each HBT is designed and wired according to a desired circuit configuration. FIG. 5 illustrates only the ESD protection element (ESD protection unit 216) and the HBT connected thereto. Actually, an ESD protection element may be provided in each HBT of the input part or output part of the high-frequency signal in the same high-frequency circuit.

  In the first and second embodiments, the structure of the ESD protection element formed on the GaAs substrate has been described. These are examples comprising a combination of GaAs (n-type conductive layer) and AlGaAs (undoped layer), which can be easily manufactured as an ESD protection element. However, the combination is not limited to the above embodiment as long as a nin structure or a pip structure and a wide forbidden band width of the i layer can be used. For example, InAlP or InGaP may be combined. Further, in a higher performance compound semiconductor device using an InP substrate, if lattice matching with the InP substrate is performed, for example, a combination of InGaAsP (n-type conductive layer) and InP (undoped layer) or InGaAs (n-type conductive layer) A combination with InAlGaAs (undoped layer) may be used.

1, 2 Compound semiconductor elements 101, 201 Semi-insulating substrate 102 n-type buffer layer 103 n-type channel layer 104 Schottky layer 105 n-type contact layer 106 source electrode 107 drain 108 gate electrodes 109, 211 n-type conductive layers 110, 212 n-type low-concentration layers 111, 213 undoped layers 112, 214 n-type low-concentration layers 113, 215 n-type conductive layers 114, 216 ESD protection portions 115, 217 Dielectric protective films 116, 117, 218, 219 Electrodes of ESD protection portions 202 n-type subcollector layer 203 n-type collector layer 204 p-type base layer 205 n-type emitter layer 206 n-type sub-emitter layer 207 n-type contact layer 208 emitter electrode 209 base electrode 210 collector electrode

Claims (9)

A transistor portion comprising a field effect transistor or a heterojunction bipolar transistor;
An ESD protection unit connected in parallel with the transistor unit,
The ESD protection unit is
First and second semiconductor layers containing impurities of a first conductivity type;
Formed between the first and second semiconductor layers, having a forbidden band wider than the forbidden band of the first and second semiconductor layers, and having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less. A compound semiconductor device comprising: a third semiconductor layer.   The first conductivity type is n-type, and the energy difference between the conduction band of the third semiconductor layer and the conduction bands of the first and second semiconductor layers is 0.3 eV or more. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is provided.   The first conductivity type is p-type, and the energy difference between the conduction band of the third semiconductor layer and the conduction bands of the first and second semiconductor layers is 0.2 eV or more. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is provided. An impurity concentration of the first conductivity type of the first and second semiconductor layers is 1 × 10 ¹⁸ cm ⁻³ or more;
The first conductive type impurity is contained between each of the first and second semiconductor layers and the third semiconductor layer, and the concentration thereof is higher than the concentration in the third semiconductor layer and 1 × 10 ¹⁷ cm ^-3 or less fourth and compound semiconductor device according to claim 1 in which the fifth semiconductor layer, characterized in that it is formed. 5. The compound semiconductor element according to claim 1, wherein an impurity concentration of a second conductivity type in the third semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or less.   The compound semiconductor element according to claim 1, wherein a thickness of the third semiconductor layer is 0.1 to 1.0 μm.   The compound according to any one of claims 1 to 6, wherein the first and second semiconductor layers are made of GaAs, and the third semiconductor layer is made of any one of AlGaAs, InAlP, and InGaP. Semiconductor element.   The first and second semiconductor layers are made of InP, InAlGaAs, or InGaAsP, and the third semiconductor layer is made of InAlAs or InGaAsP. Compound semiconductor device. Forming a transistor portion comprising a field effect transistor or a heterojunction bipolar transistor;
Forming an ESD protection part connected in parallel with the transistor part,
The step of forming the ESD protection part includes:
Forming a first semiconductor layer containing an impurity of a first conductivity type;
Forming a second semiconductor layer containing an impurity of the first conductivity type;
Located between the first and second semiconductor layers, the forbidden band width is wider than that of the first and second semiconductor layers, and the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less. Forming a third semiconductor layer. A method for manufacturing a compound semiconductor element.

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