JP2010140127A - Data transfer processing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a logical scale from being increased in performing specific data processing by a hardware circuit in parallel with the data transfer of a non-aligned data unit. <P>SOLUTION: A data processing circuit and an aligner for the data processing circuit are installed at a position different from the transfer path of a data unit. The aligner for the data processing circuit is configured to align the address of the data unit input to the aligner so that non-transfer object data is prevented from being included in the leading section of the aligned data unit. The transferred data unit is input to the aligner for the data processing circuit in parallel with the data transfer, and the address of the data in the input data unit is aligned, and the aligned data unit is input to the data processing circuit by the input data width unit of the data processing circuit, and the aligned data unit input to the data processing circuit is processed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to data transfer processing, and specifically relates to data transfer processing in a communication interface device such as a host bus adapter (HBA) provided in an information processing device such as a server.

  An information processing apparatus such as a server is equipped with a communication interface apparatus as disclosed in Patent Document 1, for example. The information processing device communicates with an external device such as an external storage device via the communication interface device.

JP 2002-183072 A

  The information processing apparatus may be provided with a data transfer processing apparatus called a direct memory access controller (DMAC) from the viewpoint of improving the performance of the entire information processing apparatus. In the DMAC, data transfer is performed in place of a CPU (Central Processing Unit).

  FIG. 10 shows an example of the configuration of the DMAC.

  The DMAC 10 is, for example, a communication interface device (for example, a host bus adapter (HBA)) for communicating with an external storage device (for example, a disk array device) 20. The DMAC 10 communicates with the external storage device 20 and communicates with information processing resources including the CPU 31 and the main memory 22 via the internal bus 32.

The DMAC 10 includes, for example, the following components (1) to (5),
(1) a reception buffer 11 for temporarily storing data blocks read from the external storage device 20;
(2) a DMA control unit 21 that transfers a data block stored in the reception buffer 11 to an information processing resource (for example, main memory 22) in a predetermined transfer unit;
(3) a transmission buffer 12 for temporarily storing data blocks to be written to the external storage device 20;
(4) DMA control unit 22 for transferring data blocks stored in information processing resources (for example, main memory 22) to transmission buffer 12 in a predetermined transfer unit;
(5) a microprogram control unit 13 for controlling the operation of the DMAC 10;
Is provided. One or both of the reception buffer 11 and the transmission buffer 12 are provided from the viewpoint of improving the data transfer performance by increasing the multiplicity of transmission and reception. The microprogram control unit 13 includes a CPU, a local memory, and the like. The microprogram control unit 13 sets a data transfer start command in the DMA control unit 21 or 22. Thereby, the DMA control unit 21 or 22 interprets the start command and performs data transfer. For this reason, the microprogram control unit 13 can perform another process, and the performance of the information processing apparatus 30 as a whole is improved.

  Since the transmission / reception buffers 11 and 12 exchange data with the external storage device 20, information for control is added in addition to data for each interface standard. For this reason, the data in the transmission / reception buffers 11 and 12 are not necessarily aligned.

  Also, the memory address in the information processing apparatus 30 that is the data transfer destination or transfer source is specified by an application program in the information processing resource. For this reason, there is a possibility that the memory addresses in the information processing resource serving as the transfer destination or transfer source are shifted from the transmission / reception buffers 11 and 12 and are not aligned.

  For the above reasons, it is necessary to perform data transfer corresponding to the case where alignment is not performed. Therefore, as shown in the DMA control unit 21 (22) in FIG. 10, the aligner 14 (15) is provided on the data transfer path, and the data unit from the transfer source to the transfer destination passes through the aligner 14 (15). . As a result, the data address in the data unit is aligned with the address designated by the transfer destination, and the aligned data unit is transferred to the transfer destination. Specifically, for example, as shown in FIG. 2, data units are read from the transfer source in the order of “AB”, “CDEF”, “GHIJ”, “KLMN”, “OP”, and the aligner 14 (15). Then, the aligned data units “ABC”, “DEFG”, “HIJK”, “LMNO”, “P” are transferred to the transfer destination. The “data unit” referred to here is data having a transfer unit size, specifically, a set of four 4-byte data, and thus the size of the data unit is 16 bytes. Further, the above-mentioned 4 bytes of data A to P (data displayed in gray blocks in FIG. 2) are data (data to be transferred) required at the transfer destination, and transfer in one data unit. Data other than the target data (data displayed in white blocks in FIG. 2) is data that is not required at the transfer destination (non-transfer target data).

  In data transfer, data inspection is required to improve reliability. One of the typical data inspection methods is a cyclic redundancy check. In the cyclic redundancy check, a check code is generated by applying a generator polynomial to a data block of a predetermined size. For example, at the transfer source, a check code of another predetermined size is added to a data block of a predetermined size, and a set of data blocks and check codes (hereinafter, data / code set) is sent to the transfer destination. At the transfer destination, the generator polynomial is applied to the data block in the data / code set that is sent, so that the check code is generated again, and the generated check code is the check code in the data / code set. It is determined whether or not they match. In this way, data integrity is guaranteed.

  The cyclic redundancy check is defined in various interface standards, and a generator polynomial and a calculation method for generating a check code are respectively determined.

  As an example of the cyclic redundancy check, there is a DIF (Data Integrity Field) of a SCSI (Small Computer System Interface) interface. In DIF, for example, an 8-byte check code is added to a data block for every 512 bytes. The 8-byte check code is composed of arbitrary 6-byte tag information and a 2-byte cyclic redundancy check code, and the cyclic redundancy check code can be generated by applying the following generator polynomial to a 512-byte data block. (X16 + x15 + x11 + x9 + x8 + x7 + x5 + x4 + x2 + x + 1).

  In the DMAC 10 shown in FIG. 10, since the data / code set is temporarily stored in the buffer 11 (12), the microprogram control unit 13 receives the data / code set from the buffer 11 (12) before data transfer. By reading, it is possible to check or generate a check code by DIF.

  However, if the microprogram control unit 13 inspects or generates the check code by the DIF, the buffer 11 (12) is occupied during the processing, and the multiplicity of transmission / reception is lowered. It is assumed that the performance of the DMAC 10 is degraded due to the execution of the microprogram processing that has not been performed.

  As a method for preventing the performance degradation of the DMAC 10, it is conceivable to perform data transfer and check code inspection or generation in parallel.

  In order to inspect or generate a DIF check code in parallel with data transfer, a hardware circuit (hereinafter referred to as DIF circuit) for inspecting or generating a check code is provided, and when a data unit is read from a transfer source, or A method of inputting the data unit to the DIF circuit at the same timing when writing the data unit to the transfer destination can be considered. In other words, a method of providing a DIF circuit on the upstream side (transfer source side) or the downstream side (transfer destination side) of the aligner 14 (15) shown in FIG. 10 on the data transfer path can be considered.

  FIG. 3 shows an example of inputting the data unit to the DIF circuit when writing the data unit to the transfer destination. For the first data unit “ABC”, a DIF circuit for 12-byte data is required. This is because the number of transfer target data is 3, and 3 × 4 bytes = 12 bytes is the size of the transfer target data group. For the same reason, a DIF circuit for 16-byte data is required for the following data units “DEFG”, “HIJK”, and “LMNO”, and 4 bytes for the last “P” data unit. A DIF circuit having a data width is required.

  In this way, if the check code is inspected or generated for an unaligned data unit at the same timing as the data transfer, the fractional data (in the first data unit and the last data unit of the transfer is included in each data block). (Non-transfer target data) may appear. For this reason, as shown in FIG. 6, it is necessary to prepare a plurality of types of DIF circuits corresponding to a plurality of types of fraction data width (the size of the fraction data group, in other words, the number of fraction data). Increasing the logical scale is an issue.

  The above problem is that the processing in the check code generation circuit other than the DIF circuit or the data processing circuit other than the check code generation circuit (for example, a hardware circuit for performing encryption processing) is transferred from the transfer source to the transfer destination. This is a problem that may occur when an attempt is made at the same timing as the data transfer.

  Accordingly, an object of the present invention is to prevent the logical scale from increasing when specific data processing is performed by a hardware circuit in parallel with data transfer of unaligned data units.

  A data processing circuit for processing the input data unit and an aligner for the data processing circuit are provided at a position different from the transfer path of the data unit transferred from the transfer source to the transfer destination in a predetermined transfer unit. . The aligner for the data processing circuit is configured to align the address of the data unit input to the aligner so that the non-transfer target data is not included in the head portion of the aligned data unit. In parallel with the data transfer, the data unit to be transferred is input to the aligner for the data processing circuit, the address of the data in the input data unit is aligned, and the aligned data unit is the input data width of the data processing circuit The unit is input to the data processing circuit, and the aligned data unit input to the data processing circuit is processed.

  As the data processing circuit, various circuits such as an error detection circuit and an encryption processing circuit can be employed. As the encryption processing circuit, for example, a circuit that performs encryption using CFB (Cipher FeedBack) can be employed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows an information processing apparatus according to an embodiment of the present invention.

  The information processing apparatus 300 includes a DMAC 100 that connects information processing resources (such as the CPU 310 and the main memory 220) connected to the internal bus 320, the external storage device 200, and the information processing apparatus 300 to perform data transfer. The external storage device 200 is, for example, a storage system (for example, a disk array device) including a plurality of physical storage media (for example, a hard disk or a flash memory). The information processing device 300 is, for example, a host device (for example, a server) that reads / writes data in block units from / to a logical volume provided from the external storage device 200. The DMAC 100 is, for example, a host bus adapter (HBA).

  The DMAC 100 includes a reception buffer 110, a transmission buffer 120, a DIF circuit 152, a microprogram control unit 130, and DMA control units 210 and 211.

  The reception buffer 110 has a function of receiving the data read from the external storage device 200, storing the received data, and receiving and storing all the data, and reporting the reception completion to the microprogram control unit 130. On the other hand, the transmission buffer 120 has a function of storing data to be written in the external storage device 200 and reporting the completion of transmission to the microprogram control unit 130 when all the data in the buffer 120 has been transmitted. A plurality of at least one of the reception buffer 110 and the transmission buffer 120 are provided, so that transmission / reception is not disabled due to a buffer shortage in transmission and / or reception. In the present embodiment, it is assumed that a data / code set in which an 8-byte check code is added to a 512-byte data block is stored in the reception buffer 110.

  The microprogram control unit 130 includes a CPU, a local memory, and the like, and executes a microprogram for controlling the DMAC 100 by the CPU. As one of the functions of the microprogram, there is a function of issuing a data transfer instruction between the transmission / reception buffers 110 and 120 and the main memory 220 when receiving a reception or transmission completion report.

  The DIF circuit 152 is a circuit for adding a check code to the transmitted data block. The DIF circuit 152 generates a check code based on the data block read from the transmission buffer 120. The generated check code is read from the transmission buffer 120, added to the data block flowing through the data transfer path, and transmitted to the external storage device 200. The DIF circuit 152 is provided at a position different from the data transfer path. Whether the data block read from the transmission buffer 120 passes through the DIF circuit 152 in addition to the data transfer path is controlled by the microprogram control unit 120.

  One feature of this embodiment is the configuration of the DMA control unit 210 (211). That is, in addition to the data transfer aligner 140 (142) provided on the data transfer path, the DMA control unit 210 (211) has a DIF circuit 150 (151) at a position different from the data transfer path. , An aligner 141 (143) for the DIF circuit is provided. Such a configuration may be employed only in one of the reception-system DMA control unit 210 and the transmission-system DMA control unit 211, and the other may be, for example, the configuration of the DMA control unit 21 or 22 shown in FIG. . Hereinafter, the aligner for data transfer is referred to as “first aligner”, and the aligner for DIF circuit is referred to as “second aligner”. Whether the data block is input to both the first aligner 140 (142) and the second aligner 141 (143) in parallel is controlled by the microprogram control unit 120.

  The first aligner 140 (142) performs alignment according to the transfer destination. In this embodiment, the size of the transfer unit is 16 bytes.

  The DIF circuit 150 (151) is a hardware circuit for inspecting or generating a check code. The input data width of the DIF circuit 150 (151) is a fixed length and a divisor of the size of the fixed length data block. In this embodiment, the size of the data block is 512 bytes, and the input data width is 16 bytes which is the same as the size of the transfer unit. That is, it is the same as the size of the transfer unit.

  The second aligner 141 (143) performs alignment in accordance with the DIF circuit 150 (151), not the transfer destination. Specifically, the second aligner 141 (143) performs alignment according to the input data width of the DIF circuit 150 (151). The second aligner 141 (143) is provided on the upstream side (for example, immediately before) of the DIF circuit 150 (151). In other words, in the DMA controller 210 for the reception system, the second aligner 141 is located closer to the reception buffer 110 than the DIF circuit 150. In the DMA controller 211 for the transmission system, the second aligner 143 is connected to the DIF circuit 151. Rather than the main memory 220 side.

  FIG. 4 shows an example in which the first aligner 140 (142) and the second aligner 141 (143) are used simultaneously.

  That is, in the data transfer from the transfer source (reception buffer 110 or main memory 220) to the transfer destination (main memory 220 or transmission buffer 120), the data unit is transferred in units of transfer from the transfer source to the transfer destination. In order to pass through the first aligner 140 (142), alignment according to the transfer destination is performed. That is, data units read in the order of “AB”, “CDEF”, “GHIJ”, “KLMN”, “OP” from the transfer source are “ABC”, “DEFG”, “HIJK”, “LMNO”, “LMNO”, Aligned as “P”.

In parallel with the data transfer from the transfer source to the transfer destination, the following processes (A) to (D):
(A) The data unit read from the transfer source is input to the second aligner 141 (143);
(B) The second aligner 141 (143) aligns the address of the data in the data unit input to the second aligner 141 (143);
(C) The data unit after alignment by the second aligner 141 (143) is input to the DIF circuit 150 (151) in units of the input data width of the DIF circuit 150 (151);
(D) The aligned data unit input to the DIF circuit 150 (151) is processed;
Is done. That is, data transfer and the processes (A) to (D) described above are performed in synchronization with the clocks generated at the same time.

  The second aligner 141 (143) reads the data units read from the transfer source in the order of “AB”, “CDEF”, “GHIJ”, “KLMN”, “OP” in the order of “ABCD”, “EFGH”, Align like “IJKL”, “MNOP”. That is, the second aligner 141 (143) is a data unit input to the aligner 141 (143) so that fraction data (non-transfer target data) is not included in the head portion of the aligned data unit. It is configured to align the addresses. Examples of the fraction data include frame header information.

  In DIF, an 8-byte check code is added to a 512-byte data block. Therefore, in accordance with the DIF circuit 150 (151) having an input data width of 16 bytes, if alignment is performed so that fraction data is not included in the head portion of the data unit as in the present embodiment, 512 bytes ÷ 16 bytes = All 32 data units do not contain fractional data. Further, although an 8-byte check code is added to the 512-byte data block, the 8-byte check code is always present in the first half (upper half) of the 33rd 16-byte data unit in this embodiment. For this reason, every time 32 data units are input, the DIF circuit 150 (151) is attached to the first half of the data unit to be input next to a data block composed of these 32 data units. You can see that there is a check code. For these reasons, in this embodiment, it is not necessary to prepare a plurality of types of DIF circuits corresponding to a plurality of types of fraction data widths, and one type of DIF circuit 150 (151) as shown in FIGS. That is, the DIF circuit 150 (151) having an input data width of 16 bytes is sufficient.

  According to FIG. 7, when the initial value s of the DIF calculation is stored in the register 701 and the first data unit after alignment (“ABCD” in the embodiment) is input for one data block, A value calculated based on the data unit and the initial value s is stored in the register 701. Next, it is calculated based on the value and the data unit after the next alignment (“EFGH” in the embodiment), and a value representing the calculation result is stored in the register 701. The above processing is performed for 32 data units, and for the 33rd data unit, the comparator 703 checks the value stored in the register 301 (that is, the check generated based on the 512-byte data block). Code) and a value (that is, a check code added to the 512-byte data block) existing in the first half of the 33rd data unit. As described above, since the 8-byte check code is always present in the first half (upper half) of the 33rd 16-byte data unit in this embodiment, the check code position can be easily determined.

  From the above, it is possible to prevent the logical scale from increasing when the check code is inspected or generated by the DIF circuit in parallel with the data transfer of the unaligned data units.

  FIG. 8 shows a flow of transferring the data / code set stored in the reception buffer 110 from the external storage device 200 to the information processing device 300.

  The reception buffer 110 reports the completion of data storage to the microprogram control unit 130 (step 801), and the microprogram control unit 130 receives the report and issues a DMA activation instruction and a check code check instruction to the DMA control unit 210. (Step 802). As a result, the above-described processing (A) to (D) (check code inspection) is performed in parallel with the data transfer from the reception buffer 110 to the main memory 220 (step 803). When these processes are completed, a completion report is input from the DMA control unit 210 to the microprogram control unit 130 (step 804), and the microprogram control unit 130 performs a DMA end process (step 805).

  FIG. 9 shows a flow of transferring data to the transmission buffer 120 in order to send data from the information processing device 300 to the external storage device 200.

  The microprogram control unit 130 requests the transmission buffer 120 to secure the buffer (step 901), receives the completion of securing the buffer (step 902), and issues a DMA activation instruction (step 903). As a result, the data transfer from the main memory 220 to the transmission buffer 120 and the processes (A) to (D) described above (check code check) are performed in parallel with the data transfer (step 904). When these processes are completed, a completion report is input from the DMA control unit 211 to the microprogram control unit 130 (step 905), and the microprogram control unit 130 performs a DMA end process (step 906).

  Note that at least one of steps 803 and 904 does not necessarily require the check code to be inspected. In other words, whether or not to check the check code is controlled by an instruction from the microprogram control unit 130 to the DMA control unit 210 (211).

  For example, when the check code is not added to the data block from the transfer source, the microprogram control unit 130 may control the data unit from the transmission source not to be input to the second aligner 141 or 143. .

  Further, for example, when the check code is not added to the data block from the transfer source, the microprogram control unit 130 inputs the data unit from the transmission source to the second aligner 141 or 143, and the DIF circuit The DMA control unit 210 or 211 may be controlled to add the check code generated in 151 to the data block via the first aligner 140 or 142.

Also, for example, when a check code is added to the data block from the transfer source, the microprogram control unit 130 inputs the data unit from the transmission source to the second aligner 141 or 143, and the DIF circuit The DMA control unit 210 or 211 may be controlled to delete the check code checked in 151 from the data block to be transferred. In this case, the DIF circuit 151 does not have to check the check code.
The DIF check is not unnecessary.

  As mentioned above, although preferred embodiment of this invention was described, it cannot be overemphasized that this invention can be variously changed in the range which is not limited to this embodiment and does not deviate from the summary.

  For example, if the size of the transfer unit is N times the input data width (N is a natural number), the clock cycle for data transfer is performed after the process (C) (after alignment by the second aligner 141 (143)). The data unit is 1 / N times the clock cycle for the input data width unit of the DIF circuit 150 (151) to the DIF circuit 150 (151). Therefore, for example, if the size of the transfer unit is twice the input data width, the clock cycle for data transfer is ½ times the clock cycle for the process (C). On the other hand, if the input data width is M times the size of the transfer unit (M is a natural number), the clock cycle for the process (C) is 1 / M times the clock cycle for data transfer. . Therefore, for example, if the input data width is twice the size of the transfer unit, the clock cycle for the process (C) is ½ times the clock cycle for data transfer.

1 shows an information processing apparatus according to an embodiment of the present invention. It is the figure which showed the example of transfer of the data unit which is not aligned. FIG. 3 is a diagram showing an example of inputting data to a DIF circuit when writing to a transfer destination in the data transfer of FIG. 2. It is the figure which showed the example of the data transfer at the time of implementing the alignment for DIF circuits in one Embodiment of this invention. It is the figure which showed the example which performs DIF calculation at the time of implementing the alignment shown in FIG. FIG. 4 is a diagram illustrating a hardware configuration related to the DIF calculation illustrated in FIG. 3. FIG. 6 is a diagram illustrating a hardware configuration related to the DIF calculation illustrated in FIG. 5. It is the figure which showed the data transfer flow from a receiving buffer to main memory. It is the figure which showed the data transfer flow from the main memory to the transmission buffer. 1 shows an information processing apparatus including a DMAC in which a microprogram control unit performs DIF calculation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... DMAC (direct memory access controller), 110 ... Reception buffer, 120 ... Transmission buffer, 130 ... Microprogram control part, 140 ... Aligner, 141 ... Aligner, 142 ... Aligner 143 Aligner 150 DIF circuit 151 DIF circuit 152 DIF circuit 200 External storage device 300 Information processing device 310 Central processing unit, 320 ... main memory

Claims (6)

A data processing circuit for processing the input data unit and an aligner for the data processing circuit are provided at a position different from the transfer path of the data unit transferred from the transfer source to the transfer destination in a predetermined transfer unit,
The aligner for the data processing circuit is configured to align the address of the data unit input to the aligner so that the non-transfer target data is not included in the head portion of the aligned data unit. ,
In parallel with the data transfer from the transfer source to the transfer destination,
(A) The data unit to be transferred is input to the aligner for the data processing circuit,
(B) The address of the data in the data unit input to the aligner for the data processing circuit is aligned,
(C) A data unit after alignment by the aligner for the data processing circuit is input to the data processing circuit in units of input data width of the data processing circuit;
(D) The aligned data unit input to the data processing circuit is processed.
Data transfer processing device. An aligner for data transfer is provided on the transfer path,
An unaligned data unit is input in a predetermined transfer unit to both the data transfer aligner and the data processing circuit aligner,
The data processing circuit is a DIF (Data Integrity Field) circuit,
The input data width of the DIF circuit is a fixed length and a divisor of the size of the fixed length data block,
The size of the transfer unit is N times the input data width (N is a natural number), or the input data width is M times the size of the transfer unit (M is a natural number),
The data transfer and the processes (A) to (D) are performed in synchronization with a clock generated at the same time,
When the size of the transfer unit is N times the input data width, the clock cycle for the data transfer is 1 / N times the clock cycle for the processing of (C),
When the input data width is M times the size of the transfer unit, the clock cycle for the process (C) is 1 / M times the clock cycle for the data transfer.
The data transfer processing device according to claim 1. The data transfer processing device is a host bus adapter provided in an information processing device for communicating with an external storage device.
The data transfer processing device according to claim 2. The data processing circuit is a check code generation circuit that generates a check code corresponding to each size of a fixed-length data block,
The input data width of the check code generation circuit is a fixed length, and is a divisor of the size of the fixed length data block.
The data transfer processing device according to claim 1. In parallel with the data transfer in a predetermined transfer unit from the transfer source to the transfer destination,
(A) align the data unit to be transferred for the data processing circuit;
(B) The data unit after being aligned for the data processing circuit is input to the data processing circuit in units of input data width of the data processing circuit;
(C) The data processing circuit processes the input data unit after alignment.
Data transfer processing method. An information processing unit including a CPU and a memory;
A communication interface device for the information processing unit to communicate with an external storage device;
The communication interface device transfers data in a predetermined transfer unit in at least one of a reading unit in which a data block read from the external storage device flows and a writing unit in which a data block written to the external storage device flows. A data processing circuit for processing the input data unit, and an aligner for the data processing circuit, at a position different from the path through which the data unit flows.
The aligner for the data processing circuit is configured to align the address of the data unit input to the aligner so that the non-transfer target data is not included in the head portion of the aligned data unit. ,
In parallel with the data transfer from the transfer source to the transfer destination,
(A) The data unit to be transferred is input to the aligner for the data processing circuit,
(B) The address of the data in the data unit input to the aligner for the data processing circuit is aligned,
(C) A data unit after alignment by the aligner for the data processing circuit is input to the data processing circuit in units of input data width of the data processing circuit;
(D) The aligned data unit input to the data processing circuit is processed.
Information processing device.

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