JP2009164435A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance cleaning effect on the gap between a circuit board and a semiconductor element of a semiconductor device. <P>SOLUTION: Solder resist 22 is formed on a surface of the circuit board 2, and a first opening is formed in the solder resist 22 to expose an electrode 21; and polyimide 23 is formed on a surface of the semiconductor element 3 and a second opening is formed in the polyimide 32 to expose an electrode 31. A solder bump 34 is formed on the electrode 31, and at least one of the electrode 21 and solder bump 34 is coated with flux; and the solder resist 22 and polyimide 32 are made to face each other to join the solder bump 34 to the electrode 21, and a cleaning liquid is supplied to the gap between the circuit board 2 and semiconductor element 3 to clean flux remaining in the gap. A recess is formed in at least one of the solder register 22 and polyimide 32 before the process of cleaning the flux. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method and a semiconductor device configured by mounting a semiconductor element on a circuit board.

  2. Description of the Related Art In recent years, with the reduction in size and density of electronic devices such as mobile phones, there has been a demand for improvement in mounting density for mounting semiconductor elements on circuit boards. In order to satisfy this requirement, bumps (projections) made of solder or the like are arranged in a grid pattern on the surface electrode of the semiconductor element, and the surface of the semiconductor element is placed below the electrode formed on the circuit board surface. A BGA (Ball Grid Array) package, FCBGA, which uses a mounting method called FC (Flip Chip) that directly joins toward the substrate, is widely used.

  In FCBGA, flux is applied to solder bumps and electrodes when a semiconductor element is bonded to a substrate by solder bumps. If the flux remains between the circuit board and the semiconductor element after bonding the semiconductor element to the circuit board, a short circuit occurs due to migration between the electrodes due to ion components, which reduces the reliability of the semiconductor device. End up.

  In FCBGA, in order to improve the connection reliability of solder bumps, a mounting method is used in which a gap between a semiconductor element and a circuit board is filled with an underfill resin. As shown in FIG. 17A, if the flux 1007 remains when the underfill resin 1006 is filled, the filling of the underfill resin 1006 is hindered by the remaining flux 1007. As a result, voids 1008 are formed in the underfill resin 1006, and the possibility of a decrease in connection strength and a short circuit increases, and the reliability of the semiconductor device 1001 decreases. Furthermore, since the gap between the FCBGA circuit board 1002 and the semiconductor element 1003 is as narrow as 50 to 100 μm, it is difficult to clean the flux in the gap.

  On the other hand, as a general cleaning method for residual flux, there are a method of cleaning the flux by oscillating while immersing the semiconductor device in a cleaning solution such as water, and a method of cleaning the flux with ultrasonic waves.

In addition, the cleaning liquid enters the gap between the circuit board of the FCBGA and the semiconductor element, and by forming a high-speed flow of the cleaning liquid along the gap, the cleaning liquid that has entered the gap is sucked, so that the gap A technique for cleaning the inside is known (see, for example, Patent Document 1).
JP-A-11-300294

  By the way, even when the inside of the FCBGA gap is washed by a method of oscillating while immersing the semiconductor device in the washing liquid and washing the flux, the washing liquid hardly enters the minute gap of the FCBGA as described above. Even if it moves, the cleaning liquid itself in the gap of the FCBGA hardly moves, so that there is a problem that it is difficult to obtain an effective cleaning effect.

  In addition, even if the inside of the FCBGA gap is cleaned by a method of cleaning the flux with ultrasonic waves, if a generally used low frequency ultrasonic wave is used, a strong cleaning effect by cavitation can be obtained. There is a problem that the element may be damaged. A cleaning machine for cleaning semiconductor element devices using ultrasonic waves in a high frequency band that does not generate cavitation has also been developed. Even if this is used for cleaning in the gaps of FCBGA, a sufficient cleaning effect is obtained. There is a problem that it is difficult to be done.

  In the technique described in Patent Document 1, as shown in FIG. 17B, a low-pressure water flow 1087 is caused to flow in the cleaning tank so that the gap between the circuit board 1002 of the semiconductor device 1001 and the semiconductor element 1003 is obtained. A high cleaning effect can be expected for the cleaning of the flux 1007. However, if there is a path of the water flow 1087 other than this gap, the water flow 1087 flows through the path and the liquid flow into the gap is weakened, so that the cleaning performance is deteriorated. For this reason, a dedicated cleaning jig for controlling the water flow 1087 is required for each work, and there is a problem that the cost is increased.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a highly reliable manufacturing method of a semiconductor device and a semiconductor device by enhancing a cleaning effect of a gap between a circuit board and a semiconductor element. And

  The method for manufacturing a semiconductor device includes a step of preparing a circuit board having a first electrode on a surface, a step of forming a first film on the surface of the circuit board, and a first layer on the first film. Forming an opening to expose the first electrode; preparing a semiconductor element having a second electrode on a surface; forming a second film on the surface of the semiconductor element; Forming a second opening in the second film to expose the second electrode; forming a solder bump on the second electrode; and forming the first electrode and the solder bump A step of applying a flux to at least one, a step of facing the first film and the second film, and bonding the solder bump to the first electrode; and the circuit board and the semiconductor element Supply cleaning liquid to the gap and remove the flux present in the gap. A step of purification, before the step of cleaning the flux, be a requirement to include a step of forming a recess in at least one of the first film and the second film.

  According to such a method of manufacturing a semiconductor device, a circuit board having a first electrode on the surface is prepared. Next, a first film is formed on the surface of the circuit board. Next, a first opening is formed in the first film, and the first electrode is exposed. Next, a semiconductor element having a second electrode on the surface is prepared. Next, a second film is formed on the surface of the semiconductor element. Next, a second opening is formed in the second film, and the second electrode is exposed. Next, solder bumps are formed on the second electrode. Next, flux is applied to at least one of the first electrode and the solder bump. Next, the first film and the second film are opposed to each other, and a solder bump is bonded to the first electrode. Next, a cleaning liquid is supplied to the gap between the circuit board and the semiconductor element. Next, the flux present in the gap is cleaned. Here, a recess is formed in at least one of the first film and the second film before the step of cleaning the flux.

  The method of manufacturing a semiconductor device includes a step of preparing a circuit board having a first electrode on a surface, a step of forming a first film on the surface of the circuit board, and a first on the first film. A step of exposing the first electrode, a step of preparing a semiconductor element having a second electrode on the surface, a step of forming a second film on the surface of the semiconductor element, Forming a second opening in the second film to expose the second electrode; forming a solder bump on the second electrode; and the first electrode and the solder bump A step of applying a flux to at least one of the above, a step of making the first film and the second film face each other and bonding the solder bump to the first electrode, the circuit board and the semiconductor element The cleaning liquid is supplied to the gap of the flux, and the flux is present in the gap. A step of cleaning, before the step of cleaning the flux, be a requirement to include a step of forming a convex portion on at least one of the first film and the second film.

  According to such a method for manufacturing a semiconductor device, a circuit board having a first electrode on its surface is prepared. Next, a first film is formed on the surface of the circuit board. Next, a first opening is formed in the first film, and the first electrode is exposed. Next, a semiconductor element having a second electrode on the surface is prepared. Next, a second film is formed on the surface of the semiconductor element. Next, a second opening is formed in the second film, and the second electrode is exposed. Next, solder bumps are formed on the second electrode. Next, flux is applied to at least one of the first electrode and the solder bump. Next, the first film and the second film are opposed to each other, and a solder bump is bonded to the first electrode. Next, the cleaning liquid is supplied to the gap between the circuit board and the semiconductor element, and the flux present in the gap is cleaned. Here, before the step of cleaning the flux, convex portions are formed on at least one of the first film and the second film.

  Further, the semiconductor device includes a circuit board having a first electrode on a surface thereof, a first film having a first opening formed on the surface of the circuit board and exposing the first electrode, A semiconductor element mounted on the surface of the circuit board and having a second electrode on the surface facing the first film, and a second element formed on the surface of the semiconductor element and exposing the second electrode A second film having an opening, a solder bump formed on the second electrode and connecting the second electrode to the first electrode, and the first film and the second film. It is a requirement to include a concave portion or a convex portion formed on at least one side.

  According to such a semiconductor device, the first electrode is provided on the surface of the circuit board. A first film having a first opening exposing the first electrode is formed on the surface of the circuit board. Further, on the surface of the circuit board, a semiconductor element having a second electrode on the surface facing the first film is mounted. In addition, a second film having a second opening exposing the second electrode is formed on the surface of the semiconductor element. In addition, solder bumps are formed on the second electrode to connect the second electrode to the first electrode. In addition, a concave portion or a convex portion is formed in at least one of the first film and the second film.

  According to the disclosed semiconductor device manufacturing method and semiconductor device, the cleaning effect of impurities inside the gaps of the semiconductor device by the cleaning liquid is enhanced.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
First, a first embodiment of the present invention will be described.

First, the main part of the semiconductor device manufacturing method according to the present embodiment will be described. FIG. 1 is a diagram for explaining the main part of the semiconductor device manufacturing method according to the first embodiment.
The method for manufacturing the semiconductor device 1 according to the present embodiment shown in FIG. 1 will be described in detail later with reference to FIGS. 4 to 11. The step of preparing the circuit board 2 having the electrodes 21 on the surface, Forming a solder resist 22, forming an opening in the solder resist 22 to expose the electrode 21, preparing a semiconductor element 3 having an electrode 31 on the surface, and forming a polyimide (polyimide) on the surface of the semiconductor element 3 ) 32, forming an opening in the polyimide 32 to expose the electrode 31, forming the solder bump 34 on the electrode 31, applying flux to at least one of the electrode 21 and the solder bump 34, The process of joining the solder bumps 34 to the electrodes 21 with the solder resist 22 and the polyimide 32 facing each other, and cleaning the gap between the circuit board 2 and the semiconductor element 3 It is composed of a step of supplying a cleaning liquid flow 81 which is a flow of liquid and cleaning the flux existing in the gap. Further, before the step of cleaning the flux, at least one of the solder resist 22 and the polyimide 32 is provided. And a step of forming recesses (dimples 23 and 33, respectively).

  In the method of manufacturing the semiconductor device 1 according to the present embodiment, first, the circuit board 2 having the electrode 21 on the surface is prepared, the solder resist 22 is formed on the surface of the circuit board 2, and then an opening is formed in the solder resist 22. Then, the electrode 21 is exposed. Also, a semiconductor element 3 having an electrode 31 on the surface is prepared, and after forming polyimide 32 on the surface of the semiconductor element 3, an opening is formed in the polyimide 32 to expose the electrode 31, and then solder bumps are applied to the electrode 31. 34 is formed.

  The solder resist 22 is a photosensitive material that covers a conductor of a wiring portion such as a copper foil on the surface of the circuit board 2 so that the solder does not adhere to a portion other than the electrode 21 where soldering is unnecessary when the solder bump 34 is soldered. And an epoxy-based synthetic resin film having insulating properties and thermosetting properties.

  The polyimide 32 is a protective film formed on the surface of the semiconductor element 3 made of a polymer containing an imide bond in the repeating unit. The polyimide 32 protects the surface of the semiconductor element 3 physically and electrically by insulation.

  Next, flux is applied to at least one of the electrode 21 and the solder bump 34, the solder resist 22 and the polyimide 32 are opposed to each other, the solder bump 34 is bonded to the electrode 21, and then the gap between the circuit board 2 and the semiconductor element 3 is formed. A cleaning liquid flow 81 is supplied to clean the flux present in the gap.

  Further, the present embodiment includes a step of forming dimples 23 and 33 in the solder resist 22 and the polyimide 32, respectively, before cleaning the flux. The dimples 23 and 33 are depressions formed on the surfaces of the solder resist 22 and the polyimide 32, respectively, and generate a turbulent flow by changing the flow of the cleaning liquid flow 81 in order to improve the cleaning effect.

  In the present embodiment, the dimples 23 are formed in a step immediately after the solder resist 22 is formed on the circuit board 2 for ease of processing. Similarly, the dimple 33 is formed in a process immediately after the polyimide 32 is formed on the semiconductor element 3. The step of forming the dimples 23 and 33 may be performed at any stage as long as possible before the step of cleaning the flux (see FIG. 4).

  In the present embodiment, in this way, the semiconductor device 1 from which the flux supplied to the electrode 21 and the solder bump 34 and the impurities adhering in other gaps are removed is manufactured.

  Next, an outline of the configuration of the semiconductor device of the present embodiment will be described. FIG. 2 is a schematic plan view illustrating the basic structure of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the basic structure of the semiconductor device according to the first embodiment. FIG. 3A illustrates a cross section taken along the line AA of the semiconductor device illustrated in FIG. FIG. 3B is an enlarged view of a portion B of the cross section of the semiconductor device illustrated in FIG.

  As shown in FIG. 2, the semiconductor device 1 of the present embodiment includes a circuit board 2, a semiconductor element 3, and an underfill resin 6. As shown in FIGS. 3A and 3B, the circuit board 2 includes an electrode 21, a solder resist 22, and solder balls 24. The semiconductor element 3 includes an electrode 31, a polyimide 32, and a solder bump 34.

As shown in FIG. 3A, the underfill resin 6 is filled in a gap between the circuit board 2 and the semiconductor element 3 in order to protect the circuit board 2 and the semiconductor element 3.
The semiconductor element 3 uses silicon (Si) or the like as a base material. The semiconductor element 3 is provided with an electrode opening having an electrode 31 on the surface, and, for example, a tin (Sn) -lead (Pb) -based solder is formed on the electrode 31 as shown in FIG. A plurality of solder bumps 34 are provided. The semiconductor element 3 is mounted on the circuit board 2 face down by flip chip bonding using the solder bumps 34. Thereby, electrical connection for power supply and signal input / output between the circuit board 2 and the semiconductor element 3 is realized. Further, portions other than the electrode openings of the semiconductor element 3 are covered with the polyimide 32.

  The circuit board 2 is made of a material such as glass epoxy or ceramic, and a wiring (not shown) is provided on the surface. As shown in FIG. 3B, the circuit board 2 is provided with an electrode opening provided with the electrode 21 in a portion that is paired with the solder bump 34 of the semiconductor element 3. Further, portions other than the electrode openings of the circuit board 2 are covered with the solder resist 22.

  The solder balls 24 are formed of solder, and a plurality of solder balls 24 are provided on the back surface of the circuit board 2 on which the semiconductor element 3 is mounted. The solder balls 24 serve as connection terminals when the semiconductor device 1 is mounted on a mother board or the like.

  The underfill resin 6 is a resin having an insulating property and a thermosetting property, such as an epoxy composition or a urethane composition, which is filled in a gap between the circuit board 2 and the semiconductor element 3. The underfill resin 6 is mixed with a material for buffering a difference in thermal expansion between the circuit board 2 and the semiconductor element 3 in the form of fine particles.

  The underfill resin 6 is filled in a gap between the circuit board 2 and the semiconductor element 3, and the underfill resin 6 is heated and cured to seal the gap between the circuit board 2 and the semiconductor element 3. . Thereby, the connection strength between the circuit board 2 and the semiconductor element 3 is increased, and the semiconductor device 1 is protected from the thermal expansion difference between the circuit board 2 and the semiconductor element 3. Further, even when the solder bump 34 is melted by reheating when the semiconductor device 1 is mounted in the gap, it is possible to prevent short circuit with other solder bumps and / or conductor portions.

  The manufacturing method of the semiconductor device 1 according to the present embodiment improves the reliability of the semiconductor device 1 by ensuring the filling of the underfill resin 6 by increasing the flux cleaning effect.

Next, the manufacturing process of the semiconductor device 1 of the present embodiment will be described. FIG. 4 is a diagram for explaining the outline of the manufacturing process of the semiconductor device according to the first embodiment.
The semiconductor device 1 of the present embodiment includes a step of preparing a circuit board 2, a step of forming a solder resist 22 on the circuit board 2, a step of forming dimples 23 on the solder resist 22, and a step of exposing the electrodes 21. A step of preparing the semiconductor element 3, a step of forming the polyimide 32 on the semiconductor element 3, a step of forming the dimple 33 on the polyimide 32, a step of exposing the electrode 31, and a solder bump 34 on the electrode 31. A step of applying a flux to the electrode 21 and the solder bump 34, a step of bonding the solder bump 34 to the electrode 21, and a step of cleaning the flux in the gap between the circuit board 2 and the semiconductor element 3. The

  Here, the process of applying flux to the electrode 21 and the solder bump 34, the process of bonding the solder bump 34 to the electrode 21, and the process of cleaning the flux in the gap between the circuit board 2 and the semiconductor element 3 will be mainly described.

  First, as shown in the manufacturing step 41 in the upper left of FIG. 4, flux 7 is applied to the electrodes 21 formed on the circuit board 2 and the solder bumps 34 formed on the semiconductor element 3, and then the semiconductor element 3 is attached to the circuit board 2. Face the surface of the face down. Next, as shown in manufacturing step 42, the solder bump 34 and the electrode 21 are aligned, and the semiconductor element 3 is mounted on the circuit board 2. Next, as shown in the manufacturing step 43, after the solder bump 34 is melted by reheating (reflow), the solder bump 34 and the electrode 21 are joined, so that the semiconductor element 3 is made up of a plurality of solder bumps 34. Then, it is melt bonded to the circuit board 2 by flip chip bonding.

  Next, as shown in the manufacturing step 44, a cleaning liquid flow 81 is supplied to the gap between the semiconductor element 3 and the circuit board 2 in order to remove the flux 7 adhering to the semiconductor element 3 and the circuit board 2. Flux 7 is washed. The cleaning of the flux 7 by supplying the cleaning liquid flow 81 in this embodiment will be described in detail later with reference to FIG.

  Next, as shown in the manufacturing step 45, the underfill resin 6 is filled in the gap between the semiconductor element 3 and the circuit board 2. Next, as shown in manufacturing step 46, the circuit board 2 is turned upside down and turned over, and a flux 74 is applied to the electrode (not shown) on the back surface of the circuit board 2 (upper surface in the manufacturing step 45 in the figure). Thereafter, the solder balls 24 are mounted. Although the description is omitted here, the back surface of the circuit board 2 is also provided with electrodes (not shown) and solder resist (not shown) in the same manner as the front surface.

Next, as shown in the manufacturing step 47, the solder balls 24 mounted on the back surface of the circuit board 2 are reheated and melted, and joined to the semiconductor device 1.
Next, as shown in the manufacturing step 48, the flux 74 remaining on the back surface of the semiconductor device 1 and the solder balls 24 is cleaned by the cleaning liquid flow 82. Next, as shown in the manufacturing step 49, the semiconductor device 1 is inverted again. Thereby, the manufacturing process of the semiconductor device 1 of the present embodiment is completed.

  Here, an example has been described in which the flux 7 in the gap between the circuit board 2 and the semiconductor element 3 and the flux 74 on the back surface of the semiconductor device 1 are separately cleaned by the cleaning liquid flows 81 and 82, respectively. You may wash | clean the flux 7 and the flux 74 simultaneously.

Further, the fluxes 7 and 74 are applied to the circuit board 2 and the semiconductor element 3, respectively, but any one of the fluxes 7 and 74 may be applied to only one of them.
Further, the dimples 23 and 33 are formed on the solder resist 22 and the polyimide 32, respectively, but dimples (any of the dimples 23 and 33) may be formed on only one of them.

  Next, a process for forming the dimples 23 and 33 in the present embodiment will be described. FIG. 5 is a diagram illustrating a process of forming dimples on the circuit board of the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating a process of forming dimples in the semiconductor element of the semiconductor device according to the first embodiment.

  In the present embodiment, the dimples 23 of the circuit board 2 and the dimples 33 of the semiconductor element 3 are individually formed before the semiconductor element 3 is attached to the circuit board 2 (see manufacturing step 41 in FIG. 4). .

First, the formation of the dimples 23 on the circuit board 2 side will be described with reference to FIG.
As shown in the forming step 51 in FIG. 5, the dimple 23 is formed by first attaching a DFR (dry film resist) 71 on the surface of the circuit board 2 to which the solder resist 22 is applied, and forming the dimple 23. The portion at the position where the dimple 23 is formed is covered with a mask 72 so that only the other portions are exposed, and then the DFR 71 is exposed by the exposure device 73. Thereby, only a portion other than the position where the dimple 23 is formed is exposed. The DFR 71 is a photosensitive resist film and is used to form an etching resistant film by exposure and development.

  Next, as shown in the forming step 52, the DFR 71 is developed. As a result, an etching resistant film by DFR 71 is formed on the surface of the portion other than the position where the dimple 23 is formed, which is exposed by being not covered with the mask 72.

  Next, as shown in the formation step 53, an etching process is performed in a state where the DFR 71 is opened only in a portion where the dimple 23 is formed. As a result, the surface of the solder resist 22 is corroded to form dimples 23 that are minute recesses.

By removing the excess portion of the solder resist 22 by this etching process, the formation of the dimples 23 of the circuit board 2 is completed as shown in the formation step 54.
Similarly, the dimple 33 of the semiconductor element 3 is also formed by performing an etching process on the surface of the polyimide 32. Next, the formation of the dimple 33 on the semiconductor element 3 side will be described with reference to FIG.

  As in the dimple 23 on the circuit board 2 side, the dimple 33 is formed by first attaching DFR 91 on the surface of the semiconductor element 3 to which the polyimide 32 is applied, as shown in the formation step 61 of FIG. After covering with a mask 92 so that only portions other than the position 33 are exposed, the DFR 91 is exposed by an exposure machine 93. Next, as shown in the forming step 62, the DFR 91 is developed.

  Next, as shown in the formation step 63, an etching process is performed with the DFR 91 opened only in the portion where the dimple 33 is to be formed. As a result, the surface of the polyimide 32 is corroded to form the dimple 33 that is a minute recess. By removing the excess portion of the polyimide 32 by this etching process, the formation of the dimple 33 of the semiconductor element 3 is completed as shown in the formation step 64.

  In this way, after the dimples 23 and 33 are formed on the circuit board 2 and the semiconductor element 3, respectively, the semiconductor element 3 is bonded to the circuit board 2 through the process described with reference to FIG. Note that in this embodiment mode, dry etching is used as the etching treatment, but wet etching may be used.

  Next, the position and diameter of the dimple provided on the circuit board will be described. FIG. 7 is a diagram illustrating an arrangement reference regarding the dimple position and diameter of the circuit board of the semiconductor device according to the first embodiment. FIG. 7A is a schematic plan view of a circuit board when dimples are formed by orthogonal arrangement. FIG. 7B is a schematic plan view of a circuit board when dimples are formed in a staggered arrangement.

  The placement location of the dimples 23 may be an arbitrary position, but since there is little interference with other structures, it is considered that the placement is relatively difficult. The midpoint position of the pitch is preferred.

As shown in FIG. 7A, when the dimples 23 of the circuit board 2 are formed in an orthogonal arrangement, the arrangement criteria regarding the position and diameter of the dimple 23 are as follows.
a1: bump pitch b1: solder resist opening diameter c1: dimple diameter
c1 ≦ a1-b1 (1)
The arrangement and diameter of the dimples are designed so as to satisfy this inequality (1).

  Here, the “bump pitch” is the distance between the centers of the adjacent solder bumps 34 (and the electrodes 21 to be joined). The “solder resist opening diameter” is the diameter of the electrode opening provided to expose the electrode 21 in the solder resist 22. “Dimple diameter” is the diameter of the dimple 23.

Inequality (1) indicates that the dimple diameter in the case of orthogonal arrangement is equal to or less than the difference between the bump pitch and the solder resist opening diameter.
As shown in FIG. 7B, when the dimples 23 of the circuit board 2 are formed in a staggered arrangement, the arrangement criteria regarding the position and diameter of the dimples 23 are as follows.

a2: Staggered bump pitch b2: Solder resist opening diameter c2: Dimple diameter
c2 ≦ a2-b2 (2)
The arrangement and diameter of the dimples are designed so as to satisfy this inequality (2).

Here, the “staggered bump pitch” is the distance between the centers of the solder bumps 34 (and the electrodes 21 joined thereto) adjacent to each other in the diagonal direction of the circuit board 2.
Inequality (2) indicates that the dimple diameter in the staggered arrangement is less than or equal to the difference between the staggered bump pitch and the solder resist opening diameter.

In the present embodiment, the position of the dimple 23 is set at the center of the bump pitch, but may be offset from the center.
Next, the depth of the dimple provided on the circuit board will be described. FIG. 8 is a diagram for explaining an arrangement reference regarding the dimple depth of the circuit board of the semiconductor device according to the first embodiment. FIG. 8A illustrates the depth of the dimple when the wiring pattern has only the same potential and there is no wiring pattern with a different potential and / or when there is no wiring pattern immediately below the dimple. FIG. FIG. 8B is a diagram illustrating the depth of the dimple when a wiring pattern having a different potential exists in the wiring pattern.

  As shown in FIG. 8A, when the wiring pattern of the circuit board 2 has only the same potential and there is no wiring pattern with a different potential, and / or the wiring pattern is directly under the dimple 23 of the circuit board 2. If not, the disposition reference regarding the depth of the dimple 23 is as follows.

s: Solder resist thickness p: Pattern thickness d: Dimple depth
d ≦ s (3)
10 μm ≦ d ≦ 50 μm (4)
The dimple depth is designed to satisfy these inequalities (3) and (4).

  Here, the “solder resist thickness” is the thickness of the solder resist 22 formed on the circuit board 2. “Pattern thickness” is the thickness of the wiring pattern disposed on the circuit board 2. “Dimple depth” is the depth of the dimple 23.

  Inequalities (3) and (4) indicate that the dimple depth of the dimple 23 is preferably equal to or smaller than the solder resist thickness, and that the dimple depth is preferably designed to be 10 μm or more and 50 μm or less.

  As shown in FIG. 8B, in the circuit board 2, if there is a different potential electrode 21 a that is a wiring pattern having a different potential from the solder bump 34 adjacent immediately below the dimple 23, there is a risk that a short circuit may occur. Therefore, the position of the dimple 23 is shifted, or the dimple depth is adjusted so that the different potential electrode 21a is not exposed. The standard regarding the depth of the dimple 23 in this case is as follows.

s: Solder resist thickness p: Pattern thickness d: Dimple depth
d <s−p (5)
The dimple depth is designed to satisfy this inequality (5).

  Inequality (5) indicates that the dimple depth of the dimple 23 is less than the difference between the solder resist thickness and the pattern thickness. This is because it is necessary to leave the solder resist 22 without completely removing it in order to insulate the solder bumps 34 and / or the wiring patterns having different potentials.

  Next, the position and diameter of the dimple provided in the semiconductor element will be described. FIG. 9 is a diagram for explaining an arrangement reference regarding the dimple position and diameter of the semiconductor element of the semiconductor device according to the first embodiment. FIG. 9A is a schematic plan view of a semiconductor element when dimples are formed by orthogonal arrangement. FIG. 9B is a schematic plan view of a semiconductor element when dimples are formed in a staggered arrangement.

  The placement location of the dimple 33 may be any position as in the dimple 23 of the circuit board 2, but it is considered that there is little interference with other structures, so that it is considered relatively difficult to place the solder bump. A midpoint position of 34 orthogonal pitches or a midpoint position of a staggered pitch is preferable.

As shown in FIG. 9A, when the dimples 33 of the semiconductor element 3 are formed in an orthogonal arrangement, the arrangement reference regarding the position and diameter of the dimple 33 is as follows.
a3: bump pitch b3: polyimide opening diameter c3: dimple diameter
c3 ≦ a3-b3 (6)
The arrangement and diameter of the dimples are designed so as to satisfy this inequality (6).

  Here, “bump pitch” is the distance between the centers of adjacent solder bumps 34 (electrodes 31 on which the bumps are disposed). The bump pitch on the semiconductor element 3 side is the same as the bump pitch of the dimples 23 formed on the circuit board 2 side. The “polyimide opening diameter” is a diameter of an electrode opening provided to expose the electrode 31 in the polyimide 32. The “dimple diameter” is the diameter of the dimple 33. The dimple diameter on the semiconductor element 3 side can be the same as or different from the dimple diameter on the circuit board 2 side.

Inequality (6) indicates that the dimple diameter in the orthogonal arrangement is equal to or less than the difference between the bump pitch and the polyimide opening diameter.
As shown in FIG. 9B, when the dimples 33 of the semiconductor element 3 are formed in a staggered arrangement, the arrangement reference regarding the position and diameter of the dimple 33 is as follows.

a4: Staggered bump pitch b4: Polyimide opening diameter c4: Dimple diameter
c4 ≦ a4-b4 (7)
The arrangement and diameter of the dimples are designed so as to satisfy this inequality (7).

Here, the “staggered bump pitch” is the distance between the centers of the solder bumps 34 (electrodes 31 on which they are formed) adjacent to each other in the diagonal direction of the semiconductor element 3.
Inequality (7) indicates that the dimple diameter in the staggered arrangement is equal to or smaller than the difference between the staggered bump pitch and the polyimide opening diameter.

  In the present embodiment, the position of the dimple 33 is set at the center position of the bump pitch similarly to the dimple 23 of the circuit board 2, but may be offset from the center.

  Next, the depth of the dimple provided in the semiconductor element will be described. FIG. 10 is a diagram for explaining an arrangement reference regarding the dimple depth of the semiconductor element of the semiconductor device according to the first embodiment.

As shown in FIG. 10, the arrangement reference regarding the depth of the dimple 33 of the semiconductor element 3 is as follows.
s: polyimide thickness d: dimple depth
d ≦ s (8)
The depth of the dimple is designed so as to satisfy this inequality (8).

  Here, “polyimide thickness” is the thickness of the polyimide 32 formed in the semiconductor element 3. “Pattern thickness” is the thickness of the wiring pattern disposed in the semiconductor element 3. “Dimple depth” is the depth of the dimple 33.

Inequality (8) indicates that the dimple depth of the dimple 33 is equal to or less than the polyimide thickness.
The dimple depth of the polyimide 32 is preferably designed to be 1 μm or more and 10 μm or less.

  Next, cleaning of the gap of the semiconductor device 1 performed by supplying the cleaning liquid flow 81 to the gap between the circuit board 2 and the semiconductor element 3 of the semiconductor device 1 in the present embodiment will be described. FIG. 11 is a diagram illustrating a process of cleaning the semiconductor device according to the first embodiment. FIG. 11 shows a state in which a cleaning liquid flow is passed through the cleaning tank.

In the present embodiment, a plurality of semiconductor devices 1 are collectively accommodated in the cleaning tank 111 and cleaned by the cleaning liquid flow 81.
First, an apparatus used for cleaning the semiconductor device 1 of the present embodiment will be described. As shown in FIG. 11, in the present embodiment, as described above, the cleaning tank 111 and the tray 112 are used.

The cleaning tank 111 of the present embodiment is a tank capable of sealing the inside for housing the semiconductor device 1 and cleaning it with the cleaning liquid flow 81.
When cleaning with the cleaning liquid flow 81 shown in FIG. 11, the cleaning tank 111 opens the lid 113 and the valve 114 so that the cleaning liquid flow 81 flows in from the upper lid 113 and flows out from the lower valve 114. it can.

  The tray 112 is an instrument for installing a plurality of semiconductor devices 1 in the cleaning tank 111. The tray 112 supports the semiconductor device 1 and guides it for accurate positioning. When the semiconductor device 1 is installed in the cleaning tank 111, all the semiconductor devices 1 to be installed are temporarily fixed on the tray 112 and arranged. Next, the semiconductor device 1 is placed in the cleaning tank 111 together with the tray 112. When the semiconductor device 1 is taken out from the cleaning tank 111, the whole tray 112 is taken out. By using this tray 112, a plurality of semiconductor devices 1 can be arranged and taken out at a time.

  Next, the cleaning of the semiconductor device 1 in the present embodiment will be specifically described. In this embodiment, after the electrodes 21 and the solder bumps 34 are joined in the process before cleaning (manufacturing step 43 in FIG. 4), first, as shown in FIG. The semiconductor devices 1 are mounted in a state of being arranged on the tray 112. These semiconductor devices 1 are arranged in the cleaning tank 111 together with the tray 112.

  Next, in the present embodiment, the lid 113 and the valve 114 of the cleaning tank 111 are opened, and the cleaning liquid flow 81 is caused to flow from the lid 113 as shown in FIG. The flowing cleaning liquid flow 81 flows around the tray 112 and then flows out from the valve 114. At this time, when the semiconductor device 1 is attached to the tray 112 in advance, the gap between the semiconductor devices 1 is parallel to the direction in which the cleaning liquid flow 81 flows, and the cleaning liquid flow 81 is arranged to easily flow into the gap. As a result, the cleaning liquid flow 81 flows into the gap between the circuit board 2 and the semiconductor element 3 of the semiconductor device 1.

  At this time, the cleaning liquid flow 81 flows while cleaning the flux 7 and the like adhering in the gap, and is discharged from the lower portion of the gap. Thus, the flux 7 supplied to the electrode 21 and the solder bump 34 in the first step and other impurities adhering in the gap are removed by the cleaning liquid.

  In the present embodiment, dimples 23 and 33 are respectively provided on the solder resist 22 of the circuit board 2 and the polyimide 32 of the semiconductor element 3 inside the minute gap between the circuit board 2 and the semiconductor element 3. However, the present invention is not limited to this, and dimples may be formed only on one of the solder resist 22 of the circuit board 2 and the polyimide 32 of the semiconductor element 3. The dimples 23 and 33 can be formed at arbitrary positions on the solder resist 22 and the polyimide 32, respectively.

  As described above, according to the present embodiment, in advance on the solder resist 22 of the circuit board 2 and the polyimide 32 of the semiconductor element 3 inside the minute gap between the circuit board 2 and the semiconductor element 3. Then, minute recesses (dimples 23 and 33) are formed. As a result, when cleaning impurities such as flux 7 in a minute gap between the circuit board 2 and the semiconductor element 3, the cleaning liquid flow 81 comes into contact with the dimples 23 and 33, thereby generating a turbulent flow in the cleaning liquid flow 81. Let

  Here, conventionally, the flux 7 is washed to some extent, and when the path of the cleaning liquid flow 81 is formed, the flow becomes laminar and the cleaning effect is greatly reduced. However, according to the present embodiment, the cleaning liquid flow 81 Even after the path is formed, turbulence is generated by the dimples 23 and 33. As a result, the cleaning effect of impurities inside the gap of the semiconductor device 1 by the cleaning liquid is enhanced.

[Second Embodiment]
Next, a second embodiment will be described. Differences from the first embodiment will be mainly described, and the same reference numerals are used for the same matters, and descriptions thereof are omitted.

  The second embodiment is different from the first embodiment in that the dimple 223 is formed by irradiating a laser 274 to the solder resist 222 formed on the circuit board 2 of the semiconductor device 201.

  Below, the process in which the dimple 223 in this Embodiment is formed is demonstrated. FIG. 12 is a diagram illustrating a process of forming dimples on the circuit board of the semiconductor device according to the second embodiment. The formation of the dimple 223 by the laser 274 of the present embodiment will be described along FIG.

  As shown in the formation step 121 in FIG. 12, the dimple 223 is formed by irradiating a predetermined position of the solder resist 222 formed on the surface of the circuit board 2 with a high-power laser 274 to form the solder resist 222. The surface is heated and melted. As a result, a dimple 223 as shown in the formation step 122 is formed on the surface of the solder resist 222 of the circuit board 2.

  At this time, the size and depth of the dimple 223 can be adjusted by adjusting the output of the laser 274 to be irradiated and the irradiation time. The depth of the dimple 223 is preferably 10 μm or more and 50 μm or less.

  Here, when the hole diameter of the dimple 223 is about 25 to 70 μm, an excimer laser and a YAG laser are preferable, and when the hole diameter is about 80 to 180 μm, a pulse carbon dioxide laser is preferable. Other lasers can be used in the diameter range and in other diameter ranges.

  In this embodiment, the case where the dimple 223 on the circuit board 2 side is formed using the laser 274 is described as an example. However, the dimple is formed on the polyimide on the semiconductor element 3 side using the laser. May be.

  As described above, a minute recess (dimple 223) is formed in advance on the solder resist 222 of the circuit board 2 inside the minute gap between the circuit board 2 and the semiconductor element 3 by the laser 274. deep. Thus, according to the present embodiment, as in the first embodiment, the cleaning liquid flow 81 is generated when cleaning impurities such as the flux 7 in the minute gap between the circuit board 2 and the semiconductor element 3. By contacting the dimple 223, a turbulent flow is generated in the cleaning liquid flow 81. As a result, the cleaning effect of impurities inside the gap of the semiconductor device 201 by the cleaning liquid is enhanced.

[Third Embodiment]
Next, a third embodiment will be described. Differences from the first embodiment will be mainly described, and the same reference numerals are used for the same matters, and descriptions thereof are omitted.

  The third embodiment is different from the first embodiment in that the dimples 323 are formed by performing a blast process on the solder resist 322 formed on the circuit board 2 of the semiconductor device 301.

  Below, the process in which the dimple 323 in this Embodiment is formed is demonstrated. FIG. 13 is a diagram illustrating a process of forming dimples on the circuit board of the semiconductor device according to the third embodiment. The formation of the dimple 323 by the blast process of the present embodiment will be described along FIG.

  As shown in the forming step 131 in FIG. 13, first, the dimple 323 is formed such that the solder resist 322 formed on the surface of the circuit board 2 is subjected to blasting only at the position where the dimple 323 is formed. Then, a process of covering the portion other than the position where the dimple 323 is formed with the mask 372 is performed. Next, as shown in the formation step 132, the projection material 374 is injected by blasting. At this time, the projection material 374 sprayed onto the solder resist 322 is sprayed only on the portion where the dimple 323 is formed by the mask 372 applied in the forming step 131, and the portion is cut. As a result, a dimple 323 as shown in the formation step 133 is formed on the surface of the solder resist 322 of the circuit board 2.

  At this time, the size and depth of the diameter of the dimple 323 can be adjusted by adjusting the material, the projection amount, the size (abrasive particle size), the injection pressure, the injection time, and the like of the projection material 374 to be injected. . The depth of the dimple 323 is preferably 10 μm or more and 50 μm or less.

  Here, as for the abrasive grain size of the projection material 374, considering that the dimple diameter is 75 μm or less when the bump pitch, which is the interval between the solder bumps 34, is 150 μm or less, the number is 1000 (10 to 20 μm) to 10000 (0). ˜1 μm) is preferred.

  The blasting process may be either wet blasting or dry blasting. The injection pressure of the projection material 374 is set according to the state of the target surface, but is generally about 0.4 to 0.6 MPa.

  In the present embodiment, the case where the dimple 323 on the circuit board 2 side is formed by using the blast process shown in the formation steps 131 to 133 is described as an example. The dimples may be formed using blasting.

  As described above, a minute recess (dimple 323) is formed in advance on the solder resist 322 of the circuit board 2 inside the minute gap between the circuit board 2 and the semiconductor element 3 by blasting. deep. Thus, according to the present embodiment, as in the first embodiment, the cleaning liquid flow 81 is generated when cleaning impurities such as the flux 7 in the minute gap between the circuit board 2 and the semiconductor element 3. By contacting the dimple 323, a turbulent flow is generated in the cleaning liquid flow 81. As a result, the cleaning effect of impurities inside the gap of the semiconductor device 301 by the cleaning liquid is enhanced.

[Fourth Embodiment]
Next, a fourth embodiment will be described. Differences from the first embodiment will be mainly described, and the same reference numerals are used for the same matters, and descriptions thereof are omitted.

  In the fourth embodiment, a solder resist 422 is further applied on the solder resist 422 formed on the circuit board 2 of the semiconductor device 401 so that the protrusions 423 are formed instead of the dimples. It differs from the first embodiment in that a protrusion 433 is formed in place of the dimple by further applying polyimide 435 on the polyimide 432 formed on the element 3.

First, the main part of the semiconductor device manufacturing method according to the present embodiment will be described. FIG. 14 is a diagram for explaining the main part of the semiconductor device manufacturing method according to the fourth embodiment.
The manufacturing method of the semiconductor device 401 of the present embodiment shown in FIG. 14 is similar to the first embodiment in the step of preparing the circuit board 2 provided with the electrodes 21 on the surface, and the solder on the surface of the circuit board 2. A step of forming a resist 422, a step of forming an opening in the solder resist 422 to expose the electrode 21, a step of preparing the semiconductor element 3 having the electrode 31 on the surface, and a polyimide 432 on the surface of the semiconductor element 3 A step of forming an opening in the polyimide 432 to expose the electrode 31, a step of forming a solder bump 34 on the electrode 31, a step of applying a flux to at least one of the electrode 21 and the solder bump 34, a solder resist 422 and polyimide 432 facing each other and bonding the solder bumps 34 to the electrodes 21, the flow of the cleaning liquid into the gap between the circuit board 2 and the semiconductor element 3. The cleaning liquid flow 481 is supplied and the flux existing in the gap is cleaned. Further, before the flux cleaning step, at least one of the solder resist 422 and the polyimide 432 has a convex portion. (Respective protrusions 423 and 433) are formed.

  In the manufacturing method of the semiconductor device 401 in the present embodiment, as in the first embodiment, first, the circuit board 2 having the electrodes 21 on the surface is prepared, and the solder resist 422 is formed on the surface of the circuit board 2. After that, an opening is formed in the solder resist 422 to expose the electrode 21. Also, a semiconductor element 3 having an electrode 31 on the surface is prepared, and after polyimide 432 is formed on the surface of the semiconductor element 3, an opening is formed in the polyimide 432 to expose the electrode 31, and then a solder bump is applied to the electrode 31. 34 is formed.

  Similar to the first embodiment, the solder resist 422 is an epoxy-based synthetic resin film having photosensitivity, insulation and thermosetting that covers the conductor of the wiring portion such as the copper foil on the surface of the circuit board 2. is there.

The polyimide 432 is a protective film formed on the surface of the semiconductor element 3 as in the first embodiment, and protects the surface of the semiconductor element 3 physically and electrically by insulation.
Next, as in the first embodiment, flux is applied to at least one of the electrode 21 and the solder bump 34, the solder resist 422 and the polyimide 432 are opposed to each other, and the solder bump 34 is joined to the electrode 21. A cleaning liquid flow 481 is supplied to the gap between the substrate 2 and the semiconductor element 3 to clean the flux present in the gap.

  Further, in the present embodiment, before the flux is cleaned, a step of forming the protrusions 423 and 433 on the solder resist 422 and the polyimide 432, respectively, is included. The protrusions 423 and 433 are protrusions formed on the surfaces of the solder resist 422 and the polyimide 432, respectively, and generate a turbulent flow by changing the flow of the cleaning liquid flow 481 in order to improve the cleaning effect. In the present embodiment, the protrusions 423 are formed in the process immediately after the solder resist 422 is formed on the circuit board 2 in the same manner as in the first embodiment because of ease of processing. Similarly, the protrusion 433 is formed in a process immediately after the polyimide 432 is formed on the semiconductor element 3. The step of forming the protrusions 423 and 433 may be performed at any stage as long as possible, as long as it is before the step of cleaning the flux (see FIG. 4 of the first embodiment).

  In the present embodiment, in this way, the semiconductor device 401 from which the flux supplied to the electrode 21 and the solder bump 34 and other impurities adhering in the gap are removed is manufactured.

  In this embodiment, the protrusions 423 and 433 are formed on the solder resist 422 and the polyimide 432, respectively, but the protrusions (any one of the protrusions 423 and 433) may be formed on only one of them.

  Next, a process of forming the protrusions 423 and 433 in this embodiment will be described. FIG. 15 is a diagram illustrating a process of forming protrusions on the circuit board of the semiconductor device according to the fourth embodiment. FIG. 16 is a diagram illustrating a process of forming protrusions on the semiconductor element of the semiconductor device according to the fourth embodiment.

  In the present embodiment, the protrusion 423 of the circuit board 2 and the protrusion 433 of the semiconductor element 3 are formed before the semiconductor element 3 is attached to the circuit board 2 (see the manufacturing step 41 in FIG. 4 of the first embodiment). , Each formed individually.

First, the formation of the protrusion 423 on the circuit board 2 side will be described with reference to FIG.
As shown in the forming step 151 of FIG. 15, the protrusion 423 is formed by previously forming a first-layer solder resist 422 so as to expose the electrode 21 on the surface of the circuit board 2 and then forming the electrode 21 from above. Further, a second layer of solder resist 425 is formed so as to cover. Next, DFR471 is affixed on the surface of the circuit board 2, and a part other than the position where the protrusion 423 is formed is covered with a mask 472 so that the position where the protrusion 423 is formed is exposed. To expose. As a result, the DFR 471 in the portion where the protrusion 423 is formed is exposed.

  Next, as shown in the forming step 152, the DFR 471 is developed. As a result, an etching resistant film by DFR471 is formed on the surface of the portion where the protrusion 423 is formed, which is exposed by being not covered with the mask 72.

  Next, as shown in the formation step 153, an etching process is performed in a state where the DFR 471 other than the position where the protrusion 423 is formed is removed. As a result, the surface of the second-layer solder resist 425 is corroded, so that the solder resist 425 at portions other than the protrusions 423 is removed, and the protrusions 423 that are minute protrusions are formed. Note that in this embodiment mode, dry etching is used as the etching treatment, but wet etching may be used.

  By removing the portions other than the protrusions 423 of the second-layer solder resist 425 by this etching process, the formation of the protrusions 423 of the circuit board 2 is completed as shown in the forming step 154.

  Similarly, the protrusion 433 of the semiconductor element 3 is also formed by etching the surface of the second polyimide 435 of the polyimides 432 and 435 that are doubly formed on the surface of the semiconductor element 3. Next, the formation of the protrusion 433 on the semiconductor element 3 side will be described with reference to FIG.

  The method for forming the protrusion 433 is similar to the protrusion 423 on the circuit board 2 side, as shown in the forming step 161 in FIG. 16, the first layer of polyimide is previously exposed so that the electrode 31 is exposed on the surface of the semiconductor element 3. 432 is formed, and further overlaid thereon so as to cover the electrode 31, a second layer of polyimide 435 is formed. Next, DFR491 is affixed on the surface of the semiconductor element 3, and it covers with the mask 492 so that the position which forms the processus | protrusion 433 may be exposed, Then, DFR491 is exposed with the exposure machine 493. Next, as shown in the forming step 162, the DFR 491 is developed.

  Next, as shown in the formation step 163, etching is performed in a state where the DFR 491 other than the position where the protrusion 433 is formed is removed. As a result, as shown in the forming step 164, the surface of the second layer polyimide 435 is corroded, so that the portions other than the projections 433 of the second layer polyimide 435 are removed, and the projections 433 which are minute convex portions. Is completed.

  After the protrusions 423 and 433 are formed on the circuit board 2 and the semiconductor element 3 in this way, the semiconductor element 3 is joined to the circuit board 2 through the process described in FIG. 4 of the first embodiment. The semiconductor device 1 is completed. The height of the projections 423 and 433 is preferably designed to be 10 μm or more and 50 μm or less. Note that in this embodiment mode, dry etching is used as the etching treatment, but wet etching may be used.

  As described above, the solder resist 425 is further formed on the solder resist 422 of the circuit board 2 in advance. A polyimide 435 is further formed on the polyimide 432 of the semiconductor element 3. Then, by etching, the solder resist 425 is partially removed inside the minute gap between the circuit board 2 and the semiconductor element 3 to form a protrusion 423 that is a minute convex portion, and the polyimide 435 is partially removed. The protrusions 433 that are minute convex portions are formed by removing them. Thus, according to the present embodiment, as in the first embodiment, the cleaning liquid flow 481 is projected when cleaning impurities such as flux in a minute gap between the circuit board 2 and the semiconductor element 3. By contacting 423 and 433, a turbulent flow is generated in the cleaning liquid flow 481. As a result, the cleaning effect of impurities inside the gap of the semiconductor device 401 by the cleaning liquid is enhanced.

  The above merely shows the principle of the present invention. In addition, many modifications and changes can be made by those skilled in the art, and the present invention is not limited to the precise configuration and application shown and described above, and all corresponding modifications and equivalents may be And the equivalents thereof are considered to be within the scope of the invention.

It is a figure explaining the principal part of the manufacturing method of the semiconductor device in 1st Embodiment. 1 is a schematic plan view illustrating a basic structure of a semiconductor device according to a first embodiment. It is a cross-sectional schematic diagram explaining the basic structure of the semiconductor device of 1st Embodiment. It is a figure explaining the outline | summary of the manufacturing process of the semiconductor device in 1st Embodiment. It is a figure explaining the process in which a dimple is formed in the circuit board of the semiconductor device in 1st Embodiment. It is a figure explaining the process in which a dimple is formed in the semiconductor element of the semiconductor device in 1st Embodiment. It is a figure explaining the arrangement | positioning reference | standard regarding the position and diameter of the dimple of the circuit board of the semiconductor device in 1st Embodiment. It is a figure explaining the arrangement | positioning reference | standard regarding the dimple depth of the circuit board of the semiconductor device in 1st Embodiment. It is a figure explaining the arrangement | positioning reference | standard regarding the position and diameter of the dimple of the semiconductor element of the semiconductor device in 1st Embodiment. It is a figure explaining the arrangement | positioning reference | standard regarding the dimple depth of the semiconductor element of the semiconductor device in 1st Embodiment. It is a figure explaining the process of cleaning the semiconductor device in a 1st embodiment. It is a figure explaining the process in which a dimple is formed in the circuit board of the semiconductor device in 2nd Embodiment. It is a figure explaining the process in which a dimple is formed in the circuit board of the semiconductor device in 3rd Embodiment. It is a figure explaining the principal part of the manufacturing method of the semiconductor device in 4th Embodiment. It is a figure explaining the process in which a processus | protrusion is formed in the circuit board of the semiconductor device in 4th Embodiment. It is a figure explaining the process in which a protrusion is formed in the semiconductor element of the semiconductor device in 4th Embodiment. It is a figure which shows the outline | summary of the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1, 201, 301, 401 Semiconductor device 2 Circuit board 3 Semiconductor element 6 Underfill resin 7, 74 Flux 21, 31 Electrode 21a Different potential electrode 22, 222, 322, 422, 425 Solder resist 23, 33, 223, 323 Dimple 24 Solder balls 32, 432, 435 Polyimide 34 Solder bumps 41-49 Manufacturing steps 51-54, 61-64, 121, 122, 131-133, 151-154, 161-164 Formation steps 71, 91, 471, 491 DFR
72, 92, 372, 472, 492 Mask 73, 93, 473, 493 Exposure machine 81, 82, 481 Cleaning liquid flow 111 Cleaning tank 112 Tray 113 Cover part 114 Valve 274 Laser 374 Projection material 423, 433 Projection

Claims (5)

Preparing a circuit board having a first electrode on the surface;
Forming a first film on the surface of the circuit board;
Forming a first opening in the first film to expose the first electrode;
Preparing a semiconductor element having a second electrode on the surface;
Forming a second film on the surface of the semiconductor element;
Forming a second opening in the second film to expose the second electrode;
Forming solder bumps on the second electrode;
Applying a flux to at least one of the first electrode and the solder bump;
Bonding the solder bumps to the first electrode with the first film and the second film facing each other;
Supplying a cleaning liquid to a gap between the circuit board and the semiconductor element to wash the flux present in the gap;
Forming a recess in at least one of the first film and the second film before the step of cleaning the flux;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the recess is formed in the first film during the step of forming the first opening in the first film.   The method of manufacturing a semiconductor device according to claim 1, wherein the recess is formed in the second film during the step of forming the second opening in the second film. Preparing a circuit board having a first electrode on the surface;
Forming a first film on the surface of the circuit board;
Forming a first opening in the first film to expose the first electrode;
Preparing a semiconductor element having a second electrode on the surface;
Forming a second film on the surface of the semiconductor element;
Forming a second opening in the second film to expose the second electrode;
Forming solder bumps on the second electrode;
Applying a flux to at least one of the first electrode and the solder bump;
Bonding the solder bumps to the first electrode with the first film and the second film facing each other;
Supplying a cleaning liquid to a gap between the circuit board and the semiconductor element to wash the flux present in the gap;
Before the step of cleaning the flux, forming a protrusion on at least one of the first film and the second film;
A method for manufacturing a semiconductor device, comprising: A circuit board having a first electrode on the surface;
A first film having a first opening formed on a surface of the circuit board and exposing the first electrode;
A semiconductor element mounted on the surface of the circuit board and having a second electrode on the surface facing the first film;
A second film formed on the surface of the semiconductor element and having a second opening exposing the second electrode;
A solder bump formed on the second electrode and connecting the second electrode to the first electrode;
A recess or projection formed in at least one of the first film and the second film;
A semiconductor device comprising:

Images