JP2009158513A - Nonvolatile semiconductor storage element, nonvolatile semiconductor storage device, data writing method of nonvolatile semiconductor storage element, and data rewriting method of nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which is high in scalability and rewritten in the unit of bits or bytes. <P>SOLUTION: Nonvolatile semiconductor storage elements are arrayed in a matrix form, and a page buffer is provided to a Y side. After data in memory cells connected to one word line are read out to the page buffer, the data in those memory cells are erased. Then, one or a plurality of data among the data read to the page buffer are rewritten and contents of the rewritten page buffer are written back to the respective cells connected to the one word line. Those processes are carried out at high speed to emulate the rewriting by the bits or bytes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that can be rewritten in units of bits or bytes.

  In recent years, LSIs such as microcomputers have been incorporated into various devices, and along with this, there has been an increasing demand to store small to medium-capacity data in each of these many LSIs in a nonvolatile manner. For this purpose, since a medium capacity is sufficient, a non-volatile memory capable of rewriting data in a small unit (about bytes to several bytes) is required.

  Conventionally, there is an EEPROM as a memory element used for such a purpose. However, since the EEPROM has a large cell size and a high operating voltage, it is inferior in scalability, and even at present, only a capacity of about 1 Mbit is realized. That is, (1) Since a voltage of about 20 V is required for the operating voltage, the channel lengths of the selection transistor and the memory cell transistor cannot be shortened, and scaling is difficult, and (2) the tunnel region (thin overlapping the drain region) Therefore, there is a problem that the memory transistor is enlarged, and (3) the structure is complicated and the cell area is difficult to scale.

  On the other hand, flash memories typified by NAND type are now widely used with large capacity and low price. However, the flash memory has a write unit of bytes to pages (about 1 kbytes) and an erase unit of pages (about 1 kbytes) to blocks (about 64 kbytes), which satisfies the rewrite unit required for the above-mentioned embedded use. It was not a thing.

  Conventionally, memories such as pFLASH (registered trademark) (see Patent Document 1) and NeoFlash (registered trademark) (see Patent Document 2) have been proposed.

International Publication No. 99/19880 pamphlet US Pat. No. 7,250,654

  The above-described pFLASH (registered trademark) and NeoFlash (registered trademark) are memory devices composed of memory cells composed of two transistors. However, since they are composed of P channel transistors, they are composed of N channel transistors. Compared with the conventional EEPROM, the operating voltage is relatively low and the cell area is also relatively small.

  However, any of the memory devices cannot be rewritten in units of bytes, and the limit of the scalability of the gate length of the memory cell is about 100 nm, which is the same as that of the NOR flash memory.

  pFLASH (registered trademark) (see Patent Document 1) uses BTBT hot electron injection for writing to reduce current consumption during writing. For this reason, a high voltage (a larger absolute value than the power supply voltage) is applied to the drain. A negative voltage) is required, the select transistor requires a long gate length to turn this voltage on and off, and the storage transistor requires a long gate length to prevent punch-through. Therefore, scaling is difficult.

  Further, NeoFlash (registered trademark) (see Patent Document 2) uses a channel hot electron injection for writing, and thus consumes a large amount of current during writing. Further, since it is necessary to apply a negative high voltage to the drain in order to generate channel hot electrons, it is difficult to scale the gate length of both the select transistor and the memory transistor as in the case of pFLASH (registered trademark).

  The present invention relates to a nonvolatile semiconductor memory device that is highly scalable and can be rewritten in units of bits or bytes, a nonvolatile semiconductor memory element suitable for the nonvolatile semiconductor memory device, and a data writing method for the nonvolatile semiconductor memory element, An object of the present invention is to provide a data rewriting method for a nonvolatile semiconductor memory device.

  The invention according to claim 1 is an n-type well formed in a semiconductor substrate, and a first p + region, a second p + region, and a third p + region formed on the surface of the n-type well at a predetermined interval. A first channel region between the first and second p + regions of the n-type well, a first gate insulating film and a first gate electrode formed above the first channel region; The second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, and a second gate insulating film are formed above the first channel region. And a second gate electrode, wherein the first gate insulating film has a thickness of a gate insulating film of a transistor for a standard power supply voltage (Vcc), or Transistors for external input / output (I / O) Characterized in that it is the same as the thickness of the over gate insulating film.

  According to a second aspect of the present invention, there is provided an n-type well formed in a semiconductor substrate, and a first p + region, a second p + region, and a third p + region formed at predetermined intervals on the surface of the n-type well. And a first channel region between the first and second p + regions of the n-type well, and a first gate insulating film and a first gate electrode formed above the second channel region, The second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, and a second gate insulating film formed above the second channel region. And a second gate electrode, wherein the thickness of the first gate insulating film and the thickness of the tunnel insulating film are the same.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the structure near the boundary between the second p + region and the second channel region of the third p + region is different.

According to a fourth aspect of the present invention, in the third aspect of the invention, the impurity concentration in the vicinity of the second channel region of the second p + region is greater than the impurity concentration in the vicinity of the second channel region of the third p + region. It is also characterized by high.
The nonvolatile semiconductor memory element according to claim 3.

  According to a fifth aspect of the invention, the nonvolatile semiconductor memory elements according to any one of the first to second aspects are arranged in a matrix of X (rows) Y (columns), and word lines provided for each row; A memory cell array having a bit line provided for each column, an X decoder for controlling the voltage of each word line, and a Y decoder for controlling the voltage of each bit line and detecting a sense voltage appearing on each bit line And buffer the sense voltage appearing on all the bit lines, and buffer the write voltage applied to all the bit lines, and control the X decoder and Y decoder to write data to each memory cell, A nonvolatile semiconductor memory device including a controller that performs erasing and reading, wherein the controller stores data in memory cells connected to one word line After reading to the page buffer, the data in these memory cells are erased, and after rewriting one or more of the read data, the contents of the rewritten page buffer are transferred to the one word line. Control is performed to write back to each memory cell connected to the.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the page buffer is formed in the same structure as a standard power supply voltage (Vcc) transistor or an external input / output (I / O) transistor. Features.

  According to a seventh aspect of the present invention, there is provided a data rewriting method for a nonvolatile semiconductor memory device, in which memory cells each comprising a memory transistor and a selection transistor are arranged in a matrix of X (row) Y (column), and word lines provided for each row A memory cell array having a bit line provided for each column; an X decoder for controlling the voltage of each word line; and controlling the voltage of each bit line and detecting a sense voltage appearing on each bit line A nonvolatile semiconductor memory device having a Y decoder and a page buffer for buffering a sense voltage appearing on all bit lines and buffering a write voltage applied to all bit lines is connected to one word line. The procedure for reading the data of the memory cells read into the page buffer, the procedure for erasing the data of these memory cells, the page buffer Procedure for rewriting one or more data among the read data to the file, the procedure written back to the memory cell the contents of the rewritten page buffers connected to said one word line, and controls that cause the execution.

  According to an eighth aspect of the present invention, there is provided a data writing method for a nonvolatile semiconductor memory element comprising: an n-type well formed on a semiconductor substrate; and a first p + region formed at a predetermined interval on the n-type well surface; A first channel region is defined between the second p + region and the third p + region and the first and second p + regions of the n-type well, and the first channel region is formed above the first channel region. A tunnel insulating film formed above the first channel region, with the second channel region defined between the gate insulating film and the first gate electrode of the n-type well and the second and third p + regions of the n-type well A method for writing bit data to a nonvolatile semiconductor memory element having a charge storage layer, a second gate insulating film, and a second gate electrode, wherein the n-type well has a voltage higher than a power supply voltage (Vcc). Positive write back A gate voltage Vwell (p) is applied, a negative voltage Vsg (p) that makes the first channel region conductive is applied to the first gate electrode, and a power voltage is applied to the second gate electrode. By applying a high positive voltage Vcg (p) and setting the first and second p + regions to the ground potential, band-to-band tunneling is performed in the vicinity of the region where the second p + region and the second gate electrode are in contact with each other. Hot electrons are generated by the electrons generated by the above-described method, and the hot electrons are injected into the charge storage layer to write data.

  The invention according to claim 9 is an n-type well formed in a semiconductor substrate, and a first p + region, a second p + region, and a third p + region formed on the surface of the n-type well at a predetermined interval. And a first channel region between the first and second p + regions of the n-type well, and a first gate insulating film and a first gate electrode formed above the second channel region, The second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, and a second gate insulating film formed above the second channel region. And a second gate electrode, wherein a structure near a boundary between the second p + region and the second p + region of the third p + region is different. And

  According to a tenth aspect of the present invention, in the ninth aspect, the impurity concentration in the vicinity of the second channel region of the second p + region is greater than the impurity concentration in the vicinity of the second channel region of the third p + region. It is also characterized by high.

  The invention of claim 11 is a plurality of nonvolatile semiconductor memory elements (hereinafter referred to as memory cells) according to claim 1 or 2 arranged in a matrix of X (rows) Y (columns) and the matrix. And an n-type well block having a word line connected to the second gate electrode of the memory cell in the same row, a gate voltage supply line formed in the Y direction, and each word A memory cell array in which a plurality of pairs each having a p-type well block provided in each line and corresponding to each gate line corresponding to the gate voltage supply line are arranged in the X direction; And a word line selection line connected to the gate electrode of the transfer gate of the same row and a memory of the same row provided for each row of the memory cell array. A memory cell selection line connected to the first gate electrode of the memory cell, a bit line provided for each column of the memory cell array and connected to the first p + region of the memory cells in the same row, And a source line connected to the third p + region of each memory cell of the memory cell array.

  A twelfth aspect of the invention is characterized in that, in the invention of the eleventh aspect, each n-type well block has the number of columns (1 byte) of data write units arranged therein.

The invention of claim 13 is a method of erasing data stored in a memory cell of the nonvolatile semiconductor memory device according to claim 11 or claim 12,
By applying a negative high voltage to one gate voltage supply line and applying a voltage higher than the voltage applied to the gate voltage supply line to one word line selection line, the one gate line The stored contents of only the memory cells connected to the one word line in the n-type well block corresponding to the p-type well block to which the voltage supply line belongs are erased.

  According to the present invention, both the storage transistor (the transistor in the second channel region) and the selection transistor (the transistor in the first channel region) can greatly improve the scalability.

  Further, according to the present invention, simultaneous writing of multiple bits can be performed at high speed. Therefore, even if the rewrite unit is one word line, one word line is read and only necessary bits are rewritten and written back. It is possible to emulate rewriting in bit units from the outside.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of a memory cell according to an embodiment of the present invention. This memory cell is an EEPROM type memory cell having a storage transistor and a selection transistor. FIG. 4A shows an embodiment of a floating gate type EEPROM, and FIG. 4B shows an embodiment of a MONOS type EEPROM.

  In FIG. 1A, the difference from a conventional floating gate type EEPROM is that the transistor is a P-channel MOS transistor, and the insulating film thickness of the selection transistor is used in a peripheral circuit or the like. The film thickness is that of the Vcc transistor and I / O transistor. That is, the conventional EEPROM transistor is composed of a high breakdown voltage transistor capable of turning on / off a voltage of 20 V (drain-source voltage Vds), for example, but the transistor of this embodiment is generally used in a logic LSI. The withstand voltage is the same as that of the transistor used.

  In FIG. 1A, an N-type well 101 is formed near the surface of a P-type substrate 100. A memory cell 1 is formed inside the N-type well 101. The memory cell 1 includes a storage transistor 10 and a selection transistor 11. The storage transistor 10 is a floating gate type transistor, and is a tunnel formed above the channel region 110 between the P + region 104 serving as the source and the P + region 103 serving as the drain (and serving as the source of the selection transistor 11). It consists of an oxide film 111, a floating gate 112, a gate insulating film 113, and a control gate 114. The gate insulating film 113 has a structure in which a dielectric film such as a nitride film is sandwiched between oxide films in order to increase the capacitance between the floating gate 112 and the control gate 114.

  In the select transistor 11, a gate insulating film 117 and a select gate 118 are formed above a channel region 116 between a P + region 102 serving as a drain and a P + region 103 serving as a source. Here, in order to make the formation process of the selection transistor 11 and the storage transistor 10 common, the select gate 118 of the selection transistor 11 opens a hole in the gate insulating film 113 of the storage transistor 10 and forms a polysilicon layer of the control gate 114. The floating gate 112 is penetrated.

  Here, P− regions 105 and 106 as LDD regions are provided on the channel region 116 side of the P + region 102 serving as the drain of the selection transistor and the channel region 110 side of the P + region 104 serving as the source of the storage transistor, respectively. It has been. The P− regions 105 and 106 are intended to prevent unwanted BTBT (interband tunneling) from occurring when a high back gate voltage is applied to the N-well 101 during writing, which will be described later.

  The control gate 114 of the storage transistor 10 is formed as a part of a word line of a memory array configured by arranging the memory chips in an array. The source (P + region) 104 of the storage transistor 10 is connected to the source line of the memory array. The drain (P + region) 102 of the selection transistor 11 is connected to the bit line of the memory array. The select gate 118 of the select transistor 11 is formed as part of the select line of the memory array.

  In FIG. 1 (B), the same number is attached | subjected to the part of the same structure as the figure (A). An N-type well 101 is formed near the surface of the P-type substrate 100. A memory cell 1 is formed inside the N-type well 101. The memory cell 1 includes a storage transistor 10 and a selection transistor 11. The storage transistor 10 is a MONOS type transistor, and is a tunnel oxide formed above a channel region 110 between a P + region 104 serving as a source and a P + region 103 serving as a drain (and serving as a source of the selection transistor 11). The film 111 includes a charge storage layer 112 ′, a gate insulating film 113 ′, and a control gate 114. A non-conductive charge storage film such as a nitride film, a nanocrystal layer, or the like can be applied to the charge storage layer 112 ′.

  In the select transistor 11, a gate insulating film 117 and a select gate 118 are formed above a channel region 116 between a P + region 102 serving as a drain and a P + region 103 serving as a source.

  The control gate 114 of the storage transistor 10 is formed as a part of a word line of a memory array configured by arranging the memory chips in an array. The source (P + region) 104 of the storage transistor 10 is connected to the source line of the memory array. The drain (P + region) 102 of the selection transistor 11 is connected to the bit line of the memory array. The select gate 118 of the select transistor 11 is formed as part of the select line of the memory array.

  FIG. 2 is a plan view of a memory cell array configured by arranging the memory cells shown in FIG. 1 in an X and Y matrix array. The memory cell 1 has a structure in which two transistors (Vcc or I / O transistor and storage transistor) are arranged in the Y direction. Among these, the transistor in the −Y direction (lower side in the drawing) is the storage transistor 10, and the transistor in the + Y direction (upper side in the drawing) is the selection transistor 11. A word line CG is formed in the X direction above the storage transistor 10, and a selection line SG is formed in the X direction above the selection transistor 11. A source line SL is formed below the word line CG, and a bit line BL is formed further above the selection line SG. The bit line BL is formed in the Y direction for each column. The source line is formed in common for all memory cells in the memory array. The bit line BL and the drain 102 of the selection transistor 11 of the memory cell 1 are connected by a contact plug. The source line SL and the source 104 of the storage transistor 10 of the memory cell 1 are connected.

  The write, erase, and read operations of the memory cell 1 will be described with reference to FIGS. FIG. 3A is a comparison diagram of operating conditions of writing, erasing, and reading. 4 and 5 are diagrams showing voltage application conditions and pulse sequences during writing. 6 and 7 are diagrams showing voltage application conditions and a pulse sequence at the time of erasing (first form). 8 and 9 are diagrams showing voltage application conditions and a pulse sequence at the time of erasing (second form). 10 and 11 are diagrams showing voltage application conditions and a pulse sequence during reading.

  First, with reference to FIG. 3A, FIG. 4, and FIG. 5, an operation when data is written to the memory cell, that is, when a memory transistor is programmed (written) will be described.

  A feature of the write operation of this memory cell is that the storage transistor is programmed by hot electrons (BBHE) by BTBT (band-to-band tunneling). A program using BBHE has a writing efficiency about 1000 times higher than that using a channel hot electron (CHE), and simultaneous writing (high-speed writing) of memory cells 1000 times is possible. Still further, the memory cell has a write operation characterized by applying a back gate voltage (for example, 8 V) to the N-type well 101 at the time of writing, so that a small Vds (the drain-source voltage of the storage transistor) can bring BBHE near the drain. It is a point that is generated. As a result, the channel length of the storage transistor can be shortened to increase the scaling efficiency, and the drive transistor for driving the bit line can be configured with a high-speed Vcc transistor (or I / O transistor). High speed writing becomes possible.

  In the initial state, the bit line BL, the selection gate SG, the control gate CG, and the source line SL are all at Vcc (or I / O voltage: hereinafter the same in the description of FIGS. 3 to 11).

(1) The selection gate of the non-selected cell is set to Vsg (p) (for example, -3V) in advance, and the selection transistor of the non-selected cell is turned on in advance, and the back gate voltage of Vwell (p) (for example, 8V) is applied to the N well. Apply. By applying this back gate voltage, BBHE is likely to occur in the selected cell. Since the selection transistor is turned on in the non-selected cell, the drain of the storage transistor (source of the selection transistor) is kept at Vcc, and the voltage does not increase due to coupling with the N well.
The selection gate voltage of the non-selected cell returns to Vcc after the voltage of the N well is stabilized at Vwell (p).

  (2) Next, the bit line of the selected cell is set to 0 V, the selection gate is lowered to Vsg (p) (for example, −3 V) to turn on the selection transistor 11, and the voltage of the control gate CG is set to Vcg (p) ( For example, the voltage is increased to 8V). As a result, the drain (P + region) 103 of the storage transistor 10 becomes 0 V, and BBHE is generated in the vicinity of the drain due to a potential difference with the N well. This BBHE is attracted by the voltage of the control gate CG and injected into the charge storage layer (including the floating gate).

  (3) Thereafter, the bit line, the selection gate, and the control gate of the selected cell are returned to Vcc, and the voltage of the N well is returned to Vcc to complete the writing.

  In the operation (2), an inhibit voltage Vubl (p) (about twice that of Vcc and Vio) is applied to the bit line of the non-selected cell in order to reduce the influence on the non-selected cell sharing the word line with the selected cell. You may apply.

  In the above operation (1), before the back gate voltage of Vwell (p) is applied to the N well, the selection gate of the non-selected cell is turned on in advance by setting the selection gate of the non-selected cell to Vsg (p). However, instead of this, the selection transistor may be turned on by lowering the control gate of the non-selected cell to Vucg (p) (for example, −3 V) as indicated by a dotted line in FIG.

  With reference to FIG. 3A, FIG. 6, and FIG. 7, an operation (first mode) for erasing data in a memory cell will be described. This erasing operation is a charge extracting operation by an FN (Fowler-Nordheim) tunnel current.

  In the initial state, the bit line BL, the selection gate SG, the control gate CG, and the source line SL are all Vcc, and the selection transistors of all the memory cells are turned off.

  In this state, erase voltage Vcg (e1) (for example, −20 V) is applied to the control gate of the selected cell (selected row). As a result, charges are extracted from the charge storage layer toward the substrate, and the memory transistor is erased.

  With reference to FIGS. 3A, 8, and 9, an operation of erasing data in the memory cell (second embodiment) will be described. This erasing operation is a charge extracting operation by the FN tunnel current as in the first embodiment. However, by biasing the entire memory cell (memory cell array) by about 10 V, the erasing voltage applied to the control gate is reduced to about -10 V. (Absolute value). This makes it possible to use a high-speed transistor with a low breakdown voltage as a transistor for driving the control gate.

  All voltages except the control gate of the selected cell (row), that is, N well, source line, bit line of selected cell, selected gate of selected cell, bit line of unselected cell, selected gate of unselected cell, unselected The voltages of Vwell (E2), Vsl (E2), Vbl (E2), Vsg (E2), Vbl (E2), Vsg (E2), and Vucg (E2) are applied to the control gates of the cells, respectively. These voltages may be substantially the same voltage, for example, 10V. Since the N-well has a large capacitance and takes a long time for voltage transition, application may be started slightly earlier than other voltages as shown in FIG. At the same time, the control gate of the selected cell is lowered to Vcg (E2) (for example, −10V). That is, the sum of the bias voltage and the control gate voltage of the selected cell may be a voltage that generates FN. As a result, charges are extracted from the charge storage layer toward the substrate, and the memory transistor is erased.

  With reference to FIG. 3A, FIG. 10, and FIG. 11, the operation of reading data in the memory cell will be described. The application of the Vcc voltage to the bit line of the selected cell is canceled and the selection gate is lowered to 0 V to turn on the selection transistor. Then, the control gate of the storage transistor is lowered to a predetermined voltage. The voltage value Vcg (R) to be lowered is determined by the specification of the storage transistor, that is, by how many V the threshold voltage at the time of programming is set. When the storage transistor is depleted at the time of programming, reading can be performed only by turning on the selection transistor (the control gate voltage remains unchanged). As a result, a current corresponding to on / off of the storage transistor flows through the bit line, and reading is performed by detecting this with a reading circuit (sense amplifier).

  Various voltages are applied to each part at the time of writing, erasing, and reading as described above. FIG. 3B shows a magnitude relational expression of the voltages. In this equation, “=” means that they are substantially equal, such as being supplied from the same power supply circuit, and does not mean that they are strictly the same voltage.

  FIG. 12 is a diagram illustrating a configuration example of a memory device including a memory cell array in which the above-described memory cells are arranged in a matrix of X (row) and Y (column). FIG. 13 is a circuit block diagram for one cell of a page buffer incorporated in the memory device. The page buffer includes the number (for example, 1024) of sense amplifiers and write buffers corresponding to all the bit lines.

  In the memory cell array 20, for example, 1024 memory cells are arranged in the 1024 × Y (column) direction in the X (row) direction. A word line and a selection line are provided for each row, and a bit line is provided for each column. Each word line and each selection line are driven by the X decoder 21. Each bit line is driven by a Y decoder 22. A page buffer 23 is connected between the Y decoder 22 and the memory cell array. The page buffer 23 buffers data of memory cells for one word line (1024 in this example). The page buffer 23 buffers data read from the memory cell and buffers data to be written to the memory cell.

  The operations of the X decoder 21, the Y decoder 22, and the page buffer 23 are controlled by the controller 30. The controller controls writing and erasing of data to a predetermined memory cell and reading of data from the predetermined memory cell in accordance with an instruction from the outside.

  In this memory device, a characteristic operation is a 1-bit rewrite emulation operation.

  This memory device has a page buffer 23 for buffering data for one word line, and can simultaneously write data for one word line by BBHE writing. Since the selection transistor is provided, data can be erased in units of memory cells sharing the word line. Therefore, by causing the controller 30 to perform the following control, data rewriting in 1-bit units can be emulated.

(1) All the data of the memory cells connected to one word line are read out to the page buffer 23.
(2) Erase the data in the memory cells connected to this word line.
(3) Of the data read to the page buffer, rewrite one or more data requested to be rewritten from the outside.
(4) The contents of the rewritten page buffer are written back to the original memory cell connected to the one word line.
The operations (2) and (3) may be performed in the reverse order.

14 to 16 are diagrams showing another embodiment of the memory device. In these embodiments, the connection form of the memory device of FIG. 12 and the page buffer is different. In the embodiment of FIG. 14, the page buffer 23 is arranged on the opposite side of the memory cell array 20 when viewed from the Y decoder 22. In the embodiment of FIG. 15, the page buffer 23 is arranged on the opposite side of the Y decoder when viewed from the memory cell array 20. In the embodiment of FIG. 16, the Y decoder 22 (22A, 22B) and the page buffer 23 (23A, 23B) are provided on both sides of the memory cell array 20 on the Y side (upper) and -Y side (lower). The Y decoder 22A and page buffer 23A decode and buffer odd-numbered bit lines, and the lower Y decoder 22B and page buffer 23B perform decoding and buffering even-numbered bit lines. . Since the circuits of the Y decoder 22 and the page buffer 23 are larger than those of the memory cells, space can be spared by dividing the upper and lower sides in this way, and the scaling efficiency of the memory cells (memory cell array) can be further utilized. it can.
<< Other Embodiments of Memory Cell Array >>
The above embodiment has shown an example of a memory cell array in which one word line is provided for each row. That is, in the memory cell array in which a plurality of memory cells are arranged in a matrix in the XY direction, a word line and a selection line are arranged for each row, and a common source line is arranged for the entire memory cell array.

The memory cell array according to the second embodiment to be described below has a configuration in which the memory cell array is divided into one byte at a time in the row (X) direction and is provided separately for each byte obtained by dividing the word line. Here, 1 byte means a data read / write unit (for example, data bus width), and is not limited to 8 bits.
With such a configuration, rewriting (reading → erasing → writing) can be performed in units of 1 byte.

  17 to 20 are plan views showing the configuration of the memory cell array according to the second embodiment. FIG. 17 shows voltage application conditions at the time of writing. FIG. 18 shows voltages at the time of erasing (first form). FIG. 19 shows voltage application conditions during erasing (second form), and FIG. 20 shows voltage application conditions during reading.

  17-20, each memory cell 101 which comprises the memory cell array 100 is the same as that shown in FIG. 1, FIG. The N well 102 in which each memory cell is arranged is divided into byte blocks (n-type well blocks) 102-n in units of 1 byte (4 bits: 4 columns in the figure), and between the divided N wells. A P-well (p-type well block) 103-n is formed. The memory cell selection line SG is formed for each row across the entire row direction of the memory cell array across the plurality of byte blocks. On the other hand, the word line CG is provided for each row in units of byte blocks. Each word line CG in byte units is connected to a gate voltage supply line MG through a transfer gate Tr. The transfer gate Tr is formed in the P well 103 for each word line CG in byte units. Transfer gates Tr formed in the same P well 103-n and arranged in the column (Y) direction are connected to the same gate voltage supply line MG. Further, the gates of the transfer gates Tr arranged in the same row across the plurality of byte blocks 102-n are connected to the word line selection line WLSG provided over the entire row direction of the memory cell array 100.

  In the memory cell array configured as described above, the voltage to be applied to the word line (control gate) among the write voltage, erase voltage, and read voltage of the first embodiment shown in FIGS. (Or write) is applied to the gate voltage supply line MG of the byte block in which the byte to be written exists. The voltages applied to each bit line, source line, each N well, and each selection line (selection gate) are the same as those in the first embodiment.

  In this embodiment, the following voltages are applied to the word line selection line WLSG and each P well in order to rewrite in units of bytes by applying a voltage only to the word line CG of the byte to be rewritten. .

  At the time of writing shown in FIG. 17, the gate voltage of the transfer gate Tr that applies a voltage to the word line CG of the write byte 110 is set to the same voltage as the voltage applied to the gate voltage supply line MG, and the transfer gate Tr is turned on. . Here, since 10 V is applied to the gate voltage supply line MG, 10 V is also applied to the gate of the transfer gate Tr of the write byte. That is, 10 V is applied to the selected word line selection line WLSG. The other (non-selected) gate voltage supply line MG is 0V, and the other (non-selected) word line selection line WLSG is 0V. All P wells are at 0V.

  At the time of erasing in the first form shown in FIG. 18, −20 V is applied to the gate voltage supply line MG for applying a voltage to the word line (control gate) of the erase byte 111, and the gate voltage supply line MG corresponds to this gate voltage supply line MG. -20V is also applied to the P well 103-1. Then, the selected word line selection line WLSG is set to 0V to turn on the erase gate transfer gate Tr, and -20V is applied to the non-selected word line selection line WLSG to turn off the non-selected transfer gate. Note that the non-selected gate voltage supply line MG and the non-selected P well 103-n are 0V.

  At the time of erasing in the second mode shown in FIG. 19, -10V is applied to the gate voltage supply line MG for applying a voltage to the word line (control gate) of the erase byte 111, and this gate voltage supply line MG is supported. -10 V is also applied to the P well 103-1. Then, the selected word line selection line WLSG is set to 0V to turn on the erase gate transfer gate Tr, and -10V is applied to the non-selected word line selection line WLSG to turn off the non-selected transfer gate. In this erase operation, as shown in FIGS. 8 and 9, 10 V is applied only to the N well 102-1 where the erase byte is arranged. The non-selected gate voltage supply line MG and the non-selected P well 103-n are 0 V, and a voltage (Vcc or IO voltage) of about 1.8 V is applied to the non-selected N well 102-n. .

  At the time of reading shown in FIG. 20, a predetermined voltage (−2V / 0V / 1.8V) is applied to the selected gate voltage supply line MG. What voltage is applied is determined by the specification of the memory transistor of the memory cell. The transfer gate of the read byte is turned on when 3 V is applied to the selected word line selection line WLSG. A voltage of about −2 V to 0 V is applied to the other non-selected word line selection lines WLSG according to the gate voltage. Similarly, a voltage of about −2 V to 0 V is applied to the P well 103-1 in which the transfer gate of the read byte 112 is arranged, depending on the gate voltage. The voltages of the other non-selected P wells 103 are 0V.

  Note that the P wells 103-1 to 103-n in which the transfer gate Tr is formed may be formed in common and controlled to the same potential.

FIG. 21 is a diagram illustrating a configuration example of a memory device including the memory cell array illustrated in FIGS. A sense amplifier / write driver circuit 31 that controls the bit lines and an MG driver 32 that controls the gate voltage supply lines are provided around the Y side of the memory cell array 30. These circuits are provided in a number corresponding to the unit of writing / reading (1 byte), and are assigned to the bit line and MG line on which writing / reading is performed. Further, an SG driver 33 for controlling the selection line SG and a WLSG driver 34 for controlling the word line selection line WLSG are provided around the X side. The operations of the drivers 31 to 34 are controlled by the control circuit / power supply circuit 35.
With the above configuration and voltage application conditions, writing, erasing, and reading can be performed in byte units.

Sectional block diagram of a memory cell (nonvolatile semiconductor memory element) according to an embodiment of the present invention Plane configuration diagram of a memory cell array in which the memory cells are arranged Comparison diagram of operating conditions of writing, erasing and reading of the memory cell The figure which shows the write-voltage application conditions of the said memory cell The figure which shows the pulse sequence at the time of the write-in of the said memory cell The figure which shows the erase (1st aspect) voltage application conditions of the said memory cell The figure which shows the pulse sequence at the time of the erasure | elimination (1st aspect) of the said memory cell The figure which shows the erase (2nd aspect) voltage application conditions of the said memory cell The figure which shows the pulse sequence at the time of the erasure | elimination (2nd aspect) of the said memory cell The figure which shows the read-voltage application conditions of the said memory cell The figure which shows the pulse sequence at the time of the reading of the said memory cell Schematic structure diagram of a memory device including the memory cell Block diagram of a page buffer of the memory device The figure which shows other embodiment of the said memory device. The figure which shows other embodiment of the said memory device. The figure which shows other embodiment of the said memory device. The figure which shows other embodiment (at the time of writing) of a memory cell array The figure which shows other embodiment (at the time of erasing) of a memory cell array The figure which shows other embodiment (at the time of erasing) of a memory cell array The figure which shows other embodiment (at the time of reading) of a memory cell array Schematic structure diagram of a memory device including the memory cell array

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell 10 ... Memory transistor 11 ... Selection transistor 20 ... Memory cell array 21 ... Y decoder 22 ... X decoder 23 ... Page buffer 30 ... Controller 30 ... Memory cell array 31 ... Sense amplifier and write driver circuit 32 ... MG driver 32
33 ... SG driver 33
34 ... WLSG driver 35 ... Control circuit / Power supply circuit

Claims (13)

An n-type well formed in a semiconductor substrate;
A first p + region, a second p + region, and a third p + region formed on the n-type well surface at a predetermined interval;
The first channel region is defined between the first and second p + regions of the n-type well, and a first gate insulating film and a first gate electrode formed above the first channel region,
A second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, a second gate insulating film, and a second channel region formed above the second channel region A second gate electrode;
A non-volatile semiconductor memory device comprising:
The thickness of the first gate insulating film is the same as the thickness of the gate insulating film of the transistor for standard power supply voltage (Vcc) or the thickness of the gate insulating film of the transistor for external input / output (I / O). A non-volatile semiconductor memory element characterized by the above. An n-type well formed in a semiconductor substrate;
A first p + region, a second p + region, and a third p + region formed on the n-type well surface at a predetermined interval;
The first channel region is defined between the first and second p + regions of the n-type well, and a first gate insulating film and a first gate electrode formed above the second channel region;
A second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, a second gate insulating film, and a second channel region formed above the second channel region A second gate electrode;
A non-volatile semiconductor memory device comprising:
The nonvolatile semiconductor memory element, wherein the thickness of the first gate insulating film and the thickness of the tunnel insulating film are the same.   3. The nonvolatile semiconductor memory element according to claim 1, wherein a structure in a vicinity of a boundary between the second p + region and the second channel region of the third p + region is different.   The nonvolatile concentration according to claim 3, wherein an impurity concentration in the vicinity of the second channel region of the second p + region is higher than an impurity concentration in the vicinity of the second channel region of the third p + region. Semiconductor memory element. The nonvolatile semiconductor memory elements according to claim 1 are arranged in a matrix of X (rows) Y (columns), word lines provided for each row, and provided for each column. A memory cell array having bit lines;
An X decoder for controlling the voltage of each word line;
A Y decoder for controlling the voltage of each bit line and detecting a sense voltage appearing on each bit line;
A page buffer that buffers the sense voltage appearing on all bit lines and buffers the write voltage applied to all bit lines;
A controller that controls the X decoder and the Y decoder to write, erase, and read data from and to each memory cell;
A non-volatile semiconductor memory device comprising:
The controller reads data of memory cells connected to one word line to the page buffer, erases data of these memory cells, and further, one or more data among the read data A nonvolatile semiconductor memory device that controls to rewrite the contents of the rewritten page buffer to each memory cell connected to the one word line.   6. The nonvolatile semiconductor memory device according to claim 5, wherein the page buffer is formed in the same structure as a transistor for standard power supply voltage (Vcc) or a transistor for external input / output (I / O). A memory cell array having memory cells made up of memory transistors and select transistors arranged in a matrix of X (rows) Y (columns), word lines provided for each row, and bit lines provided for each column; An X decoder that controls the voltage of each word line, a voltage of each bit line, a Y decoder that detects a sense voltage appearing on each bit line, and a buffer that senses the voltage appearing on all bit lines A nonvolatile semiconductor memory device including a page buffer that buffers a write voltage applied to the bit line of
A procedure for reading data of memory cells connected to one word line to the page buffer;
Procedures to erase the data in these memory cells,
A procedure for rewriting one or more of the data read to the page buffer;
A procedure for writing back the contents of the rewritten page buffer to each memory cell connected to the one word line;
A method for rewriting data in a non-volatile semiconductor memory device, wherein control is performed to execute. An n-type well formed in a semiconductor substrate, a first p + region, a second p + region, and a third p + region formed at a predetermined interval on the surface of the n-type well, and the n-type well A first channel region is defined between the first and second p + regions, a first gate insulating film and a first gate electrode formed above the first channel region, and the n-type well A second channel region is defined between the second and third p + regions, and a tunnel insulating film, a charge storage layer, a second gate insulating film, and a second gate electrode formed above the first channel region A method of writing bit data in a nonvolatile semiconductor memory element having
A negative voltage that applies a positive write back gate voltage Vwell (p) higher than a power supply voltage (Vcc) to the n-type well and makes the first channel region conductive to the first gate electrode. By applying Vsg (p), applying a positive voltage Vcg (p) higher than the power supply voltage to the second gate electrode, and setting the first and second p + regions to the ground potential, Hot electrons are generated by electrons generated by interband tunneling in the vicinity of a region where the second p + region and the second gate electrode are in contact with each other, and data is written by injecting the hot electrons into the charge storage layer. A method for writing data in a nonvolatile semiconductor memory element. An n-type well formed in a semiconductor substrate;
A first p + region, a second p + region, and a third p + region formed on the n-type well surface at a predetermined interval;
The first channel region is defined between the first and second p + regions of the n-type well, and a first gate insulating film and a first gate electrode formed above the first channel region,
A second channel region is defined between the second and third p + regions of the n-type well, and a tunnel insulating film, a charge storage layer, a second gate insulating film, and a second channel region formed above the second channel region A second gate electrode;
A non-volatile semiconductor memory device comprising:
A non-volatile semiconductor memory element, wherein a structure in the vicinity of a boundary between the second p + region and the third channel region of the third p + region is different.   10. The nonvolatile memory according to claim 9, wherein an impurity concentration in the vicinity of the second channel region of the second p + region is higher than an impurity concentration in the vicinity of the second channel region of the third p + region. Semiconductor memory element. A plurality of nonvolatile semiconductor memory elements (hereinafter referred to as memory cells) according to claim 1 or 2 arranged in a matrix of X (row) Y (column), and provided for each row of the matrix, An n-type well block having a word line connected to the second gate electrode of the memory cells in the same row, a gate voltage supply line formed in the Y direction, and provided for each of the word lines, A memory cell array in which a plurality of p-type well blocks each having a transfer gate for opening and closing a word line with respect to the gate voltage supply line are arranged in the X direction;
A word line selection line provided for each row of the memory cell array and connected to the gate electrode of the transfer gate of the same row;
A memory cell selection line provided for each row of the memory cell array and connected to the first gate electrode of the memory cells in the same row;
A bit line provided for each column of the memory cell array and connected to the first p + region of memory cells in the same row;
A source line connected to the third p + region of each memory cell of the memory cell array;
A non-volatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 11, wherein the memory cells are arranged in each n-type well block by the number of columns (1 byte) of a data write unit. A method for erasing data stored in a memory cell of the nonvolatile semiconductor memory device according to claim 11 or 12,
By applying a negative high voltage to one gate voltage supply line and applying a voltage higher than the voltage applied to the gate voltage supply line to one word line selection line,
Data of a nonvolatile semiconductor memory device for erasing the memory contents of only the memory cells connected to the one word line in the n-type well block corresponding to the p-type well block to which the one gate voltage supply line belongs Erasing method.

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