JP2009141260A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce manufacturing cost by about 4% by decreasing lithography steps, and to reduce characteristic variations in V<SB>t</SB>(threshold voltage) and I<SB>on</SB>(on current) among transistors by forming source/drain regions to a recess portion in a self-alignment way. <P>SOLUTION: A manufacturing method of a semiconductor device includes the steps of: (1) providing a first mask; (2) forming an impurity diffusion region by implanting impurities using the first mask for a mask; (3) depositing a second mask on the entire surface; (4) carrying out an etching-back step to leave the second mask by etching-back and to expose a part of the impurity diffusion region; (5) forming a groove portion in a semiconductor substrate by using the first and the second masks for a mask for etching; (6) implanting impurities into the groove portion by using the first and the second masks as the mask; (7) forming a gate insulating film; and (8) forming a gate electrode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a recessed channel transistor, and a semiconductor device manufactured by the method for manufacturing a semiconductor device.

  With the miniaturization of semiconductor devices such as DRAM cells, recess channel transistors have been devised to suppress the short channel effect of transistors. This recess channel type transistor has a gate insulating film and a gate electrode in a groove provided in a semiconductor substrate. Source / drain regions are provided on the surface side of the semiconductor substrate on both sides of the gate electrode. Patent Document 1 and Non-Patent Document 1 disclose this recess channel type transistor.

  A typical manufacturing method for manufacturing the recess channel transistor is shown in FIGS. First, an element isolation region 2 having a depth of about 300 nm is formed on a P-type Si substrate 1 by STI technology. Thereafter, a pad oxide film 3 of about 20 nm is formed on the surface of the P-type Si substrate 1 by thermal oxidation, and then a silicon nitride film is formed on the pad oxide film 3 by about 100 nm by CVD. Thereafter, the photoresist 5 is patterned by using a lithography technique to form a resist pattern having an opening at a position where a recess portion (groove portion) is provided. Next, a mask pattern 4 of a silicon nitride film is formed by dry etching using this resist pattern as a mask (FIG. 2A).

  Thereafter, the resist pattern is removed by an ashing process. Next, in this state, the P-type Si substrate 1 is etched using the mask pattern 4 of the silicon nitride film as a mask to form a Si recess portion (groove portion) 6 having a width of about 90 nm and a depth of about 150 nm (FIG. 2 (b)).

  Subsequently, the mask pattern 4 of the silicon nitride film is removed using high-temperature phosphoric acid, and then the pad oxide film 3 existing on the planar portion is removed with a solution containing hydrofluoric acid (HF). Next, by performing a thermal oxidation method in this state, a silicon oxide film of about 6 nm is formed as a gate insulating film 7 in the Si recess portion (groove portion) 6 (FIG. 3A).

Next, a conductive polysilicon region (phosphorus concentration: 2 × 10 ²⁰ cm ⁻³ ) 8 is formed with a height of about 100 nm so as to fill the Si recess portion (groove portion) 6 by DOPOS (Doped Polycrystalline Silicon) method. It grows so that it may become (FIG.3 (b)).

Subsequently, a photoresist resist mask (not shown) having an opening is formed on a region where the recess channel transistor is to be formed by a normal lithography technique. In this state, boron (B) is implanted under conditions of an implantation energy of 40 keV to 70 keV and a dose of 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² , and a P-type channel region is formed near the bottom of the Si recess portion (groove portion) 6. A doped layer 9 is formed (FIG. 3C).

  Next, a tungsten film 10 having a thickness of about 50 nm is formed on the entire surface by a normal CVD method or sputtering method (FIG. 4A). Thereafter, a silicon nitride film (SiN film) 11 is formed to a thickness of about 150 nm by low pressure CVD. Thereafter, a photoresist mask pattern (not shown) is formed by lithography so as to have a mask on the conductive polysilicon region 8 embedded in the recess (groove) 6. In this state, using this photoresist as a mask, the silicon nitride film 11, the tungsten film 10, and the conductive polysilicon region 8 are sequentially etched by a dry etching technique. Thereby, the gate electrode 12 composed of the tungsten film 10 and the conductive polysilicon region 8 is formed.

In this state, a photoresist mask pattern (not shown) is formed so as to have an opening over the region where the recess channel transistor is to be formed, as before. Next, using this photoresist mask pattern as a mask, phosphorus (P) is implanted under conditions of an implantation energy of 10 keV to 40 keV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² to form a P-type Si substrate. An N-type diffusion layer (source / drain region) 13 is formed on the surface of 1 (FIG. 4B). Thereafter, the photoresist mask is removed by an ashing process.

  Subsequently, a silicon nitride film (SiN film) having a thickness of about 40 nm is formed on the entire surface by CVD, and then etched back by dry etching to form the sidewall film 14 on the side surface of the gate electrode 12. Thereafter, a BPSG film (B, P-containing silicon oxide film) is formed on the entire surface and reflowed, and then planarized by a CMP process to form an interlayer insulating film 15.

  Next, a resist mask (not shown) having an opening is provided on the N-type diffusion layer 13 by lithography. Thereafter, a contact hole is formed so as to penetrate the interlayer insulating film 15 and reach the N-type diffusion layer 13 by a dry etching technique using this resist mask as a mask. Thereafter, conductive polysilicon is formed in the contact hole by DOPOS film formation, and then the cell contact plug 16 is formed by planarization by CMP technique. Next, by performing heat treatment (800 ° C., about 30 min), phosphorus in the cell contact plug 16 is diffused into the N-type diffusion layer (source / drain region) 13 to form the N-type diffusion layer 17. (FIG. 4 (c)).

As described above, in the conventional method for manufacturing a semiconductor device including a recess channel type transistor, it is necessary to use a lithography process in the following process.
(A) Element isolation region forming step (B) Silicon nitride film mask pattern 4 for forming a recess portion (FIG. 2A)
(C) Channel region impurity doping step (FIG. 3C)
(D) Process of processing into shape of gate electrode (FIGS. 4A and 4B)
(E) Source / drain region impurity implantation step (FIG. 4B)
(F) Contact hole forming step (5 (c)).

As described above, the conventional method of manufacturing a semiconductor device requires a large number of lithography processes. In particular, the above steps (C) and (E) increase the manufacturing cost, and the above steps (C) and (E) increase the total manufacturing cost by about 4%. In addition, (E) source / drain region impurity implantation is performed after (D) gate electrode patterning. For this reason, when misalignment occurs between the recess portion (groove portion) and the gate electrode, there is a problem that the source / drain regions cannot be formed in self-alignment with respect to the recess portion (groove portion). .
JP 2006-332211 A J. et al. Y. KIM et al. Symp. on VLSI Tech. , P11-12, 2003

  The present invention has been made in view of the above problems, and by implanting a source / drain region impurity by using a first mask provided in advance as a mask, a source / drain region (impurity diffusion region) is self-aligned. Form. Further, a recess (groove) is formed in self-alignment using the first and second masks as masks. The present invention provides a method of manufacturing a semiconductor device that can reduce the number of lithography steps and reduce the cost by these steps, and can form a source / drain region in a self-aligned manner with respect to a recess portion (groove portion). With the goal.

In order to solve the above problems, the present invention is characterized by having the following configuration.
(1) providing a first mask having a predetermined pattern on a semiconductor substrate;
(2) forming an impurity diffusion region by implanting impurities into the semiconductor substrate using the first mask as a mask;
(3) depositing a second mask on the entire surface;
(4) performing a etch back to leave the second mask on the side surface of the first mask and exposing a part of the impurity diffusion region;
(5) By performing etching of the semiconductor substrate using the first and second masks as masks, a source / drain composed of the impurity diffusion regions on both sides of the groove in the semiconductor substrate. Forming a region;
(6) removing the first and second masks after implanting impurities into the groove using the first and second masks as masks;
(7) forming a gate insulating film on the inner wall of the trench,
(8) forming a gate electrode so as to fill the trench,
A method of manufacturing a semiconductor device comprising a recess channel transistor, comprising:

Compared with the conventional method for manufacturing a semiconductor device, the number of lithography processes can be reduced by two, so that the manufacturing cost as a whole can be reduced by about 4%. In addition, since the source / drain regions can be formed in a self-aligned manner with respect to the recess portion, variations in characteristics such as V _t (threshold voltage) and I _on (on current) of the transistor can be reduced.

The method for manufacturing a semiconductor device of the present invention includes the following steps.
(1) providing a first mask having a predetermined pattern on a semiconductor substrate;
(2) forming an impurity diffusion region by implanting impurities into the semiconductor substrate using the first mask as a mask;
(3) depositing a second mask on the entire surface;
(4) performing a etch back to leave the second mask on the side surface of the first mask and exposing a part of the impurity diffusion region;
(5) A step of forming a source / drain region composed of impurity diffusion regions on both sides of the groove in the semiconductor substrate by etching the semiconductor substrate using the first and second masks as a mask. When,
(6) removing the first and second masks after implanting impurities into the groove using the first and second masks as masks;
(7) forming a gate insulating film on the inner wall of the trench,
(8) A step of forming a gate electrode so as to fill the trench.

  In the method for manufacturing a semiconductor device of the present invention, a lithography process is used in the above steps (1) and (8). Further, in the manufacturing method of the present invention, it is assumed that an element isolation region is formed and a cell contact plug is formed by the STI technique), and in addition to the above steps (1) and (8), an element isolation region forming step is further performed. In the formation of the contact hole, a lithography process is used. As a result, in the manufacturing method of the present invention, a total of two lithography processes are used when the element isolation region and the cell contact plug formation process are not considered, and the total when the element isolation region and the cell contact plug formation process is considered. Four lithography processes will be used.

  In particular, the present invention requires one extra lithography step in step (1) than the conventional manufacturing method. On the other hand, according to the present invention, source / drain regions (impurity diffusion regions) can be formed in self-alignment by implanting source / drain region impurities using a first mask provided in advance as a mask. Further, in the step (5), using the first mask and the second mask as a mask, the central portion of the impurity diffusion region is etched in the thickness direction to form a recess portion (groove portion) in self-alignment. it can. At this time, impurity diffusion regions (that is, source / drain regions) are formed on both sides of the groove.

Further, in the step (6), the recess (groove) can be formed and the impurity for the channel region can be implanted in self-alignment using the first mask and the second mask as masks. As a result, the steps (B), (C), and (E) of the conventional manufacturing method are not required, and the entire manufacturing method can reduce the number of lithography steps twice compared to the conventional manufacturing method. It becomes. As a whole, the manufacturing cost can be reduced by about 4%. In addition, since the source / drain regions can be formed in a self-aligned manner with respect to the recess portion, variations in characteristics such as V _t (threshold voltage) and I _on (on current) of the transistor can be reduced.

  In the step (5), it is preferable to form a groove having a depth of 50 to 200 nm. By forming the groove having a depth of 50 to 200 nm, a recessed channel transistor having stable and high driving characteristics can be obtained.

  The semiconductor device of the present invention has a recess (groove) structure in a portion of a semiconductor substrate partitioned by an element isolation region. A gate insulating film is provided on the inner wall of the recess (groove), and a gate electrode is provided inside the recess (groove). In addition, source / drain regions are provided on both sides of the recess portion (groove portion) of the surface portion of the semiconductor substrate. A recess channel type transistor is constituted by the gate electrode, the gate insulating film, the source / drain region, and the semiconductor region in the vicinity of the recess (groove). In this recess channel type transistor, when a voltage is applied to the gate electrode, a channel current flows between the source / drain regions via the semiconductor region near the recess (groove) due to the electric field effect. The recess channel type transistor may be an N-type transistor or a P-type transistor.

  In addition, the semiconductor device of the present invention may have one recess channel type transistor or a plurality of recess channel type transistors. FIG. 1 is a top view illustrating an example of a semiconductor device of the present invention having a plurality of recessed channel transistors. FIG. 1 shows three source / drain regions 13 surrounded by an ellipse. Two gate electrodes (word lines) 12 are provided on each source / drain region, and two recess channel transistors are configured. A central portion of each source / drain region 13 surrounded by an ellipse is shared between the two recess channel type transistors. Further, the central portion of each source / drain region 13 surrounded by an ellipse is electrically connected to the bit line via the bit contact plug 21.

Examples of the gate insulating film include a silicon oxide film (SiO ₂ ), a silicon nitride film (Si ₃ N ₄ ), a silicon oxynitride film, a laminate of these films, and an oxide containing hafnium (Hf). Can be mentioned. As the gate insulating film, for example, a metal oxide, a metal silicate, a metal oxide, or a high dielectric constant insulating film in which nitrogen is introduced into a metal silicate can be used.

The “high dielectric constant insulating film” refers to an insulating film having a relative dielectric constant (about 3.6 in the case of SiO ₂ ) larger than that of SiO ₂ widely used as a gate insulating film in a semiconductor device. Typically, the dielectric constant of the high dielectric constant insulating film can be several tens to thousands. As the high dielectric constant insulating film, for example, HfSiO, HfSiON, HfZrSiO, HfZrSiON, ZrSiO, ZrSiON, HfAlO, HfAlON, HfZrAlO, HfZrAlON, ZrAlO, ZrAlON, or the like can be used.

The gate electrode can be composed of, for example, conductive polysilicon, metal, silicide, or a laminate thereof. The conductive polysilicon can be obtained, for example, by including N-type impurities in the polysilicon. At this time, the concentration of the N-type impurity is preferably in the range of 1.0 × 10 ^{20 to} 1.0 × 10 ²¹ / cm ³ . Examples of the N-type impurity include phosphorus and arsenic.

Specific examples of the silicide include NiSi, Ni ₂ Si, Ni ₃ Si, NiSi ₂ , WSi, TiSi ₂ , VSi ₂ , CrSi ₂ , ZrSi ₂ , NbSi ₂ , MoSi ₂ , TaSi ₂ , CoSi, CoSi _2. , PtSi, Pt ₂ Si, Pd ₂ Si, and the like, but WSi is preferably used from the viewpoint of conductivity and workability.

  The semiconductor device of the present invention may have, for example, a planar field effect transistor or a fin field effect transistor around the recess channel transistor.

  Furthermore, the memory cell can be configured by electrically connecting the source / drain region of the recess channel transistor and the capacitor via the cell contact plug. In this case, one memory cell is composed of one recess channel transistor and one capacitor. A DRAM (Dynamic Random Access Memory) can be configured by providing a plurality of memory cells and electrically connecting the gate electrodes of the recess channel transistors to form word lines.

(First embodiment)
First, an element isolation region 2 having a depth of about 300 nm was formed in a P-type Si substrate 1 by STI (shallow trench isolation) method. Thereafter, a pad oxide film 3 of about 10 nm was formed on the surface of the P-type Si substrate 1 by thermal oxidation. Thereafter, a silicon nitride film having a thickness of about 100 nm was formed on the entire surface by CVD. Thereafter, after forming a resist mask by lithography, the silicon nitride film is processed by dry etching using the resist mask as a mask to form a first mask 18 having a desired pattern (FIG. 5A). Step (1)).

Next, using the first mask 18 as a mask, phosphorus (P) is ion-implanted into the P-type Si substrate 1 under conditions of an implantation energy of 10 keV to 50 keV and a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ^2. Thus, the impurity diffusion region 13 was formed (FIG. 5B; step (2)). In this step (2), since the first mask 18 already exists on the P-type Si substrate 1 as described above, this becomes a mask at the time of impurity implantation for the impurity diffusion region, and a new lithography step is added. Without this, phosphorus can be injected into a desired location by self-alignment.

  Next, a silicon nitride film having a thickness of about 30 nm was formed on the entire surface by CVD to form a second mask 19 (FIG. 5C; step (3)). Next, the second mask 20 was formed by allowing the silicon nitride film to remain on the side surfaces of the first mask by the entire surface etch back. At this time, the pad oxide film 3 on the impurity diffusion region in the semiconductor substrate was exposed (step (4)).

  In this state, the Si recess portion (groove portion) 6 was formed in the P-type Si substrate 1 by etching the P-type Si substrate 1 using the first and second masks as masks. At this time, the previously formed impurity diffusion regions remain on both sides of the Si recess portion (groove portion) 6, and the impurity diffusion regions remaining on both sides of the Si recess portion (groove portion) 6 are connected to the source / drain regions 13. (FIG. 6A; step (5)).

Next, boron (B) is implanted on the entire surface under conditions of an implantation energy of 5 keV to 15 keV and a dosage of 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² , or BF ₂ is implanted with an implantation energy of 10 to 50 keV and a dosage. The injection was performed under the condition of 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² . As a result, a P-type channel region doped layer 9 was formed (FIG. 6B; step (6)). In the steps (5) and (6), the first mask, the second mask, and the element isolation region 2 function as a mask, as in the impurity implantation step in the step (2), so that a new lithography step is not required. Can do. At this time, boron or BF ₂ was doped only at the bottom of the Si recess portion (groove portion) 6.

Next, the first and second masks of the silicon nitride film were removed using high temperature phosphoric acid. Thereafter, a thermal oxidation method was performed in this state to form a silicon oxide film having a thickness of about 6 nm as the gate insulating film 7 in the Si recess portion (groove portion) 6 (step (7)). Next, a conductive polysilicon region (phosphorus concentration: 2 × 10 ²⁰ cm ⁻³ ) 8 is formed with a height of about 100 nm so as to fill the Si recess portion (groove portion) 6 by DOPOS (Doped Polycrystalline Silicon) method. Grown to be.

  Next, a tungsten film 10 having a thickness of about 50 nm was formed on the entire surface by an ordinary CVD method or sputtering method. Thereafter, a silicon nitride film (SiN film) 11 having a thickness of about 150 nm was formed by low-pressure CVD. Thereafter, a photoresist resist mask (not shown) was formed by lithography so as to have a mask on the recess (groove). In this state, using the resist mask as a mask, the silicon nitride film 11, the tungsten film 10, and the conductive polysilicon region 8 were sequentially etched by a dry etching technique. As a result, a gate electrode 12 composed of the tungsten film 10 and the conductive polysilicon region 8 was formed (FIG. 6C; step (8)).

  Subsequently, a silicon nitride film (SiN film) having a thickness of about 40 nm was formed on the entire surface by CVD, and then etched back by dry etching to form a sidewall film 14 on the side surface of the gate electrode. Thereafter, a BPSG film (B, P-containing silicon oxide film) was formed on the entire surface and reflowed, and then planarized by a CMP process to form an interlayer insulating film 15.

  Next, a resist mask (not shown) having an opening was provided on the N-type diffusion layer 13 by lithography. Thereafter, a contact hole was formed so as to penetrate the interlayer insulating film 15 and reach the N-type diffusion layer 13 by a dry etching technique using this resist mask as a mask. Thereafter, conductive polysilicon was formed in the contact hole by DOPOS film formation, and then the cell contact plug 16 was formed by planarization by CMP technique. Next, by performing heat treatment (800 ° C., about 30 min), phosphorus in the cell contact plug 16 is diffused to the N-type diffusion layer (source / drain region) 13 to form an N-type diffusion layer 17 ( FIG. 7).

  In the manufacturing method shown in this embodiment, the number of lithography processes is reduced by two as a whole compared with the conventional manufacturing method, so that the manufacturing cost can be reduced. Further, an impurity diffusion region is provided in advance, a Si recess portion (groove portion) 6 is formed in the central portion of the impurity diffusion region, and a gate electrode and a gate insulating film are formed in the Si recess portion (groove portion) 6. Therefore, the source / drain regions can be formed in a self-aligned manner with respect to the Si recess portion (groove portion) 6.

(Second embodiment)
In this embodiment, a capacitor (not shown) is provided so as to be electrically connected to the cell contact plug of FIG. 7 in the first embodiment, and the recess channel transistor and the capacitor constitute a memory cell. The present invention relates to a semiconductor device.

  The semiconductor device can be manufactured in the same manner as in the first embodiment up to FIGS. A known method can be used as a capacitor manufacturing process.

(Third embodiment)
This embodiment differs from the semiconductor device of the first embodiment in that the gate electrode of the recess channel transistor is made of silicide. When forming the gate electrode, for example, in the steps of FIGS. 6B to 6C, after filling the Si recess portion (groove portion) 6 with a polysilicon layer, the gate electrode is formed on the polysilicon layer. Deposit a metal layer. Then, silicide can be formed by heat treatment. Note that the thickness of the polysilicon layer, the type of metal and the thickness of the metal layer, and the temperature and time during the heat treatment may be appropriately adjusted according to the desired silicide. Examples of the silicide include NiSi, Ni ₂ Si, Ni ₃ Si, NiSi ₂ , WSi, TiSi ₂ , VSi ₂ , CrSi ₂ , ZrSi ₂ , NbSi ₂ , MoSi ₂ , TaSi ₂ , CoSi, CoSi ₂ , PtSi, Pt. ₂ Si, Pd ₂ Si and the like can be mentioned, but WSi is preferably used from the viewpoint of conductivity and workability.

  The semiconductor device of the present invention can be used as a memory cell for DRAM (Dynamic Random Access Memory) or the like.

It is a figure showing an example of the semiconductor device of the present invention. It is a figure showing the manufacturing method of the conventional semiconductor device. It is a figure showing the manufacturing method of the conventional semiconductor device. It is a figure showing the manufacturing method of the conventional semiconductor device. It is a figure showing an example of the manufacturing method of the semiconductor device of this invention. It is a figure showing an example of the manufacturing method of the semiconductor device of this invention. It is a figure showing an example of the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

1 P-type Si substrate 2 Element isolation region 3 Pad oxide film 4 Silicon nitride film mask pattern 5 Resist pattern 6 Recessed portion (groove portion)
7 Gate insulating film 8 Conductive polysilicon region 9 P-type channel region doped region 10 Tungsten film 11 Silicon nitride film 12 Gate electrode 13 Source / drain region 14 Side wall film 15 Interlayer insulating film 16 Cell contact plug 17 N-type diffusion layer 18 1 mask 19, 20 second mask 21 bit contact plug 22 bit line

Claims (8)

(1) providing a first mask having a predetermined pattern on a semiconductor substrate;
(2) forming an impurity diffusion region by implanting impurities into the semiconductor substrate using the first mask as a mask;
(3) depositing a second mask on the entire surface;
(4) performing a etch back to leave the second mask on the side surface of the first mask and exposing a part of the impurity diffusion region;
(5) By performing etching of the semiconductor substrate using the first and second masks as masks, a source / drain composed of the impurity diffusion regions on both sides of the groove in the semiconductor substrate. Forming a region;
(6) removing the first and second masks after implanting impurities into the groove using the first and second masks as masks;
(7) forming a gate insulating film on the inner wall of the trench,
(8) forming a gate electrode so as to fill the trench,
A method of manufacturing a semiconductor device comprising a recess channel transistor, comprising: In the step (5),
The method for manufacturing a semiconductor device according to claim 1, wherein the groove portion having a depth of 50 to 200 nm is formed. In the step (6),
B as the impurity has an implantation energy of 5 to 15 keV and a dose of 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² , or BF ₂ as the impurity has an implantation energy of 10 to 50 keV and a dose of 1 × 10 ^{12 to} 5 ×. The method for manufacturing a semiconductor device according to claim 1, wherein the implantation is performed under a condition of 10 ¹³ / cm ² . The step (8)
(9) forming a conductive polysilicon region so as to fill the groove portion;
(10) forming a metal layer on the conductive polysilicon region;
Have
The method for manufacturing a semiconductor device according to claim 1, wherein a gate electrode made of the conductive polysilicon region and a metal layer is formed as the gate electrode. In the step (9),
5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive polysilicon region is formed by a DOPOS (Doped Polycrystalline Silicon) method. After the step (8),
(11) forming an interlayer insulating film on the entire surface;
(12) forming a contact plug so as to penetrate through the interlayer insulating film to the source / drain region;
(13) forming a capacitor so as to be electrically connected to the contact plug;
The method for manufacturing a semiconductor device according to claim 1, wherein: In the step (12), a contact plug composed of conductive polysilicon containing impurities is formed as the contact plug,
After the step (12),
(14) The method according to claim 6, further comprising the step of diffusing impurities in the conductive polysilicon into the source / drain regions by performing a heat treatment.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.

Images