JP2009076736A - Semiconductor device, display device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing variation in threshold voltage etc., and has high-reliability and high-performance TFT characteristics. <P>SOLUTION: The semiconductor device has: a polycrystalline semiconductor layer 4a which is formed on a substrate and has a source region 4c, a drain region 4d, and a channel region 4b; a metallic conductive layer 6 formed on the source region 4c and drain region 4d of the polycrystalline semiconductor layer 4a; and an alloy layer 5 formed between the polycrystalline semiconductor layer 4a and metallic conductive layer 6, wherein the polycrystalline semiconductor layer 4a has a recessed portion 4e formed so that the film thickness in the channel region 4b is less than the film thickness in the region where the metallic conductive layer 6 is formed, and satisfies expression (1) of 0.1t≤Y≤0.3t and expression (2) of 0.3Y≤X≤2Y, wherein X is the depth of the recessed portion 4e, Y is the thickness of the alloy layer 5 and (t) is the thickness of the metallic conductive layer 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a display device, and a manufacturing method thereof, and more particularly, a semiconductor device, a display device, and a semiconductor device using polysilicon, which is a polycrystalline semiconductor layer obtained by crystallizing amorphous silicon, which is an amorphous semiconductor layer, by laser annealing. It relates to a manufacturing method.

  In recent years, a display device such as a liquid crystal display or an organic EL display using a semiconductor device having a low-temperature polysilicon TFT (Thin Film Transistor) structure has attracted attention because it can obtain high definition, high mobility, and high reliability.

  A method for manufacturing a semiconductor device having a low-temperature polysilicon TFT structure will be described below with reference to FIG. FIG. 10 shows a structure of a conventional semiconductor device. First, amorphous silicon is sequentially formed on the glass substrate 1 as a base nitride film 2, a base oxide film 3, and an amorphous semiconductor layer by plasma CVD. Next, annealing is performed to reduce the hydrogen concentration in the amorphous silicon. Then, the amorphous silicon is crystallized by laser annealing to form polysilicon which is a polycrystalline semiconductor layer. Next, the metallic conductive layer 6 is formed by sputtering. At this time, the alloy layer 5 of the polycrystalline semiconductor layer and the metallic conductive layer 6 is formed at the interface between the metallic conductive layer and the polycrystalline semiconductor layer.

  Thereafter, the metallic conductive layer 6 is patterned into a desired pattern by photolithography. Next, the polycrystalline semiconductor layer is patterned into a desired pattern by photolithography. Then, the metal conductive layer 6 corresponding to the channel region 4b of the polycrystalline semiconductor layer is removed by etching. Next, the alloy layer 5 of the polycrystalline semiconductor layer and the metallic conductive layer 6 is removed by etching. The metallic conductive layer 6 is formed only in the source region 4c, the drain region 4d and the storage capacitor portion excluding the channel region 4b of the polycrystalline semiconductor layer.

  Next, the gate insulating film 7 is formed by the CVD method. Then, the gate wiring 8 is formed by sputtering. The gate wiring 8 is a metal material or an alloy material such as Al, Cr, Mo, Ti, and W. Next, a resist pattern is formed by photolithography and the gate wiring 8 is patterned into a desired shape with an etching solution, and then the resist is removed.

  Next, impurities are introduced into the source region 4c and drain region 4d of the polycrystalline semiconductor layer using the formed gate wiring 8 as a mask. Here, P and B can be used as impurity elements to be introduced. If P is introduced, an n-type TFT can be formed, and if B is introduced, a p-type TFT can be formed. One-channel low-temperature polysilicon TFTs can be made n-type or p-type depending on the specifications of the display device used. Further, both the n-type and p-type low-temperature polysilicon TFTs can be formed as in the CMOS structure.

Next, the interlayer insulating layer 9 is formed by plasma CVD. The interlayer insulating layer 9 includes a silicon oxide film obtained by reacting SiH ₄ and N ₂ O, or TEOS (tetra ethoxy silane, Si (OC ₂ H ₅ ) ₄ ) and O _2, and nitriding obtained by reacting SiH ₄ and NH _3. A single layer film or a stacked film of a silicon film or a silicon oxynitride film obtained by reacting SiH ₄ with N ₂ O and NH ₃ can be used.

  Next, heat treatment is performed to diffuse doped P (phosphorus) and B (boron) by ion doping. Next, the signal line 10 is formed by sputtering. The conductive film that becomes the signal line 10 is Cr, Mo, W, Ta, Al, or an alloy film containing these as a main component. Next, a resist pattern is formed by photolithography and the signal line 10 is patterned into a desired shape with an etching solution, and then the resist is removed.

  Next, the protective film 11 is formed by plasma CVD. Thereafter, a resist pattern is formed by photolithography, contact holes are formed in the gate insulating film 7, the interlayer insulating layer 9, and the protective film 11 by a dry etching method, and then the resist is removed.

  Next, the pixel electrode 13 is formed by sputtering. The pixel electrode 13 may be a conductive film having transparency such as ITO or IZO. Next, a resist pattern is formed by photolithography, and the pixel electrode 13 is patterned into a desired shape with an etching solution, and the resist is removed. By the above manufacturing method, a semiconductor device having a low-temperature polysilicon TFT structure is completed. A semiconductor device in which the thickness of the channel region is thinner than that of the source region 4c and the drain region 4d is described in Patent Document 1, for example.

JP 2006-313776 A

  As described above, in the conventional semiconductor device, the metal conductive layer 6 and the alloy layer 5 on the channel region 4b of the polycrystalline semiconductor layer are removed. However, it was found that a clean channel region of the polycrystalline semiconductor layer was not formed only by removing the metal conductive layer 6 and the alloy layer 5 on the channel region 4b of the polycrystalline semiconductor layer. For this reason, there is a problem that characteristics such as a threshold voltage vary and the TFT characteristics of the semiconductor device are deteriorated.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device having high-reliability and high-performance TFT characteristics that can reduce variations in threshold voltage and the like. It is providing the display apparatus using these, and these manufacturing methods.

A semiconductor device according to one embodiment of the present invention includes a semiconductor layer formed over a substrate and having a source region, a drain region, and a channel region, and a metal conductive layer formed over the source region and the drain region of the semiconductor layer. And an alloy layer of the semiconductor layer and the metallic conductive layer formed between the semiconductor layer and the metallic conductive layer, wherein the semiconductor layer has a thickness of the channel region, It has a recess formed to be thinner than the thickness of the region where the metallic conductive layer is formed, the depth X of the recess, the thickness Y of the alloy layer, and the thickness of the metallic conductive layer. t satisfies the relationship of the following two expressions.
0.1t ≦ Y ≦ 0.3t
0.3Y ≦ X ≦ 2Y

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a semiconductor layer over a substrate, a metal conductive layer over the semiconductor layer, and the semiconductor layer between the semiconductor conductive layer and the metal conductive layer. Forming an alloy layer of the semiconductor layer and the metallic conductive layer, removing the metallic conductive layer on the channel region of the semiconductor layer, and the alloy on the channel region of the semiconductor layer. Removing the layer and removing the channel region of the semiconductor layer to form a recess in the channel region of the semiconductor layer, the depth X of the recess, the film thickness Y of the alloy layer, The concave portion is formed so that the thickness t of the metallic conductive layer satisfies the relationship of the following two formulas.
0.1t ≦ Y ≦ 0.3t
0.3Y ≦ X ≦ 2Y

  According to the present invention, variations in threshold voltage and the like can be reduced, and a highly reliable semiconductor device having high-performance TFT characteristics, a display device using the semiconductor device, and a manufacturing method thereof can be provided.

  Embodiments to which the present invention can be applied will be described below. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate.

Embodiment 1 FIG.
A display device according to Embodiment 1 of the present invention will be described with reference to FIGS. The display device according to this embodiment is an active matrix display device including a thin film transistor (TFT) which is an example of a semiconductor device. Here, a transmissive liquid crystal display device will be described as an example of a display device. FIG. 1 is a plan view showing a configuration of a liquid crystal display device 100 according to the present embodiment. FIG. 2 is a cross-sectional view showing the configuration of the liquid crystal display device 100 according to the present embodiment. For the sake of explanation, the counter substrate and the like are not shown in FIG.

  As shown in FIGS. 1 and 2, the liquid crystal display device 100 includes a liquid crystal panel 101 and a backlight 102. The liquid crystal panel 101 includes a thin film transistor substrate (TFT substrate) 1, a counter substrate 20, a sealing material 21, a liquid crystal 22, a spacer 23, a gate line (scanning line) 24, a source line (signal line) 25, an alignment film 26, and a counter electrode 27. , A polarizing plate 28, a gate driver 29, and a source driver 30. A point to be noted in the present invention is a TFT formed on the TFT substrate 1, which will be described in detail later.

  A plurality of gate lines 24 and a plurality of source lines 25 are formed in the display area of the TFT substrate 1. The plurality of gate lines 24 are provided in parallel. Similarly, the plurality of source lines 25 are provided in parallel. The gate line 24 and the source line 25 are formed so as to cross each other through an insulating layer.

  A thin film transistor (TFT) 31 is provided near the intersection of the gate line 24 and the source line 25. A pixel electrode (not shown) is formed in a region surrounded by the adjacent gate line 24 and source line 25. A region surrounded by the adjacent gate line 24 and source line 25 is a pixel. Accordingly, pixels are arranged in a matrix on the TFT substrate 1. The gate of the TFT 31 is connected to the gate line 24, the source is connected to the source line 25, and the drain is connected to the pixel electrode. The pixel electrode is formed of a transparent conductive thin film such as ITO (Indium Tin Oxide).

  As shown in FIG. 2, the liquid crystal panel 101 has a configuration in which a liquid crystal 22 is sealed in a space between a TFT substrate 1, a counter substrate 20 disposed to face the TFT substrate 1, and a sealing material 21 for bonding the two substrates. have. A distance between the two substrates is maintained by a spacer 23 so as to have a predetermined interval. As the TFT substrate 1 and the counter substrate 20, an insulating substrate such as a light transmissive glass substrate or a quartz substrate is used.

  In the TFT substrate 1, an alignment film 26 is formed on each of the electrodes and wirings described above. On the other hand, a color filter (not shown), a BM (Black Matrix) (not shown), a counter electrode 27, an alignment film 26, and the like are formed on the surface of the counter substrate 20 facing the TFT substrate 1. A polarizing plate 28 is attached to each of the outer surfaces of the TFT substrate 1 and the counter substrate 20.

  Further, as shown in FIG. 1, a gate driver 29 and a source driver 30 are provided in the peripheral region of the TFT substrate 1. The gate line 24 extends from the display area to the peripheral area. The gate line 24 is connected to the gate driver 29 at the end of the TFT substrate 1. Similarly, the source line 25 extends from the display area to the peripheral area. The source line 25 is connected to the source driver 30 at the end of the TFT substrate 1.

  A backlight 102 is provided on the back surface of the liquid crystal panel 101. The backlight 102 irradiates the liquid crystal panel 101 with light from the non-viewing side of the liquid crystal panel 101. As the backlight 102, for example, a backlight having a general configuration including a light source, a light guide plate, a reflection sheet, a diffusion sheet, a prism sheet, a reflection polarizing sheet, and the like can be used.

Here, the TFT substrate 1 will be described in detail with reference to FIG. FIG. 3 is a diagram showing a configuration of the TFT substrate 1 using the semiconductor device according to the present embodiment. As described above, the TFT substrate 1 is a transparent insulating substrate such as a glass substrate or a quartz substrate. As shown in FIG. 3, a first base film 2 and a second base film 3 are sequentially stacked on the TFT substrate 1 as a base film of a semiconductor layer. As the first base film 2 and the second base film 3, a SiN film or a SiO ₂ film which is a transmissive insulating film can be used. These base films are provided mainly for the purpose of preventing mobile ions such as Na from the glass substrate from diffusing into the semiconductor layer.

  A polycrystalline semiconductor layer 4 a is formed on the second base film 3. The polycrystalline semiconductor layer 4a has a source region 4c, a channel region 4b, and a drain region 4d. Specifically, the polycrystalline semiconductor layer 4a has a conductive region containing impurities, and this portion forms a source region 4c and a drain region 4d. A region sandwiched between the source / drain regions becomes a channel region. Further, the polycrystalline semiconductor layer 4a is formed to extend to a region that becomes a storage capacitor portion. A TFT and a storage capacitor are formed using the polycrystalline semiconductor layer 4a.

  A metal conductive layer 6 is formed on the polycrystalline semiconductor layer 4a so as to correspond to the source region 4c and the drain region 4d. As the metallic conductive layer 6, a metal film such as Cr, Mo, W, Ta, or the like, or an alloy film having a conductivity containing a metal or a non-metal element as a main component thereof is used. The metallic conductive layer 6 is electrically connected to the source region 4c and the drain region 4d. The metallic conductive layer 6 is also formed on the polycrystalline semiconductor layer 4 a that forms a storage capacitor connected in series to the TFT 31. By laminating the low-resistance metallic conductive layer 6 on the polycrystalline semiconductor layer 4a serving as the lower electrode of the storage capacitor, a desired voltage can be reliably applied to the lower electrode, and the stable capacitance can be obtained. Is formed. In addition, since the metallic conductive layer 6 is formed on the polycrystalline semiconductor layer 4a, the polycrystalline semiconductor layer is oxidized even when a transparent conductive oxide film, which will be described later, is connected via a contact hole. This is advantageous in that good contact resistance can be obtained.

  Here, the film thickness t of the metallic conductive layer 6 is 30 nm or less, preferably 25 nm or less. When the thickness of the metallic conductive layer 6 exceeds 30 nm, impurity ions cannot sufficiently reach the lower polycrystalline semiconductor layer 4a, and ohmic contact between the metallic conductive layer 6 and the polycrystalline semiconductor layer 4a occurs. This is because it cannot be obtained.

  Further, when the metallic conductive layer 6 is formed on the polycrystalline semiconductor layer 4 a, an alloy layer of the polycrystalline semiconductor layer 4 a and the metallic conductive layer 6 is formed at the interface between the polycrystalline semiconductor layer 4 a and the metallic conductive layer 6. 5 is formed. This alloy layer 5 is formed in a range of 0.1 t ≦ Y ≦ 0.3 t, where Y is the film thickness. Since the substrate temperature increases as the film thickness t of the metallic conductive layer 6 to be formed increases, the film thickness of the alloy layer 5 also increases.

  In the polycrystalline semiconductor layer 4a, a recess 4e is formed so that the channel region 4b is thinner than the region where the metal conductive layer 6 is formed. Here, with reference to FIG. 4, the recessed part 4e formed in the polycrystalline-semiconductor layer 4a is demonstrated in detail. FIG. 4 is a diagram showing a part of the structure of the TFT according to the present invention. As shown in FIG. 4, a recess 4e is formed in the channel region 4b of the polycrystalline semiconductor layer 4a.

  The depth X of the recess 4e (the amount of shaving of the channel region 4b of the polycrystalline semiconductor layer 4a) and the film thickness Y of the alloy layer 5 are set to satisfy the relationship of 0.3Y ≦ X ≦ 2Y. Further, the depth Z (total cutting amount of the alloy layer 5 and the channel region 4b) obtained by adding the depth X of the recess 4e and the film thickness Y of the alloy layer 5 satisfies 1.3Y ≦ Z ≦ 3Y. Become.

  In such a semiconductor device in which the recess 4e is formed in the channel region 4b of the polycrystalline semiconductor layer 4a, the depth Z (total cutting amount Z = the sum of the depth X of the recess 4e and the film thickness Y of the alloy layer 5). The relationship between (X + Y) and the CV characteristic will be described. In general, the CV curve is a CV curve A shown in FIG. However, if the surface of the channel region 4b is not clean and there is metal contamination or the like, the CV curve becomes the CV curve B.

  In the present embodiment, the total cutting amount Z (Z = X + Y) is changed, and the CV curve at that time is obtained. Here, since the film thickness Y of the alloy layer 5 is fixed at Y = 2 nm, the depth X of the recess 4e (the amount of cutting of the polycrystalline semiconductor layer 4a) X is changed. And the inclination of the tangent of the inclination part of the CV curve was calculated | required. The inclination of the tangent line of the inclined portion of the CV curve corresponds to the inclination of the tangent line A and tangent line B in FIG.

  FIG. 6 shows the relationship between the total amount of cutting Z and the slope of the tangent line. It shows that the larger the slope of the tangent (in arbitrary units), the cleaner the surface of the channel region and the better the CV characteristics. Referring to FIG. 6, the CV characteristic is good when the total amount of cutting Z is in the range of 2.3 nm ≦ Z ≦ 6.2 nm. In this embodiment, since the film thickness Y of the alloy layer 5 is fixed at Y = 2 nm, the state in which the alloy layer 5 remains on the channel region 4b when the total scraping amount Z is smaller than 2 nm in FIG. It becomes.

  Therefore, if the channel region 4b of the polycrystalline semiconductor layer 4a is etched so as to satisfy the relational expressions 0.3Y ≦ X ≦ 2Y and 1.3Y ≦ Z ≦ 3Y, a semiconductor device having good TFT characteristics can be obtained. . That is, when Y = 2 nm, the depth X of the recess 4e is 0.6 nm ≦ X ≦ 4 nm, and the total amount of cutting Z is 2.6 nm ≦ Z ≦ 6 nm. Thereby, the CV characteristic of a semiconductor device can be made into a favorable range.

  Further, when manufacturing a semiconductor device, if TFT characteristics are measured after the semiconductor device is created, it takes time because the result is known only at the end. However, according to the present invention, if the film thickness of the channel region 4b of the polycrystalline semiconductor layer 4a is measured and managed, the TFT characteristics can be grasped during the manufacturing. At this time, if there is a problem, a countermeasure can be taken immediately, and a decrease in yield can be suppressed.

A gate insulating layer 7 is formed on the polycrystalline semiconductor layer 4 a and the metallic conductive layer 6. As the gate insulating layer 7, a SiN film, a SiO ₂ film or the like is used. On the gate insulating layer 7, a conductive film 8 for forming an upper electrode, a gate electrode, and a gate wiring of the storage capacitor portion is formed. As the conductive film 8, Cr, Mo, W, Ta, or an alloy film containing these as a main component can be used. On the conductive film 8, an interlayer insulating layer 9 is formed so as to cover substantially the entire surface of the substrate. A signal line 10 is formed on the interlayer insulating layer 9. As the signal line 10, Cr, Mo, W, Ta, Al, or an alloy film containing these as a main component can be used.

  A protective film 11 is formed on the signal line so as to cover substantially the entire surface of the substrate. As the protective film 11, a SiN film is used. Contact holes 12 are formed in the protective film 11, the interlayer insulating layer 9, and the gate insulating film 5. The contact hole 12 includes a contact hole 12a reaching the source region 4c of the polycrystalline semiconductor layer 4a, a contact hole 12b reaching the drain region 4d, and a contact hole 12c reaching the signal line 10. In the contact hole 12a reaching the source region 4c and the contact hole 12b reaching the drain region 4d of the polycrystalline semiconductor layer 4a, the protective film 11, the interlayer insulating layer 9, and the gate insulating film 5 are removed, and the polycrystalline semiconductor layer 4a The metal conductive layer 6 on the source region 4c and the drain region 4d is exposed. That is, the metallic conductive layer 6 is the bottom of the contact holes 12a and 12b. Further, the signal line 10 is exposed in the contact hole 12c reaching the signal line 10.

  A pixel electrode 13 is formed on the protective layer 11. The pixel electrode 13 is connected to the metallic conductive layer 6 on the signal line 10, the source region 4 c and the drain region 4 d through the contact hole 12. As the pixel electrode 13, a transparent conductive film such as ITO or IZO is used.

Here, a manufacturing method of the display device according to the present embodiment will be described with reference to FIGS. 7 to 9 are manufacturing process cross-sectional views of the display device according to the present embodiment. As shown in FIG. 7A, a first base layer 2 and a second base layer 3 are formed on the TFT substrate 1 by using a CVD method. In the present embodiment, a stacked structure is employed in which a SiN film is formed to a thickness of 40 to 60 nm on a glass substrate, and a SiO ₂ film is further formed to a thickness of 180 to 220 nm. In addition, it is not restricted to said film | membrane structure and film thickness.

  Next, an amorphous semiconductor layer 4 is formed on the second underlayer 3 by a CVD method. In this embodiment, an amorphous silicon film is used as the amorphous semiconductor layer 4. The amorphous silicon film is formed to a thickness of 30 to 100 nm, preferably 60 to 80 nm. These base films 2 and 3 and the amorphous semiconductor layer 4 are preferably formed continuously in the same apparatus or in the same chamber. Thereby, contaminants such as boron existing in the air atmosphere can be prevented from being taken into the interface of each film.

  Note that it is preferable to perform annealing at a high temperature after the amorphous semiconductor layer 4 is formed. This is performed in order to reduce hydrogen contained in a large amount in the amorphous semiconductor layer 4 formed by the CVD method. In the present embodiment, the inside of the chamber held in a low vacuum state in a nitrogen atmosphere is heated to about 480 ° C., and the substrate on which the amorphous semiconductor layer 4 is formed is held for 45 minutes. By performing such treatment, when the amorphous semiconductor layer 4 is crystallized, rapid desorption of hydrogen does not occur even if the temperature rises. Then, surface roughness of the amorphous semiconductor layer 4 can be suppressed. Then, the natural oxide film formed on the surface of the amorphous semiconductor layer 4 is removed by etching with hydrofluoric acid or the like.

  Next, as shown in FIG. 7B, laser light is irradiated from above the amorphous semiconductor layer 4 while blowing a gas such as nitrogen to the amorphous semiconductor layer 4. The laser light is converted into a linear beam through a predetermined optical system, and is irradiated onto the amorphous semiconductor layer 4. In the present embodiment, the second harmonic (oscillation wavelength: 532 nm) of a YAG laser is used as the laser light. It is also possible to use an excimer laser instead of the second harmonic of the YAG laser. Here, by irradiating the amorphous semiconductor layer 4 with laser light while blowing nitrogen, it is possible to suppress the raised height generated at the crystal grain boundary portion. In the present embodiment, the average roughness of the crystal surface is reduced to 3 nm or less. Thereby, the amorphous semiconductor layer 4 is crystallized to obtain a polycrystalline semiconductor layer 4a. A TFT and a storage capacitor are formed using the polysilicon film which is the polycrystalline semiconductor layer 4a formed in this way.

  As described above, the polycrystalline semiconductor layer 4a has a conductive region containing impurities, and this portion forms the source region 4c and the drain region 4d. A region sandwiched between the source / drain regions is a channel region 4b.

  Further, as shown in FIG. 7C, a metallic conductive layer 6 is formed on the polycrystalline semiconductor layer 4a that forms a storage capacitor connected in series to the TFT 31, and on the source region 4c and the drain region 4d. The metallic conductive layer 6 on the polycrystalline semiconductor layer 4a is formed by sputtering. As the metallic conductive layer 6, a metal film such as Cr, Mo, W, Ta, or the like, or an alloy film having the conductivity as a main component and containing a metal or a nonmetallic element can be used. In this embodiment, the Mo film is formed with a thickness of about 20 nm by a sputtering method using a DC magnetron.

  Thus, the metallic conductive layer 6 is in contact with the source region 4c and the drain electrode 4d of the polycrystalline semiconductor layer 4a. Therefore, even when a transparent conductive oxide film, which will be described later, which is a pixel electrode is connected via a contact hole, the polycrystalline semiconductor layer 4a is not oxidized, and a good contact resistance can be obtained. Play.

  In addition, by laminating the low-resistance metallic conductive layer 6 on the polycrystalline semiconductor layer 4a serving as the lower electrode of the storage capacitor, it is possible to reliably apply a desired voltage to the lower electrode, and to stabilize the capacitance. Can be formed. Furthermore, since the metallic conductive layer 6 is formed on the polycrystalline semiconductor layer 4a for the lower electrode of the storage capacitor, the doping process for reducing the resistance of the polycrystalline semiconductor layer 4a can be reduced. . For this reason, it is possible to reduce the photolithography process, and the productivity is improved.

  Here, although the film thickness t of the metallic conductive layer 6 is 20 nm, it may be 30 nm or less, preferably 25 nm or less. In the case of a film thickness exceeding 30 nm, it becomes a mask for impurity ion doping to be performed later, impurity ions cannot sufficiently reach the lower polycrystalline semiconductor layer, and the ohmic contact between the metallic conductive layer 6 and the polycrystalline semiconductor layer 4a. This is because no sexual contact can be obtained.

  When the metallic conductive layer 6 is formed on the polycrystalline semiconductor layer 4a, the alloy layer 5 of the metallic conductive layer 6 and the polycrystalline semiconductor layer 4a is formed at the interface between the metallic conductive layer 6 and the polycrystalline semiconductor layer 4a. Has been. In the present embodiment, a MoSi layer is formed as the alloy layer 5. The alloy layer 5 is formed in a range of 0.1 t ≦ Y ≦ 0.3 t, where Y is the film thickness. As the film thickness of the metallic conductive layer 6 to be formed increases, the substrate temperature increases, so the film thickness of the alloy layer 5 also increases. Here, assuming that the temperature during sputtering is 180 ° C. and the film thickness t of the metal conductive layer 6 to be formed is 20 nm, the film thickness Y of the formed alloy layer 5 is 2 nm.

  Next, by using a known halftone mask on the polycrystalline semiconductor layer 4a and the metallic conductive layer 6 formed on and in contact with the polycrystalline semiconductor layer 4a, a photoresist pattern having a step in one photolithography process. Form. That is, the photoresist film of the desired polycrystalline semiconductor layer shape portion is formed thin, and the photoresist film of the desired metallic conductive layer shape portion is formed thick. The metallic conductive layer 6 and the polycrystalline semiconductor layer 4a are patterned using such a resist pattern. Such photoresist patterns having different film thicknesses can be formed using a halftone exposure technique or a gray tone exposure technique. That is, it is possible to use a method of providing a photomask with a filter film or filter layer that reduces the transmittance of exposure light, or a method of using a light diffraction phenomenon by dividing a pattern into fine slits.

Then, the metallic conductive layer 6 is processed into a desired shape by a wet etching method using a chemical solution in which phosphoric acid and nitric acid are mixed. Thereafter, the polycrystalline semiconductor layer 4a is processed into an island shape by a dry etching method using a gas in which CF ₄ and O ₂ are mixed. Further, since O ₂ is mixed in the etching gas, it is possible to perform etching while retracting the resist formed by the photoengraving method. Thus, as shown in FIG. 8D, the polycrystalline silicon layer 4a can be structured to have a tapered shape at the end.

  Next, the entire thickness of the photoresist pattern is reduced by ashing to remove the resist where the photoresist thickness was previously thinned, leaving only the resist pattern in the desired metallic conductive layer shape. Let Thereby, the reflective metal film 21b made of the third metal conductive film is exposed in the region.

Next, using the remaining photoresist pattern, the metallic conductive layer 6 is patterned again by a wet etching method using a chemical solution in which phosphoric acid and nitric acid are mixed. At this time, as shown in FIG. 8E, the metallic conductive layer 5 on the channel region of the polycrystalline semiconductor layer 4a is removed. Thereafter, the alloy layer 5 on the channel region of the polycrystalline semiconductor layer is removed by a dry etching method using a mixed gas of CF ₄ and Ar or a mixed gas of CF ₄ and O ₂ . The channel region 4b is shaved to form a recess 4e (FIG. 8 (f)).

  After removing metallic conductive layer 6 on channel region 4b of polycrystalline semiconductor layer 4a, alloy layer 5 on channel region 4b of polycrystalline semiconductor layer 4a and channel region 4b of polycrystalline semiconductor layer 4a are collectively collected. Etch to reveal clean channel region surface. As described above, the channel region 4b of the polycrystalline semiconductor layer 4a is etched so as to satisfy the relational expressions 0.3Y ≦ X ≦ 2Y and 1.3Y ≦ Z ≦ 3Y. Here, when Y = 2 nm, the depth X of the recess 4e is 0.6 nm ≦ X ≦ 4 nm, and the total shaving amount Z is 2.6 nm ≦ Z ≦ 6 nm. Thereby, the CV characteristic of a semiconductor device can be made into a favorable range. Further, variation in threshold voltage can be reduced, and a highly reliable high-performance semiconductor device can be realized.

Next, the photoresist is removed with a stripping solution. After performing the cleaning process, a gate insulating film 7 is formed so as to cover the entire substrate surface (FIG. 9G). In the present embodiment, the cleaning process is a buffered hydrofluoric acid (BHF) process. As the gate insulating film 7, a SiN film, a SiO ₂ film, or the like is used. In this embodiment, a SiO ₂ film is used as the gate insulating film 7 and is formed to a thickness of 70 to 100 nm by a CVD method.

  Next, as shown in FIG. 9G, the conductive film 8 for forming the upper electrode 8b, the gate electrode 8a, and the gate wiring (not shown) of the storage capacitor is formed. As the conductive film 8, Cr, Mo, W, Ta, or an alloy film containing these as a main component can be used. In this embodiment, a Mo film is formed as the conductive film 8 by a sputtering method using a DC magnetron so as to have a film thickness of 200 to 400 nm.

  Next, the formed conductive film 8 is patterned into a desired shape using a known photoengraving method to form the upper electrode 8b, the gate electrode 8a, and the gate wiring of the storage capacitor. In the present embodiment, the conductive film 8 is etched by a wet etching method using a chemical solution in which phosphoric acid and nitric acid are mixed.

  Then, impurities are introduced into the source region 4c and the drain region 4d of the polycrystalline semiconductor layer 4a using the formed gate electrode 8a as a mask. Here, P and B can be used as impurity elements to be introduced. If P is introduced, an n-type TFT can be formed, and if B is introduced, a p-type TFT can be formed. Further, if the processing of the gate electrode 4a is performed twice for the n-type TFT gate electrode and the p-type TFT gate electrode, the n-type and p-type TFTs can be separately formed on the same substrate. Here, the introduction of impurity elements such as P and B was performed using an ion doping method. Through the above steps, the source region 4c and the drain region 4d are formed.

Next, as shown in FIG. 9H, an interlayer insulating layer 9 is formed so as to cover the entire substrate surface. That is, the interlayer insulating layer 9 is formed on the gate electrode 8a. In the present embodiment, a SiO ₂ film having a thickness of 500 to 1000 nm is formed as the interlayer insulating layer 9 by the CVD method. And it hold | maintained for about 2 hours in the annealing furnace heated at 450 degreeC in nitrogen atmosphere. This is performed to activate the impurity element introduced into the source / drain regions of the polycrystalline semiconductor layer.

  Next, a conductive film for forming the signal line 10 is formed. As this conductive film, Cr, Mo, W, Ta, Al, or an alloy film containing these as a main component can be used. In this embodiment, a Mo (upper layer) / Al (lower layer) laminated film is formed, the Mo film has a thickness of 100 to 200 nm, the Al film has a thickness of 200 to 400 nm, and the conductive film is formed by a sputtering method using a DC magnetron. .

Next, the formed conductive film is patterned into a desired shape using a known photoengraving method to form a signal line 10 (FIG. 9H). In the present embodiment, the etching for forming the signal line 10 is performed by a dry etching method using a mixed gas of SF ₆ and O _{2 and} a mixed gas of Cl ₂ and Ar. Then, the protective film 11 is formed so as to cover the entire substrate surface. In this embodiment, a SiN film is formed by a CVD method as a protective film so as to have a thickness of 300 to 600 nm.

Next, the formed gate insulating film 5, interlayer insulating layer 9, and protective film 11 are patterned into a desired shape using a known photolithography method. Here, a contact hole 12a reaching the source region 4c of the polycrystalline semiconductor layer 4a, a contact hole 12b reaching the drain region 4d, and a contact hole 12c reaching the signal line 10 are formed. In the contact holes 12a, 12b reaching the source region 4c and the drain region 4d of the polycrystalline semiconductor layer 4a, the gate insulating film 5, the interlayer insulating layer 9, and the protective film 11 are removed, and the source region 4c of the polycrystalline semiconductor layer 4a, The metallic conductive layer 6 on the drain region 4d is exposed. In the contact hole 12c reaching the signal line 10, the protective layer 11 is removed and the signal line 10 is exposed. In the present embodiment, the contact hole 12 is etched by a dry etching method using a mixed gas of CHF ₃ , O ₂ , and Ar.

Next, a conductive film for forming the pixel electrode 13 is formed. The conductive film may be a conductive film having transparency such as ITO or IZO. In this embodiment, ITO is formed as a transparent conductive film by sputtering using a DC magnetron so as to have a film thickness of 80 to 120 nm. Sputtering was performed using a gas mixture of Ar gas, O ₂ gas, and H ₂ O gas. Thereby, the workability is easy and an amorphous transparent conductive film is formed.

  Then, the formed transparent conductive film is patterned into a desired shape using a known photoengraving method to form the pixel electrode 13 (FIG. 9 (i)). In the present embodiment, the transparent conductive film is etched by a wet etching method using a chemical solution mainly composed of oxalic acid. Next, annealing for crystallizing the amorphous transparent conductive film is performed. With the above manufacturing method, a semiconductor device having a low-temperature polysilicon TFT structure is completed. The liquid crystal display device 100 can be manufactured using the TFT substrate on which the TFT is formed.

  In this way, after removing the metallic conductive layer 6 on the channel region 4b of the polycrystalline semiconductor layer 4a, the alloy layer 5 on the channel region 4b of the polycrystalline semiconductor layer 4a and the channel region 4b of the polycrystalline semiconductor layer 4a. Are collectively etched to obtain a clean channel region surface. As described above, the channel region 4b of the polycrystalline semiconductor layer 4a is etched so as to satisfy the relational expressions 0.3Y ≦ X ≦ 2Y and 1.3Y ≦ Z ≦ 3Y. Thereby, the CV characteristic of a semiconductor device can be made into a favorable range. Further, variation in threshold voltage can be reduced, and a highly reliable high-performance semiconductor device can be realized.

Embodiment 2. FIG.
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. The present embodiment is basically the same as the TFT manufacturing method described in the first embodiment. The present embodiment is different from the first embodiment in the etching method of the metallic conductive layer 6 on the channel region of the polycrystalline semiconductor layer 4a. Hereinafter, this point will be described.

  As described in the first embodiment, as shown in FIG. 8D, on the first underlayer 2 and the second underlayer 3, a polycrystalline silicon layer 4a having a predetermined shape, a metallic conductive layer. 6 is formed. Further, the formation of the metallic conductive layer 6 forms an alloy layer 5 of the polycrystalline silicon layer 4 a and the metallic conductive layer 6 at the interface between the polycrystalline silicon layer 4 a and the metallic conductive layer 6.

  Thereafter, as described above, the film thickness of the photoresist pattern is entirely reduced by ashing, and the resist in the portion where the photoresist film thickness has been formed thin is removed, and the resist pattern in the desired metallic conductive layer shape portion. Leave only. Thereby, the reflective metal film 21b made of the third metal conductive film is exposed in the region.

Next, using the remaining photoresist pattern, the metallic conductive layer 6 is patterned again by a dry etching method using Cl ₂ gas. At this time, the metallic conductive layer 6 on the channel region 4b of the polycrystalline semiconductor layer 4a is removed. Thereafter, the CF ₄ and a dry etching method using a mixed mixed gas or CF4 _and O ₂ gas Ar, to remove the alloy layer 5 on the channel region of the polycrystalline semiconductor layer, a polycrystalline semiconductor layer channel The region 4b is cut away to form a recess 4e (FIG. 8 (f)).

  After removing metallic conductive layer 6 on channel region 4b of polycrystalline semiconductor layer 4a, alloy layer 5 on channel region 4b of polycrystalline semiconductor layer 4a and channel region 4b of polycrystalline semiconductor layer 4a are collectively collected. Etch to reveal clean channel region surface. As described in the first embodiment, the channel region 4b of the polycrystalline semiconductor layer 4a is etched so as to satisfy the relational expressions 0.3Y ≦ X ≦ 2Y and 1.3Y ≦ Z ≦ 3Y. Thereafter, a semiconductor device having a low-temperature polysilicon TFT structure is completed through the same steps as those in the first embodiment.

  Also in the semiconductor device created by the manufacturing method according to the present embodiment, the relationship between the total chipping amount Z (Z = X + Y) and the CV characteristics is as shown in FIG. Therefore, as in the first embodiment, the CV characteristics of the semiconductor device can be in a favorable range. Further, variation in threshold voltage can be reduced, and a highly reliable high-performance semiconductor device can be realized.

  In the above-described embodiment, the case of a conventional LTPS TFT made of polysilicon formed by laser annealing has been described. However, the present invention is not limited to this, and a crystalline silicon TFT formed by various other methods. The same effect can be obtained in. Furthermore, the structure according to the present invention is applicable not only to the LCD but also to other display devices such as an organic EL display device.

It is a top view which shows the structure of the display apparatus which concerns on embodiment. It is sectional drawing which shows the structure of the display apparatus which concerns on embodiment. It is a figure which shows the structure of the semiconductor device which concerns on embodiment. It is a figure which shows the structure of a part of semiconductor device which concerns on embodiment. It is a figure which shows the CV characteristic of TFT which concerns on this Embodiment. It is a graph which shows the relationship between the total amount of cutting and the inclination of a CV curve. It is manufacturing process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is manufacturing process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is manufacturing process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 TFT substrate 2 1st base layer 3 2nd base layer 4 Amorphous semiconductor layer 4a Polycrystalline semiconductor layer 4b Channel region 4c Source region 4d Drain region 4e Recess 5 Alloy layer 6 Metallic conductive layer 7 Gate insulating layer 8 Conductivity Layer 9 Interlayer insulating layer 10 Signal line 11 Protective films 12a, 12b, 12c Contact hole 13 Pixel electrode 20 Counter substrate 21 Sealing material 22 Liquid crystal 23 Spacer 24 Gate line 25 Source line 26 Orientation film 27 Counter electrode 28 Polarizing plate 29 Gate driver 30 Source driver 100 Liquid crystal display device 101 Liquid crystal panel 102 Backlight

Claims (13)

A semiconductor layer formed over a substrate and having a source region, a drain region, and a channel region;
A metallic conductive layer formed on a source region and a drain region of the semiconductor layer;
An alloy layer formed between the semiconductor layer and the metallic conductive layer, the alloy layer of the semiconductor layer and the metallic conductive layer;
The semiconductor layer has a recess formed so that the thickness of the channel region is thinner than the thickness of the region where the metallic conductive layer is formed,
The semiconductor device, wherein the depth X of the recess, the film thickness Y of the alloy layer, and the film thickness t of the metallic conductive layer satisfy the following two formulas.
0.1t ≦ Y ≦ 0.3t
0.3Y ≦ X ≦ 2Y   The semiconductor device according to claim 1, wherein the semiconductor layer is a polycrystalline semiconductor layer formed by crystallizing an amorphous semiconductor layer.   The semiconductor device according to claim 1, wherein a film thickness of the metallic conductive layer is 30 nm or less.   4. The semiconductor device according to claim 1, wherein the metallic conductive layer is made of Cr, Mo, W, Ta, or an alloy containing these as a main component.   A display apparatus provided with the semiconductor device of any one of Claims 1-4. Forming a semiconductor layer on the substrate;
Forming a metallic conductive layer on the semiconductor layer, and forming an alloy layer of the semiconductor layer and the metallic conductive layer between the semiconductor layer and the metallic conductive layer;
Removing the metallic conductive layer on the channel region of the semiconductor layer;
Removing the alloy layer on the channel region of the semiconductor layer, removing the channel region of the semiconductor layer, and forming a recess in the channel region of the semiconductor layer,
The recess is formed so that the depth X of the recess, the film thickness Y of the alloy layer, and the film thickness t of the metallic conductive layer satisfy the following two relations: Device manufacturing method.
0.1t ≦ Y ≦ 0.3t
0.3Y ≦ X ≦ 2Y   The method for manufacturing a semiconductor device according to claim 6, wherein the alloy layer on the channel region of the semiconductor layer and the channel region of the semiconductor layer are collectively removed by radicalizing the gas. 8. The alloy layer on the channel region of the semiconductor layer and the channel region of the semiconductor layer are removed using a mixed gas of CF ₄ and Ar or a mixed gas of CF ₄ and O _2. The manufacturing method of the semiconductor device as described in 2.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the metallic conductive layer on the channel region of the semiconductor layer is removed with a chemical solution.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the metallic conductive layer on the channel region of the semiconductor layer is removed by radicalizing a gas.   The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor layer is a polycrystalline semiconductor layer formed by crystallizing an amorphous semiconductor layer.   The method for manufacturing a semiconductor device according to claim 6, comprising a step of forming an insulating layer between the substrate and the semiconductor layer.   A method for manufacturing a display device, comprising a step of manufacturing a semiconductor device by the method according to claim 6.

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