JP2009076125A - Semiconductor test apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test apparatus capable of accurately and efficiently discriminating normal/defective products of a device to be tested. <P>SOLUTION: The semiconductor test apparatus 1 includes discrimination sections 15a-15n for discriminating conditions of the devices 30a-30n to be tested, based on ready/busy signals RB1-RBn. These discrimination sections 15a-15n are equipped with: condition discrimination sections 22 for discriminating whether a command can be received or not by the devices 30a-30n to be tested (Match/Unmatch); defective block decision sections 24 for deciding size relation between the number of Unmatch times counted for every block of the devices 30a-30n to be tested and a predetermined first threshold; busy time decision sections 25 for deciding size relation between busy times of the devices 30a-30n to be tested accumulated for every block and a predetermined second threshold; and result decision sections 26 for deciding whether the block is defective or not, based on these decision results. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus suitable for testing a device under test having a storage area divided by a predetermined unit such as a NAND flash memory.

  As is well known, a NAND flash memory has a storage area divided into block units and a block divided into page units. Data writing and reading are performed in page units and data erasing is blocked. It is a non-volatile memory that is stored in units and does not lose its stored contents even when the power is turned off. One page has a size of about several hundred to several thousand bytes.

In the following Patent Document 1, it is determined whether or not a block (bad block) is unusable by performing pass / fail judgment between a signal output from a flash memory and an expected pattern, and the block is determined to be a bad block. In such a case, a semiconductor test apparatus is disclosed in which a test of the flash memory is efficiently performed by performing control to end the test of the block.
JP 2003-194891 A

  By the way, the NAND flash memory is characterized in that it does not accept the next command until it becomes ready (command acceptable state). In addition, the NAND flash memory outputs a signal from the ready / busy pin indicating whether its own state is a ready state or a busy (BUSY) state (command reception disabled state). Using this feature, in the NAND flash memory test, the time until the signal output from the ready / busy pin changes from the busy state to the ready state is measured for each page in the block. However, when the time obtained by adding the times measured in the block is within a predetermined reference time, a test for determining that the product is non-defective may be performed.

  However, when such a test is performed on a NAND flash memory that is allowed even if there are defective pages in the block and the number of defective pages is less than a predetermined number, the determination of a non-defective product or a defective product is not always performed accurately. There was a problem that it was not. In other words, the reason why the above reference time is exceeded is because it takes a long time to test a defective page that can be repaired in the block, or there are a number of defective pages that cannot be repaired in the block. Since it is not possible to determine whether this is because of the failure, there is a problem that even if the repair is actually possible, it is determined to be defective.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor test apparatus capable of accurately and efficiently determining whether a device under test is a non-defective product or a defective product.

In order to solve the above problems, the semiconductor test apparatus of the present invention includes a storage area divided in predetermined block units, and a status signal (RB1) indicating whether or not a command (C1) can be received. In the semiconductor test apparatus (1) for testing the devices under test (30a to 30n) that output (RBn), the device under test accepts the command based on the state signal output from the device under test. A state determination unit (22) that determines whether or not the device can be received, and the number of times the state determination unit determines that the command cannot be received for each block of the device under test. And a first determination unit (24) for determining a magnitude relationship between the first threshold and a predetermined first threshold value, and the state determination unit after the command is received by the device under test. A second determination unit (25) for accumulating a time until it is determined that reception is possible for each block of the device under test, and determining a magnitude relationship between the accumulated time and a predetermined second threshold; And a pass / fail judgment unit (26) for judging whether or not the block is a defective block based on a judgment result of the second judgment unit.
According to this invention, in the first determination unit, the number of times that the state determination unit determines that the command cannot be received is counted for each block of the device under test, and the magnitude relationship with the predetermined first threshold is determined. In the second determination unit, the time from when the command is received by the device under test until the state determination unit determines that the command can be received is accumulated for each block of the device under test, The magnitude relationship is determined, and the quality determination unit determines whether the block of the device under test is a defective block based on the determination results of the first and second determination units.
In the semiconductor test apparatus of the present invention, the first threshold value is set to a value indicating the number of defects per block allowed in the device under test, and the second threshold value is determined by the device under test as the command. It is characterized by being set to a value indicating a target time for each block that can be accepted.
In the semiconductor test apparatus of the present invention, when the count value is equal to or greater than the first threshold, the first determination unit excludes the device under test from being tested until the block is completed. It is characterized by.
In the semiconductor test apparatus of the present invention, when the first determination unit excludes the device under test from the test target, the device under test is excluded from the test target even with respect to the second determination unit. It is characterized by that.
Furthermore, the semiconductor test apparatus of the present invention includes a defective block storage unit (27) for storing an address designating at least a part of the blocks determined as defective blocks by the pass / fail determination unit, and the state determination unit Is characterized in that mask control is performed so that the address stored in the defective block storage unit is excluded from the test target.

  According to the present invention, the first determination unit counts the number of times that the state determination unit determines that the command cannot be received for each block of the device under test, and determines the magnitude relationship with the predetermined first threshold value. In the second determination unit, the time from when the command is received by the device under test until it is determined that the command can be received by the state determination unit is accumulated for each block of the device under test as a predetermined second threshold value. In the pass / fail judgment section, it is judged whether the block of the device under test is a defective block based on the judgment results of the first and second judgment sections. There is an effect that a non-defective product and a defective product can be accurately determined. In addition, when the count value of the first determination unit is equal to or greater than the first threshold value, the device under test is excluded from the test target until the end of the block. There is an effect that can be.

  Hereinafter, a semiconductor test apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a semiconductor test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus 1 of this embodiment includes a command generation instruction unit 11, a command generation unit 12, a driver 13, an address pointer 14, determination units 15 a to 15 n, and a CPU (central processing unit) 16. A plurality of (n) devices under test 30a to 30n are tested in parallel.

  In this embodiment, it is assumed that the devices under test 30a to 30n are NAND flash memories. In other words, the storage area is divided into block units and the inside of the block is divided into page units, and the nonvolatile memory performs writing and reading of data in units of pages and erasing data in units of blocks. . The devices under test 30a to 30n are in a busy state when a write command is given from the command generation unit 12 via the driver 13, and are in a ready state when the writing is completed. Busy signals RB1 to RBn (status signals) are output from the ready / busy pins P1 to Pn, respectively.

  The command generation instructing unit 11 controls the command generating unit 12 based on the state determination signals J1 to Jn output from the determination units 15a to 15n. Specifically, when all of the state determination signals J1 to Jn are signals indicating “Match”, the command generation instruction signal C0 for generating a command to the command generation unit 12 is output. The state determination signals J1 to Jn are either “Match” indicating that the devices under test 30a to 30n are in a ready state or “Unmatch” indicating that the devices under test 30a to 30n are in a busy state. It is a signal that takes

  Based on the command generation instruction signal C0, the command generator 12 generates a command signal C1 including a test pattern to be applied to the devices under test 30a to 30n, an address signal indicating the storage destination address of the test pattern, a write enable signal, and the like. And output to the driver 13. The command generator 12 also outputs a command signal to the driver 13 when the command generation instruction signal C0 is not input even after a predetermined time has elapsed. The command generation unit 12 generates expected patterns E1 to En and outputs them to the state determination units 22 of the determination units 15a to 15n, respectively. Further, the command generation unit 12 generates an address increment signal I1 indicating address switching and a block increment signal I2 indicating block switching, and each of the command generation unit 12 and the bad block determination unit 24 provided in the determination units 15a to 15n and the busy state. Output to the time determination unit 25.

  The driver 13 outputs an upper limit voltage value (VIH) or a lower limit voltage value (VIL) according to the level of the command signal C1 output from the command generation unit 12. The signal output from the driver 13 is output to the devices under test 30 a to 30 n via the signal output terminal 17. The address pointer 14 generates an address A1 for accessing the defective block storage unit 27 provided in the determination units 15a to 15n, based on the block increment signal I2 output from the command generation unit 12.

  The determination units 15a to 15n are provided corresponding to the devices under test 30a to 30n, respectively, and ready / busy signals RB1 output from the devices under test 30a to 30n and input through the signal input terminals 18a to 18n. The states of the devices under test 30a to 30n are determined based on RBn, and state determination signals J1 to Jn indicating the determination results are output, respectively. The determination units 15a to 15n also determine whether or not there are defective blocks in the devices under test 30a to 30n. These determination units 15a to 15n include a comparator 21, a state determination unit 22, a strobe signal generation unit 23, a defective block determination unit 24 (first determination unit), a busy time determination unit 25 (second determination unit), and a result determination unit 26. (A pass / fail judgment unit) and a defective block storage unit 27 are provided. Since the determination units 15a to 15n have the same configuration, the determination unit 15a will be described below as an example, and description of the determination units 15b to 15n will be omitted.

  The comparator 21 provided in the determination unit 15a compares the ready / busy signal RB1 of the device under test 30a with a predetermined upper limit reference voltage (VOH) and a predetermined lower limit reference voltage (VOL), and shows the comparison result. A value signal (a signal composed of an “H (high)” level and an “L (low)” level) is output to the state determination unit 22. The state determination unit 22 compares the binary signal output from the comparator 21 with the expected pattern E1 output from the command generation unit 12 at a timing defined by the strobe signal ST1 output from the strobe signal generation unit 23. Thus, it is determined whether the corresponding device under test 30a is in a ready state or a busy state.

  When the state determination unit 22 determines that the device under test 30a is in the ready state, it outputs an “H” level signal indicating “Match” as a state determination signal, and when it is determined that the device under test 30a is busy. Outputs an “L” level signal indicating “Unmatch” as a state determination signal. The strobe signal generator 23 outputs a strobe signal ST1 for determining the ready / busy determination timing to the corresponding state determination unit 22. Here, the strobe signal generator 23 outputs the strobe signal ST1 several hundred to several thousand times every time a write command is output once. As a result, the binary signal output from the comparator 21 is sampled by the state determination unit 22 in the period of the strobe signal ST1, and “Match” or “Unmatch” is determined. Although not shown in FIG. 1, the strobe signal ST1 output from the strobe signal generator 23 is also input to the busy time determination unit 25 provided in the determination unit 15a.

  The bad block determination unit 24 counts the number of times that the state determination signal output for each page from the state determination unit 22 becomes “Unmatch” (“L” level) for each block. Specifically, when an “L” level state determination signal is input from the state determination unit 22 at the time when the count end signal (details will be described later) is output from the busy time determination unit 25, the next address increment is performed. The count value is incremented in synchronization with the rising edge of the signal I1. When the block increment signal I2 is output from the command generation unit 13, the defective block determination unit 24 resets the count value in synchronization with the rising edge.

  Moreover, the bad block determination part 24 determines whether said count value corresponds with the setting value (1st threshold value) preset by CPU16 for every page. Here, the set value set by the CPU 16 is a threshold value serving as a reference for determining that a block is a defective block, and specifically, is the number of “Unmatch” allowed for each block. If the bad block determination unit 24 determines that the count value is different from the set value, the bad block determination unit 24 outputs the state determination signal output from the state determination unit 22 as the state determination signal J1, and the “H” level indicating “pass” Is output to the result determination unit 26. On the other hand, when it is determined that the count value matches the set value, the corresponding device under test 30a is excluded from the test target until the count value is reset from the next address (until the block ends). A signal indicating that this is to be performed (hereinafter referred to as “non-target signal”) is output to the busy time determination unit 25, and an “H” level signal indicating “Match” is output as the state determination signal J1, and further “fail” Is output to the result determination unit 26.

  The busy time determination unit 25 obtains, for each page, a time (busy time) from when a write command to the device under test 30a is output until data writing is completed at the device under test 30a, and determines the busy time for each page. Find the integrated value integrated in the block. Specifically, the busy time determination unit 25 outputs a strobe signal until the state determination signal from the state determination unit 22 becomes “H” level indicating “Match” after the command signal C1 is output from the command generation unit 12. The strobe signal ST1 output from the generator 23 is counted for each page, and the count value for each page is integrated in the block.

  The busy time determination unit 25 outputs a strobe signal generation unit 23 when a state determination signal indicating “Match” is output from the state determination unit 22 within a predetermined determination time for each page. The strobe signal ST1 is counted, and a count end signal indicating that the count is completed is output to the defective block determination unit 24. Further, when the state determination signal from the state determination unit 22 does not become “Match” and the determination time has elapsed, the count value of the page is reset and the count end signal is output. In addition, when the above-described non-target signal is output from the bad block determination unit 24, the busy time determination unit 25 counts the bad block determination unit 24 without counting for each page until the block ends. Output an end signal. As a result, the device under test 30a is also excluded from the test target from the busy time determination unit 25 until the end of the block.

In addition, the busy time determination unit 25 determines whether or not the count value accumulated in the block is equal to or less than a target count value (second threshold) preset by the CPU 16. Here, the target count value set by the CPU 16 is obtained by converting the target value of the busy time per block into the clock count value, and is expressed by the following equation.
Target count value = target value of busy time per page × number of pages per block / cycle of strobe signal ST1

  When it is determined that the count value integrated in the block is equal to or less than the target count value, the busy time determination unit 25 outputs a determination signal R1 of “H” level indicating “pass” to the result determination unit 26, When it is determined that the count value accumulated in the block exceeds the target count value, an “L” level determination signal R 1 indicating “fail” is output to the result determination unit 26. The result determination unit 26 determines whether the block is good or bad based on the determination signal Q1 of the defective block determination unit 24 and the determination signal R1 of the busy time determination unit 25. Specifically, when at least one of the determination signal Q1 of the defective block determination unit 24 and the determination signal R1 of the busy time determination unit 25 indicates “fail”, the block is determined as a defective block. The block is determined to be a good block only when both the determination signal Q1 of the bad block determination unit 24 and the determination signal R1 of the busy time determination unit 25 indicate “pass”. The result determination unit 26 can be realized by, for example, an AND (logical product) circuit.

  The bad block storage unit 27 includes a PSR (Per Site Memory: a memory that can store information in each device under measurement / Site), and the determination result (information indicating the defective block) of the result determination unit 26 is stored in the address pointer 14. Is written to the PSR address specified by the output signal. Further, the defective block storage unit 27 outputs a mask signal M1 to the state determination unit 22 based on the information stored in the PSR. In the second and subsequent tests, the state determination unit 22 performs mask control based on the mask signal M1 so that the address in the defective block is excluded from the test target.

  The CPU 16 sets the above-described set value for the defective block determination unit 24 provided in each of the determination units 15a to 15n, and for the busy time determination unit 25 provided in each of the determination units 15a to 15n. The target count value described above is set. The setting value set in the bad block determination unit 24 and the target count value set in the busy time determination unit 25 can be set to different values for each of the determination units 15a to 15n.

  Next, the operation of the semiconductor test apparatus 1 of the present embodiment having the above configuration will be described. In the following description, the setting value set for the defective block determination unit 24 provided in each of the determination units 15a to 15n is “2”, and the busy value provided in each of the determination units 15a to 15n. A case where the target count value set for the time determination unit 25 is a value corresponding to 20 msec will be described as an example. The memory map of the devices under test 30a to 30n is as shown in FIG.

  FIG. 2 is a diagram illustrating an example of a memory map of the devices under test 30a to 30n. As shown in FIG. 2, the devices under test 30 a to 30 n are divided into “0” to “1FFF” blocks in hexadecimal notation, and each block is displayed on a page “0” to “3F” in hexadecimal notation. Suppose that they are classified. Each page has a size of 2048 bytes (“800” bytes in hexadecimal notation). The size of the storage area of each of the devices under test 30a to 30n is calculated by the number of blocks × number of pages × 1 page. In the example shown in FIG. 2, about 1 Gbyte (“2000” × “40”). X “800” = “40000000” (1073741824 in decimal) bytes).

  When the command generation signal C0 is output from the command generation instruction unit 11 shown in FIG. 1, a test for the devices under test 30a to 30n having the memory map shown in FIG. 2 is started. The command generation signal C0 output from the command generation instruction unit 11 is input to the command generation unit 12. As a result, the command generator 12 outputs the command signal C1 including the test pattern, the address signal, the write enable signal, and the like and the expected patterns E1 to En. The command signal C1 output here is a signal instructing writing to the page “0” in the block “0” shown in FIG. Strobe signals ST1 to STn are output from the strobe signal generator 23 provided in each of the determination units 15a to 15n.

  The command signal C1 output from the command generator 12 is applied to each of the devices under test 30a to 30n via the driver 13 and the signal output terminal 17 in order. As a result, in the devices under test 30a to 30n, the write operation for the page "0" in the block "0" shown in FIG. 2 is started, and a ready / busy signal indicating that the ready / busy pins P1 to Pn are busy. RB1 to RBn are output. Further, the expected patterns E1 to En output from the command generation unit 12 are output to the state determination units 22 provided in the determination units 15a to 15n, respectively. On the other hand, the strobe signals ST1 to STn output from the strobe signal generation unit 23 are output to the corresponding state determination unit 22 and busy time determination unit 25.

  The ready / busy signals RB1 to RBn output from the devices under test 30a to 30n are input to the determination units 15a to 15n via the signal input terminals 18a to 18n, respectively. In the following description, the internal operation of the determination units 15a to 15n will be described using the determination unit 15a as a representative for the sake of simplicity. A ready / busy signal RB1 from the device under test 30a is first input to the comparator 21 and compared with a predetermined upper reference voltage (VOH) and a predetermined lower reference voltage (VOL). The binary signal indicating the comparison result of the comparator 21 is input to the state determination unit 22 and compared with the expected pattern E1 at the timing of the strobe signal ST1 output from the strobe signal generation unit 23, and the device under test 30a is ready. Or whether it is busy. Here, since the device under test 30 a is in a busy state, an “L” level signal (“Unmatch”) is output to the defective block determination unit 24 and the busy time determination unit 25 as a state determination signal.

  Here, the busy time determining unit 25 starts counting the strobe signal ST1 output from the strobe signal generating unit 23 immediately after the command signal C1 is output from the command generating unit 12. Thereby, measurement of the busy time of the device under test 30a is started. When the state determination signal output from the state determination unit 22 is “Unmatch”, the strobe signal ST1 is continuously counted.

  On the other hand, when the device under test 30a completes the write operation to the page “0” in the block “0” shown in FIG. 2, the ready / busy pin P1 of the device under test 30a indicates a ready state. / Busy signal RB1 is output. As a result, an “H” level signal (“Match”) indicating that the device under test 30 a is in a ready state is sent from the state determination unit 22 to the bad block determination unit 24 and the busy time determination unit 25 as a state determination signal. Is output.

  The busy time determination unit 25 ends the count of the strobe signal ST1 when the state determination signal output from the state determination unit 22 becomes “Match”, and outputs a count end signal to the defective block determination unit 24. . When the preset determination time for each page has elapsed, the busy time determination unit 25 resets the count value of the page and then outputs the count end signal. When the count end signal from the busy time determination unit 25 is input, the bad block determination unit 24 determines whether the state determination signal output from the state determination unit 22 is “Match” or “Unmatch”. Determine. Here, it is determined as “Match”. If it is determined as “Match”, the count value is not incremented even if the next address increment signal I1 is input. However, if it is determined as “Unmatch”, the increment is performed.

  Next, the bad block determination unit 24 determines whether or not the count value matches the set value “2” set by the CPU 16. Here, since the count value remains the initial value “0”, it is determined that the count value is different from the set value of the CPU 16. As a result, the bad block determination unit 24 outputs a state determination signal indicating “Match” from the state determination unit 22 to the command generation instructing unit 11 as the state determination signal J1, and a determination signal Q1 indicating “pass” Is output to the result determination unit 26.

  Operations similar to the operations described above are also performed in the determination units 15b to 15n. When all of the state determination signals J1 to Jn output from the determination units 15a to 15n and input to the command generation instruction unit 11 are signals indicating “Match”, the command generation instruction unit 11 sends a command to the command generation unit 12. The command generation instruction signal C0 for generating the next command is output. As a result, the command generation unit 12 outputs the next command signal C1 and expected patterns E1 to En, and the address increment signal I1 is provided in the determination units 15a to 15n and the busy block determination unit 24 and busy time determination unit. Are output to each of 25. The command signal C1 output here is a signal for instructing writing to the page “1” in the block “0” shown in FIG.

  When the above operation is repeated in units of pages of the devices under test 30a to 30n and one block is completed, the busy time determination unit 25 provided in the determination units 15a to 15n includes the block (block “0”). A count value obtained by integrating the count value for each page is obtained. Then, it is determined whether or not the accumulated count value exceeds a target count value (a value corresponding to 20 msec) set by the CPU 16, and determination signals R1 to Rn indicating the determination results are sent to the corresponding result determination unit 26. Is output. The result determination unit 26 calculates the logical product of the determination signals (determination signals R1 to Rn) from the corresponding busy time determination unit 25 and the determination signals (determination signals Q1 to Qn) from the corresponding defective block determination unit 24. Thus, it is determined whether or not the block is a bad block. Information indicating the determination result of the result determination unit 26 is stored in the PSR of the defective block storage unit 27 specified by the address A1 output from the address pointer 14.

  The same operation as the above is repeated for the remaining blocks of the devices under test 30a to 30n, and the determination result shown in FIG. 3 is obtained. FIG. 3 is a diagram illustrating an example of determination results obtained by the determination units 15a to 15n. As shown in FIG. 3, the determination results of the determination units 15a to 15n are obtained in units of blocks or pages. In FIG. 3, “Match / Unmatch” is a determination result of “Match” or “Unmatch” for each page in the bad block determination unit 24, and “Busy time” is busy for each page obtained by the busy time determination unit 25. It is the accumulated time of time and busy time within the block. The “determination result Q” indicates the determination result (determination signals Q1 to Qn) of the defective block determination unit 24, and the “determination result R” indicates the determination result (determination signals R1 to Rn) of the busy time determination unit 25. Show. Further, “good / bad determination result” indicates the determination result of the result determination unit 26. In the following, for the sake of simplicity, it is assumed that the determination result shown in FIG. 3 is the determination result of the determination unit 15a.

  In the example illustrated in FIG. 3, in the pages “0” to “3” of the block “0” in the device under test 30 a, the state determination indicating “Match” from the state determination unit 22 within the predetermined determination time for each page. Since the signal is output, the bad block determination unit 24 determines “Match”. On the other hand, since the above determination time has elapsed for page “4”, the count value for that page of the busy time determination unit 25 is reset and the busy time is set to “0”, and the bad block determination It is determined as “Unmatch” by the unit 24. Note that the determination result of the defective block determination unit 24 is “Match” in any of the remaining pages “5” to “3F” of the block “0”.

  For this reason, in the block “0”, only the page “4” is “Unmatch”, and the count value is different from the set value “2” set by the CPU 16. (Determination signal Q1) becomes “pass”. The count value obtained by integrating the count values for each page in the block “0” (cumulative time of the busy time in the block “0”) is 17.1 msec, and the target count value set by the CPU 16 (to 20 msec) Therefore, the determination result R (determination signal R1) of the busy time determination unit 25 is “pass”. Therefore, since both the determination signal Q1 of the defective block determination unit 24 and the determination signal R1 of the busy time determination unit 25 are “pass”, the determination result of the result determination unit 26 (“good / bad determination result”) is a good block. Become.

  On the other hand, in the example shown in FIG. 3, the block “1” of the device under test 30a is determined as “Match” on page “0”, but continuously on pages “1” and “2”. It is determined as “Unnaatch”. Then, the count value of the bad block determination unit 24 becomes “2”, and the count value matches the set value “2” set by the CPU 16. As a result, the bad block determination unit 24 outputs a “H” level signal indicating “Match” to the command generation support unit 11 as the state determination signal J1 until the block “1” is completed. A determination signal Q 1 indicating “fail” is output to the unit 26, and an out-of-target signal is output to the busy time determination unit 25.

  When this non-target signal is input, the busy time determination unit 25 does not count for each page until the block “1” ends, and outputs a count end signal to the bad block determination unit 24. In this way, when the count value of the bad block determination unit 24 matches the set value set by the CPU 16, the device under test 30a and the busy block determination unit 24 and the busy time until the block “1” ends. The determination unit 25 is excluded from the test target. Further, the count value obtained by integrating the count values for each page in the block “1” (the accumulated time of the busy time in the block “1”) is 0.39 msec, and the target count value set by the CPU 16 (to 20 msec) Therefore, the determination result R (determination result R1) of the busy time determination unit 25 is “pass”. Therefore, the determination result R1 of the busy time determination unit 25 is “pass”, but the determination result Q1 of the defective block determination unit 24 is “fail”, so the determination result of the result determination unit 26 (“good / bad determination result”) is It becomes a bad block.

  Further, in the example illustrated in FIG. 3, for the block “2” of the device under test 30 a, the determination result of the defective block determination unit 24 is “pass”. However, the count value obtained by integrating the count values for each page in the block “2” (the accumulated time of the busy time in the block “2”) is 21.3 msec, and the target count value set by the CPU 16 (20 msec) Therefore, the determination result R (determination signal R1) of the busy time determination unit 25 is “fail”. For this reason, the determination result of the result determination unit 26 (“good / bad determination result”) is a defective block.

  As described above, in the present embodiment, whether or not the number of “Ummatch” in the block in the defective block determination unit 24 provided in each of the determination units 15a to 15n is equal to or larger than the allowable number set by the setting value of the CPU 16. In addition, the busy time determination unit 25 determines whether or not the integrated value of the count values for each page in the block exceeds the target count value, and whether or not the block is a bad block based on these determination results. Therefore, the non-defective product / defective product of the devices under test 30a to 30n can be accurately determined. Further, when the number of “Ummatch” in the block becomes equal to or greater than the set value in the bad block determination unit 24, the command to the devices under test 30a to 30b is excluded from the test target until the block ends. Since the application of the signal C1 is resumed at an early stage, the devices under test 30a to 30b can be efficiently tested.

  Although the semiconductor test apparatus according to one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above-described embodiment, the case where the devices under test 30a to 30n are NAND flash memories has been described. However, the present invention includes a storage area divided in predetermined block units and can accept commands. Any device under test that outputs a status signal indicating whether or not there is a test object can be used.

It is a block diagram which shows the principal part structure of the semiconductor test apparatus by one Embodiment of this invention. It is a figure which shows an example of the memory map of device under test 30a-30n. It is a figure which shows an example of the determination result obtained in the determination parts 15a-15n.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 22 State determination part 24 Bad block determination part 25 Busy time determination part 26 Result determination part 27 Bad block memory | storage part 30a-30n Device under test C1 Command signal RB1-RBn Ready / busy signal

Claims (5)

In a semiconductor test apparatus for testing a device under test that outputs a status signal indicating whether or not a command can be received, having a storage area divided in units of a predetermined block,
A state determination unit that determines whether the device under test can accept the command based on the state signal output from the device under test;
A first determination unit that counts the number of times the state determination unit determines that the command cannot be received for each block of the device under test, and determines a magnitude relationship between the count value and a predetermined first threshold; ,
The time from when the command is received by the device under test until the state determination unit determines that the command can be received is accumulated for each block of the device under test, and the accumulated time and a predetermined second time are accumulated. A second determination unit for determining a magnitude relationship with the threshold;
A semiconductor test apparatus comprising: a pass / fail determination unit that determines whether or not the block is a defective block based on determination results of the first and second determination units. The first threshold is set to a value indicating the number of defects per block allowed in the device under test,
The semiconductor test apparatus according to claim 1, wherein the second threshold value is set to a value indicating a target time for each block in which the device under test can accept the command.   The said 1st determination part excludes the said to-be-tested device from test object until the block is complete | finished, when the said count value becomes more than the said 1st threshold value. 2. The semiconductor test apparatus according to 2.   4. The device according to claim 3, wherein when the first determination unit excludes the device under test from the test target, the device under test is also excluded from the test target with respect to the second determination unit. Semiconductor test equipment. A defective block storage unit for storing an address designating at least a part of the blocks determined as defective blocks by the pass / fail determination unit;
5. The semiconductor test apparatus according to claim 1, wherein the state determination unit performs mask control in which an address stored in the defective block storage unit is excluded from a test target. 6. .

Images