JP2009033230A - Amplifier, and liquid crystal driving circuit with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rail-to-rail amplifier which can improve through rate while suppressing increases in circuit scale and current consumption and also improving stability. <P>SOLUTION: The amplifier has a differential pair of NMOS transistors MN1 and MN2 and a differential pair of PMOS transistors MP1 and MP2 connected to an input respectively, and is provided with a pair of NMOS transistors MN21 and MN22 which have drains and sources connected in parallel between drains and sources of the respective NMOS transistors constituting the differential pair and input a predetermined bias voltage at gates, and a pair of PMOS transistors MP21 and MP22 which have drains and sources connected between the drains and sources of the PMOS transistors constituting the differential pair, thereby making a DC bias of an output stage constant. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an amplifier and a liquid crystal driving circuit including the amplifier, and more particularly to an amplifier capable of operating the output signal of the amplifier on a rail-to-rail basis and performing a high output dynamic range operation with low power consumption. The present invention relates to a liquid crystal driving circuit.

  As a conventional rail-to-rail amplifier, an input signal (input voltage) is obtained by adding an input stage having an NMOS transistor differential pair and a PMOS transistor differential pair and an output current from the input stage to obtain an output voltage. What has an output part to generate is known. Here, the rail-to-rail means a voltage range from the voltage (VDD) of the high potential power source to the voltage (VSS) of the low potential power source. The rail-to-rail amplifier is an amplifier that drives an input signal and an output signal in a voltage range from the voltage of the high potential power supply VDD to the voltage of the low potential power supply VSS. FIG. 5 shows such a conventional amplifier.

  As shown in FIG. 5, the input stage 101 of the conventional amplifier 100 has a differential pair of NMOS transistors MN101 and MN102 and a differential pair of PMOS transistors MP101 and MP102. Signals INN and INP are input. The sources of the NMOS transistors MN101 and MN102 are connected in common and are connected to the low potential power supply VSS via the current source I101. The sources of the PMOS transistors MP101 and MP102 are connected in common and connected to the high potential power supply VDD via the current source I102. The drains of the NMOS transistors MN101 and MN102 and the drains of the PMOS transistors MP101 and MP102 are the outputs of the input stage 101, respectively.

  The output unit 102 of the amplifier 100 is a circuit that adds the output currents IP1, IP2, IN3, and IN4 of the input stage 101 and outputs a voltage VOUT corresponding to the result. The first current mirror unit 110, A current mirror unit 111; a pair of transistor sets 112 (a set of transistors MN110 and MP110) and 113 (a set of transistors MN111 and MP111) connected to the current mirror units 110 and 111; and an output stage 104 ing.

  The output currents IP1, IP2, IN3, and IN4 from the input stage 101 are connected to the cascode connection parts of the two transistors that constitute the current mirror parts 110 and 111, respectively, and the input stage 101 responds to the input signals INN and INP. The output current 104 is added, and the voltage VOUT corresponding to the addition result is output from the output stage 104. Note that predetermined bias voltages VP2 and VN2 are applied to the first current mirror unit 110 and the second current mirror unit 111, respectively, and predetermined bias voltages VN1 and VP1 are applied to the transistor sets 112 and 113, respectively.

  However, as described below, since the idling current value of the output stage 104 changes according to the voltage value of the input signal, the settling time deteriorates, the stability deteriorates, and the offset voltage depends on the input voltage. End up.

  A change in the value of the idling current in the output stage 104 of the amplifier 100 shown in FIG. 5 will be specifically described with reference to the drawings. FIG. 6 is a diagram for explaining a change in the value of the idling current in the output stage 104 of the amplifier 100 shown in FIG. FIG. 6 shows a characteristic example when the voltage of the high potential power supply VDD of the amplifier 100 is 3.0 V and the voltage of the low potential power supply VSS is 0 V.

  When a voltage near the middle between the voltage of the high potential power supply VDD and the voltage of the low potential power supply VSS is input to the input stage 101 of the amplifier 100 as the input signals INN and INP, the cascode connection section of the first current mirror section 110 The same positive and negative currents are respectively input to the cascode connection portion of the second current mirror unit 111. For example, as shown in FIG. 6A, when an intermediate voltage of 1.5 V is input, a negative current of 5 μA is output from the input stage 101 to each cascode connection section of the first current mirror section 110, and the input stage 101 To 5 μA of positive current is output to each cascode connection portion of the second current mirror portion 111. Accordingly, an equivalent current (for example, 10 μA) flows through the PMOS transistor MP109 and the NMOS transistor MN109 in the output stage 104. Therefore, the idling current in the output stage 104 has the same current value in the PMOS transistor MP109 and the NMOS transistor MN109.

  Further, when a voltage close to the voltage of the high-potential power supply VDD is input to the input stage 101 of the amplifier 100 as the input signals INN and INP, for example, as shown in FIG. A negative current of 5 μA is input to the cascode connection part, and no current flows through the cascode connection part of the second current mirror unit 111 (0 μA). Accordingly, the idling current in the output stage 104 is such that the current value (10 μA) of the PMOS transistor MP109 is higher than the current value (5 μA) of the NMOS transistor MN109.

  On the other hand, when a voltage close to the voltage of the low potential power supply VSS is input to the input stage 101 of the amplifier 100 as the input signals INN and INP, for example, as shown in FIG. No current flows through the cascode connection portion (0 μA), and a current of 5 μA flows through the cascode connection portion of the second current mirror unit 111. Therefore, the idling current in the output stage 104 has a current value (10 μA) of the NMOS transistor MN109 higher than the current value (5 μA) of the PMOS transistor MP109.

  As described above, in the conventional amplifier 100, the value of the idling current of the output stage 104 changes depending on the voltage value of the input signal. As a result, the settling time is deteriorated, the stability is deteriorated, and the offset voltage depends on the input voltage. Will occur.

  In response to such deterioration of stability, it has been generally performed to increase the capacitance value of a phase compensation capacitor not shown in FIG.

  However, an increase in the capacitance value of the phase compensation capacitor causes a deterioration in slew rate due to a deterioration in settling time, and an increase in layout area. Therefore, it has a great influence on a circuit such as a liquid crystal driving circuit in which many amplifiers are used.

  As means for solving these problems, Patent Document 1 discloses a differential input circuit including a transistor differential pair for inputting an input signal and a current source, and a dummy transistor pair corresponding to the differential input circuit. And a differential input circuit composed of a dummy current source, and an amplifier for controlling the dummy current source is disclosed.

  Further, as means for solving the above problem, Patent Document 2 discloses an amplifier that controls a bias voltage of a differential transistor pair for inputting an input signal by a bias circuit.

Further, as means for solving the above problem, Patent Document 3 discloses, as shown in FIG. 7, a differential pair of NMOS transistors MN101 and MN102 and a differential pair of PMOS transistors MP101 and MP102 in the input stage 101 ′. By providing the transistor pairs MP131, MP132 and MN131, MN132 composed of transistors of opposite conductivity type, this transistor pair is also operated in accordance with the input signals INN, INP, and an amplifier that makes the idling current of the output stage constant is provided. Are listed.
JP 2004-201064 A JP 2000-1983672 A JP-A-11-270644

  However, in the amplifier described in Patent Document 1, a complicated circuit is required to make the transconductance gm constant, which in turn increases the layout area. Also, an increase in current consumption occurs.

  In the amplifier described in Patent Document 2, the back gate voltage must be controlled, and there is a restriction that an arbitrary voltage must be applied to the back gate in the semiconductor process. Moreover, there is a problem that latch-up is likely to occur due to back gate control.

  Further, the amplifier described in Patent Document 3 is affected by variations in the threshold values of the dummy NMOS transistor and the PMOS transistor connected in parallel, so that the dummy transistor pair connected in parallel at the input voltage at which the input differential pair is turned off. It is not possible to guarantee that the current will switch. When the dummy transistor pair is turned on and the differential pair MOS transistor is turned off, the source potential (node to which the current source is connected) of the turned off differential pair MOS transistor fluctuates, and the transient response Will be worsened.

  As described above, any of the above improvement methods has problems such as an increase in circuit current, circuit complexity (layout area increase), slew rate deterioration, offset voltage dependency on input voltage, process restrictions, latch-up, etc. was there.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide an amplifier that suppresses an increase in circuit scale and current consumption and improves the slew rate while improving the stability.

  According to the first aspect of the present invention, the differential pair of the first conductivity type transistor and the differential pair of the second conductivity type transistor that respectively input input signals are connected in common to the differential pair of the first conductivity type transistor. And an input stage having a first current source for supplying a bias current to the connected source and a second current source for supplying a bias current to the sources commonly connected in the differential pair of the second conductivity type transistors. A pair of first conductivity type transistors, each having a drain and a source connected to the drain and source of each first conductivity type transistor constituting the differential pair, and a predetermined bias voltage being input to the gate; The drain and the source are connected to the drain and the source of each second conductivity type transistor constituting the differential pair, and a predetermined bias voltage is gated. And a pair of second conductivity type transistor input.

  According to a second aspect of the present invention, in the first aspect of the present invention, the differential pair of the first conductivity type transistor and the second conductivity type transistor are provided between the high potential power source and the low potential power source. An output stage that outputs a voltage based on an output from each drain of the differential pair, and the predetermined bias voltage input to the pair of first conductivity type transistors is set to a voltage value of the low-potential power source. A voltage obtained by adding the value of the gate-source voltage when the first conductivity type transistor is in an ON state and the value of the operating voltage of the first current source is added to the pair of second conductivity type transistors. The predetermined bias voltage to be input is determined from the voltage value of the high-potential power supply, the value of the gate-source voltage when the second conductivity type transistor is in the ON state, and the operating voltage of the second current source. And the value of Characterized in that the voltage of the calculated values.

  According to a third aspect of the present invention, there is provided a liquid crystal driving circuit for driving a liquid crystal panel, which decodes an input serial image signal and outputs a driving digital signal for each vertical line of the liquid crystal panel. A D / A conversion circuit for converting the driving digital signal into a driving analog signal, and a driving analog signal for each vertical line output from the D / A conversion circuit for current amplification to the liquid crystal panel. An amplifier group including a plurality of amplifiers for outputting, wherein the amplifier includes a differential pair of a first conductivity type transistor and a differential pair of a second conductivity type transistor for inputting the driving analog signal; A first current source for supplying a bias current to sources commonly connected in a differential pair of conductive transistors; and a differential pair of the second conductive transistors. An amplifier having an input stage having a second current source for supplying a bias current to a source connected to the drain, and a drain connected to each of the drain and the source of each first conductivity type transistor constituting the differential pair A drain and a source are connected to a drain and a source of a pair of first conductivity type transistors that are connected to the source and a predetermined bias voltage is input to the gate and each second conductivity type transistor that constitutes the differential pair. And a pair of second conductivity type transistors having a predetermined bias voltage input to the gate.

  According to the present invention, the DC bias voltage and idling current of the output stage can be made constant regardless of the input voltage, and as a result, the settling time, the stability, and the offset voltage dependence on the input voltage are suppressed. be able to. Moreover, since the phase compensation capacitance value can be reduced, the slew rate can be improved.

  A liquid crystal display circuit according to an embodiment of the present invention is a rail-to-rail type including an input stage having a differential pair of an NMOS transistor (first conductivity type transistor) and a differential pair of a PMOS transistor (second conductivity type transistor). An amplifier is provided.

  The input stage includes a first current for supplying a bias current to a differentially connected pair of NMOS transistors and a differential pair of PMOS transistors respectively connected to an input signal, and a source commonly connected in the differential pair of NMOS transistors. And a second current source for supplying a bias current to sources commonly connected in the differential pair of PMOS transistors.

  In addition, a pair of NMOS transistors (hereinafter also referred to as “dummy NMOS transistors”) in which the drain and source are connected to the drain and source of each NMOS transistor constituting the differential pair and a predetermined bias voltage is input to the gate. And a pair of PMOS transistors (hereinafter also referred to as “dummy PMOS transistors”) in which the drain and source are connected to the drain and source of each PMOS transistor constituting the differential pair, respectively, and a predetermined bias voltage is input to the gate. And have.

  The pair of dummy NMOS transistors operate in a complementary manner to the differential pair of NMOS transistors with respect to the in-phase input signals INN and INP, and the pair of dummy PMOS transistors has a difference between the PMOS transistors. Operates complementary to the moving pair.

  Therefore, regardless of the input voltage, the DC bias current and bias voltage of the output stage become constant, and in the amplifier, an increase in circuit scale and current consumption is suppressed, and the slew rate is improved while improving the stability. Is possible.

<< First Embodiment >>
Hereinafter, a specific configuration of the amplifier according to the present embodiment will be described with reference to the drawings. The amplifier according to the present embodiment is built in a liquid crystal driving circuit described below. First, the configuration of the liquid crystal driving circuit will be described below.

  FIG. 1 is a diagram showing a configuration of a liquid crystal driving circuit in the present embodiment. This liquid crystal drive circuit is a liquid crystal driver that is composed of a semiconductor integrated circuit and drives a liquid crystal panel based on input data. Embodiments of the present invention will be described below with reference to the drawings.

  The liquid crystal driving circuit (source driver circuit) shown in FIG. 1 has a function of sequentially switching and outputting a driving signal for each horizontal line to a data line of a liquid crystal panel based on an input serial image signal.

  As shown in FIG. 1, the liquid crystal driving circuit 20 decodes an input serial image signal, outputs a driving digital signal for each vertical line of the liquid crystal panel, and outputs these driving digital signals. A D / A conversion circuit unit (digital-analog conversion circuit unit) 22 for converting each of the signals into a driving analog signal, and a driving analog signal for each vertical line output from the D / A conversion circuit unit 22 are subjected to current amplification. And an amplifier group 23 for outputting to the liquid crystal panel.

  The D / A conversion circuit unit 22 includes a reference voltage generator 31 that generates a plurality of reference voltages, and a plurality of selectors 30 that select and output a voltage corresponding to the driving digital signal from the plurality of reference voltages. Based on the driving digital signal for each vertical line, each selector 30 is controlled to be converted into a plurality of driving analog signals and output.

  The amplifier group 23 includes a plurality of rail-to-rail amplifiers 1 and amplifies the driving analog signals output from the selectors 30 and outputs the amplified signals to the liquid crystal panel.

  Here, since the liquid crystal drive circuit 20 drives a liquid crystal panel, the number of amplifiers 1 (number of CHs) is required to be several hundred or more. In a high-definition liquid crystal drive circuit having a large number of CHs, a reduction in layout area is required, and in addition, low power consumption is particularly required for mobile applications.

  Therefore, the amplifier 1 in the present embodiment is configured as follows, and the layout area can be reduced. That is, the amplifier 1 according to the present embodiment realizes an improvement in the slew rate while improving the stability while suppressing an increase in circuit scale and current consumption, and the configuration thereof will be specifically described below with reference to the drawings. explain. FIG. 2 is a diagram showing the configuration of the amplifier 1 shown in FIG.

  As shown in FIG. 2, the amplifier 1 in this embodiment includes an input stage 2 that inputs driving analog signals output from the D / A conversion circuit unit 22 as input signals INN and INP, And an output unit 3 that generates an output voltage VOUT corresponding to the output.

  The input stage 2 has a differential pair of NMOS transistors MN1 and MN2 and a differential pair of PMOS transistors MP1 and MP2. An input signal INN is input to the NMOS transistor MN1 and the PMOS transistor MP1, and the NMOS transistor MN2 The input signal INP is input to the PMOS transistor MP2. The sources of the NMOS transistors MN1 and MN2 are connected in common, and further connected to the low potential power supply VSS via a first current source I1 that supplies a bias current. The sources of the PMOS transistors MP1 and MP2 are connected in common, and further connected to the high potential power supply VDD via the second current source I2 that supplies a bias current.

  The differential pair of the NMOS transistors MN1 and MN2 and the differential pair of the PMOS transistors MP1 and MP2 operate when the differential pair of the PMOS transistors MP1 and MP2 operates when the input signals INN and INP are low level inputs. When the signals INN and INP are high level inputs, the differential pair of the NMOS transistors MN1 and MN2 operates, and when the input signals INN and INP are intermediate level inputs, the differential pair of the PMOS transistors MP1 and MP2 and the NMOS Transistors MN1 and MN2 operate together.

  Further, in the input stage 2 of the amplifier 1, the drain and source of a transistor of the same conductivity type (hereinafter also referred to as “dummy transistor”) are connected in parallel to the drain and source of a transistor constituting a differential pair. A predetermined bias voltage is applied to the gate of each dummy transistor.

  More specifically, the input stage 2 includes a dummy NMOS transistor MN21 in which the drain and the source are connected to the drain and source of the NMOS transistor MN1, respectively, and a drain and a source in the drain and source of the NMOS transistor MN2, respectively. The connected dummy NMOS transistor MN22, the dummy PMOS transistor MP21 connected to the drain and source of the PMOS transistor MP1, respectively, and the dummy PMOS connected to the drain and source of the PMOS transistor MP2, respectively. And a transistor MP22.

  The gate of the dummy NMOS transistor MN21 and the gate of the dummy NMOS transistor MN22 are connected to a common bias input node, and a predetermined bias voltage VN3 is applied. The gate of the dummy PMOS transistor MP21 and the gate of the dummy PMOS transistor MP22 are connected to a common bias input node, and a predetermined bias voltage VP3 is applied.

  In this way, by biasing the gate voltages of the dummy NMOS transistors MN21 and MN22 with the voltage VN3, when the voltage of the input signals INN and INP becomes VN3 or less, the differential pair of the NMOS transistors MN1 and MN2 is turned off. Complementarily, a current corresponding to the voltages of the input signals INN and INP flows through the pair of dummy NMOS transistors MN21 and MN22. Similarly, by biasing the gate voltages of the dummy PMOS transistors MP21 and MP22 to the voltage VP3, when the voltage of the input signals INN and INP becomes equal to or higher than VP3, the differential pair of the PMOS transistors MP1 and MP2 is turned off, but complementary. A current corresponding to the voltages of the input signals INN and INP flows through the pair of dummy PMOS transistors MP21 and MP22. Therefore, the DC bias current of the output stage can be made constant. Although not shown, the value of the phase compensation capacitance can be made smaller than the conventional value.

  Since the input stage 2 is configured in this way, the DC bias current and the bias voltage of the output stage 5 described later can be made constant regardless of changes in the voltage values of the input signals INN and INP. In addition, it is possible to improve the slew rate while improving the stability while suppressing an increase in current consumption.

  That is, in the conventional amplifier (for example, see FIG. 5), as described above, the DC bias currents of the PMOS transistor MP109 and the NMOS transistor MN109 in the output stage 104 change depending on the voltage state of the input signals INN and INP. A change in the bias current appeared as a change in the input offset voltage. In addition, since the DC bias voltage changes depending on the voltage of the input signal, overshoot or undershoot may occur when a large amplitude operation is performed (see the characteristic (1) shown in FIG. 3), or micro oscillation may occur. In order to prevent this, the phase compensation capacity needs to be increased.

  However, in the amplifier 1 according to the present embodiment, since the DC bias current is constant, there is no decrease in phase margin due to the decrease in the bias current of the output stage 5, and the voltage value of the DC bias is constant. During the amplitude operation, neither overshoot or undershoot nor change in input offset voltage occurs. FIG. 3 shows the waveform of the output voltage VOUT of the amplifier 1 when the input signals INN and INP change from the intermediate voltage to the low level voltage and from the intermediate voltage to the high level voltage (shown in FIG. 3). 2) and a waveform of the output voltage VOUT of the conventional amplifier 100 (see (1) shown in FIG. 3). As can be seen from FIG. 3, in the amplifier 1 according to this embodiment, the occurrence of overshoot and undershoot is suppressed.

  Moreover, in the amplifier 1 according to the present embodiment, the current between the dummy transistor pair and the differential pair is switched without being affected by variations in the threshold values of the NMOS transistor and the PMOS transistor as in the conventional amplifier 100 ′ shown in FIG. Therefore, it is possible to suppress the deterioration of the transient response due to the fluctuation of the source potential of the MOS transistors constituting the differential pair.

  Therefore, as described above, in the amplifier 1 according to the present embodiment, it is possible to improve the slew rate while improving the stability while suppressing an increase in circuit scale and current consumption.

Here, the voltage values of the bias voltages VN3 and VP3 are desirably set as follows in order to realize a rail-to-rail input range. Vmngs is the gate-source voltage of the dummy NMOS transistors MN21 and MN22 (when the transistor is on), Vmpgs is the gate-source voltage of the dummy PMOS transistors MP21 and MP22 (when the transistor is on), and Vov1 is the first current source I1. Vov2 is the lowest voltage at which the second current source I2 operates.
VN3 = VSS + Vmngs + Vov1 (1)
VP3 = VDD− (Vmpgs + Vov2) (2)

  Thus, the bias voltage VN3 is set to the voltage value of the low potential power supply VSS, the gate-source voltage value Vmngs when the NMOS transistor is in the ON state, and the operating voltage value Vov1 of the first current source I1. It is desirable to set the voltage to a value obtained by adding. Further, the bias voltage VP3 is obtained from the voltage value of the high potential power supply VDD, the gate-source voltage value Vmpgs when the PMOS transistor is in the ON state, and the operating voltage value Vov2 of the second current source. It is desirable that the voltage is a value obtained by subtraction. Note that Vov1 and Vov2 are overdrive voltages (Vgs−Vth) of the MOS transistors when the first current sources I1 and I2 are formed of MOS transistors.

  Next, the configuration of the output unit 3 will be specifically described with reference to FIG.

  The output unit 3 is a class AB output stage that receives the output currents IP1, IP2, IN3, and IN4 of the input stage 2 and outputs a voltage VOUT based on the input result. The output unit 3 includes the first current mirror unit 10 and the second current mirror unit 10. A current mirror unit 11, a pair of transistor sets 12 (a set of transistors MN10 and MP10) and 13 (a set of transistors MN11 and MP11) connected to the current mirror units 10 and 11, and an output stage 5; ing.

  The first current mirror section 10 has two cascode-connected PMOS transistors MP5 and MP7 and two cascode-connected PMOS transistors MP6 and MP8. The sources of the PMOS transistors MP5 and MP6 are connected to the voltage of the high potential power supply VDD, respectively, and the drains are connected to the sources of the PMOS transistors MP7 and MP8, respectively. The gate of the PMOS transistor MP5 is connected to the gate of the PMOS transistor MP6 and the drain of the PMOS transistor MP7. The gate of the PMOS transistor MP7 is applied with the gate of the PMOS transistor MP8 and a predetermined bias voltage VP2. Further, the output current IP1 of the input stage 2 is input to the cascode connection portion of the PMOS transistors MP5 and MP7, and the output current IP2 of the input stage 2 is input to the cascode connection portion of the PMOS transistors MP6 and MP8. .

  The second current mirror unit 11 includes two cascode-connected NMOS transistors MN5 and MN7 and two cascode-connected NMOS transistors MN6 and MN8. The sources of the NMOS transistors MN5 and MN6 are connected to the voltage of the low potential power supply VSS, respectively, and the drains are connected to the sources of the NMOS transistors MN7 and MN8, respectively. The gate of the NMOS transistor MN5 is connected to the gate of the NMOS transistor MN6 and the drain of the NMOS transistor MN7. The gate of the NMOS transistor MN7 is applied with the gate of the NMOS transistor MN8 and a predetermined bias voltage VN2. The output current IN3 of the input stage 2 is input to the cascode connection portion of the NMOS transistors MN5 and MN7, and the output current IN4 of the input stage 2 is input to the cascode connection portion of the NMOS transistors MN6 and MN8. .

  The pair of transistors 12 includes an NMOS transistor MN10 and a PMOS transistor MP10, and is connected between the drain of the PMOS transistor MP7 and the drain of the NMOS transistor NM7. The source and drain of the NMOS transistor MN10 are connected to the drain and source of the PMOS transistor MP10, respectively. A predetermined bias voltage VN1 is applied to the gate of the NMOS transistor MN10, and a predetermined bias voltage VP1 is applied to the gate of the PMOS transistor MP10.

  The pair of transistors 13 includes an NMOS transistor MN11 and a PMOS transistor MP11, and is connected between the drain of the PMOS transistor MP8 and the drain of the NMOS transistor NM8. The source and drain of the NMOS transistor MN11 are connected to the drain and source of the PMOS transistor MP11, respectively. A predetermined bias voltage VN1 is applied to the gate of the NMOS transistor MN11, and a predetermined bias voltage VP1 is applied to the gate of the PMOS transistor MP11.

Here, the bias voltages VN1, VP1, VN2, and VP2 described above are set to voltages represented by the following equations (3) to (6). Vmn5gs, Vmn7gs, and Vmn10gs are the gate-source voltages of the NMOS transistors MN5, MN7, and MN10, respectively (when the transistor is on), and Vmp5gs, Vmp7gs, and Vmp10gs are the gate-source voltages of the PMOS transistors MP5, MP7, and MP10, respectively. Vthn is the threshold voltage of the NMOS transistor MN5, and Vthp is the threshold voltage of the PMOS transistor MP5.
VN1 = VSS + Vmn5gs + Vmn10gs (3)
VN2 = VSS + Vmn7gs + (Vmn5gs−Vthn) (4)
VP1 = VDD− (Vmp5gs + Vmp10gs) (5)
VP2 = VDD- {Vmp7gs + (Vmp5gs-Vthp)} (6)
Here, for example, if the voltage value of the high potential power supply VDD is 3V, the voltage of the low potential power supply VSS is 0V, Vgs of each MOS transistor is 0.8V, Vthn is 0.5V, and Vthp is 0.5V, then VP1 = 1.4V, VP2 = 1.9V, VN1 = 1.6V, and VN2 = 1.1V.

  The output stage 5 includes a PMOS transistor MP9 and an NMOS transistor MN9 connected in series between the voltage of the high potential power supply VDD and the voltage of the low potential power supply VSS. The source of the PMOS transistor MP9 is connected to the voltage of the high potential power supply VDD, and the drain thereof is connected to the drain of the NMOS transistor MN9. The source of the NMOS transistor MN9 is connected to the voltage of the low potential power supply VSS. The gate of the PMOS transistor MP9 is connected to the drain of the PMOS transistor MP8, and the gate of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN8.

  As described above, the output unit 3 is configured, and currents obtained by adding the output currents IP1 and IP2 from the input stage 2 flow through the PMOS transistors MP5 and MP6 of the first current mirror unit 10, respectively. Further, the currents obtained by adding the output currents IN3 and IN4 from the input stage 2 flow through the NMOS transistors MN5 and MN6 of the second current mirror unit 11, respectively. A voltage VOUT corresponding to the added current is output from the output stage 5.

  Since it is configured as described above, the amplifier 1 in this embodiment can make the DC bias voltage and idling current of the output stage 5 constant regardless of the voltages of the input signals INN and INP. Deterioration of settling time, deterioration of stability, and dependence of offset voltage on input voltage can be suppressed. In addition, the stability at light load can be increased regardless of the voltage range of the input signals INN and INP, and the settling time can be shortened. In addition, since the phase compensation capacitance value can be reduced, the slew rate can be improved, the layout area can be reduced, and the number of channels in the liquid crystal drive circuit can be increased. The configuration of the output stage 5 is not limited to that described above, and can be selected as appropriate.

<< Second Embodiment >>
Next, the configuration of the amplifier 1 ′ in the liquid crystal drive circuit of the second embodiment will be specifically described with reference to the drawings. FIG. 4 is a diagram showing a configuration of an amplifier in the liquid crystal drive circuit of the second embodiment. The amplifier 1 ′ in the second embodiment is the same circuit as the amplifier 1 in the first embodiment, but the bias voltages VN3 and VP3 applied to the gates of the dummy transistors MN21, MN22, MP21, and MP22 are applied to the second current. The bias voltages VN2 and VP2 of the mirror unit 11 and the first current mirror unit 10 are the same.

  In this way, by making the bias voltages VN3 and VP3 to the dummy transistor common with the bias voltages VN2 and VP2 of the current mirror part, a voltage generation circuit for generating the bias voltages VN3 and VP3 to the dummy transistor is unnecessary. Thus, the layout area can be further reduced.

  At this time, it is desirable to adjust the voltages of the bias voltages VN2 and VP2 to the values shown in the above-described equations (1) and (2).

  Although several embodiments of the present invention have been described in detail with reference to the drawings, these are merely examples, and the present invention can be implemented in other forms that are variously modified and improved based on the knowledge of those skilled in the art. It is possible to implement.

  For example, in the above-described embodiment, the MOS transistor is used as the transistor. However, the present invention is not limited to this and can be applied to the bipolar TR.

It is a figure which shows the structure of the driver for liquid crystal display devices in one Embodiment of this invention. It is a figure which shows the structure of the amplifier shown in FIG. It is a figure which shows the characteristic of the amplifier shown in FIG. It is a figure which shows the structure of the other amplifier in 2nd Embodiment. It is a figure which shows the structure of the conventional amplifier. It is a figure which shows the change of the idling current of the conventional amplifier. It is a figure which shows the other structure of the conventional amplifier.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Amplifier 2 Input stage 3 Output part 5 Output stage 10 1st current mirror part 11 2nd current mirror part 12, 13 Transistor set 20 Liquid crystal drive circuit 21 Register 22 D / A conversion circuit block 23 Amplifier block

Claims (3)

A differential pair of a first conductivity type transistor and a differential pair of a second conductivity type transistor, each of which receives an input signal;
A first current source for supplying a bias current to sources commonly connected in the differential pair of the first conductivity type transistors;
An amplifier having an input stage having a second current source for supplying a bias current to sources commonly connected in the differential pair of the second conductivity type transistors;
A pair of first conductivity type transistors each having a drain and a source connected to a drain and a source of each first conductivity type transistor constituting the differential pair, and a predetermined bias voltage input to the gate;
An amplifier comprising: a pair of second conductivity type transistors each having a drain and a source connected to a drain and a source of each second conductivity type transistor constituting the differential pair, and a predetermined bias voltage input to the gate. An output stage provided between a high potential power source and a low potential power source and outputting a voltage based on an output from each drain of the differential pair of the first conductivity type transistor and the differential pair of the second conductivity type transistor; Prepared,
The predetermined bias voltage input to the pair of first conductivity type transistors is set to a voltage value of the low potential power source, and a value of a gate-source voltage when the first conductivity type transistor is in an ON state, The voltage of the value obtained by adding the value of the operating voltage of the first current source,
The predetermined bias voltage input to the pair of second conductivity type transistors is determined from the voltage value of the high potential power source, the value of the gate-source voltage when the second conductivity type transistor is in an ON state, 2. The amplifier according to claim 1, wherein the voltage is a value obtained by subtracting the value of the operating voltage of the second current source. A liquid crystal driving circuit for driving a liquid crystal panel,
A register that decodes an input serial image signal and outputs a driving digital signal for each vertical line of the liquid crystal panel;
A D / A conversion circuit for converting each of the driving digital signals into a driving analog signal;
An amplifier group including a plurality of amplifiers that current-amplify driving analog signals for each vertical line output from the D / A conversion circuit and output the analog signals to the liquid crystal panel;
The amplifier is
A differential pair of a first conductivity type transistor and a differential pair of a second conductivity type transistor for inputting the driving analog signal;
A first current source for supplying a bias current to sources commonly connected in the differential pair of the first conductivity type transistors;
An amplifier having an input stage having a second current source for supplying a bias current to sources commonly connected in the differential pair of the second conductivity type transistors,
A pair of first conductivity type transistors, each having a drain and a source connected to the drain and source of each first conductivity type transistor constituting the differential pair, and a predetermined bias voltage input to the gate;
A liquid crystal drive comprising: a pair of second conductivity type transistors each having a drain and a source connected to the drain and source of each second conductivity type transistor constituting the differential pair, and a predetermined bias voltage input to the gate circuit.

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