JP2009032724A - Field effect transistor (fet), power amplifier module and mobile communication device with the same, and method of manufacturing fet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor (FET), etc. which can change the gain without increasing a cost, increasing or decreasing ON resistance Ron, and increasing the number of processes. <P>SOLUTION: The FET 1 has such a structure that a gate electrode 26 is formed on a multilayer semiconductor layer 20 and a drain electrode 27 and a source electrode 28 are so formed as to face each other with the gate electrode 26 in between. On the multilayer semiconductor layer 20 between the gate electrode 26 and the drain electrode 27, a field plate electrode 29 connected to the source electrode 28 via an insulation film 18 is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor, a power amplifier module and a mobile communication device including the same, and a method for manufacturing the field effect transistor.

  Since mobile communication devices such as mobile phones and PDAs (Personal Digital Assistance) use high frequency signals, the RF transceiver circuit uses a MMIC (Microwave Integrated Integrated Circuit) which is a high frequency integrated circuit. It transmits and receives high-frequency signals.

  In such an RF transceiver circuit, a power amplifier module for transmission that consumes a large amount of power is used, but performance such as higher gain and higher power added efficiency has been achieved due to the trend toward lower power consumption in mobile communication devices. There is a strong demand for improvement.

  For example, in the specification of W-CDMA (third generation mobile phone), a transmission power amplifier module having high gain characteristics is desired. For this reason, in conventional power amplifier modules for transmission, power amplifiers with high-performance amplifying elements are connected in multiple stages, and gain control at each stage is controlled using a circuit method to provide device performance that meets specifications is doing.

  FIG. 10 shows a schematic cross section of a field effect transistor which is an amplifying element used in a conventional power amplifier module. The field-effect transistor shown in this figure is a junction type high electron mobility transistor (JPHEMT), and among other field-effect transistors, particularly high gain and high power added efficiency (Power Added Efficiency). This is a field-effect transistor that is considered suitable for fabrication (see, for example, FIG. 11 of Patent Document 1).

In FIG. 10, a conventional junction type high electron mobility transistor 100 includes an undoped GaAs buffer layer 102, an undoped InGaAs channel layer 103, an undoped AlGaAs spacer layer 104, an n-type AlGaAs doping layer 105 on a semi-insulating GaAs substrate 101. The n-type AlGaAs barrier layer 106 has a stacked semiconductor layer formed sequentially by epitaxial growth. Here, the n-type AlGaAs doping layer 105 and the n-type AlGaAs barrier layer 106 are doped with an n impurity, for example, silicon (Si), and the concentration of the n-type AlGaAs doping layer 105 is 2 × 10 ¹⁸ / cm ^3. ˜5 × 10 ¹⁸ / cm ³ , and the n-type AlGaAs barrier layer 106 is about 5 × 10 ¹⁶ / cm ³ .

  A gate region 107 made of a p-type AlGaAs region doped with a p-type impurity such as zinc (Zn) is formed immediately below the gate electrode formation region of the n-type AlGaAs barrier layer 106.

On the n-type AlGaAs barrier layer 106, for example, silicon nitride (SiN) is deposited to form an insulating film 108. The insulating film 108 has openings in the source electrode formation region, the drain electrode formation region, and the gate electrode formation region, and the drain electrode 127 is connected to the n-type AlGaAs barrier layer 106 through the openings. The source electrode 128 is formed, and the gate electrode 126 is formed so as to be connected to the gate region 107.
Japanese Patent Laid-Open No. 2003-100774

  Incidentally, in the W-CDMA specification, as shown in FIG. 11, a power amplifier having a two-stage power amplifier in which the gain of the power amplifier 152 at the front stage is 15.0 dB and the gain of the power amplifier 154 at the rear stage is 14.0 dB. A module is required. These gains are generally controlled by introducing matching circuits 151, 153, and 155 as shown in FIG. 11, and the performance of the power amplifier itself is the same in both stages.

  In manufacturing the power amplifier module 150 having the above characteristics, the configuration of the matching circuits 151, 153, and 155 for adjusting the gain characteristics should consider the performance of the junction type high electron mobility transistor that constitutes the power amplifiers 152 and 154. It must be complicated.

  Therefore, as a method for simplifying the design process of these matching circuits, it is conceivable to design a device so that the gain of the junction type high electron mobility transistor constituting the power amplifier is different in each stage of the power amplifier.

  In order to improve the gain of the junction type high electron mobility transistor, it is a simple technique to shorten the gate length of the junction type high electron mobility transistor. However, an increase in photolithography and etching processes and capital investment are unavoidable, and there are significant demerits in terms of throughput and cost.

  As another method for improving the gain of the junction type high electron mobility transistor, it is conceivable to change the device size such as the gate-drain distance (Lgd). However, as a side effect thereof, there is a change in the on-resistance Ron. As a result, the efficiency increases and decreases, which may increase the complexity of matching.

  In addition, as disclosed in Japanese Patent Application Laid-Open No. 2006-237286, there is a proposal for improving the device characteristics of a junction type high electron mobility transistor by forming a field plate electrode in a floating state along the sidewall of the gate electrode. In this case, in this case, a process for forming only the field plate electrode is added to the conventional process flow, which causes an increase in TAT (Turn Around Time) and cost due to an increase in the number of processes.

  The present invention has been made to solve such a problem, and a field effect transistor capable of changing the gain without increasing the cost, increasing or decreasing the on-resistance Ron, and increasing the number of processes, and a power amplifier including the same Another object of the present invention is to provide a mobile communication device and a method of manufacturing a field effect transistor.

  In order to solve this problem, the invention according to claim 1 is a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other with the gate electrode interposed therebetween are formed on a laminated semiconductor layer. And a field plate electrode connected to the source electrode through an insulating film is provided on the stacked semiconductor layer between the gate electrode and the drain electrode.

  According to a second aspect of the present invention, there is provided a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on a laminated semiconductor layer. The field effect transistor is connected to the source electrode via an insulating film on the stacked semiconductor layer between the gate electrode and the drain electrode. A field plate electrode is provided.

  The invention according to claim 3 is the invention according to claim 2, wherein the position of the field plate electrode is different for each power amplifier.

  According to a fourth aspect of the present invention, there is provided a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on a laminated semiconductor layer. In a power amplifier module formed by providing a plurality of power amplifiers, a field effect transistor constituting at least one power amplifier of the plurality of power amplifiers is configured such that the field effect transistor between the gate electrode and the drain electrode A field plate electrode connected to the source electrode through an insulating film is provided on the laminated semiconductor layer.

  According to a fifth aspect of the present invention, in the mobile communication device including a transmission circuit that amplifies and transmits a high-frequency signal with a power amplifier, the power amplifier includes a gate electrode and a gate electrode on the stacked semiconductor layer. A field effect transistor having a source electrode and a drain electrode opposed to each other with an electrode interposed therebetween, wherein the field effect transistor is insulated on the stacked semiconductor layer between the gate electrode and the drain electrode A field plate electrode connected to the source electrode through a film is provided.

  According to a sixth aspect of the present invention, there is provided a field effect transistor manufacturing method in which a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on a stacked semiconductor layer. Forming an insulating film on the laminated semiconductor layer; selectively removing the insulating film; and using the insulating film as a mask, forming a gate region in a barrier layer formed on the uppermost layer of the laminated semiconductor layer Forming the gate electrode on the gate region; selectively removing the insulating film; and forming the drain electrode and the source electrode on the stacked semiconductor layer; and the gate electrode and the Forming a field plate electrode on the stacked semiconductor layer between the drain electrodes via the insulating film; and the field plate electrode and the source electrode And a step of connecting.

  The invention according to claim 7 is characterized in that the step of forming the gate electrode and the step of forming the field plate electrode are the same step.

  According to the present invention, a field effect transistor capable of changing the gain without increasing cost, increasing or decreasing the on-resistance Ron, and increasing the number of processes, and a power amplifier, a mobile communication device, and a field effect transistor including the field effect transistor are provided. A manufacturing method can be provided.

  The field effect transistor according to the embodiment of the present invention is, for example, a heterojunction junction type high electron mobility transistor using a heterointerface, and is applied to a power amplifier module in which power amplifiers are connected in multiple stages. Can do. This power amplifier module can be used as a power amplifier of a mobile communication device such as a mobile phone or a PDA. In the following description, a heterojunction junction type high electron mobility transistor will be described as an example.

  In the field effect transistor according to the present embodiment, a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on the stacked semiconductor layer, and the stacked semiconductor layer between the gate electrode and the drain electrode is formed. A field plate electrode connected to the source electrode through an insulating film is provided thereon.

  The gain characteristics of the electron mobility transistor can be changed by the arrangement of the field plate electrode. For example, the closer the field plate electrode is to the gate electrode, the more the gain can be improved. Conversely, the closer to the drain electrode, the less the gain improvement effect. Therefore, it is possible to change the gain characteristics of the electron mobility transistor without increasing the cost or increasing or decreasing the on-resistance Ron.

  Therefore, by applying the electron mobility transistor including the field plate electrode to at least one stage of power amplifier, it becomes easy to provide a power amplifier module including a plurality of stages of power amplifiers having different gain characteristics. .

  The electron mobility transistor in this embodiment includes, for example, a step of forming an insulating film on the stacked semiconductor layer and a barrier layer formed on the uppermost layer of the stacked semiconductor layer using the selectively removed insulating film as a mask. Forming a gate region on the gate region; forming a gate electrode on the gate region; selectively removing the insulating film; forming a drain electrode and a source electrode on the stacked semiconductor layer; It can be manufactured by a step of forming a field plate electrode on the laminated semiconductor layer between the drain electrodes via an insulating film and a step of connecting the field plate electrode and the source electrode.

  Moreover, by making the step of forming the gate electrode and the step of forming the field plate electrode the same step, the gain characteristics of the electron mobility transistor can be improved without increasing the number of steps.

  Hereinafter, an embodiment of a semiconductor device including a field effect transistor according to the present invention will be described in detail with reference to the schematic cross-sectional view of FIG. FIG. 1 shows, as an example, a configuration applied to a single heterojunction junction high electron mobility transistor (JPHEMT) using a heterointerface of InGaAs and AlGaAs.

  As shown in FIG. 1, a buffer layer 12, a channel layer 13, a spacer layer 14, a doping layer 15, and a barrier layer 16 are, for example, epitaxially grown in order from the lower layer on the substrate 11. Form. As the substrate 11, for example, a semi-insulating GaAs substrate is used. As the buffer layer 12, for example, an undoped GaAs buffer layer having a thickness of 500 nm is used. As the channel layer 13, an undoped InGaAs channel layer having a thickness of 20 nm is used as an example. For example, an undoped AlGaAs spacer layer having a thickness of 10 nm is used for the spacer layer 14. For example, an n-type AlGaAs doping layer having a thickness of 5 nm is used for the doping layer 15. As the barrier layer 16, an n-type AlGaAs barrier layer having a thickness of 200 nm is used as an example.

The doping layer 15 and the barrier layer 16 are doped with, for example, silicon (Si) as an n-type impurity, and the concentration of the doping layer 15 is 2 × 10 ¹⁸ / cm ^{3 to} 5 × 10 ¹⁸ / cm ^{3 in the} doping layer 15. The barrier layer 16 has a degree of about 5 × 10 ¹⁶ / cm ³ .

  A gate region 21 is formed immediately below the gate electrode formation region of the barrier layer 16. The gate region 21 is formed of a p-type AlGaAs region doped with a p-type impurity such as zinc (Zn).

  An insulating film 18 is formed on the barrier layer 16 by, for example, silicon nitride (SiN). In the insulating film 18, openings 23, 24, and 25 for forming electrodes are formed. A gate electrode 26 connected to the gate region 21 is formed in the opening 23. The gate electrode 26 has a laminated structure of, for example, titanium (Ti), platinum (Pt), and gold (Au). In addition, a drain electrode 27 and a source electrode 28 connected to the barrier layer 16 are formed in the openings 24 and 25. As the drain electrode 27 and the source electrode 28, for example, an alloy of gold (Au), germanium alloy (AuGe), and nickel (Ni) is used.

  On the insulating film 18 between the gate electrode 26 and the drain electrode 27, a field plate electrode 29 connected to the source electrode 28 through the wiring portion 40 is disposed. The field plate electrode 29 is formed at the same time as the gate electrode 26 in the same process, and has, for example, a laminated structure of titanium (Ti), platinum (Pt), and gold (Au).

  As described above, by arranging the field plate electrode 29 connected to the source electrode 28 on the insulating film 18 between the gate electrode 26 and the drain electrode 27, the electric field concentration in the vicinity of the gate electrode 26 is reduced, and the gate -The extrinsic part of the drain-to-drain parasitic capacitance Cgd can be reduced.

  Therefore, the carrier concentration directly under the source, gate, and drain does not decrease, and the gain characteristics can be improved efficiently without increasing the source-gate parasitic resistance Rs and the gate-drain parasitic resistance Rd.

  Moreover, since the device size such as Lg is the same as the conventional one, it is possible to change the gain which is one of the RF characteristics without changing the DC characteristics at all.

  FIG. 2 shows the result of prototyping the junction-type high electron mobility transistor 1 described above using the manufacturing method of the present embodiment and evaluating MSG (Maximum Stable Gain). FIG. 2 shows the relationship between the maximum stable gain MSG and the distance Lfp (see FIG. 2B) between the gate electrode 26 and the field plate electrode 29 in the junction type high electron mobility transistor 1 in this embodiment. It is a figure (refer FIG.2 (b)) shown. As shown in FIG. 2, the closer the field plate electrode 29 is to the gate electrode 26, the more the gain can be improved. Conversely, when the field plate electrode 29 is closer to the drain electrode 27, the gain improvement effect is reduced. For example, the maximum stable gain MSG = 20.5 to 20.8 dB when the distance Lfp = 1.0 μm, whereas the maximum stable gain MSG = 19.5 to 19.8 dB when the distance Lfp = 3.0 μm. It is. Therefore, the gain can be adjusted by the arrangement of the field plate electrode 29, and as described later, it becomes easy to create a power amplifier module in which power amplifiers having different gains are arranged in multiple stages.

(About manufacturing method)
Next, an embodiment of the method for manufacturing the high electron mobility transistor 1 of the present invention will be described with reference to the manufacturing process sectional views of FIGS. In this manufacturing method, a manufacturing method of the junction type high electron mobility transistor 1 described with reference to FIG. 1 will be described.

As shown in FIG. 3A, on the substrate 11, for example, a buffer layer 12, a channel layer 13, a spacer layer 14, a doping layer 15, and a barrier layer 16 are epitaxially grown in order from the lower layer, for example, and a laminated semiconductor having an epitaxial structure. Form a layer. As the substrate 11, for example, a semi-insulating GaAs substrate is used. As the buffer layer 12, for example, an undoped GaAs buffer layer having a thickness of 500 nm is used. As the channel layer 13, an undoped InGaAs channel layer having a thickness of 20 nm is used as an example. For example, an undoped AlGaAs spacer layer having a thickness of 10 nm is used for the spacer layer 14. For example, an n-type AlGaAs doping layer having a thickness of 5 nm is used for the doping layer 15. As the barrier layer 16, for example, an n-type AlGaAs barrier layer having a thickness of 200 nm is used. The doping layer 15 and the barrier layer 16 are doped with, for example, Si as an n-type impurity, and the concentration of the doping layer 15 is about 2 × 10 ¹⁸ / cm ^{3 to} 5 × 10 ¹⁸ / cm ³ . In the layer 16, it is set to about 5 × 10 ¹⁶ / cm ³ .

  Next, as illustrated in FIG. 3B, an insulating film 18 is formed on the barrier layer 16. The insulating film 18 is formed by depositing SiN by, for example, the CVD method (Chemical Vapor Deposition).

  Next, as shown in FIG. 3C, a resist film 30 is formed by applying a resist on the insulating film 18 by a coating technique. Next, an opening 31 is formed in the resist film 30 on the gate formation region by photolithography (Photolithography) technology. Next, using this resist film 30 as an etching mask, a part of the insulating film 18 is etched to form an opening 32. This etching is performed by, for example, RIE (Reactive Ion Etching). Thereafter, the resist film 30 is removed.

  Next, as shown in FIG. 4A, zinc (Zn) is introduced into the barrier layer 16 from the opening 32 by vapor phase diffusion using p-type impurities, for example, diethyl zinc (DEZ) which is an organometallic compound of Zn. ) To form a gate region 21 made of a p-type AlGaAs region.

  Next, an electrode forming film which is a conductive film is formed on the insulating film 18 including the inside of the opening 32. The electrode forming film is formed by sequentially depositing, for example, titanium (Ti), platinum (Pt), and gold (Au). Subsequently, as shown in FIG. 4B, by forming a mask by photolithography technique and milling technique using the mask, the gate electrode 26 made of the electrode forming film is formed, and at the same time, between the gate and the drain. Then, a field plate electrode 29 made of the electrode forming film is formed, for example, at a position 1.5 μm away from the gate electrode 26. The gate electrode 26 is connected to the gate region 21 through the opening 32.

  Next, a resist film is formed on the insulating film 18 by a coating technique so as to cover the gate electrode 26 and the field plate electrode 29. Next, an opening is formed in the resist film so that an opening is formed on the drain electrode formation region for forming the drain electrode 27 and the source formation electrode region for forming the source electrode 28 by photolithography. Next, as shown in FIG. 4C, the insulating film 18 is etched using the resist film as an etching mask to form openings 33 and 34 on the drain electrode formation region and the source electrode formation region. . This etching is performed by RIE, for example.

  Next, after sequentially depositing ohmic electrode materials such as gold / germanium alloy (AuGe), nickel (Ni), Au on the entire surface, a lift-off method and a subsequent alloying process, as shown in FIG. A drain electrode 27 is formed in the opening 33, and a source electrode 28 is formed in the opening 34.

  Thereafter, as shown in FIG. 5B, the field plate electrode 29 and the source electrode 28 are connected in the wiring portion 40.

  By such a manufacturing method, the carrier concentration directly under the source, gate, and drain is not decreased, and the gain characteristics are efficiently improved without increasing the source-gate parasitic resistance Rs and the gate-drain parasitic resistance Rd. In addition, a junction type high electron mobility transistor structure that can change the gain without changing the DC characteristics can be realized.

  In the above description, a single heterojunction type high electron mobility transistor using a heterointerface of InGaAs and AlGaAs has been described as an example. However, a double heterojunction type structure can also be applied. . As a stacked semiconductor layer of a double heterojunction junction type high electron mobility transistor, for example, on a semi-insulating GaAs substrate, an undoped GaAs buffer layer, a first undoped AlGaAs layer, a first n-type AlGaAs doping layer, a first A stacked semiconductor layer in which one undoped AlGaAs spacer layer, an undoped InGaAs channel layer, a second undoped AlGaAs spacer layer, a second n-type AlGaAs doping layer, and an n-type AlGaAs barrier layer are sequentially stacked is used. Other configurations are the same as those of the single heterojunction type high electron mobility transistor.

(About power amplifier module)
Next, a power amplifier module in which power amplifiers configured to include the above-described junction type high electron mobility transistor 1 are connected in multiple stages on the same substrate 11 will be described with reference to the drawings. FIG. 6 is a diagram showing a circuit configuration of a power amplifier module that meets the W-CDMA specification requirements.

  As shown in FIG. 6, the power amplifier module 50 includes an input matching circuit 51, a front power amplifier 52, an intermediate matching circuit 53, a rear power amplifier 54, and an output matching circuit 55. The gain of the front-stage power amplifier 52 is set to 15.0 dB, and the gain of the rear-stage power amplifier 54 is set to 14.0 dB.

  The pre-stage power amplifier 52 and the post-stage power amplifier 54 are configured to include the above-described junction type high electron mobility transistor 1 as an amplifying element. Each of the power amplifiers 52 and 54 realizes the different gains described above by making the distance Lfp between the gate electrode and the field plate electrode different.

  As shown in FIG. 2B described above, in the junction type high electron mobility transistor 1, the distance Lfp between the gate electrode 26 and the field plate electrode 29 and the gain MSG have a function relationship. For example, the distance Lfp When the gain is 1.0 μm, the power amplifier gain is 15.0 dB, and when the distance Lfp is 2.0 μm, the power amplifier gain is 14.0 dB, as shown in FIG. The distance Lfp of the junction type high electron mobility transistor 1 constituting the amplifier 52 is set to 1.0 μm, and as shown in FIG. By setting the distance Lfp to 2.0 μm, it is possible to meet the above W-CDMA specification requirements.

  In this way, power amplifiers having different gains can be manufactured simply by changing the distance Lfp between the gate electrode and the field plate electrode, so that the gain can be increased without increasing the cost, increasing or decreasing the on-resistance Ron, or increasing the number of processes. The circuit design can be simplified.

  Further, the above-described junction type high electron mobility transistor 1 is applied only to the front stage power amplifier 52, and the conventional junction type high electron mobility transistor without the field plate electrode 29 is applied to the rear stage power amplifier 54. It is good.

  For example, the gain of the power amplifier is 15.0 dB when the distance Lfp of the junction type high electron mobility transistor 1 is 2.0 μm, and the gain of the power amplifier when the field plate electrode 29 is not provided is 14.0 dB. In this case, as shown in FIG. 8A, the distance Lfp of the junction type high electron mobility transistor 1 constituting the front-stage power amplifier 52 is set to 2.0 μm, and as shown in FIG. The junction-type high electron mobility transistor that forms the junction 54 is a junction-type high electron mobility transistor that does not include the field plate electrode 29, so that the above-described W-CDMA specification requirements can be met.

  In this way, the gain of the power amplifier in each stage may be realized by providing the field plate electrode 29 connected to the source electrode 28 only in the previous stage power amplifier 52. In this case, for example, in the junction-type high electron mobility transistor constituting the post-stage power amplifier 54, in order to realize the conventional structure, a drawing pattern that does not form the field plate electrode 29 on the mask should be prepared. That's fine. Depending on the gain of each stage, it is possible to appropriately determine which part from the previous stage to the final stage is a junction type high electron mobility transistor that does not have the field plate electrode 29.

  In the above description, an example of a power amplifier module in which power amplifiers are connected in multiple stages on the same substrate and conforming to the W-CDMA specification requirements has been described, but not limited to the W-CDMA specification, The junction-type high electron mobility transistor 1 having the above-described epitaxial structure can be applied to a power amplifier module having a multistage power amplifier that meets various specifications.

  For example, the junction type high electron mobility transistor 1 having the above-described epitaxial structure can be applied to a power amplifier module having a two-stage power amplifier in a communication device using a high speed downlink packet access (HSDPA) modulation. In this case, for example, a gain characteristic of 15.5 dB is required for the front-stage power amplifier and 13.0 dB for the rear-stage power amplifier. Therefore, in order to realize the field plate structure of the junction type high electron mobility transistor 1 in each stage power amplifier, for example, the distance Lfp is 0.5 μm and the latter stage power amplifier is used in the junction type high electron mobility transistor 1 of the former stage power amplifier. The junction type high electron mobility transistor 1 has a distance Lfp of 3.2 μm or a structure without the field plate electrode 29.

  Further, in the HSDPA modulation communication system apparatus, the junction type high electron mobility transistor 1 having the above-described epitaxial structure can be applied to a power amplifier module including a three-stage power amplifier. In this case, for example, a gain characteristic of 4.5 dB is required for the first stage power amplifier, 14.0 dB for the middle stage power amplifier, and 10.5 dB for the final stage power amplifier. In order to realize this with the field plate structure of the junction type high electron mobility transistor 1 in each stage, for example, the junction type high electron mobility transistor 1 of the middle stage power amplifier has a distance Lfp of 0.5 μm and the final stage power amplifier. The junction type high electron mobility transistor 1 has a distance Lfp of 3.2 μm or a structure without the field plate electrode 29. Note that the junction type high electron mobility transistor 1 of the first stage power amplifier does not require a field plate structure because the output power is small and a large gain is not required.

(About mobile communication devices)
Next, the configuration of the mobile communication device on which the power amplifier module 50 of the above embodiment is mounted will be described. FIG. 9 is a diagram showing a schematic configuration of the mobile communication device.

  The mobile communication device 60 shown in FIG. 9 includes a CPU 61, a ROM 62, a RAM 63, an input unit 64, a display unit 65, a voice input / output unit 66, and a wireless transmission / reception circuit 67. A mobile phone or a personal digital assistant (PDA).

  The wireless transmission / reception circuit 67 (corresponding to an example of a transmission circuit) includes the power amplifier module 50 including the junction type high electron mobility transistor 1 described in the above embodiment as a power amplifier, and is modulated. The high frequency signal is amplified by the power amplifier module 50 and output as a radio signal via the duplexer 71 and the antenna 72. Note that radio signals from other radio apparatuses are amplified by a power amplifier 73 via an antenna 72 and a duplexer 71, and then demodulated and processed.

  Thus, the power amplifier module 50 described above can be applied to a mobile communication device or the like.

  Although several embodiments of the present invention have been described in detail with reference to the drawings, these are merely examples, and the present invention can be implemented in other forms that are variously modified and improved based on the knowledge of those skilled in the art. It is possible to implement.

It is a schematic structure sectional view of a high electron mobility transistor in one embodiment concerning the present invention. FIG. 2 is a diagram for explaining the relationship between the arrangement of field plate electrodes and the gain in the high electron mobility transistor of FIG. 1. It is manufacturing process sectional drawing of the high electron mobility transistor in one embodiment which concerns on this invention. It is manufacturing process sectional drawing of the high electron mobility transistor in one embodiment which concerns on this invention. It is manufacturing process sectional drawing of the high electron mobility transistor in one embodiment which concerns on this invention. It is a figure which shows schematic structure of the power amplifier module in one embodiment which concerns on this invention. It is a figure which shows schematic structure sectional drawing of the power amplifier module in one embodiment which concerns on this invention. It is a figure which shows schematic structure sectional drawing of the other power amplifier module in one embodiment which concerns on this invention. It is a figure which shows schematic structure of the mobile communication apparatus in one embodiment which concerns on this invention. It is a schematic structure sectional view of the conventional high electron mobility transistor. It is a figure which shows schematic structure of a power amplifier module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High electron mobility transistor 11 Substrate 12 Buffer layer 13 Channel layer 14 Spacer layer 15 Doping layer 16 Barrier layer 18 Insulating film 20 Laminated semiconductor layer 21 Gate region 26 Gate electrode 27 Drain electrode 28 Source electrode 29 Field plate electrode 50 Power amplifier module 52 Pre-stage power amplifier 54 Post-stage power amplifier

Claims (7)

In a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on the stacked semiconductor layer,
A field effect transistor comprising a field plate electrode connected to the source electrode through an insulating film on the stacked semiconductor layer between the gate electrode and the drain electrode. A power formed by providing a plurality of power amplifiers each including a field effect transistor having a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode on the stacked semiconductor layer. In the amplifier module,
The field effect transistor is characterized in that a field plate electrode connected to the source electrode through an insulating film is provided on the stacked semiconductor layer between the gate electrode and the drain electrode.   The power amplifier module according to claim 2, wherein the position of the field plate electrode is different for each power amplifier. A power formed by providing a plurality of power amplifiers each including a field effect transistor having a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode on the stacked semiconductor layer. In the amplifier module,
A field effect transistor constituting at least one power amplifier of the plurality of power amplifiers is formed on the stacked semiconductor layer between the gate electrode and the drain electrode and on the source electrode via an insulating film. A power amplifier module comprising a connected field plate electrode. In a mobile communication device equipped with a transmission circuit that amplifies and transmits a high-frequency signal with a power amplifier,
The power amplifier includes a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other across the gate electrode are formed on a stacked semiconductor layer,
The field effect transistor is characterized in that a field plate electrode connected to the source electrode through an insulating film is provided on the stacked semiconductor layer between the gate electrode and the drain electrode. . In a method of manufacturing a field effect transistor in which a gate electrode and a source electrode and a drain electrode facing each other with the gate electrode interposed therebetween are formed on the stacked semiconductor layer,
Forming an insulating film on the laminated semiconductor layer;
Selectively removing the insulating film, and using the insulating film as a mask, forming a gate region in a barrier layer formed on the uppermost layer of the stacked semiconductor layer;
Forming the gate electrode on the gate region;
Selectively removing the insulating film and forming the drain electrode and the source electrode on the stacked semiconductor layer;
Forming a field plate electrode on the stacked semiconductor layer between the gate electrode and the drain electrode via the insulating film;
And a step of connecting the field plate electrode and the source electrode.   7. The method of manufacturing a field effect transistor according to claim 6, wherein the step of forming the gate electrode and the step of forming the field plate electrode are the same step.

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