JP2008518476A - Semiconductor device including semiconductor region having strain channel region distorted differently and method for manufacturing the same - Google Patents

Abstract

The charge carrier mobilities of different transistor elements are individually adjusted by partially modifying the inherent stress of the insulating layer that laterally surrounds the gate electrode structure of the transistor structure formed by the inlaid technique. In particular, in an inlaid gate structure transistor structure, NMOS and PMOS transistors can receive tensile and compressive stresses, respectively.

Description

  The present invention relates generally to semiconductor circuits, and more particularly to the formation of semiconductor regions with increased charge carrier mobility, such as channel regions of field effect transistors, by creating strain in the semiconductor regions.

The manufacture of integrated circuits requires the formation of many circuit elements on a given chip area with a specific circuit layout.
For this purpose, substantially crystalline semiconductor regions with or without additional dopant material serve as “active” regions, ie at least temporarily as conductive regions. As defined in part of a special substrate.
In general, multiple process technologies are currently performed on complex circuits such as microprocessors, storage chips, and the like. For these, MOS technology is currently the most effective approach due to its superior characteristics considering processing speed and / or power consumption and / or cost efficiency.
In the manufacture of complex integrated circuits using MOS technology, millions of transistors, N-channel transistors and / or P-channel transistors, are formed on a substrate that includes a crystalline semiconductor layer.
A MOS transistor includes a so-called PN junction formed by a highly doped drain and source region interface, regardless of whether an N-channel transistor or a P-channel transistor is considered. A slightly doped or undoped channel region is disposed between the drain region and the source region.
The conductivity of the channel region, i.e. the drive current capability of the conductive channel, is controlled by a gate electrode adjacent to the channel region and separated by an insulating film.
The conductivity of the channel region in the formation of a conductive channel by applying an appropriate control voltage to the gate electrode is the transistor over the distance between the source and drain regions, also called dopant concentration, charge carrier mobility, and channel length. Depends on the given extension of the channel region in the width direction.
Therefore, when applying a control voltage to the gate electrode, the conductivity of the channel region, along with the ability to rapidly create a conductive channel below the insulating layer, substantially affects the performance of the MOS transistor.
Thus, the rate at which the channel is generated (ie, the conductivity of the gate electrode), and the channel resistivity substantially determine the transistor characteristics, so that the channel length is reduced, the associated channel resistivity is reduced, and the gate. The increase in resistivity is a major design criterion for channel length in order to increase the processing speed of integrated circuits.

However, continually reducing transistor dimensions has a number of problems associated with this that must be dealt with in a way that does not significantly reduce the benefits obtained by reliably reducing the channel length of the MOS transistor.
One of the major issues in this regard is enhanced photolithography and etching to ensure that critical dimension circuit elements, such as transistor gate electrodes, for new device generations are reproduced and produced. Develop a strategy.
Furthermore, highly complex dopant profiles are required in the drain and source regions in the vertical as well as the horizontal direction to provide low sheet and contact resistivity with the desired channel controllability. Is done.
In addition, reducing the channel length further requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulating film and channel region, so that the vertical of the PS junction with respect to the gate insulating film. The critical location also represents a critical design criterion that takes into account leakage current control, which requires elaborate injection techniques.
According to another method, the epitaxially grown regions, called elevated drain and source regions, simultaneously increase the conductivity of the elevated drain and source regions while maintaining a shallow PN junction with respect to the gate dielectric. The gate electrode is formed by being shifted from the gate electrode by a predetermined amount.

In another conventional solution, the polysilicon gate electrode in an extremely scaled device is maintained while maintaining a self-aligned process sequence to form the drain and source regions and the gate electrode. The problem of increased resistivity has been to replace the currently used polysilicon doped with metal as the gate electrode material.
This can be accomplished by forming a dummy gate in conjunction with a removable sidewall spacer that can serve as an implantation mask during the formation of the drain and source regions.
After the dummy gate is embedded in the interlayer insulating film, the dummy gate can be replaced with a highly conductive gate material such as metal.
With this “inlaid” gate electrode approach, transistor performance can be significantly improved.
However, the problem of limited channel conductivity is not solved by this method.

Furthermore, the continuous size of the critical dimension, i.e. the reduction of the transistor gate length, requires adaptation to the very complex process technology and new developments for the above process steps.
This has also been proposed to improve the device performance of transistor elements by increasing the charge carrier mobility of the channel region for a given channel length, which makes it possible to It presents the possibility of achieving the same performance improvement as progressing to a future technology node for downsized devices while avoiding much of the process adjustment.

Accordingly, it has been proposed to introduce, for example, a silicon / germanium layer or a silicon / carbon layer in or below the channel region in order to generate a tensile or compressive stress that can result in a corresponding pressure.
By introducing layers that generate stress in or below the channel region, transistor performance can be significantly enhanced, but significant efforts must be made to implement the formation of stress layers corresponding to conventional known MOS technology. There is.
For example, additional epitaxial growth techniques need to be developed and implemented in the process flow to form a stress layer containing germanium or carbon at an appropriate location in or below the channel region.
Thus, process complexity is significantly increased, thereby further increasing the possibility of reducing manufacturing costs and production yields.

  From the above situation, it is possible to create an improved transistor architecture, including the introduction of a high conductivity gate electrode, while allowing the creation of different desired stress states in different semiconductor regions. Technology is required.

  The following provides an overview of the present invention in order to provide a basic understanding of some aspects of the present invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. The purpose here is to provide some concepts of the invention in a simplified form as a prelude to the more detailed description that follows.

Summary of the Invention

In general, the present invention provides so-called “in-laid” with enhanced stress or strain to provide at least two different strain magnitudes or types in two different semiconductor regions. The present invention relates to a technology that enables a combination of process strategies having the potential to form advanced transistor technologies such as transistor devices including gate electrodes.
Thus, different regions within a die region or across a substrate having a plurality of individual die regions individually make their charge carrier mobilities, i.e. their conductivity, suitable for specific process and device requirements. And receiving a differently distorted semiconductor region.
In particular, different types of transistors, such as N-type or N-channel transistors, P-type or P-channel transistors, can receive different types or different magnitudes of distortion within their respective channel regions, if desired. The gate conductivity can be enhanced at the same time by the possibility of forming an inlaid gate electrode structure based on a highly conductive material such as metal.

According to an example embodiment of the present invention, a method includes forming a first placeholder structure on a first semiconductor region formed in a semiconductor layer deposited on a substrate.
The second semiconductor region is formed on the second semiconductor region formed in the semiconductor layer. Then, an insulating layer having a specific inherent stress to surround the first and second placeholder structures. Stack on the semiconductor layer.
Further, the part of the insulating layer surrounding the second placeholder structure is changed to change the inherent stress in the part.
Finally, the first and second placeholder structures are replaced with a conductive material.

According to an example of another embodiment of the present invention, a method forms a first placeholder structure on a first channel region of a first transistor and a second placeholder structure on a second channel region of a second transistor. Forming.
Further, the first drain and source regions are formed adjacent to the first channel region, and the second drain and source regions are formed adjacent to the second channel region.
Furthermore, a first insulating layer having a first intrinsic stress is formed on the first drain and source regions, and a second insulating layer different from the first intrinsic stress is formed on the second drain and source regions. A second insulating layer having an inherent stress is formed.
Finally, the first placeholder structure is replaced with the first gate electrode structure, and the second placeholder structure is replaced with the second gate electrode structure.

According to an example of still another embodiment of the present invention, a semiconductor device includes a first transistor element having a first gate electrode having a first height, and a second gate electrode having a second height. A second transistor element having;
The device further includes a first insulating layer having a first inherent stress and laterally surrounding the first gate electrode. This first intrinsic stress behaves substantially homogeneously within the first insulating layer up to the first height.
Further, the device further includes a second insulating layer having a second intrinsic stress that is different from the first intrinsic stress and laterally surrounding the second gate electrode. This second inherent stress behaves substantially homogeneously within the second insulating layer up to the second height.

The invention may be understood by reference to the detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numerals indicate like elements.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail.
However, the drawings and detailed description are not intended to limit the invention to the particular form disclosed. On the contrary, the invention extends to the spirit and scope of the invention as defined by the appended claims, modifications, equivalents and alternatives.

  An exemplary embodiment of the present invention is described below. For clarity, not all features of an actual product are described in this specification. In developing such real products, a number of implementation-specific decisions are made to meet the system and business-related limitations that change from implementation to implementation to achieve the developer's special purpose. There must be. Moreover, such development efforts can be complex and time consuming, but nonetheless are routine for those skilled in the art who would benefit from this disclosure.

The present invention will be described below with reference to the accompanying drawings.
While various structures, systems and devices are described in the drawings as having a very precise and unambiguous arrangement and distribution, in practice, those skilled in the art will understand that these regions and structures are described in the drawings. Recognize that it is not accurate enough. However, the attached drawings are included to describe and explain one example of embodiments of the present invention. The terms and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those terms and phrases by those skilled in the art. Unless a term or phrase has a special definition (i.e., a definition that is different from the normal, general meaning understood by those of ordinary skill in the art), it will mean by consistent use of the term or phrase herein. As long as the term or phrase has a special meaning (i.e., a meaning other than that understood by one of ordinary skill in the art), such special definitions are specified so that they provide a direct and explicit definition for the term or phrase. Explained in the book.

The present invention provides a material layer in which strain in a semiconductor region, such as a channel region of a transistor element, has a specific intrinsic stress formed proximate to the semiconductor region of interest. It is based on the concept that it can be generated well.
A process strategy that includes multiple die regions, such as in different channel regions of a pair of complementary transistors, allowing for effective local adjustment of strain in very small scale die regions or different substrate regions. By providing advanced distortion technology can be combined with advanced transistor architecture. This provides high gate conductivity along with high charge carrier mobility, and thus channel conductivity, even for highly scaled transistor devices.
With reference to the accompanying drawings, further embodiments of the present invention will be described in more detail.

FIG. 1a is a schematic cross-sectional view of a semiconductor device 100 including a substrate 101, for example, any suitable substrate on which circuit elements of an integrated circuit such as a microprocessor, memory chip, and the like are formed. obtain.
The substrate 101 may represent a bulk semiconductor substrate such as a silicon substrate. Alternatively, in certain embodiments, a silicon-on-insulator (SOI) substrate may be shown. The semiconductor layer 102 may indicate a crystalline silicon layer formed on an insulating layer (not shown) in the substrate 101.
In the following description, the semiconductor layer 102 may often be referred to as silicon because most of the advanced integrated circuits manufactured by MOS technology are manufactured based on silicon. It should be appreciated that other suitable semiconductor materials may also be used in the present invention, such as gallium arsenide, germanium, silicon / germanium, or other III-V or II-VI semiconductor materials.
Similarly, although shown as separate layers, the semiconductor layer 102 may represent the top of the bulk semiconductor substrate.

The semiconductor device 100 includes a first placeholder structure 104a formed from any suitable material such as silicon dioxide, amorphous carbon, and the like.
The first placeholder structure 104a is formed on the first semiconductor region 107a. If a transistor is to be formed by means of the first placeholder structure 104a, the first semiconductor region 107a may represent a first channel region.
The first doped region 106a, which can be arranged symmetrically or asymmetrically with respect to the first semiconductor region 107a, can be formed in the form of drain and source regions in the layer 102 in the illustrated embodiment.
That is, the longitudinal and lateral dopant profiles of the first doped region 106a can be designed according to the device requirements of the particular transistor type.
Thus, in certain embodiments, doped region 106a represents the first drain and source region. This first drain and source region contains a dopant material that provides these regions with a particular type of conductivity.
In this embodiment, the region 106a can be N-doped, and the region 106a connected to the first semiconductor region 107a can have the characteristics of an N-channel transistor.
Further, the sidewall spacer 105a is formed on the sidewall of the first placeholder structure 104a. This sidewall spacer 105a may differ from the material configuration from the first placeholder structure 104a in certain embodiments to exhibit a desired high etch selectivity in a subsequent etching procedure.
For example, the sidewall spacer 105a can be composed of amorphous carbon, silicon nitride, silicon dioxide, and the like.

Similarly, the second placeholder structure 104b may be formed on the second semiconductor region 107b. This second semiconductor region 107b may represent the channel region of the second transistor element in some of the embodiments.
Further, the doped region 106b adjacent to the second semiconductor region 107b can be formed to define a drain and source region and a particular transistor type channel region in certain embodiments.
For example, the second semiconductor region 107b surrounded by the doped region 106b can be located next to the first semiconductor region 107a surrounded by the respective doped region 106a, but is commonly used in advanced semiconductor devices. As such, it can be isolated therefrom by an isolation structure 103 which can be provided in the form of a trench isolation structure.
In the case of showing a transistor structure, the regions 107b and 106b may be the same type as the regions 107a and 106a. Alternatively, different types of transistors such as P-type or P-channel transistors may be shown.
However, the first and second semiconductor regions 107a, 107b are located at very different locations within the same die region, but are required to undergo different types or sizes of strains to provide different electrical characteristics. It is possible to indicate a circuit element to be taken.
Similarly, regions 107a, 107b may represent different circuit elements or different die portions in different substrate regions such as the central region and the peripheral region. The strain technique for the first and second semiconductor regions 107 a and 107 b can provide more uniform electrical behavior of semiconductor devices fabricated on the central and peripheral regions of the substrate 101.
With respect to the material configuration of the sidewall spacer 105b and the second placeholder structure 104b formed on that sidewall, the same criteria apply as described for the corresponding components 104a and 105a.

A typical process flow for forming a semiconductor device 100 as shown in FIG. 1a may include the following processes.
After forming the substrate 101 including the semiconductor layer 102, or after receiving the same from the substrate manufacturer, an implantation process may be performed with specific longitudinal dopants in the first and second semiconductor regions 107a, 107b. Can be executed to form a profile.
Thereafter, the first and second placeholders 104a and 104b can be formed by known deposition, photolithography, and etching techniques. The length of the first and second placeholders 104a and 104b, that is, the lateral dimension (or gate length dimension) of these components in FIG. 1a can be about 100 nm depending on design conditions. It can also be much smaller in highly advanced integrated circuits.
Thereafter, dopant species may be introduced to form doped regions 106a, 106b therein. Depending on device conditions, the device 100 may be masked with, for example, a photoresist mask to form each doped region 106a, 106b with a desired type of dopant material.
During these implantations, the placeholders 104a, 104b serve as implantation masks that substantially avoid dopant penetration into the respective semiconductor regions 107a, 107b.
Thereafter, a corresponding material layer is deposited, and the sidewall spacers 105a and 105b can be formed by anisotropically etching the material layer. In general, it should be appreciated that the liner material may be deposited prior to the spacer material so that the surface of the semiconductor layer 102 is not excessively damaged when exposed to an anisotropic etch atmosphere. For simplicity, the corresponding liner is not shown in FIG.
A further implantation process can then be performed, for example on the photoresist mask. The first and second placeholders 104a and 104b connected to the sidewall spacers 105a and 105b serve as implantation masks for obtaining desired vertical dopant profiles in the doped regions 106a and 106b, respectively.
Thereafter, a corresponding annealing cycle can be performed to activate the dopants in the regions 106a, 106b and to recrystallize the damaged crystal parts. Alternatively, a corresponding annealing process may be performed after the one or more implants.

In some examples, when a highly complex longitudinal dopant profile is required before a further implantation step to obtain a more complex dopant profile in regions 106a, 106b, an additional unillustrated side It should be noted that wall spacers can be formed.
In certain embodiments, the sidewall spacer regions 105a, 105b can then be removed by a selective etching process based on known process recipes.
For example, when the spacers 105a and 105b are made of silicon nitride, they can be selectively removed with hot phosphoric acid.
In other examples, the spacers 105a, 105b can be removed by a plasma etch process. In some embodiments, a liner (not shown) that is typically used as an etch stop layer is left during the implantation cycle and can be used as an etch stop layer during removal of the spacers 105a, 105b.
In other embodiments, spacers 105 a, 105 b can be left during further processing of device 100.

FIG. 1b schematically shows the device 100 in the next manufacturing stage. In this figure, the device 100 includes an insulating layer 108 having a specific inherent stress. This inherent stress is formed so as to surround the first and second placeholders 104a and 104b.
The term “intrinsic stress” is understood as a type of stress, ie tensile or compressive stress, or a deformation thereof, ie as well as magnitude, direction-dependent tensile or compressive stress.
Thus, in one example embodiment, the insulating layer 108 may have an inherent tensile stress having a magnitude of about 0.1 to 1.0 GPa (Giga Pascal).
The insulating layer 108 may be composed of any suitable material such as silicon nitride.
In one example embodiment, device 100 has a conformal etch stop that has a different material configuration compared to insulating layer 108 and has a significantly smaller thickness compared to insulating layer 108. Further included is layer 109. The etching stop layer 109 may be made of, for example, silicon dioxide.

When formed, the etch stop layer 109 can be formed by a known plasma enhanced chemical vapor deposition (PECVD) technique based on a precursor material such as TEOS or silane.
The insulating layer 108 can be formed by PECVD technology based on well-known process recipes.
This process parameter can be adjusted to the desired inherent stress. For example, silicon nitride may be deposited under high compressive or tensile stress. The type and magnitude of this stress can be controlled by controlling process parameters such as deposition temperature, deposition pressure, tool configuration, bias force to adjust ion bombardment during the deposition process, plasma power, and the like. Can be adjusted easily.
For example, assuming that the remaining parameters are the same, increased ion bombardment, i.e., increased bias force, during the deposition of silicon nitride promotes the generation of compressive stress.
In some specific embodiments, the microstructure formed as a result of the deposition of the insulating layer 108 can be planarized, for example, by chemical mechanical polishing (CMP), according to known process recipes.
Thereby, excess material in the insulating layer 108 may be removed to an extent that results in a substantially flat surface, and in certain embodiments, removal of the material may cause the top surfaces of the first and second race holders 104a, 104b to be Can continue until exposed.
However, in other embodiments, further processing can be performed without planarizing the layer 108.

FIG. 1c schematically shows the device 100 in a further manufacturing stage. At this stage, a portion of the layer 108 surrounding the second placeholder 104b has been removed, while the first placeholder 104a is still buried at least laterally by the remaining insulating layer 108 (108a).
In addition, a resist mask 110 is formed on the device 100 to expose the second placeholder 104b and the relevant portion of the layer 102 that includes this layer when an etch stop layer is formed.

The resist mask 110 can be formed by photolithography techniques that can be used to dope the P-type and N-type transistors differently, and the corresponding processes are known.
Thereafter, the insulating layer 108 can be selectively etched by an anisotropic process recipe to finally obtain an insulating layer 108a having a specific inherent stress. If an etch stop layer 109 is formed during the anisotropic etch process, inappropriate material removal and / or damage to exposed portions of the semiconductor layer 102 can be prevented.

FIG. 1d schematically shows the device 100 with a second insulating layer 111 having a second specific intrinsic stress. The second insulating layer 111 covers the insulating layer portion 108a, the second placeholder 104b, and the exposed semiconductor layer 102 or etching stop layer 109.
If it is considered that the anisotropic etching process of the previous insulating layer 108 causes some damage to the exposed portion of the etching stopper layer 109, the exposed portion of the etching stopper layer 109 is deposited before the second insulating layer 111 is deposited. Note that may be removed.
In this case, an additional etch stop layer similar to layer 109 can be deposited. Thereafter, the etch stop layer may also cover the insulating layer portion 108a (shown in dashed lines) and cover the exposed portions of the semiconductor layer 102 and the second placeholder 104b.
For convenience, this portion of the etch stop layer is shown as 109. Providing the etch stop layer 109 on the semiconductor layer 102 can be advantageous for forming contact openings in later manufacturing steps.
However, in other embodiments, the etch stop layer 109 may be omitted.

The second insulating layer 111, which can be composed of any suitable material, such as silicon nitride, can be deposited by known deposition recipes, and its process parameters provide the desired inherent stress depending on device requirements. To be controlled.
As noted above, silicon nitride can be easily deposited based on known process recipes with a wide range of compressive and tensile stresses, for example, ranging from 1.0 GPa compressive stress to 1.0 GPa tensile stress. .
In an example of a particular embodiment, when the second semiconductor region 107b represents a channel region of a P-type transistor, the inherent stress of the second insulating layer 111 causes a compressive stress in the second semiconductor region 107b. It is formed.
Thereafter, as shown in FIGS. 1c and 1d, if the insulating layer 108 is not planarized or if the first placeholder 104a is planar enough, the insulating layer 111 and possibly the layer portion 108a The excess material is removed by the CMP process, which further planarizes the device 100 microstructure.

FIG. 1e schematically shows the device 100 after the process sequence described above. Thus, the device 100 includes a substantially flat microstructure with a layer portion 108a surrounding the first placeholder 104a in the lateral direction and a second layer portion 111b surrounding the second placeholder 104b in the lateral direction.
Thus, the inherent stress that behaves substantially homogeneously in the layer portion 108a, illustrated as tensile stress shown as 118a, is deformed or strained in the first semiconductor region 107a, respectively, i.e., tensile strain in this example. Generate. This tensile strain generally increases the mobility of electrons in this region.
Similarly, a layer portion 111b having a second inherent stress that behaves substantially homogeneously, shown as compressive stress 121b in the present embodiment, is similarly deformed or deformed in the second semiconductor region 107b. Generate distortion. This deformation or distortion is compressive distortion in the present embodiment, which increases hole mobility.
Other configurations may be employed to generate different strains in the semiconductor regions 107a, 107b. For example, the intrinsic stress 118a may be a compressive stress and the intrinsic stress 121b may be a tensile stress. Alternatively, both intrinsic stresses 118a and 121b may be compressive or tensile, or may differ in the magnitude of these stresses.
In other examples, the intrinsic stress 118a or 121b may be selected such that the strain in each semiconductor region is substantially zero while the other semiconductor regions receive the desired amount of strain. .
While this configuration does not degrade the performance quality of the N-type transistor, the mobility of the P-type transistor will be increased, making the electrical characteristics of the P-type and N-type transistors more constant. Can be advantageous in terms.

  FIG. 1f schematically shows the device 100 with the placeholders 104a, 104b removed. Further, gate insulating films 113a and 113b are formed on the first and second semiconductor regions 107a and 107b, respectively.

The removal of the placeholders 104a and 104b can be performed by a selective etching process. This process may include a plasma etch process and / or a wet chemical etch process.
For example, when the placeholders 104a and 104b are made of silicon dioxide or amorphous carbon and the layer portions 108a and 111b are made of, for example, silicon nitride, the layer portions 108a and 111b can be easily and selectively etched. The materials of the first and second semiconductor regions 107a and 107b can be easily and selectively etched based on a known process recipe.
For example, the remaining portions of the first and second placeholders 104a, 104b can then be removed by a highly isotropic or wet chemical etching process so that the regions 107a, 107b are not significantly damaged. The process may include a plasma etch process that selectively removes a substantial amount of these first and second placeholders 104a, 104b.
In other embodiments, in addition or alternatively, damaged surface portions of regions 107a, 107b may be oxidized, for example, by thermal oxidation or wet chemical oxidation. Also, the oxidized portion can be removed by a wet chemical etching process with high selectivity based on, for example, fluoric acid (HF) that does not significantly damage the regions 107a and 107b.

After removing the placeholders 104a and 104b, the gate insulating films 113a and 113b can be formed by oxidation and / or vapor deposition according to the design conditions.
For example, the gate insulating films 113a, 113b may be formed by thermal or wet chemical oxidation according to known recipes to obtain a highly tuned layer thickness as required in advanced transistor devices. it can. Thereby, the thickness of the gate insulating film can be in the range of 1.5 to several nanometers.
In other embodiments, an ultra-thin thermal oxide may be formed and then deposited with a suitable insulating material so that the gate insulating films 113a, 113b are finally at the desired thickness. The corresponding stacked layer is shown in dashed lines and is illustrated as 112. The gate insulating films 113a and 113b may also be formed only by the stacked layers 112.
In some examples of embodiments, if the initial length 112a of the opening defined by the placeholder 104a is considered too large for the desired value of the gate electrode to be formed, Prior to forming 113a, 113b, an insulating layer such as layer 112 can be deposited in a manner that is very conformal and accurately defines the thickness of the layer.
Thereafter, as used in typical sidewall spacer technology, the material deposited on the bottom of this opening, ie, region 107a, can be similarly removed by an anisotropic etching process.
In this way, the gate length of the transistor structure can be fine-tuned to compensate for photolithography variations or to increase photolithography resolution. Thereafter, as described above, each gate insulating film can be formed.

FIG. 1g shows a semiconductor device 100 having a layer of conductive material 123 formed over the structure of FIG. 1f.
Layer 123 may be comprised of doped polysilicon or, in very advanced semiconductor device embodiments, may comprise a metal or metal compound. For example, the layer 123 may include tungsten, tungsten silicide, aluminum, nickel, copper, or a compound thereof, and the like.
Depending on the type of material used for layer 123, a corresponding deposition technique may be used. For example, polysilicon, aluminum, tungsten, tungsten silicide and the like can be easily deposited by known chemical vapor deposition (CVD) techniques.
In other cases, a plating method such as plating or electroless plating can be used to reliably fill the respective openings on the first and second semiconductor regions 107a, 107b.
Thereafter, the excess material of layer 123 can be removed by any suitable technique, such as etching, chemical mechanical polishing, and combinations thereof.

FIG. 1 h shows the semiconductor device 100 with the excess material of the layer 123 removed and an interlayer dielectric 126 further formed as an upper layer of the resulting structure.
Accordingly, the device 100 includes a gate electrode structure 124a on the first semiconductor region 107a and a second gate electrode structure 124b on the second semiconductor region 107b. Thus, the first transistor element 130a and the second transistor element 130b are defined.
Further, as shown in FIG. 1h, the layer portion 108a provides a first inherent stress 118a that acts substantially homogeneously on the gate electrode structure 124a up to a height 125a. On the other hand, the second layer portion 111b provides a second inherent stress 121b that acts substantially homogeneously on the second gate electrode structure 124b up to a height 125b.
Therefore, the stresses 118a and 121b cause deformations or distortions in the associated semiconductor region or channel region 107a and 107b, respectively.
Thus, the charge carrier mobility in these channel regions can be individually adjusted by controlling the stresses 118a and 121b, respectively.
The transistor configuration as shown in FIG. 1h is particularly flat and allows a self-aligned configuration of doped regions 106a, 106b, ie, the respective drain and source regions for the associated gate electrode structures 124a, 124b.
Further, the gate electrode structures 124a, 124b may be formed of a highly conductive material such as a metal, metal compound, highly doped polysilicon, or combinations thereof, and the like.
In certain embodiments, the gate electrode structures 124a, 124b are substantially composed of metal.

FIG. 2 schematically illustrates a semiconductor device 200 in an intermediate stage of manufacture, according to an example of a further embodiment of the present invention.
In FIG. 2, components that are the same as or similar to those in FIGS. 1d and 1e are indicated by the same reference numerals except that they use the 200s instead of the 100s.
Thus, the device 200 includes a substrate 201 having a semiconductor layer 202 formed thereon including first and second semiconductor regions 207a, 207b with associated doped regions 206a, 206b.
The placeholders 204a and 204b are embedded in the vertical direction in the insulating layer 208 having a specific inherent stress.
Further, a resist mask 210 is formed on the insulating layer 208 so as to expose a part of the device 200 related to the second semiconductor region 207b.
Regarding the formation of the device 200 as shown in FIG. 2, reference is made to the description in FIGS. 1a, 1b and 1c.

Further, the device 200 is exposed to ion bombardment 240 to alter the stress characteristics of the layer portion 208b of the insulating layer 208 not covered by the resist mask 210.
For example, heavy inert ions, such as xenon, argon, silicon, and the like, can be implanted into the layer portion 208b. This at least partially relieves certain inherent stresses.
Accordingly, a specific inherent stress is maintained in the layer portion 208a. Thereby, a specific deformation is generated in the first semiconductor region 207a. On the other hand, the corresponding strain in the second semiconductor region 207b may differ significantly from that of the layer portion 208a depending on the degree of relaxation in the layer portion 208b.
For example, if the regions 206a and 207a indicate a P-type transistor configuration, the insulating layer 208 may be deposited with a high compressive stress, for example, to significantly improve the hole mobility in the first semiconductor region 207a. .
By reducing the initial compressive stress in the layer portion 208b to a certain degree, the amount of decrease in electron mobility in the second semiconductor region 207b can be adjusted according to design requirements when designed as an n-type channel region. it can.
As already described above, the first and second semiconductor regions 207a and 207b do not necessarily need to indicate different types of channel regions, but can also represent the same channel region. For example, different degrees of processing operations or a desired degree to adjust device uniformity can be achieved by process technology as shown in FIG.

  Thereafter, further processing of the device 200 may be continued as further described for the device 100 described in FIGS. 1e-1h.

FIG. 3a schematically illustrates a semiconductor device 300 according to an example of a further embodiment of the present invention.
Since device 300 may represent a device similar to the device described in FIG. 1e, the same or similar components are indicated by the same reference numerals except using the 300s instead of the 100s. Therefore, details of these components are omitted here.
Furthermore, the device 300 is exposed to an ion implantation 350 to insert light ionic species such as hydrogen, helium or oxygen into the semiconductor layer 302 or substrate 301.
The ion implantation 350 is performed with a high dose and an appropriate amount of energy so that a desired depth in the layer 302 and / or the substrate 301 has a high impurity concentration. For example, the initially implanted peak concentration can be selected to achieve a concentration in the range of about 10 ²¹ to 10 ²³ atoms / cm ³ .
Typical implantation parameters for helium or hydrogen can be about 3 to 15 kev, depending on the desired permeability with a dose of 5 × 10 ⁵ to 2 × 10 ¹⁶ ions / cm ² .
Thereafter, the heat treatment can be performed at a temperature of about 350 to 1000 ° C., for example. The heat treatment is typically performed at a temperature of about 700-950 ° C. for a few minutes to create “bubbles” or “voids” 351 in the layer 302 and / or the substrate 301.
Since the ion implantation 350 is performed through the layer portions 308a, 311b with the placeholders 304a, 304b still present, the depth of the bubbles 351 can be substantially constant.
Since light inert species are introduced, the stopping mechanism during implantation is mainly based on interaction with crystal electrons so that damage, i.e. stress relaxation, in layers 308a, 311b can be neglected.
Due to the bubbles 351, some mechanical separation of the remaining layers 302 and / or regions 306a, 307a, 306b, 307b from the substrate 301 is achieved, thereby allowing the layer portions 308a, 311b to enter each region 307a, 307b. Significantly improves the transfer of stress.
Therefore, the distortion technique of the regions 307a and 307b can be significantly improved. Therefore, charge carrier mobility and channel conductivity can be improved more efficiently.

In other embodiments, the ion implantation 350 can be performed in an initial manufacturing stage, such as before forming the layer portions 308a, 311b or before forming the placeholders 304a, 304b. This avoids any mitigation effects, as described above, for example, even if they are very small.
Thereafter, bubbles 351 may be generated during an annealing cycle that activates the dopants in regions 306a, 306b.

FIG. 3 b schematically illustrates the semiconductor device 300 with the placeholders 304 a, 304 b removed prior to the ion implantation 350.
In this case, the implantation energy can be selected so that light ion species are located in the semiconductor layer 302 without substantially affecting the regions 306a and 306b. Therefore, the semiconductor regions 307 a and 307 b can be efficiently separated from the remaining semiconductor layer 302 by the bubbles 351.
Therefore, the stress moved to the regions 307a and 307b is also significantly increased.
Furthermore, the bubbles 351 themselves serve as a source of stress, thereby further generating a corresponding distortion in each region 307a, 307b.
In this way, two effective strain introduction mechanisms can be combined.

As a result, the present invention can form a flat transistor structure including a highly conductive gate electrode by this formation process,
Provided are semiconductor devices in which different semiconductor regions can be subjected to different strains, and techniques for forming the semiconductor devices.
For this purpose, the insulating layer laterally surrounding the gate electrode structure of the plurality of transistor elements is partly modified so that at least two different strain components are obtained in the respective channel regions.
Therefore, complementary transistors to be paired can be formed so that each transistor has a channel region having a different strain.
Changing the strain-inducing stress layer is accomplished by removing a specific portion of the layer and replacing it with a layer portion of a different inherent stress and / or by relaxing the inherent stress to the desired extent. be able to.
Furthermore, a combination of advanced stress or strain techniques with a process for in-laid gate electrode structures can result in a highly conductive gate electrode structure. This provides high gate and channel conductivity, even for very scaled devices with 100 nm or much shorter gate lengths.
In addition, altering the partial stress is advantageously combined with a mechanism to effectively decouple the channel region from the surrounding material, thereby significantly increasing the efficiency of stress transmission in each channel region. To rise.

  The specific embodiments shown above are for illustrative purposes only and can be implemented with modification in a different but equivalent manner to those skilled in the art having the benefit of the teachings described herein. Is clear. For example, the process procedures described above may be performed in a different order. Furthermore, nothing else described in the appended claims is intended to limit the invention to the details of construction or design shown herein. Thus, the particular embodiments described above can be substituted or modified and all such variations are considered within the spirit and scope of the invention. Accordingly, the protection required in this application is set forth in the appended claims.

In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that enables the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. In accordance with a process strategy that allows the formation of an integrated gate electrode structure, each stress layer formed near the semiconductor region produces different strains in different semiconductor regions, resulting in different manufacturing stages of semiconductor devices. FIG. FIG. 6 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing stage in which the inherent stress of the stress layer is partially altered according to an example of a further embodiment. FIG. 4 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing stage in which ionic species are deposited at predetermined locations to enhance stress transmission to the respective semiconductor regions, according to an example of a further embodiment of the present invention. FIG. 4 is a cross-sectional view schematically illustrating a semiconductor device during a manufacturing stage in which ionic species are deposited at predetermined locations to enhance stress transmission to the respective semiconductor regions, according to an example of a further embodiment of the present invention.

Claims (12)

Forming a first placeholder structure (104a) on a first semiconductor region (107a) formed in a semiconductor layer (102) deposited on a substrate (101);
Forming a second placeholder structure (104b) on the second semiconductor region (107b) formed in the semiconductor layer (102);
An insulating layer (108) having a specific intrinsic stress is deposited on the semiconductor layer (102) so as to surround the first placeholder structure (104a) and the second placeholder structure (104b);
Changing a portion of the insulating layer (108) surrounding the second placeholder structure (104b) to change the inherent stress of the portion;
Replacing the first placeholder structure (104a) and the second placeholder structure (104b) with a conductive material;
Method.   The method of claim 1, further comprising forming doped regions (106a) (106b) in the semiconductor layer (102) adjacent to the first semiconductor region (107a) and the second semiconductor region (107b).   The doped region (106a) (106b) is formed by using the first placeholder structure (104a) and the second placeholder structure (104b) as an implantation mask, while at least one dopant is formed by an ion implantation process. The method of claim 2, wherein the seed is introduced. Formation of the doped regions (106a) (106b)
Forming at least one sidewall spacer element on each sidewall of the first placeholder structure (104a) and the second placeholder structure (104b);
4. The method of claim 3, comprising using the at least one sidewall spacer as an implantation mask during at least one step of the ion implantation process.   The method of claim 5, further comprising removing the at least one sidewall spacer prior to depositing the insulating layer (108).   The method of claim 1, wherein the modification of the portion surrounding the second placeholder structure (104b) comprises removing the portion.   The method of claim 7, further comprising depositing a second insulating layer (126) on the semiconductor layer (102) having a second intrinsic stress different from the intrinsic stress of the insulating layer (108).   The method of claim 8, further comprising removing material of the second insulating layer (126) to expose an upper surface of the second placeholder structure (104b).   The method of claim 7, wherein the surface of the second insulating layer (126) is planarized prior to removing the portion surrounding the second placeholder structure (104b).   The method of claim 1, wherein the modification of the portion surrounding the second placeholder structure (104b) selectively relieves the inherent stress in the portion.   The method of claim 10, wherein the intrinsic stress is selectively relaxed by the partial ion bombardment. Further, an inert species is implanted into a region adjacent to at least one of the first semiconductor region (107a) and the second semiconductor region (107b),
The method of claim 1, wherein the substrate is heat treated to form voids due to the inert species.

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