JP2008300385A - Wiring structure, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure where an inter-wiring capacity is reduced while keeping a mechanical strength or breakdown voltage of an interlayer insulation film, in an interlayer insulation film including a low permittivity insulating material. <P>SOLUTION: In this wiring structure where a wiring layer is embedded in an interlayer insulation film, the interlayer adjoining to a wiring layer has a three-layer structure consisting of a diffusion prevention film, a porous insulation film and a cap film, and the cap film is made of SiOC or SiO<SB>2</SB>. The method of manufacturing the wiring structure includes an etching step to selectively etch a first cap film and a step to form a second cap film made of SiOC or SiO<SB>2</SB>to cover the upper surface of a semiconductor substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring structure and a manufacturing method thereof, and more particularly to a wiring structure having a reduced inter-wiring capacitance and a manufacturing method thereof.

  As the semiconductor device is miniaturized, the pitch of the wiring layer is reduced, and a delay in signal response speed due to an increase in capacitance between adjacent wirings becomes a problem. On the other hand, in a fine structure having a technology node of about 65 nm, a porous low dielectric constant (Low-k) film made of, for example, SiOC is used as an interlayer insulating film in order to reduce the capacitance between adjacent wirings. In such a fine structure, a Cu diffusion prevention film made of SiC, a low dielectric constant (Low-k) insulation film made of porous SiOC, and a cap film made of SiCO (k is about 3. 5) is formed, and a wiring layer made of a barrier metal made of TiN and a metal layer made of Cu is provided in the hole provided in the laminated structure.

In such a fine structure, the interlayer insulating film between adjacent wirings has a three-layer structure of Cu diffusion preventing film / low dielectric constant insulating film / cap film. Further, in order to reduce the capacitance between wirings, a low dielectric constant It is necessary to make the insulating film more porous (low density).
SMJang et al., Prov. VLSI, pp.18 (2002)

However, if the low dielectric constant insulating film is made more porous, the mechanical strength and withstand voltage of the low dielectric constant insulating film are lowered, so that there is a limit to the reduction in inter-wiring capacitance due to the porous structure.
On the other hand, when the inventor examined, in such an interlayer insulating film having a three-layer structure of Cu diffusion preventing film / low dielectric constant insulating film / cap film, the fringe capacitance of the Cu diffusion preventing film and the cap film ( It was found that the capacitance of the end portion of the wiring layer capacitively coupled to the adjacent wiring layer through the Cu diffusion prevention film and the cap film was large. For this reason, it was found that the inter-wiring capacitance can be reduced by reducing the fringe capacitance instead of making the low dielectric constant insulating film porous, and the present invention has been completed.

  That is, an object of the present invention is to provide a wiring structure in which an interlayer insulating film containing a low dielectric constant insulating material has a reduced inter-wiring capacitance while maintaining the mechanical strength and breakdown voltage of the interlayer insulating film.

The present invention is a wiring structure in which a wiring layer is embedded in an interlayer insulating film, and the interlayer insulating film adjacent to the wiring layer has a three-layer structure of a diffusion prevention film, a porous insulating film, and a cap film, The wiring structure is characterized in that the film is made of SiOC or SiO ₂ .

The present invention also includes a step of forming an insulating film on a semiconductor substrate, a step of sequentially forming a diffusion barrier film, a porous insulating film, and a first cap film made of SiOC or SiO _{2 on the} insulating film. A step of forming a hole from the first cap film through the porous insulating film to the diffusion preventing film, a barrier metal layer is formed on the semiconductor substrate, and a wiring metal layer is formed so as to fill the hole Etching the wiring metal layer and the barrier metal layer from above until the first cap film is exposed to reduce the film thickness, leaving the barrier metal layer and the wiring metal layer to be embedded in the opening. this include the steps of the wiring layers, an etching step of selectively etching the first cap layer, so as to cover the upper surface of the semiconductor substrate, and forming a second cap layer made of SiOC or SiO ₂ Te It is also a method for manufacturing a wiring structure according to claim.

  According to the present invention, it is possible to provide a wiring structure that prevents a delay in signal response speed while maintaining the mechanical strength and breakdown voltage of an interlayer insulating film.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, “top”, “bottom”, “left”, “right” and names including these terms are used as appropriate, but these directions make it easy to understand the invention with reference to the drawings. Therefore, a mode in which the embodiment is inverted upside down or rotated in an arbitrary direction is naturally included in the technical scope of the present invention.

  FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, indicated as a whole by 100. The semiconductor device 100 includes a semiconductor element 10 such as a transistor. The semiconductor element 10 includes a silicon substrate 1, and a gate electrode 3 made of, for example, aluminum is provided on the silicon substrate 1 via a gate insulating film 2 made of, for example, silicon oxide. On the side wall of the gate electrode 3, a side wall 4 made of, for example, silicon oxide is provided. A source / drain region 5 is provided on the silicon substrate 1 so as to sandwich the gate electrode 3. The semiconductor element 10 is covered with an interlayer insulating film 11 made of, for example, silicon oxide.

  On the interlayer insulating film 11, a diffusion preventing film 12 made of, for example, SiC is provided. In addition to SiC, SiCO, SiCN, SiN, or the like can be used for the diffusion prevention film 12, and the dielectric constant k is about 3.2 to 8.0 and the film thickness is about 25 nm.

  On the diffusion preventing film 12, a low dielectric constant (low-k) insulating film (porous insulating film) 13 made of, for example, porous SiOC is provided. The low dielectric constant insulating film 13 has a dielectric constant of about 2.7 or less and a film thickness of about 100 to 150 nm. Porous SiOC forms a large number of bubbles in the SiOC material and has a dielectric constant close to that of air (k = 1). The dielectric constant can be adjusted by the amount of bubbles introduced.

  A hole 20 is provided in the diffusion preventing film 12 and the low dielectric constant insulating film 13 so that the surface of the interlayer insulating film 11 is exposed. In the hole 20, a barrier metal layer 21 made of Ta, for example, and a metal layer 22 made of Cu, for example, are provided. A wiring layer 25 is formed from the barrier metal layer 21 and the metal layer 22. For the barrier metal layer 21, TaN, Ti, TiN or the like may be used in addition to Ta. The upper end of the wiring layer 25 composed of the barrier metal layer 21 and the metal layer 22 protrudes from the surface of the low dielectric constant insulating film 13 by, for example, about 10 nm.

  A cap film 30 made of SiC and also serving as a diffusion prevention film is provided so as to cover the low dielectric constant insulating film 13 and the wiring layer 25. The cap film 30 is formed so as to cover the side surface and the upper surface of the wiring layer 25.

Thus, in the semiconductor device 100 according to the present embodiment, the cap film 30 made of, for example, SiO ₂ or SiOC is provided between the wiring layers 25 on the low dielectric constant insulating film 13, and the dielectric constant thereof. Is about 2.8 to 4.0, preferably about 2.8 to 3.0.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and the semiconductor element 10 formed below the interlayer insulating film 11 is omitted. This manufacturing method includes the following steps 1 to 7.

Step 1: As shown in FIG. 2A, an interlayer insulating film 11 made of, for example, silicon oxide is deposited on a semiconductor element (not shown) using a CVD method.
Subsequently, for example, a diffusion preventing film 12 made of SiC and a low dielectric constant insulating film 13 made of porous SiOC are sequentially formed. For the formation of the diffusion preventing film 12 and the low dielectric constant insulating film 13, for example, a CVD method such as a PE-CVD (Plasma Enhanced-CVD) method is used.
Further, a cap insulating film (first cap film) 14 made of, for example, SiO ₂ or SiOC is formed on the low dielectric constant insulating film 13 by a CVD method. A wiring metal 15 such as aluminum is formed on the cap insulating film 14, and a resist mask 16 is further formed. Then, the wiring metal 15 is patterned using the resist mask 16.

  Step 2: As shown in FIG. 2B, the cap insulating film 14, the low dielectric constant insulating film 13, and the diffusion preventing film 12 are etched using the resist mask 16 obtained by patterning the wiring metal 15, and the hole 20 is formed. Form. Etching is performed by dry etching, for example, and the diffusion prevention film 12 whose etching rate is slower than that of the low dielectric constant insulating film 13 serves as an etching stopper layer. Etching is performed until the surface of the interlayer insulating film 11 is exposed.

Step 3: As shown in FIG. 2C, the resist mask 16 and unnecessary wiring metal 15 are removed by plasma ashing using a H ₂ / He mixed gas. In such an ashing process, since the surface of the low dielectric constant insulating film 13 is covered with the cap insulating film 14, the low dielectric constant insulating film 13 is not damaged.

  Step 4: As shown in FIG. 2D, after forming a barrier metal layer 21 made of Ti, for example, so as to cover the entire surface, a metal wiring layer 22 made of Cu, for example, is formed so as to fill the hole 20. To do. A sputtering method or a vapor deposition method is used for forming the barrier metal layer 21 and the metal wiring layer 22.

  Step 5: As shown in FIG. 2E, the barrier metal layer 21 and the metal wiring layer 22 are polished and removed from the upper surface by using the CMP method, and the barrier metal layer 21 and the metal wiring are embedded in the hole 20. Leave layer 22. The polishing removal process ends with the cap insulating film 14 remaining on the low dielectric constant insulating film 13. This can prevent the low dielectric constant insulating film 13 from being damaged in the polishing removal step.

Step 6: As shown in FIG. 2F, the cap insulating film 14 is selectively removed by dry etching using, for example, a CF-based gas such as CF ₄ or CCl ₂ F ₂ . In the etching process of the cap insulating film 14, the surface of the underlying low dielectric constant insulating film 13 is also etched, but the etching amount is small and is 100 nm or less. The height of the wiring layer 25 protruding above the surface of the low dielectric constant insulating film 13 is at least 10 nm.

Step 7: As shown in FIG. 2G, after the surface of the low dielectric constant insulating film 13 is treated with NH ₃ plasma, a cap film (second cap film) made of SiO ₂ or SiOC using, for example, a CVD method. 30 is formed. The cap film 30 also functions as a diffusion preventing layer that prevents Cu elements from diffusing and moving from the wiring metal layer 22 made of Cu, for example.

  Through the above steps, the semiconductor device 100 according to the present embodiment as shown in FIG. 1 is completed.

  FIG. 3 is a cross-sectional photograph of the semiconductor device 100 according to the present embodiment, and is a cross-section corresponding to FIG. FIG. 4 is a cross-sectional photograph of a semiconductor device having a conventional structure in which the interlayer insulating film has a three-layer structure of Cu diffusion prevention film / low dielectric constant insulating film / SiCO cap film in order from the bottom.

  FIG. 5 shows a wiring layer of the semiconductor device 100 according to the present embodiment and a semiconductor device having a conventional structure (interlayer insulating film having a three-layer structure of Cu diffusion preventing film / low dielectric constant insulating film / SiCO cap film in order from the bottom). The wiring resistance of the wiring layer is shown. In FIG. 5, the horizontal axis represents the sheet resistance of the wiring layer, the vertical axis represents the cumulative probability, and the semiconductor device 100 according to the present embodiment is represented by a circle, and the semiconductor device 100 according to the present embodiment is represented by a triangle. Both the width (L) of the wiring layer and the spacing (S) between the wiring layers are 100 nm.

  From FIG. 5, it can be seen that also in the semiconductor device 100, the sheet resistance of the wiring layer 20 substantially matches that of the semiconductor device having the conventional structure.

  FIG. 6 is a comparison of the wiring capacitance between the wiring layer of the semiconductor device 100 according to the present embodiment and the wiring layer of the semiconductor device having the conventional structure. In FIG. 6, the horizontal axis represents the reciprocal of the wiring interval, the vertical axis represents the inter-wiring capacitance, the semiconductor device 100 according to the present embodiment is represented by a circle, and the semiconductor device 100 according to the present embodiment is represented by a triangle. As can be seen from FIG. 6, the inter-wiring capacitance can be reduced by employing the structure according to this embodiment. That is, the fringe at the upper end portion of the wiring layer is obtained by removing the SiCO cap film (k = 3.5) of the conventional structure and replacing it with a cap film 30 made of SiC (k = 2.8 to 3.0). As a result, the capacitance between the wirings can be reduced.

  In particular, as can be seen from FIG. 5, since the sheet resistance of the wiring layer does not change, it can be seen that the reduction of the inter-wiring capacitance is caused by the reduction of the fringe capacitance.

  FIG. 7 shows the wiring layer of the semiconductor device 100 according to the present embodiment regarding the value of the integrated value (R × C) of the wiring resistance (R) and inter-wiring capacitance (C) that determines the delay of the signal response speed. The comparison of the wiring layer of the semiconductor device of a conventional structure is shown. In FIG. 7, the horizontal axis indicates the integrated value (R × C), the vertical axis indicates the cumulative probability, the symbol ○ indicates the semiconductor device of the conventional structure, and Δ indicates the semiconductor device 100 according to the present embodiment. . Both the width (L) of the wiring layer and the spacing (S) between the wiring layers are 100 nm.

  As can be seen from FIG. 7, in the semiconductor device 100 according to the present embodiment, the integrated value (R × C) is smaller than that of the conventional semiconductor device. As a result, a delay in signal response speed can be reduced.

As described above, in the semiconductor device 100 according to the present embodiment, the inter-wiring capacitance can be reduced as compared with the semiconductor device having the conventional structure, and thereby the delay of the signal response speed can be reduced. . This is because, at the upper end of the wiring layer, the interlayer insulating film sandwiched between the wiring layers is made of a material having a low dielectric constant instead of SiCO having a conventional structure, thereby reducing the fringe capacitance.
In particular, since the electric field concentrates on the upper end portion of the wiring layer, the capacitance between wirings can be greatly reduced by reducing the dielectric constant of this portion.

It is sectional drawing of the semiconductor device concerning embodiment of this invention. It is sectional drawing of the manufacturing process of the semiconductor device concerning embodiment of this invention. It is a cross-sectional photograph of the semiconductor device concerning embodiment of this invention. It is a cross-sectional photograph of a semiconductor device having a conventional structure. It is a comparison of wiring resistance. This is a comparison of capacitance between wirings. This is a comparison of the integrated value (R × C) of the wiring resistance (R) and the capacitance between wirings (C).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2 Gate insulating film, 3 Gate electrode, 4 Side wall, 5 Source / drain region, 10 Semiconductor element, 11 Interlayer insulating film, 12 Diffusion prevention film, 13 Low dielectric constant insulating film, 20 Hole part, 21 Barrier Metal layer, 22 Metal wiring layer, 30 Cap film, 100 Semiconductor device.

Claims (7)

A wiring structure in which a wiring layer is embedded in an interlayer insulating film,
The interlayer insulating film adjacent to the wiring layer has a three-layer structure of a diffusion prevention film, a porous insulating film, and a cap film,
A wiring structure in which the cap film is made of SiOC or SiO ₂ .   The wiring structure according to claim 1, wherein the cap film also serves as a diffusion prevention film covering the wiring layer.   The wiring structure according to claim 1 or 2, wherein a height of the wiring layer protruding upward from the upper surface of the porous insulating film is 10 nm or more.   The wiring structure according to claim 1, wherein the porous insulating film is made of porous SiOC, and the diffusion prevention film is made of SiC, SiCN, or SiN. Forming an insulating film on the semiconductor substrate;
Sequentially forming a diffusion barrier film, a porous insulating film, and a first cap film made of SiOC or SiO _{2 on the} insulating film;
Forming a hole from the first cap film through the porous insulating film to the diffusion preventing film;
Forming a barrier metal layer on the semiconductor substrate and further forming a wiring metal layer so as to fill the hole;
The wiring metal layer and the barrier metal layer are etched from above until the first cap film is exposed to reduce the film thickness, leaving the barrier metal layer and the wiring metal layer so as to be embedded in the opening. A layering process;
An etching step of selectively etching the first cap film;
Forming a second cap film made of SiOC or SiO ₂ so as to cover the upper surface of the semiconductor substrate.   6. The method for manufacturing a wiring structure according to claim 5, wherein the etching step is a step of selectively removing the first cap film by dry etching using a CF-based gas.   6. The etching step is a step of selectively etching the first cap film on the porous insulating film while suppressing an etching amount of the porous insulating film to 100 nm or less. Or the manufacturing method of the wiring structure of 6.