JP2008294751A - A/d conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion circuit which detects an accurate offset error to be corrected even when a reverse polarity offset occurs for a power supply voltage. <P>SOLUTION: This A/D conversion circuit 1 has input terminals IN<SB>1</SB>, ..., IN<SB>n-1</SB>respectively to input input voltages V<SB>1</SB>, ..., V<SB>n-1</SB>, a reference voltage input portion 3 which generates a reference voltage V<SB>ref</SB>to be obtained by dividing a reference voltage V<SB>0</SB>by a partial pressure resistance, a multiplexer 4 which inputs the input voltages V<SB>1</SB>, ..., V<SB>n-1</SB>and the reference voltages V<SB>0</SB>and V<SB>ref</SB>and selects any one of the voltage signals to be outputted, and a signal processor 9 which A/D converts the voltage signal outputted by the multiplexer 4 to generate a digital value. The signal processor 9 calculates an offset error based on a ratio between the digital value and the partial pressure resistance obtained based on the reference voltages V<SB>0</SB>and V<SB>ref</SB>, and then corrects the digital value corresponding to the input voltages V<SB>1</SB>, ..., V<SB>n-1</SB>based on the offset error. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an A / D conversion circuit that converts an input voltage into a digital value.

  Conventionally, a control microcomputer (hereinafter referred to as “microcomputer”) or the like has an A / D converter for analog / digital conversion of an input analog voltage. As this type of A / D converter, as described in Non-Patent Document 1 below, an input analog voltage having a magnitude between two reference voltages is converted from analog to digital, and the reference voltage is set appropriately. Thus, there is known an A / D converter that can compensate for a negative offset. This microcomputer incorporates one to several 8-bit to 12-bit A / D converters, and a plurality of analog inputs are selectively input to the A / D converter via a multiplexer. Thus, the analog input is converted into a digital value. The A / D converter converts an analog signal between the ground voltage and the maximum input voltage into a digital value with the resolution of the A / D converter. Since the maximum input voltage is generally fixed, a variable gain amplifier is built in after the multiplexer. By changing the gain of this variable gain amplifier, the resolution of each analog signal can be efficiently reduced. The input intensity of the A / D converter is adjusted so that it can be exhibited.

Further, Patent Document 1 below calculates a correction value from data of a ground level signal and a reference voltage signal converted by an A / D converter when analog / digital conversion of an analog input signal input to a selector is performed. An A / D conversion circuit that performs error correction using the correction value is disclosed.
JP 2005-244771 A “MSP430x4xx Family User's Guide, Mixed Signal Products SLAU056F”, Texas Instruments, 2006

  Since the conventional A / D converter described above rarely supplies a negative power source as the entire control microcomputer, it is difficult to correct the offset error in the negative direction as a result. In the A / D conversion circuit described in Patent Document 1, it is difficult to accurately detect an offset error from a ground level signal when operating with a single power source. In other words, offset errors include positive and negative offsets, but when a single power supply is used as a reference, an offset opposite to the polarity of the power supply voltage cannot be detected. For example, when operating with a positive power supply, even if a negative offset exists, the output value of the A / D converter connected to the ground can output only “0” regardless of the magnitude of the offset. Conversely, when operating with a negative power supply, even if a positive offset exists, the output value of the A / D converter connected to the ground can output only “0” regardless of the magnitude of the offset. .

  Therefore, the present invention has been made in view of such problems, and an A / D conversion circuit capable of detecting and correcting an accurate offset error even when an offset having a reverse polarity with respect to a power supply voltage has occurred. The purpose is to provide.

  In order to solve the above problems, an A / D conversion circuit according to the present invention includes first to Nth input terminals for inputting first to Nth input voltages (N is an integer of 2 or more), and an Nth A reference voltage input unit that divides the input voltage by a voltage dividing resistor to generate a first reference voltage, and the first to Nth input voltages and the first to Nth input voltages are input. And a selection circuit that selects and outputs one of the first reference voltages, and a signal processing unit that performs analog / digital conversion on the first to Nth input voltages and the first reference voltage output by the selection circuit. The signal processing unit calculates an offset error based on a digital value obtained based on the Nth input voltage and the first reference voltage and a ratio of the voltage dividing resistor, and the first to first based on the offset error. The digital value corresponding to the (N-1) th input voltage is corrected.

  According to such an A / D converter circuit, the first to Nth input voltages and the Nth input voltage from the first to Nth input terminals are divided by a known resistor in the selection circuit. After the reference voltage is input and any one of these voltages is selectively output to the signal processing unit, the voltage is converted into a digital value by the signal processing unit. At this time, the signal processing unit performs an offset error based on the result of analog / digital conversion of the Nth input voltage having the same polarity as the power supply voltage and the first reference voltage and the voltage division ratio of the first reference voltage. And the digital value for the first to (N-1) th input voltages is corrected by the offset error, so that the offset error in the A / D converter can be accurately determined even if an offset having a polarity opposite to that of the power supply voltage occurs. The digital value can be corrected by detection.

  A reference voltage generation unit that generates a second reference voltage and inputs the second reference voltage to the Nth input terminal is further provided, and the signal processing unit gains based on the second reference voltage and the ratio of the voltage dividing resistor It is preferable to further calculate an error and correct a digital value corresponding to the first to (N-1) th input voltages based on the gain error and the offset error.

  In this case, when the second reference voltage, which is a known voltage, is input to the selection circuit via the Nth input terminal, the second reference voltage and the second reference voltage are resisted by a known resistor to the signal processing unit. The divided first reference voltage is selectively input. Then, the signal processing unit first calculates the offset error and the gain error based on the second reference voltage value and the result of analog / digital conversion of the second reference voltage and the first reference voltage. Since the digital value with respect to the input voltage of N-1 is corrected, the digital value can be accurately derived even if a gain error occurs in the A / D converter.

  According to the A / D conversion circuit of the present invention, an accurate offset error can be detected and corrected even when an offset having a reverse polarity occurs with respect to the power supply voltage.

  Hereinafter, preferred embodiments of an A / D conversion circuit according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an A / D conversion circuit 1 according to the first embodiment of the present invention. The A / D conversion circuit 1 shown in the figure is built in a control microcomputer (hereinafter referred to as “microcomputer”), a personal computer, or the like, detects the magnitude of a voltage input from the outside, and detects the magnitude of the voltage. This is a circuit for generating a digital value indicating the above. The A / D conversion circuit 1 includes N (N is an integer of 2 or more) input terminals IN _{1 to} IN _n , a reference voltage generation unit 2, a reference voltage input unit 3, a multiplexer (selection circuit) 4, An A / D converter 5, a CPU (central processing unit) 6, a memory 7, and a signal processing unit 9 including a communication unit 8 are provided.

Input terminal _IN 1, ..., the _{IN n-1,} respectively, the input voltage _V 1 of the plurality of types of analog voltage value from the outside, _{..., V n-1} is input, the input terminal _IN 1, ..., IN _{n -1} input port CH1 of the multiplexer 4, ..., by being connected to CHn-1, input to the multiplexer 4 voltage _{V 1, ..., V n-} 1 is input. The reference voltage generator 2 is connected to the input terminal IN _n, and a known reference voltage (second reference voltage) V ₀ is generated by the reference voltage generator 2 and input to the input terminal IN _n . By connecting the input terminal IN _n to the input port CHn of the multiplexer 4, the reference voltage V ₀ is also input to the multiplexer 4.

The reference voltage input unit 3 includes two voltage _dividing resistors 10a and 10b connected in series between the input terminal INn and the ground. By input port CHn + 1 multiplexer 4 is connected to the connection point between the voltage dividing resistors 10a and voltage dividing resistors 10b, a reference voltage V ₀ dividing resistors 10a, criteria by resistance-dividing by 10b A voltage (first reference voltage) V _ref is input to the multiplexer 4 together.

The multiplexer 4 has a function of selecting any one of the input voltages V ₁ ,..., V _n−1 and the reference voltages V ₀ , V _ref and outputting the selected voltage to the A / D converter 5 of the signal processing unit 9. This is a selection circuit. The multiplexer 4 selectively outputs a voltage signal to the A / D converter 5 in accordance with a control signal from the CPU 6 of the signal processing unit 9.

The A / D converter 5 detects the analog voltage value of any one of the input signals V ₁ ,..., V _n−1 and the reference voltages V ₀ , V _ref output from the multiplexer 4, The digital value is generated by analog / digital conversion (AD conversion) of the voltage value, and the digital value is output to the CPU 6. For example, the A / D converter 5 converts a voltage value having a magnitude from the ground voltage to a predetermined maximum input voltage into a digital value with a resolution corresponding to the maximum number of bits that can be processed. Since an offset error and a gain error generally occur in the A / D converter 5, the A / D converter 5 generates based on the input voltage V _k (k is an integer between 1 and n−1). The digital value V _{ADk thus obtained} is _expressed by the following formula (1);
V _ADk = (1 + A) × V _k + B (1)
Given by. Here, A is a gain error in the A / D converter 5, and B is an offset error in the A / D converter 5.

The CPU 6 performs a process of correcting the digital value V _ADk output from the A / D converter 5 and stores the corrected digital value V _ADk in the memory 7. This digital value V _ADk is used for subsequent processing in a microcomputer or the like incorporating the A / D conversion circuit 1. Further, the CPU 6 can also transmit the corrected digital value V _ADk to the outside via the communication unit 8. Hereinafter, the correction function by the CPU 6 will be described in detail.

First, the CPU 6 switches and controls the multiplexer 4 to sequentially output the reference voltages V ₀ and V _ref from the output of the multiplexer 4, and the A / D converter 5 performs AD conversion of the reference voltages V ₀ and V _ref. The digital values V _AD0 and V _ADref corresponding to the respective voltage values are acquired. The digital values V _AD0 and V _ADref obtained at this time are expressed by the following equations (2) and (3) based on the equation (1).
V _AD0 = (1 + A) × V ₀ + B (2)
V _ADref = (1 + A) × V _ref + B (3)
Here, when the known resistance values of the voltage dividing resistors 10a and 10b are R ₁ and R ₂ , the relationship between the reference voltage V ₀ and the reference voltage V _ref is expressed by the following formula (4);
V _ref = R ₁ / (R ₁ + R ₂ ) × V ₀ (4)
Represented by

Therefore, the CPU 6 sets the gain error A to the following equation (5) based on the relationship of equations (2), (3), and (4).
A = {(R1 + R2) / R2} × {(V _AD0 −V _ADref ) / V ₀ } −1 (5)
Can be calculated. At this time, the resistance values R ₁ and R ₂ and the voltage value V ₀ are stored in the memory 7 in advance, and the CPU 6 determines the voltage dividing resistance ratio R ₁ / R ₂ and the voltage value specified from the values read from the memory 7. A gain error A is calculated based on V ₀ and the digital values V _AD0 and V _ADref output from the A / D converter 5. The memory 7 may store the voltage dividing resistance ratio R ₁ / R ₂ instead of the resistance values R ₁ and R ₂ .

Further, the CPU 6 calculates the offset error B based on the relationship between the equations (2) and (5) as the following equation (6);
B = {(R1 + R2) / R2} × V _{ADref −R1} / R2 × V _AD0 (6)
Calculated by That is, the CPU 6 determines the offset error B based on the voltage _dividing resistance ratio R ₁ / R ₂ specified from the value read from the memory 7 and the digital values V _AD0 and V _ADref output from the A / D converter 5. Is calculated.

The CPU 6 stores the gain error A and the offset error B calculated as described above in the memory 7 as calibration information, and then sequentially controls the multiplexer 4 to switch the input voltages V _{1 to} V _n−1 to A. The A / D converter 5 performs AD conversion on the input voltages V _{1 to} V _n−1 . Further, the CPU 6 _reads the digital values V _ADk (k = 1,..., N−1) corresponding to the input voltages V ₁ ,..., V _n−1 output from the A / D converter 5 from the memory 7. Using the calibration information obtained, the following formula (7);
AV _ADk = V _ADk / (1 + A) −B (7)
To obtain a correction value AV _ADk . This correction value AV _ADk is obtained as a value in which the offset and gain of the multiplexer 4 and the A / D converter 5 are compensated. The CPU 6 stores the calculated correction value AV _ADk in the memory 7.

Here, the significance of the correction processing executed by the CPU 6 will be described. Generally, the relationship between the input voltage V _k and the digital value V _ADk after AD conversion is as shown in FIG. 2 when the offset error is D _off . Become. AD conversion characteristics if an ideal AD conversion performed is expressed by the relationship of the straight line G ₁ passing through the origin. However, since there is actually a plus or minus offset in the digital value V _ADk , the AD conversion characteristic is a characteristic like the straight lines G ₂ and G ₃ , and the actual input analog value is _calculated from the digital value after AD conversion. It is necessary to correct this offset when calculating. At this time, assuming that two digital values V _AD0 and V _ADref are obtained by converting two analog values of two known voltage values V ₀ and V _ref , an offset B is calculated using these digital values. can do. When the analog value V _k is converted to obtain the digital value V _ADk , the true digital value is given by V _ADk -B.

It is preferable that the voltage division ratio between the voltage dividing resistor 10a and the voltage dividing resistor 10b in the reference voltage input unit 3 is set so that V _ref is approximately _½ × V ₀ . It is not preferable to set V _ref to a value close to the ground potential because the influence of the quantization error on V _ref increases. This is because the reference voltage V ₀ is set to a value close to the full scale of the A / D converter 5, and the reference voltage V _ref is set to about half of that, thereby calculating the correction line in FIG. This is because the influence of the conversion error can be reduced.

According to the A / D converter circuit 1 described above, the multiplexer 4 input terminals _IN 1, ..., input voltages _V 1 from IN _{n, ...,} and _{V n-1} and the reference voltage _{V 0,} the reference voltage _{V 0} A reference voltage V _ref divided by a known resistor is input, and one of those voltages is selectively output to the signal processing unit 9, and then the A / D converter 5 converts these voltages. Converted to a digital value. At this time, the CPU 6 calculates an offset error based on the result of AD conversion of the reference voltages V ₀ and V _ref having a finite value having the same polarity as the power supply voltage and the voltage division ratio of the reference voltage V _ref , and the offset Since the digital value with respect to the input voltages V ₁ ,..., V _n−1 is corrected by the error, the offset value in the A / D converter 5 is accurately detected even if an offset having a polarity opposite to that of the power supply voltage is generated. Can be corrected.

A reference voltage V _0, which is a known voltage, is input to the multiplexer 4 via the input terminal IN _n , and the reference voltage V ₀ and the reference voltage V ₀ are resistance-divided by a known resistor into the signal processing unit 9. The reference voltage V _ref is selectively input, and after the CPU 6 calculates the offset error and the gain error based on the reference voltage value V ₀ and the result of AD conversion of the reference voltages V ₀ and V _ref , the input voltage Since the digital values for V ₁ ,..., V _n−1 are corrected, the digital values can be accurately derived even if a gain error occurs in the A / D converter 5.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  FIG. 3 is a block diagram showing the configuration of the A / D conversion circuit 101 according to the second embodiment of the present invention. The A / D conversion circuit 101 according to the second embodiment is different from the first embodiment in that it does not include the reference voltage generation unit 2 (see FIG. 1) and does not calculate a gain error in the correction function in the signal processing unit 109. Is different. The configuration of the A / D conversion circuit 101 is a configuration that can be adopted when it is assumed that the gain error in the A / D converter 5 is sufficiently small.

Specifically, the input terminal _IN 1, ..., the IN _n, respectively, the input voltage _V 1 of the plurality of types of voltage values from external, ..., _{V n} are input, the input terminal _IN 1, ..., IN _n There input port CH1 of the multiplexer 4, ..., by being connected to CHn, input to the multiplexer 4 voltage _V 1, ..., _{V n} are input. Further, the input port CHn + 1 of the multiplexer 4 is connected to the connection point between the voltage _dividing resistor 10a and the voltage _dividing resistor 10b of the reference voltage input unit 3, so that the input voltage Vn is divided by the voltage _dividing resistors 10a and 10b. A resistance-divided reference voltage (first reference voltage) V _ref is input to the multiplexer 4 together. The multiplexer 4 converts an analog voltage signal of the input voltages V ₁ ,..., V _n and the reference voltage V _ref input from the input ports CH 1,..., CHn + 1 into an A / D converter 5 of the signal processing unit 109. Selectively output to.

The A / D converter 5 AD converts the input voltages V ₁ ,..., V _n and the reference voltage V _ref to generate digital values V _AD1 ,..., V _ADn, V _ADref and outputs them to the CPU 106. On the other hand, the CPU 106 corrects the digital values V _AD1 ,..., V _ADn as follows.

That is, the CPU 106 first controls the multiplexer 4 to sequentially output the input voltage V _n and the reference voltage V _ref from the multiplexer 4, and the A / D converter 5 converts the input voltage V _n and the reference voltage V _ref to AD. By _{performing the conversion} , digital values V _ADn and V _ADref corresponding to the respective voltage values are obtained. The digital values V _ADn and V _ADref obtained at this time are expressed by the following equations (8) and (9).
V _ADn = V _n + B (8)
V _ADref = V _ref + B (9)
Here, when the known resistance values of the voltage _dividing resistors 10a and 10b are R ₁ and R ₂ , the relationship between the input voltage V _n and the reference voltage V _ref is expressed by the following formula (10);
V _ref = R ₁ / (R ₁ + R ₂ ) × V _n (10)
Represented by

Therefore, the CPU 106 sets the offset error B to the following formula (11) based on the relationship of formulas (8), (9), and (10).
B = {(R1 + R2) / R2} × V _{ADref −R1} / R2 × V _ADn (11)
Calculated by That is, the CPU 106 determines the offset error B based on the voltage _dividing resistance ratio R ₁ / R ₂ specified from the value read from the memory 7 and the digital values V _ADn and V _ADref output from the A / D converter 5. Is calculated.

The CPU 106 stores the offset error B calculated as described above in the memory 7 as calibration information, and then the digital values corresponding to the input voltages V ₁ ,..., V _n output from the A / D converter 5. V _ADk (k = 1,..., N) is obtained by using the calibration information read from the memory 7, and the following equation (12);
AV _ADk = V _ADk -B (12)
To obtain a correction value AV _ADk .

  Even with the A / D conversion circuit 101 described above, it is possible to accurately detect the offset error in the A / D converter 5 and correct the digital value even if an offset having a polarity opposite to that of the power supply voltage occurs. In particular, in the A / D conversion circuit 101, the circuit configuration is further simplified because the reference voltage generator is not necessary.

1 is a block diagram showing a configuration of an A / D conversion circuit according to a first embodiment of the present invention. It is a graph which shows the AD conversion characteristic in the A / D converter of FIG. It is a block diagram which shows the structure of the A / D conversion circuit concerning 2nd Embodiment of this invention.

Explanation of symbols

IN ₁ ,..., IN _n ... Input terminal, ₁ , 101... A / D converter circuit, 2... Reference voltage generator, 3. , 9, 109... Signal processing unit, 10a, 10b, voltage dividing resistors.

Claims (2)

First to Nth input terminals for inputting first to Nth input voltages (N is an integer of 2 or more), and
A reference voltage input unit that divides the Nth input voltage by a voltage dividing resistor to generate a first reference voltage;
A selection circuit that receives the first to Nth input voltages and the first reference voltage, and selects and outputs one of the first to Nth input voltages and the first reference voltage;
A signal processing unit that performs analog / digital conversion on the first to Nth input voltages and the first reference voltage output by the selection circuit;
The signal processing unit calculates an offset error based on a ratio between the digital value obtained based on the Nth input voltage and the first reference voltage and the voltage dividing resistor, and based on the offset error Correcting digital values corresponding to the first to (N-1) th input voltages;
An A / D conversion circuit characterized by the above. A reference voltage generator for generating a second reference voltage and inputting the second reference voltage to the Nth input terminal;
The signal processing unit further calculates a gain error based on the second reference voltage and a ratio of the voltage dividing resistor, and based on the gain error and the offset error, Correcting the digital value corresponding to the input voltage;
The A / D conversion circuit according to claim 1.

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