JP2008251925A - Diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: a reverse recovering time trr is large due to minority carriers injected into an n-type semiconductor layer in application of forward voltage in a pn-junction diode, and a leak current becomes large in Schottky contact in a Schottky barrier diode. <P>SOLUTION: A plurality of island-like p-type semiconductor regions separated from each other are provided on a first main surface of a substrate. A first opening is provided on a first insulating film covering the top of an n<SP>-</SP>-type semiconductor layer, and a first metal layer is formed thereon. The p-type semiconductor region of the operation region contacts the first metal layer via the first opening, and works as pn-junction diode. Since a Schottky contact region does not exist, leak current can be reduced. The separated p-type semiconductor region can suppress disappearance of electrons on an anode side, and a conductivity modulation effect can be improved. Further, the second metal layer can selectively brought into contact with a second main surface of the substrate by the second insulating film provided on the second main surface of the substrate, so that the second opening, and the conductivity modulation effect can be improved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a diode, and more particularly to a diode that realizes reduction of leakage current and increase in switching time.

  As typical structures of diodes, pn junction diodes and Schottky barrier diodes are known.

  FIG. 13 shows a cross-sectional view of the pn junction diode 110.

  The pn junction diode 110 includes a p-type impurity region 113 formed by diffusing a high-concentration p-type impurity into the operation region OR on the surface of the substrate SB ′ in which the n− type semiconductor layer 112 is stacked on the n + type silicon semiconductor substrate 111 and A guard ring 117 is provided. An anode electrode 118 is provided on the insulating film 115 provided on the surface of the substrate SB ′, and the anode electrode 118 is in contact with the p-type impurity region 113 through one opening OP ′ of the insulating film 115. A cathode electrode 119 is provided on the entire back surface of the n + -type silicon semiconductor substrate 111 (see, for example, Patent Document 1).

  FIG. 14 is a cross-sectional view showing a conventional Schottky barrier diode 120.

  The substrate SB ′ is obtained by stacking an n− semiconductor layer 122 on an n + type semiconductor substrate 121. The operation region OR of the n − type semiconductor layer 122 is provided with a plurality of p + type impurity regions 123 formed of a plurality of high concentration p type impurities, and an opening OP ′ is formed on the surface of the n − type semiconductor layer 122. An insulating film 125 is provided, and a metal layer 126 that forms a Schottky junction with the n − type semiconductor layer 122 is provided through the opening OP ′. This metal layer 126 is, for example, Ti. Further, an Al layer that serves as the anode electrode 128 is provided to cover the entire surface of the metal layer 126. A guard ring 127 in which high-concentration P-type impurities are diffused is provided on the outer periphery of the semiconductor substrate SB ′, and a part thereof contacts the metal layer 126. A cathode electrode 129 is provided on the back surface of the substrate SB ′.

When a reverse bias is applied to this diode (hereinafter referred to as JBS: Junction Barrier Schottky Diode) 120, depletion layer 50 spreads from p + -type impurity region 123 to n − -type semiconductor layer 122 as shown in FIG. By providing a separation distance between adjacent p + -type impurity regions 123 that is equal to or less than the width at which the depletion layer 50 is pinched off, even if a leak current is generated at the Schottky junction when a reverse bias is applied, the depletion layer 50 can block it. is there. That is, as the characteristic of the metal layer 126, one having a low forward voltage characteristic can be selected without much considering the leakage current characteristic (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 10-335679 (page 20, FIG. 37) JP 2000-261004 A (page 2-4, FIGS. 1, 3)

  As shown in FIG. 13, the pn junction diode 110 generally has a high reverse breakdown voltage and is therefore often used for high withstand voltage applications. However, the forward voltage VF characteristic is also high, resulting in a large power consumption. .

  Further, the pn junction diode 110 has a problem that the switching characteristics deteriorate due to an increase in switching time and an increase in reverse recovery loss.

  That is, when a forward voltage is applied, holes that are minority carriers are injected from the p-type impurity region into the n − -type semiconductor layer. When a reverse voltage is applied in this state, the current cannot be interrupted unless minority carriers accumulated in the n − type semiconductor layer 122 are extracted or recombined. That is, the time required for pulling out or recombining minority carriers (reverse recovery time trr) increases, which causes deterioration of switching characteristics due to an increase in switching time and an increase in reverse recovery loss.

  In order to solve this problem, there is known a method of doping so-called lifetime killer into the n − -type semiconductor layer 112, but the forward voltage characteristics are deteriorated due to an increase in resistance even if the heavy metal is doped too much. There was a problem to do.

  As a method of shortening the reverse recovery time trr, it is conceivable to reduce the impurity concentration in the p-type impurity region and reduce the amount of holes injected into the n − -type semiconductor layer 122 serving as the drift layer.

  However, when the impurity concentration of the p-type impurity region is reduced, the amount of carriers (holes) accumulated in the n − -type semiconductor layer 122 is naturally reduced, leading to a decrease in the conductivity modulation effect. Therefore, there is a problem that the forward voltage VF near the rated current increases.

  On the other hand, a Schottky barrier diode generally has a low forward voltage characteristic and a short switching time (reverse recovery time trr). However, since the n − type semiconductor layer and the metal layer form a Schottky junction, there is a problem of high leakage current at the Schottky junction interface.

  Therefore, the JBS 120 as shown in FIG. 14 is employed, and even when a leak current is generated at the Schottky junction interface, the depletion layer 50 is cut off by using the pinch-off to reduce the leak current.

  However, even though this method is theoretically possible, it is actually difficult to completely cut off the leakage current path only by the depletion layer 50. Although the depletion layer 50 is generated by voltage application, for example, in the JBS 120 having a withstand voltage of about 40 V, the depletion layer 50 may not sufficiently spread as designed because the n− type semiconductor layer 122 has a low specific resistance. In the structure of FIG. 14, if there is a region where the depletion layer 50 is not sufficiently spread even at one place and cannot be pinched off, it is impossible to suppress the leakage current.

  The JBS 120 also has a problem that the switching time increases. For example, when the JBS 120 is operated with a forward voltage VF exceeding about 0.6 V, minority carriers (holes) are likely to be injected from the p + type semiconductor region 123 into the n − type semiconductor layer 122.

  When a reverse voltage is applied in this state, as in the case of the pn junction diode 110, the minority carriers accumulated in the n − type semiconductor layer 122 are extracted or recombined, and then the depletion layer is formed in the n − type semiconductor layer 122. 50 spreads. In other words, the JBS 120 also has a problem that the reverse recovery time trr is increased and the switching time is increased and the switching characteristics are deteriorated.

  The present invention has been made in view of the above problems. First, a substrate in which a one-conductivity-type semiconductor layer is stacked on a high-concentration one-conductivity-type semiconductor substrate, and a plurality of the one-conductivity-type semiconductor layers provided separately from each other A reverse conductivity type semiconductor region, an insulating film provided on one main surface of the substrate, an opening provided in the insulating film and exposing the reverse conductivity type semiconductor region, and provided on the insulating film, This is solved by including a metal layer that contacts the reverse conductivity type semiconductor region through the opening.

  Second, a substrate in which a one-conductivity-type semiconductor layer is stacked on a high-concentration one-conductivity-type semiconductor substrate, a plurality of opposite-conductivity-type semiconductor regions provided on the one-conductivity-type semiconductor layer and spaced apart from each other, A first insulating film provided on the first main surface; a first opening provided in the first insulating film through which the reverse conductivity type semiconductor region is exposed; provided on the first insulating film; A first metal layer in contact with the reverse conductivity type semiconductor region through the opening; a second insulating film provided on the second main surface of the substrate; and a plurality of selectively provided on the second insulating film And a second metal layer that covers the second insulating film and contacts the second main surface via the second opening.

  According to the present embodiment, first, a plurality of separated p-type semiconductor regions are provided on the first main surface of the substrate, and the first opening is provided in the first insulating film provided on the first main surface. By adopting a structure in which only the semiconductor region is exposed and the first metal layer (surface electrode) is provided, there is no region that forms a Schottky junction with the n − type semiconductor layer in the operation region, and leakage current can be reduced. .

  Second, since the p-type semiconductor region of the operation region is a region separated into a plurality of regions, the reverse recovery time trr can be reduced as compared with the conventional pn junction diode in which the p-type impurity region is formed on the entire surface shown in FIG. Can do. In the present embodiment, the metal layer forms an ohmic junction with the p-type semiconductor region in the operation region, and functions as a pn junction diode. However, compared with a pn junction diode (see FIG. 13) in which a p-type semiconductor region is formed on the entire surface of the operation region, the total volume of the p-type semiconductor region is reduced to reduce the amount of charge. For this reason, the injection of minority carriers (holes) into the n − type semiconductor layer during forward voltage application can be reduced. That is, when reverse voltage is applied, the time for hole extraction and recombination is shortened, and the reverse recovery time trr can be shortened.

  Third, since the annihilation of electrons on the anode side is reduced as compared with the conventional pn junction diode, the amount of electrons involved in the conductivity modulation increases, the conductivity modulation effect can be enhanced, and the forward voltage characteristics Can be improved.

  Fourth, a second opening is provided in the second insulating film covering the second main surface of the substrate, and the second metal layer (back electrode) provided on the second insulating film is in contact with the second main surface of the substrate. By doing so, the contact area of the second metal layer can be reduced. Thereby, the accumulation effect of minority carriers (holes) can be increased in the vicinity of the second main surface of the substrate.

  If the charge amount of the p-type impurity region of the diode is reduced in order to reduce the reverse recovery time trr, there is a problem that the conductivity modulation effect is reduced. In this embodiment, the charge amount of the p-type impurity region is reduced. Even in such a case, the conductivity modulation effect can be increased in the vicinity of the second main surface, so that an increase in the forward voltage VF at a certain current point can be prevented.

  Fifth, due to the accumulation of minority carriers in the vicinity of the second metal layer by setting the total contact (opening) area of the second metal layer to about 35% to 80% of the area of the second main surface of the semiconductor substrate. The effect of reducing the forward voltage VF can exceed the increase in resistance due to the narrowing of the current path. Therefore, the forward voltage VF can be reduced in the vicinity of the rated current where the forward voltage VF has increased in the conventional structure.

  Sixth, the plurality of openings have a regular hexagonal uniform pattern and are spaced at an equal distance from each other, so that the carriers can be drawn uniformly without concentrating on one place, and the drift current can be reduced. The path can be made uniform.

Embodiments of the present invention will be described in detail with reference to FIGS.

  First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows the diode of this embodiment. FIGS. 1A and 1B are plan views of the first main surface Sf1 of the diode 100, and FIG. 1C is a cross-sectional view taken along the line aa in FIGS. FIG. 1A is a diagram in which the metal layer on the diode surface is omitted, and FIG. 1B is a diagram illustrating a pattern of the metal layer and the insulating film.

  The diode 100 according to the first embodiment includes a one-conductivity-type semiconductor substrate 1, a one-conductivity-type semiconductor layer 2, a reverse-conductivity-type semiconductor region 3, a first insulating film 5, a first opening OP1, And a metal layer 7.

  Referring to FIGS. 1A and 1C, a substrate SB is formed by laminating an n− type semiconductor layer 2 on a high concentration one conductivity type (hereinafter n + type) silicon semiconductor substrate 1. The n − type semiconductor layer 2 is, for example, an epitaxial layer.

  A plurality of reverse conductivity type semiconductor regions 3 are provided on the surface of the n − type semiconductor layer 2 to be the first main surface Sf1 of the substrate SB. The reverse conductivity type semiconductor region 3 is a region in which, for example, a trench 10 is formed in the n − type semiconductor layer 2 and a polysilicon layer into which a high-concentration p-type impurity is introduced is buried in the trench 10. 3 is called.

  A large number of trenches 10 are provided in the n − type semiconductor layer 2 so as to be separated from each other by an equal predetermined distance. The distance d1 between the trenches 10 is, for example, about 1 μm to 10 μm. As will be described in detail later, the p-type semiconductor regions 3 adjacent to each other need to be arranged at equal intervals, and a regular hexagonal shape is desirable in the pattern of the first main surface of the substrate SB as shown in FIG. In the case of a regular hexagon, the opening width (diagonal width) d2 of the trench 10 is, for example, 10 μm.

  Polysilicon doped with high-concentration p-type impurities is buried in these trenches 10, thereby providing a plurality of p-type semiconductor regions 3 separated by an equal distance d <b> 1.

  The p-type semiconductor region 3 is not limited to the structure in which polysilicon is buried in the trench 10, but the n− type semiconductor layer 2 is preferably formed in the above pattern and spaced apart from each other at equal distances by high-concentration p-type impurities. It may be a region in which is diffused. However, in order to accurately form the pattern on the first main surface Sf1 at each distance d1 of the p-type semiconductor region 3, a configuration in which polysilicon is embedded in the trench 10 is suitable. It explains using.

  Around the entire p-type semiconductor region 3, another p-type (p + -type) semiconductor region 4 is provided in a ring shape on the outside. The other p + type semiconductor region 4 is a guard ring 4 provided to ensure a withstand voltage when a reverse voltage is applied to the diode 100. Similarly to the p-type semiconductor region 3, the guard ring 4 is a region where polysilicon doped with high-concentration p-type impurities is buried in the trench, or a region where high-concentration p-type impurities are diffused in the n − -type semiconductor layer 2. It is.

  In this embodiment, the region inside the guard ring 4 is referred to as an operation region OR as a region mainly functioning as the diode 100.

  A high concentration n-type impurity region 9 that suppresses the spread of the depletion layer is provided outside the guard ring 4. A shield metal 13 is provided on the n-type impurity region 9 in contact with the n-type impurity region 9.

  Referring to FIG. 1C, a first insulating film 5 is provided on the first main surface Sf1 of the substrate SB (n− type semiconductor layer 2). The first insulating film 5 is, for example, an oxide film having a plurality of first openings OP1. The first openings OP1 are all provided in the operation region OR in the pattern of the first main surface Sf1 shown in FIG. The first insulating film 5 is provided with another opening OP1 'from which a part of the guard ring 4 is exposed.

  The first opening OP1 is provided in the same pattern as all the p-type semiconductor regions 3 in the operation region OR. That is, only the p-type semiconductor region 3 is exposed from the first opening OP 1, and the n − -type semiconductor layer 2 in the operation region OR is covered with the first insulating film 5. The depth of the p-type impurity region 3 is shallower than the guard ring 4. A part of the guard ring 4 is exposed from the other opening OP1 '.

  1B and 1C, the first metal layer 7 is provided on the first insulating film 5 and is in contact with the p-type semiconductor region 3 through the first opening OP1. The first metal layer 7 is an aluminum (Al) layer, for example, and forms an ohmic junction only with the p-type semiconductor region 3. That is, the diode 100 functions as a pn junction diode, and the first metal layer 7 becomes the anode electrode A.

  A second metal layer 8 to be the cathode electrode CA of the diode 100 is provided on the second main surface Sf2 (the surface of the n + type silicon semiconductor substrate 1) of the substrate SB.

  Thus, in the diode 100 of this embodiment, there is no Schottky junction region in the operation region OR. Therefore, when compared with the conventional JBS 120 shown in FIG. 14 with the same chip size, the leakage current generated at the Schottky junction interface can be reduced by the absence of the Schottky junction area.

  Further, the reverse recovery time trr can be shortened as compared with the conventional pn junction diode shown in FIG.

  Hereinafter, further description will be given with reference to FIG. 2 is an enlarged cross-sectional view showing an outline of the operation region OR shown in FIG. 1. FIG. 2 (A) shows a state where a forward voltage is applied, and FIG. 2 (B) shows a reverse direction from application of the forward voltage. FIG. 2C shows a state in which a reverse voltage is applied. In FIG. 2, the guard ring is omitted.

  As shown in FIG. 2A, when a forward voltage is applied between the anode electrode A and the cathode electrode CA in the on state, minority carriers (holes) are injected from the p-type semiconductor region 3 into the n − -type semiconductor layer 2. , The conductivity of the n − type semiconductor layer 2 (drift layer) is modulated, the diode 100 is conducted, and the current I flows between the anode electrode A and the cathode electrode CA.

  The pn junction diode 100 is a conductivity modulation element, and holes are injected from the p-type semiconductor region 3 into the n − -type semiconductor layer 2. At this time, for example, when compared with the conventional pn junction diode 110 shown in FIG. 13 as the same chip size, in the present embodiment, the p-type semiconductor region 3 is formed into a plurality of islands separated from each other, whereby 3 is smaller, and the amount of charge is smaller than that of the conventional p-type impurity region 113. Therefore, the amount of minority carriers (holes) injected into the n − type semiconductor layer 2 can be reduced as compared with the conventional pn junction diode 110.

  Since the contact area of the anode electrode A is small, the disappearance of electrons from the electrode is reduced, that is, the disappearance of electrons on the anode side (the first main surface Sf1 side of the substrate SB) can be reduced. Therefore, the conductivity modulation effect becomes more effective, and the forward voltage VF can be made substantially equal as compared with the conventional pn junction diode.

  Thereafter, in order to turn off the diode 100 as shown in FIG. 2B, when switching from forward voltage application to reverse voltage application, minority carriers accumulated in the n − type semiconductor layer 2 were extracted or recombined. Later, the depletion layer spreads.

  Here, as described above, since the charge amount of the p-type semiconductor region 3 is smaller than that of the conventional pn junction diode 110 in the present embodiment, minority carriers accumulated in the n − -type semiconductor layer 2 when a forward voltage is applied. The amount of is also reduced. Accordingly, it is possible to shorten the time for extracting or recombining minority carriers (reverse recovery time: trr).

  Thereby, compared with the conventional pn junction diode 110 (FIG. 13), the reverse recovery time trr can be reduced, which can contribute to the reduction of switching time and the improvement of switching characteristics due to the reduction of reverse recovery loss.

  Next, with reference to FIG. 2C, by applying a reverse voltage, minority carriers disappear, and the depletion layer 50 spreads in the n − type semiconductor layer 2 to block the current.

  Here, the shape of the p-type semiconductor region 3 needs to be arranged at equal distances from each other so that the depletion layer 10 spreads out evenly when the reverse voltage is applied and the epitaxial layer 2 can be completely filled. The hexagonal shape is optimal.

  In addition, when a certain distance between the p-type semiconductor regions 3 can be secured, a diffusion region in which p-type impurities are ion-implanted into the epitaxial layer 2 using a mask having a regular hexagonal shape may be used. However, when the separation distance is small, the impurity diffusion region cannot be expanded in the lateral direction. Therefore, it is preferable to use the p-type semiconductor region 3 in which the polysilicon 32 is embedded in the trench 10.

  In the present embodiment, the charge amount of impurities in the p-type semiconductor region 3 is 1 to 2 times the charge amount of impurities in the n − -type semiconductor layer 2.

  FIG. 3 is a diagram showing the dependence of the charge ratio (p / n charge ratio) between the p-type impurity and the n-type impurity on the forward voltage VF and the reverse voltage VR. 3A shows the case of the forward voltage VF, and FIG. 3B shows the case of the reverse voltage VR. Each vertical axis represents voltage, and the horizontal axis represents the p / n charge ratio. For the p / n charge ratio, the forward voltage VF and the reverse voltage VR were measured by changing the charge ratio between the p-type semiconductor region 3 and the n − -type semiconductor layer 2 in the structure of the present embodiment shown in FIG.

More specifically, the charge amount of the n − type semiconductor layer 2 was fixed, and the p / n charge ratio was changed by changing the depth of the p type semiconductor region 3. Further, the impurity concentration of two types (5E15 cm ⁻³ , 1E16 cm ⁻³ ) of the p-type semiconductor region 3 was measured.

  According to this, the forward voltage VF is not a primary dependency, and the forward voltage VF hardly changes even if a certain amount or more of holes exist in the p layer. That is, from FIG. 3A, when the p / n charge ratio is 0.5 to 2, the forward voltage VF hardly changes. Further, the reverse voltage VR is a stable region of the reverse voltage VR when the p / n charge ratio is 1 or more. From this result, the charge amount of the impurity in the p-type semiconductor region 3 of the present embodiment is set to 1 to 2 times the charge amount of the impurity in the n − type semiconductor layer 2.

  FIG. 4 is a diagram comparing the leakage current characteristics of the diode 100 (solid line) of the present embodiment and the conventional JBS 120 (broken line) shown in FIG. The vertical axis is the reverse current (leakage current) IR, and the horizontal axis is the reverse voltage VR.

  As described above, in this embodiment, since the area of the Schottky junction region is small, the leak current can be significantly reduced if the chip size is the same, and good leak current characteristics can be obtained.

  Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is different from the first embodiment in the structure of the second metal layer provided on the second main surface of the substrate SB. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The diode 105 of the second embodiment includes a one-conductivity-type semiconductor substrate 1, a one-conductivity-type semiconductor layer 2, a reverse-conductivity-type semiconductor region 3, a first insulating film 5, a first opening OP1, The metal layer 7, the second insulating film 11, the second opening OP <b> 2, and the second metal layer 12 are configured.

  5 and 6 are diagrams showing the diode 105 according to the second embodiment. FIG. 5 is a cross-sectional view of the diode 105, and FIG. 6A is a plan view of the second insulating film 11 on the second main surface Sf2. FIG. 6B is a plan view in which the second metal layer 12 on the second main surface Sf2 side is provided. 5 is a cross-sectional view taken along the line bb of FIG. The configuration on the first main surface Sf1 side is the same as that of the first embodiment (FIGS. 1A and 1B).

  With reference to FIG. 5 and FIG. 6A, the second insulating film 11 is provided on the entire surface on the second main surface Sf2 side of the substrate SB. The second insulating film 11 is, for example, an oxide film, and a plurality of second openings OP2 are selectively provided.

  Each of the second openings OP2 has an equal shape (size) and is spaced from the center of the second opening OP2 by an equal distance. As a result, the separation distance d3 (FIG. 6A) between the second openings OP2 is equal. The shape of the second opening OP2 is a regular hexagon. The total area of the second opening OP2 is 35% to 80% with respect to the second main surface Sf2 of the semiconductor substrate SB.

As an example, when the area (chip size) of the second main surface of the semiconductor substrate SB is, for example, about 3 mm square, the area of one second opening OP2 is about 1000 μm ² , and they are spaced apart by about 15 μm.

  Referring to FIG. 5, the second metal layer 12 covers the second insulating film 11 and is provided on the second main surface Sf2 side, and is formed through the second opening OP2 indicated by a broken line in FIG. 6B. It contacts the second main surface (n + type silicon semiconductor substrate 1) of the substrate SB and becomes the cathode electrode CA of the diode 105.

  The second metal layer 12 has, for example, a Ti—Ni—Ag multilayer metal structure from the second main surface Sf2 side. When the chip size is as large as 0.6 mm square or more, if eutectic is used for fixing the support member 30 such as the lead frame and the diode 105, unevenness is likely to occur and cracking due to vibration is not preferable. Therefore, when the chip size is large, it is desirable to fix with an adhesive.

  For example, when the chip size is smaller than 0.6 mm square, the support material 30 such as the lead frame and the diode 105 can be fixed together by eutectic, so that the second metal layer 12 in this case is on the second main surface Sf2 side. Then, a NiCr—Au multilayer metal structure is adopted and fixed by eutectic with a support material (for example, copper (Cu)).

  In the second main surface Sf2, the second metal layer 12 is provided so as to cover the second insulating film 11 provided with the second opening OP2. As a result, the total contact area between the second metal layer 12 and the substrate SB (n + type silicon semiconductor substrate 1) is 35% to 80% of the area of the substrate SB. However, the fixing area between the second metal layer 12 and the support member 30 such as the lead frame can maintain the area (chip size) of the substrate SB, and can ensure the conventional fixing strength (see FIG. 5).

  In the second embodiment, by reducing the contact area between the second metal layer 12 and the substrate SB, the disappearance of minority carriers (holes) in the vicinity of the second metal layer 12 can be reduced, and the conductivity modulation effect can be obtained. Can be improved.

  FIG. 7 is an enlarged cross-sectional view of the vicinity of the second metal layer 12 when the forward voltage VF is applied to the diode 105.

  When a positive potential is applied to the first metal layer 7 (anode electrode A) and a negative potential is applied to the second metal layer 12 (cathode electrode CA), holes are injected from the p-type impurity region 3 into the n − -type semiconductor layer 2. Occurs, the conductivity of the n − type semiconductor layer 2 (drift layer) is modulated, the semiconductor device 20 is conducted, and a current flows from the first electrode 5 toward the second metal layer 12.

  At this time, in the vicinity of the second metal layer 12, minority carriers (holes) near the second opening OP2 of the second insulating film 11 are extracted by the second metal layer 12, but in the vicinity of the second opening OP2, Minority carriers (holes) blocked by the insulating film 11 accumulate. As a result, the conductivity modulation effect increases and the forward voltage VF decreases.

  Further, similarly to the first embodiment, the p-type semiconductor region 3 is formed in an island shape separated into a plurality on the first main surface Sf1 side of the substrate SB. Accordingly, for example, when compared with the conventional pn junction diode 110 shown in FIG. 13 as the same chip size, in this embodiment, the total volume of the p-type semiconductor region 3 is reduced, and the charge amount is larger than that of the conventional p-type impurity region 113. Less. Therefore, the amount of minority carriers (holes) injected into the n − type semiconductor layer 2 can be reduced as compared with the conventional pn junction diode 110.

  Furthermore, in the second embodiment, since the contact area of the anode electrode A is small, the disappearance of electrons from the electrode is reduced, that is, the disappearance of electrons on the anode side (the first main surface Sf1 side of the substrate SB) is eliminated. Can be reduced.

  Therefore, the conductivity modulation effect becomes more effective, and the forward voltage VF can be made substantially equal as compared with the conventional pn junction diode.

  As described above, the p-type semiconductor region 3 has its impurity concentration reduced to reduce the reverse recovery time trr and the impurity charge amount is reduced as compared with the conventional pn junction diode 110. Specifically, the charge amount of impurities in the p-type semiconductor region 3 is 1 to 2 times the charge amount of impurities in the n − -type semiconductor layer 2.

  In this case, since minority carriers (holes) injected into the n − type semiconductor layer 2 that is the drift layer are reduced, the conductivity modulation effect is reduced at this point.

  In addition, since the second insulating film 11 narrows the path of the drift current, the current resistance slightly increases.

  However, in the second embodiment, on the cathode side, the second metal layer 12 is selectively contacted, and the area and arrangement of the second opening OP2 are appropriately selected, thereby increasing the resistance of the current and a small number. A conductivity modulation effect that exceeds the reduction in the amount of injected carriers can be obtained. Therefore, it is possible to reduce the reverse recovery time trr and reduce the forward voltage VF by increasing the conductivity modulation effect.

  8 and 9 are diagrams for explaining the forward voltage VF-forward current IF characteristics depending on the impurity concentration of the p-type semiconductor region 3.

FIG. 8 shows the forward voltage VF-forward current IF characteristics for two types of impurity concentrations in the p-type impurity region 113 in the pn junction diode 110 having the conventional structure (FIG. 13). The broken line indicates the p-type impurity. This is the case where the impurity concentration of the region 113 is 2.5E18 cm ⁻³ , and the solid line is the case where the impurity concentration of the p-type impurity region 113 is 1.0E15 cm ⁻³ .

  This shows that when the forward current IF is 5 (A), the forward voltage VF increases by about 0.3 V by reducing the impurity concentration of the p-type impurity region.

FIG. 9 compares the forward current IF-forward voltage VF characteristics when the conventional pn junction diode 110 and the first main surface Sf1 of the diode 105 of the second embodiment are the conventional pn junction diode 110. FIG. The broken line is the case where the cathode electrode 119 is in contact with the entire surface of the substrate SB ′ as in the conventional structure, and the solid line is the contact area between the second electrode 12 (cathode electrode CA) and the substrate SB as in the present embodiment. This is a case of half the total area. The impurity concentration of the p-type semiconductor region 3 is 1.0E15 cm ⁻³ shown in FIG.

  As described above, according to the present embodiment, the forward current IF is about 0.1 A or more by reducing the contact area between the second electrode 12 and the semiconductor substrate SB (for example, half the total chip area). In this case, the forward voltage VF at the same forward current IF can be reduced.

  In FIG. 8, when the concentration of the p-type impurity region is low, the forward voltage IF is low (low VF) until the forward current IF is about 1 A, but in the region where the forward current IF exceeds about 1 A. The forward voltage VF at the same forward current IF increases (FIG. 8).

  However, by reducing the contact area in this embodiment, the forward voltage VF can be reversed in the region where the forward current IF is about 0.1 A or more, and the forward voltage VF value at the same forward current IF can be reduced. . When the forward current IF is about 0.1 A or less, it is better to contact the second electrode (cathode electrode) over the entire surface. This is equivalent to the case where the second electrode is provided over the entire surface with the same impurity concentration. This is because the cases of areas of 1 are compared.

  Compared with the case where the p-type impurity region (p-type semiconductor region 3) has a high concentration (FIG. 8), the low concentration has a forward current IF of about 1 A or less and a low VF (FIG. 8). Even when the VF is increased to about 0.1 A or less (FIG. 9), the VF can be made lower than the conventional structure (the pn junction diode 110 in which the p-type impurity region 113 has a high concentration and the cathode electrode contacts the entire surface).

  Since the second insulating film 11 narrows the current path, the current resistance slightly increases. However, the second insulating film 11 exceeds the current resistance increase by appropriately selecting the area and arrangement of the second opening OP2. A conductivity modulation effect can be obtained.

  FIG. 10 is a diagram illustrating the relationship between the aperture ratio of the second opening OP2 and the forward voltage VF. The horizontal axis represents the aperture ratio [%] indicating the ratio of the total area of the second opening OP2 to the area of the second main surface, and the vertical axis represents the forward voltage VF [V] at each aperture ratio.

  As a result, when the total area of the second opening OP2 is half of the total area of the second main surface of the semiconductor substrate SB, the forward voltage VF can be most reduced.

  Next, a manufacturing method of the diode 105 of the second embodiment will be described with reference to FIGS.

  First step (FIG. 11A): A substrate SB in which an n− type semiconductor layer 2 is stacked on an n + type semiconductor substrate 1 is prepared, and a mask M obtained by etching an oxide film or the like into a desired pattern is used as a first main surface Sf1. Generated on the entire surface. The surface of the n − type semiconductor layer 2 exposed from the mask M is anisotropically etched to form a trench 10 having a depth of about 4 μm, for example. The pattern of the trench 10 on one main surface of the substrate SB has a regular hexagonal shape, and the width (diagonal width) is, for example, about 10 μm. The distances d1 between the trenches 10 are equally spaced from each other, for example, about 1 μm to 10 μm.

  Second step (FIG. 11B): The mask M is removed, polysilicon doped with high-concentration p-type impurities is deposited, and the trench 10 is also filled with polysilicon. Further, after depositing non-doped polysilicon, a high concentration p-type impurity may be introduced. Then, polysilicon is left only in the trench 10 by etching back the entire surface, and the surface of the n − type semiconductor layer 2 is exposed.

  Thereafter, an oxide film is formed on the entire surface, p-type impurities in the polysilicon are activated by heat treatment, and a p-type semiconductor region 3 is formed.

  Further, when the p-type semiconductor region 3 is formed by impurity ion implantation and diffusion, the trench is not formed in the second step, but the impurity is implanted and diffused into the n − -type semiconductor layer 2 through the mask M. .

  The insulating film 5 is deposited, and the insulating film 5 is etched with a desired pattern to form the first opening, OP1, and another opening OP1 '.

  A plurality of first openings OP1 are formed separated by a predetermined distance. The first opening OP1 has a regular hexagonal shape, and its width is, for example, about 10 μm. The distances d2 between the first openings OP1 are spaced apart from each other at equal intervals.

  Third step (FIG. 11C): Thereafter, a first metal layer 7 made of an Al layer or the like is formed on the first main surface Sf1 side of the substrate SB. The first metal layer 7 forms an ohmic junction with the p-type semiconductor region 3 exposed from the first opening OP1 and becomes the anode electrode A.

  Fourth step (FIG. 12A): A second insulating film 11 such as an oxide film is provided on the second main surface Sf2 of the substrate SB. A mask (not shown) having a desired pattern is provided on the second insulating film 11, and the second insulating film 11 is etched to form the second opening OP2.

  Each of the second openings OP2 has an equal shape (size), and is formed such that the distance from the center of the second opening OP2 is an equal distance from each other, and the shape thereof is a regular hexagon. .

  The total area of the second opening OP2 is formed to be about 35% to 80% with respect to the area of the second main surface Sf2 of the substrate SB.

  Fifth step (FIG. 12B): Thereafter, a second metal layer 12 of Ti—Ni—Ag or NiCr—Au is formed on the second insulating film 11 by vapor deposition. Thus, the cathode electrode CA that selectively contacts the second main surface Sf2 (n + type silicon semiconductor substrate 1) of the substrate SB through the second opening OP2 is formed.

  In the case of the first embodiment, in the fourth step of FIG. 12A, the second insulating film 11 is not formed, and the second metal layer 8 such as Ti—Ni—Ag is used as the second step of the substrate SB. The cathode electrode CA is formed by vapor deposition or the like directly on the entire main surface Sf2.

It is (A) top view, (B) top view, (C) sectional drawing for demonstrating the diode of this invention. It is sectional drawing for demonstrating the diode of this invention. It is a characteristic view for demonstrating the diode of this invention. It is a characteristic view for demonstrating the diode of this invention. It is sectional drawing for demonstrating the diode of this invention. It is a top view for demonstrating the diode of this invention. It is sectional drawing for demonstrating the diode of this invention. It is a characteristic view for demonstrating the diode of this invention. It is a characteristic view for demonstrating the diode of this invention. It is a characteristic view for demonstrating the diode of this invention. It is sectional drawing for demonstrating the manufacturing method of the diode of this invention. It is sectional drawing for demonstrating the manufacturing method of the diode of this invention. It is sectional drawing for demonstrating the conventional pn junction diode. It is sectional drawing for demonstrating the conventional Schottky barrier diode.

Explanation of symbols

1 n + type silicon semiconductor substrate 2 n− type semiconductor layer 3 p type semiconductor region
4 Guard ring 5 First insulating film 7 First metal layer (anode electrode)
8, 12 Second metal layer (cathode electrode)
9 n-type impurity region 10 trench 11 second insulating film 50 depletion layer 100, 105 diode 110 pn junction diode
111 n + type silicon semiconductor substrate 112 n− type semiconductor layer 115 insulating film 117 guard ring 118 anode electrode 119 cathode electrode 113 p + type impurity region 120 Schottky barrier diode (JBS)
121 n + type silicon semiconductor substrate 122 n− type semiconductor layer 123 p + type impurity region 125 insulating film 126 metal layer 127 guard ring 128 anode electrode 129 cathode electrode SB, SB ′ semiconductor substrate OR operation region OP1 first opening OP2 second opening Part OP1 'other opening

Claims (9)

A substrate in which a one-conductivity-type semiconductor layer is stacked on a high-concentration one-conductivity-type semiconductor substrate;
A plurality of reverse conductivity type semiconductor regions provided apart from each other in the one conductivity type semiconductor layer;
An insulating film provided on one main surface of the substrate;
An opening provided in the insulating film and exposing the reverse conductivity type semiconductor region;
A metal layer provided on the insulating film and in contact with the reverse conductivity type semiconductor region through the opening;
A diode comprising:   2. The diode according to claim 1, wherein the charge amount of the impurity in the reverse conductivity type semiconductor region is 1 to 2 times the charge amount of the impurity in the semiconductor layer.   The diode according to claim 1, wherein the metal layer is in ohmic contact with the reverse conductivity type semiconductor region.   The diode according to claim 1, wherein a surface of the semiconductor layer between the adjacent opposite conductivity type semiconductor regions is covered with the insulating film. A substrate in which a one-conductivity-type semiconductor layer is stacked on a high-concentration one-conductivity-type semiconductor substrate;
A plurality of reverse conductivity type semiconductor regions provided apart from each other in the one conductivity type semiconductor layer;
A first insulating film provided on the first main surface of the substrate;
A first opening provided in the first insulating film and exposing the reverse conductivity type semiconductor region;
A first metal layer provided on the first insulating film and in contact with the reverse conductivity type semiconductor region through the first opening;
A second insulating film provided on the second main surface of the substrate;
A plurality of second openings selectively provided in the second insulating film;
A second metal layer provided to cover the second insulating film and in contact with the second main surface through the second opening;
A diode comprising:   The diode according to claim 5, wherein an area of the second opening is 35% to 80% with respect to the second main surface.   6. The diode according to claim 5, wherein the second openings have a uniform shape and are spaced apart from each other by an equal distance.   The diode according to claim 5, wherein the second opening has a regular hexagonal shape.   6. The diode according to claim 5, wherein the charge amount of the impurity in the reverse conductivity type semiconductor region is 1 to 2 times the charge amount of the impurity in the semiconductor layer.