JP2008205071A - Electronic-component-incorporating board, electronic apparatus using the same, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify and improve the reliability of inter-layer connection in an electronic-component-incorporating board incorporating therein a semiconductor bare chip IC. <P>SOLUTION: The electronic-component-incorporating board includes a metal block 27 which is mounted on the upper surface of a second conductive pattern 6 to be lower than the post-mounted height of an electronic component 5 incorporated in a second insulating layer 4, and a via-hole 8 which penetrates the second insulating layer 4 to electrically connect the metal block 27 to a third conductive pattern 7 via a second solder film 9. Using the metal block 27 lower than the post-mounted height of the electronic component 5 enables determining the height of the second insulating layer 4 to be a height depending on the height of the electronic component 5 and reducing the depth of the via-hole 8. As a result, connection between the metal block 27 and the third conductive pattern 7 via the second solder film 9 can be carried out certainly. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic component built-in substrate in which an electronic component is embedded in a multilayer substrate, an electronic device using the same, and a manufacturing method thereof.

  As electronic devices become smaller and lighter, demands for higher density printed wiring boards and smaller mounted components have become stricter. In the printed wiring board, the density is increased in the direction parallel to the surface of the wiring board by reducing the wiring rules. Furthermore, by adopting a build-up method, wiring is laminated, and via holes are formed between arbitrary layers, so that it is possible to increase the density in a direction perpendicular to the surface of the wiring board.

  On the other hand, as a semiconductor package, a surface mount device (SMD; Surface Mount Device) such as SOP (Small Outline Package) or QFP (Quad Flat Package) having a multi-pin lead on the outer periphery of the conventional package is used. There were many. In recent years, in order to further reduce the size of a semiconductor package, a chip size package (CSP) has been achieved by flip chip mounting in which an active surface of a semiconductor element faces a substrate. According to flip-chip mounting, a semiconductor element is directly mounted on a substrate via electrode terminals called bumps without using leads as bare chips. According to the flip chip mounting described above, the area where the bare chip semiconductor can be mounted is the surface of the substrate, and the mounting density is limited by the substrate size. Therefore, it is difficult to further improve the mounting density. Therefore, means for reducing the size of an electronic device by mounting a semiconductor element inside a substrate to increase the mounting density has been proposed.

  Hereinafter, a conventional electronic component built-in substrate will be described with reference to FIG. FIG. 8 is a cross-sectional view of a conventional electronic component built-in substrate.

  In FIG. 8, a conventional substrate with built-in electronic components has a first insulating layer 101 made of a base material and a second insulating layer 102 made of an insulating resin layer provided on the first insulating layer 101. An electronic component 103 made of a bare chip IC is mounted on the first conductive pattern 106 on the upper surface of the insulating layer 101 and is embedded in the second insulating layer 102. The connection between the first conductive pattern 106 and the electronic component 103 is made through bumps 104 formed on the electronic component 103. A second conductive pattern 108 is formed on the other upper surface of the first insulating layer 101. A third conductive pattern 110 having a predetermined pattern is formed on the second insulating layer 102 with an adhesive layer 109 interposed therebetween. The second insulating layer 102 on the second conductive pattern 108 is bonded to the second conductive layer 108. A via hole 115 is formed in the layer 109 and the third conductive pattern 110, and a conductive layer 116 is formed in the via hole 115.

  As prior art document information of this technology, for example, Patent Document 1 is known.

  As a method not using the via hole 115, a bump (not shown) having a height larger than the height after the electronic component 103 is mounted is exposed on the second conductive pattern 108 from the second insulating layer 102. A method of forming the third conductive pattern 110 on the second insulating layer 102 and electrically connecting the third conductive pattern 110 and the bump (not shown) is proposed. .

  For example, Patent Document 2 and Patent Document 3 are known as prior art document information of this technology.

  As another method, after connecting a third insulating layer (not shown) on a bump (not shown) having a height higher than the height after the electronic component 103 is mounted, the first insulating layer 101 and A method for forming the second insulating layer 102 between third insulating layers (not shown) has been proposed.

As prior art document information of this technology, for example, Patent Document 4 is known.
JP 2001-77536 A Japanese Patent No. 3500995 JP 2001-7472 A JP 2001-144244 A

  In such a conventional substrate with built-in electronic parts, the second conductive pattern 108 and the third conductive pattern 110 are electrically connected by the via hole 115 penetrating the second insulating layer 102. Since the electronic component 103 is embedded, the thickness is large, and the via hole 115 is also a deep hole. Accordingly, it is very difficult to form a plating film in the via hole 115 which is a deep hole, and there is a problem that the mass productivity is poor.

  In addition, in order to avoid the deep via hole 115, when the second conductive pattern 108 and the third conductive pattern 110 are connected using the bump 124 (not shown) instead of the via hole 115, the height of the bump 124 is an electron. If it becomes lower than the height after mounting the component 103, the bump 124 and the third conductive pattern 110 cannot be electrically connected. Therefore, the height of the bump 124 is set higher than the height after mounting the electronic component 103. There is a need to. However, if the height of the bump 124 becomes too high, the thickness of the second insulating layer 102 becomes thick this time, and the total thickness of the electronic component built-in substrate after completion becomes thick. Further, since a polishing process is required to make the second insulating layer 102 thin, there is a problem that not only the mass productivity is deteriorated but also the electronic component 103 built in is damaged by the polishing. Was.

  The present invention solves such a problem, and an object of the present invention is to provide an electronic component-embedded substrate that is simple and has high connection reliability, an electronic device using the same, and a manufacturing method thereof.

  To achieve the above object, the present invention provides a first insulating layer, a first conductive pattern and a second conductive pattern made of a first metal provided on an upper surface of the first insulating layer, and the first conductive layer. A first plating film made of a second metal formed on the upper surface of the conductive pattern and the second conductive pattern, and the second conductive pattern and the electricity through the first plating film on the second conductive pattern A metal lump that is connected to the first conductive pattern, an electronic component that is connected to the first conductive pattern via the first plating film and the bump, and the first lump so as to cover the metal lump and the electronic component. A second insulating layer provided on one insulating layer; a third conductive pattern made of the first metal provided on an upper surface of the second insulating layer; and the metal penetrating through the second insulating layer, The second plating is applied to the lump and the third conductive pattern. In this case, the via hole to be processed becomes shallow due to the presence of the metal block, and the metal layer and the third conductive pattern are formed by the second plating film. It has the effect | action that it can connect reliably.

  The invention according to claim 2 is the electronic component built-in substrate according to claim 1, wherein the second plating film is made of a first metal, and the second plating film is a third conductive material made of the first metal. Since it can be composed of the same material as that of the conductive pattern, it has an effect that a highly reliable plating film can be formed.

  According to a third aspect of the present invention, the first metal is Cu and the second metal is Au. The electronic component-embedded substrate according to the first aspect is provided, and Cu is inexpensive and highly reliable. The first to third conductive patterns can be formed by using Au, and the use of Au as the second metal can ensure high reliability for the connection between the electronic component and the first conductive pattern. Have.

  According to a fourth aspect of the present invention, in the electronic component built-in substrate according to the first aspect, the second plating film is made of at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. And has an effect that a good connection between the metal block and the third conductive pattern is possible.

  The invention according to claim 5 is the electronic component built-in substrate according to claim 1, wherein the bump is made of at least Au, Sn or Ag, and is a stud bump made of Au wire, Au or solder made by plating. Using bumps that can be formed by a simple method such as bumps, Ag bumps using conductive paste, etc., there is an effect that a highly reliable connection between the electronic component and the first conductive pattern can be realized.

  The invention according to claim 6 is the electronic component built-in substrate according to claim 1, wherein the metal block includes at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. It has an effect that it can be easily mounted on the second conductive pattern and can be easily electrically connected to the second plating film.

  The invention according to claim 7 is the electronic component built-in substrate according to claim 1, wherein the height of the metal block is lower than the sum of the height of the electronic component and the height of the bump. Since the thickness of the second insulating layer can be set according to the height of the electronic component incorporated in the layer, the second insulating layer is not made thicker than necessary, and the presence of the metal block is shallow. Since the via hole can be formed, it has an effect that a stable second plating film can be formed in the via hole.

  The invention according to claim 8 is the electronic component built-in substrate according to claim 1, wherein the metal block is fixed on the second conductive pattern by solder, and is desired by a simple method. It has an effect that a metal block can be mounted at the position.

  The invention according to claim 9 is the electronic component built-in substrate according to claim 7 in which the solder does not contain Pb, and the metal lump can be easily mounted, and the environment. This has the effect that a component-embedded substrate that does not contain a load substance can be produced.

  The invention according to claim 10 is the electronic component built-in substrate according to claim 1, wherein the metal block is fixed on the second conductive pattern by a conductive adhesive, and is a simple method. Thus, the metal lump can be mounted at a desired position.

  The invention according to claim 11 is the electronic component built-in substrate according to claim 1, wherein the metal block has a substantially spherical shape. By making the metal block spherical, the second conductive pattern can be easily formed. It has the effect that it can be mounted on.

  The invention according to claim 12 is the electronic component built-in substrate according to claim 1, wherein a resist film is formed so as to surround an outer periphery of the second conductive pattern. When mounted on the conductive pattern, the solder and the conductive adhesive can be prevented from spreading unnecessarily.

  The invention according to claim 13 is a first insulating layer, a first conductive pattern and a second conductive pattern made of a first metal provided on an upper surface of the first insulating layer, and the first conductive pattern. And a first plating film made of a second metal formed on the upper surface of the second conductive pattern, and electrically with the second conductive pattern via the first plating film on the second conductive pattern. A metal block provided to be connected, an electronic component connected to the first conductive pattern via the first plating film and the bump, and the first insulation so as to cover the metal block and the electronic component A second insulating layer provided on the layer, a third conductive pattern made of the first metal provided on an upper surface of the second insulating layer, the metal block penetrating the second insulating layer, and The third conductive pattern is formed by a second plating film It is obtained by a receiving apparatus having the electronic-part built-in substrate in which a via hole gas connecting, an effect that it is possible to realize a micro receiver.

  The invention according to claim 14 is a first insulating layer, a first conductive pattern and a second conductive pattern made of a first metal provided on an upper surface of the first insulating layer, and the first conductive pattern. And a first plating film made of a second metal formed on the upper surface of the second conductive pattern, and electrically with the second conductive pattern via the first plating film on the second conductive pattern. A metal block provided to be connected, an electronic component connected to the first conductive pattern via the first plating film and the bump, and the first insulation so as to cover the metal block and the electronic component A second insulating layer provided on the layer, a third conductive pattern made of the first metal provided on an upper surface of the second insulating layer, the metal block penetrating the second insulating layer, and The third conductive pattern is formed by a second plating film It is obtained by an electronic device having an electronic component-embedded substrate having a via hole gas connecting, such an action can be realized microelectronics.

  The invention according to claim 15 has a first conductive pattern and a second conductive pattern made of a first metal on an upper surface, and is made of a second metal on the first conductive pattern and the second conductive pattern. A step of mounting an electronic component on the first plating film on the upper surface of the first conductive pattern of the first insulating layer on which the first plating film is formed via a bump; and an upper surface of the second conductive pattern Mounting a metal lump on the first plating film, laminating a second insulating layer on the first insulating layer so as to cover the electronic component and the metal lump, and on the second insulating layer A step of laminating a metal foil made of the first metal, a step of pressurizing and integrating the laminated first insulating layer, the second insulating layer, and the metal foil, and a predetermined of the metal foil A process for exposing the second insulating layer by drilling a hole Processing the second insulating layer to expose the metal mass, electrically connecting the metal mass and the metal foil by a second plating film, and processing the metal foil to form a third This is a method of manufacturing an electronic component built-in substrate including a step of forming a conductive pattern. The depth of a via hole to be processed is reduced due to the presence of the metal block, and the metal block and the third conductivity are formed by the second plating film. It has the effect that the patterns can be reliably connected.

  The invention described in claim 16 has a first conductive pattern and a second conductive pattern made of a first metal on an upper surface, and is made of a second metal on the first conductive pattern and the second conductive pattern. A step of mounting an electronic component on the first plating film on the upper surface of the first conductive pattern of the first insulating layer on which the first plating film is formed via a bump; and an upper surface of the second conductive pattern Mounting a metal lump on the first plating film; laminating a second insulating layer on the first insulating layer so as to cover the electronic component and the metal lump; and the stacked first insulation. A step of pressing and integrating the layer and the second insulating layer while heating, a step of processing the second insulating layer to expose the metal block, and an upper surface of the second insulating layer by a second plating film Forming a third conductive pattern on the metal block This is a method for manufacturing an electronic component built-in substrate having a step of electrically connecting. The depth of a via hole to be processed is reduced due to the presence of the metal block, and the metal plate and the third conductive pattern are formed by the second plating film. Can be reliably connected.

  The invention according to claim 17 is the method for manufacturing a substrate with built-in electronic components according to claim 15 or claim 16, wherein the second plating film is made of a first metal. Since it can be comprised with the same material as the 3rd conductive pattern which consists of 1 metal, it has the effect | action that a reliable plating film formation can be performed.

  The invention according to claim 18 is the method for manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein the first metal is Cu and the second metal is Au. The first to third conductive patterns can be formed using highly reliable Cu, and high reliability is ensured for the connection between the electronic component and the first conductive pattern by using Au as the second metal. It has the effect of being able to.

  According to a nineteenth aspect of the present invention, in the fifteenth or sixteenth aspect, the second plating film is made of at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. This is a method for manufacturing an electronic component built-in substrate, and has an effect that a good connection between the metal block and the third conductive pattern is possible.

  The invention according to claim 20 is the method of manufacturing the electronic component built-in substrate according to claim 15 or 16, wherein the bump is made of at least Au, Sn, or Ag, and is a stud made of Au wire. Using bumps that can be formed by simple methods such as bumps, Au by plating or solder bumps, Ag bumps by conductive paste, etc., it is possible to realize a highly reliable connection between the electronic component and the first conductive pattern. Has an effect.

  According to a twenty-first aspect of the present invention, in the electronic component-embedded substrate according to the fifteenth or sixteenth aspect, the second insulating layer comprises a prepreg in which at least one woven or non-woven fabric is impregnated with a thermosetting resin. This method has the effect that a highly reliable electronic component-embedded substrate can be realized by using substantially the same material as the first insulating layer.

  According to a twenty-second aspect of the present invention, a gap larger than the electronic component and a gap substantially equal to or larger than the metal block are formed in the second insulating layer before the stacking, and the electronic component and the metal block are respectively stacked during the stacking The method for manufacturing an electronic component-embedded substrate according to claim 15, wherein the first insulating layer and the second insulating layer that are laminated are arranged in the corresponding gap. In the step of pressing and integrating while heating, there is an effect that an unnecessary load on the electronic component and the metal lump can be prevented.

  According to a twenty-third aspect of the present invention, a single gap is formed in the second insulating layer before the stacking so as to surround the electronic component and the metal block, and the electronic component and the metal are stacked before the stacking. The method for manufacturing an electronic component-embedded substrate according to claim 15, wherein all of the lumps are disposed in the gap, wherein the first stacked layers are simple gaps. In the step of pressurizing and integrating the insulating layer and the second insulating layer while heating, an unnecessary load on the electronic component and the metal lump can be prevented at a time.

  The invention described in claim 24 is the method of manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein the step of exposing the metal block is performed by laser processing or drilling. According to the method, the second conductive pattern can be exposed with high positional accuracy.

  According to a twenty-fifth aspect of the present invention, in the electronic component according to the fifteenth or sixteenth aspect, the metal block includes at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. This is a method for manufacturing a built-in substrate, and can be easily mounted on the second conductive pattern and can be easily electrically connected to the second plating film. .

  According to a twenty-sixth aspect of the present invention, in the method for manufacturing an electronic component built-in substrate according to the fifteenth or sixteenth aspect, the height of the metal block is lower than the sum of the height of the electronic component and the height of the bump. Since the thickness of the second insulating layer can be set according to the height of the electronic component incorporated in the second insulating layer, the second insulating layer is not made thicker than necessary, and the metal block Since the shallow via hole can be formed, there is an effect that a stable second plating film can be formed in the via hole.

  The invention according to claim 27 is the method of manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein the metal block is fixed on the second conductive pattern by solder. The metal lump can be mounted at a desired position by a simple method.

  The invention described in claim 28 is the method for manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein the solder contains no Pb, and the metal block is easily mounted. In addition, it is possible to manufacture a component-embedded substrate that does not contain an environmentally hazardous substance.

  The invention according to claim 29 is the method of manufacturing the electronic component built-in substrate according to claim 15 or 16, wherein the metal block is fixed on the second conductive pattern by a conductive adhesive. It has the effect | action that a metal lump can be mounted in a desired position by a simple method.

  According to a thirty-third aspect of the present invention, there is provided a method for manufacturing an electronic component-embedded substrate according to the fifteenth or sixteenth aspect, wherein the metal block is substantially spherical. 2 It has the effect | action that it can mount easily on a conductive pattern.

  The invention described in claim 31 is the method for manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein a resist film is formed so as to surround an outer periphery of the second conductive pattern. When the metal block is mounted on the second conductive pattern, the solder and the conductive adhesive can be prevented from spreading unnecessarily.

  According to a thirty-second aspect of the present invention, in the electronic component according to the sixteenth aspect, the third conductive pattern is patterned into a desired shape after the second plating film is formed on the entire upper surface of the second insulating layer. This is a method for manufacturing a built-in substrate, and has an effect that a substrate with a built-in electronic component can be manufactured by a simple build-up method.

  Since the metal block lower than the total height of the electronic component and the bump is mounted on the second conductive pattern, the thickness of the second insulating layer can be set on the basis of the height of the electronic component. 2 The thickness of the insulating layer is not increased, and the depth of the via hole to be processed is reduced due to the presence of the metal lump, and the metal lump and the third conductive pattern can be reliably connected by the second plating film. It is.

(Embodiment 1)
Embodiments of an electronic component built-in substrate and a method for manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an electronic component built-in substrate according to Embodiment 1 of the present invention.

  In FIG. 1, the electronic component built-in substrate of Embodiment 1 includes a first insulating layer 1 and a second insulating layer 4 provided on the first insulating layer 1. A first conductive pattern 2 and a second conductive pattern 6 are provided on the upper surface of the first insulating layer 1. The first insulating layer 1 is a multilayer wiring board whose main component is a thermosetting resin. As the thermosetting resin, for example, epoxy resin, phenol resin, cyanate resin, or BT resin (bismaleimide / triazine resin) can be used. Epoxy resins are particularly preferred because of their high heat resistance. The first conductive pattern 2 and the second conductive pattern 6 are made of a material having electrical conductivity, for example, a Cu foil or a conductive resin composition. In the present invention, Cu foil is used. The inner via 13 included in the first insulating layer 1 is made of, for example, a thermosetting conductive material such as a metal material by Cu plating or a conductive resin composition in which metal particles and a thermosetting resin are mixed. Become. Au, Ag, Cu, or the like can be used as the metal particles in the conductive material. Au, Ag, or Cu is preferable because of its high conductivity, and Cu is particularly preferable because of its high conductivity, low migration, and low cost. As the thermosetting resin, for example, an epoxy resin, a phenol resin, or a cyanate resin can be used. Epoxy resins are particularly preferred because of their high heat resistance.

  A first plating film 3 is formed on the first conductive pattern 2 on the upper surface of the first insulating layer 1. As the first plating film 3, for example, Ni plating by an electroless plating method is performed on a base metal, and an Au plating film is similarly formed on the Ni plating by an electroless plating method. The plating film forming method is not limited to the above-described method, and can be realized by various methods. However, in consideration of connection stability when the electronic component 5 is mounted later via the bump 10, It is important that an Au plating film is formed on the outermost layer.

  An electronic component 5 made of a semiconductor bare chip IC in which bumps 10 are formed on the first conductive pattern 2 on which the first plating film 3 is formed is flip-chip mounted. As a material of the bump 10, a bump that can be formed by a simple method such as a stud bump made of Au wire, Au or solder bump made by plating, or an Ag bump made of conductive paste can be used. The bumps 10 may be formed by various methods without being limited to the method described above.

  As a flip chip mounting method of the electronic component 5 made of a semiconductor bare chip IC, an Au—Au direct connection method that does not use an auxiliary material at the time of mounting or a solder connection method using a solder bump can be used. However, the method is not limited to the above method. Any method can be used as long as it is a flip chip mounting system in which a semiconductor bare chip IC is mounted face down.

  A metal block 27 is mounted on the second conductive pattern 6 by a mounting material 26 having conductivity. As the mounting material 26, solder or a conductive adhesive can be used. As the solder, materials such as Sn—Ag, Sn—Ag—Cu, Sn—Zn, and Au—Zn can be used. However, the material is not limited to these materials, and the metal lump 27 can be mounted. Any material can be used. However, it is important that this solder is a Pb-free solder that does not contain or hardly contains Pb, which is an environmental pollutant. As the conductive adhesive, a material obtained by mixing metal particles such as Au, Ag, or Cu and a thermosetting resin such as an epoxy resin, a phenol resin, or a cyanate resin can be used. Among them, a combination of Ag and an epoxy resin is particularly preferable because it has high conductivity and high heat resistance. As the metal lump 27, a single or a combination of metal materials such as Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au can be used, and using Cu has high conductivity. In addition, the cost is low, and it is particularly preferable when considering adhesion and conductivity with the second plating film 9 to be formed later.

  Further, the height of the metal block is set lower than the sum of the height of the electronic component and the height of the bump. By doing so, the tallest component after mounting the electronic component 5 and the metal lump 27 becomes the electronic component 5, and therefore the thickness of the second insulating layer 4 can be set according to the height of the electronic component 5. Therefore, the second insulating layer 4 is not made thicker than necessary. That is, when the metal block 27 is larger than the height after the electronic component 5 is mounted, the second insulating layer 4 is originally made as thin as possible while covering the electronic component 5 with the second insulating layer 4. Since the second insulating layer 4 is formed so as to cover the metal block 27 that is higher than the height after the electronic component 5 is mounted, the second insulating layer 4 portion becomes very thick. Therefore, in order to reduce the thickness of the second insulating layer 4, a step of polishing and thinning the second insulating layer 4 is required. In this case, a step of polishing is required, and the electronic component 5 is obtained by polishing. Unnecessary stress is applied, and the connection failure of the electronic component 5 is caused. Therefore, by making the metal block 27 lower than the height after the electronic component 5 is mounted, the second insulating layer 4 can have a thickness resulting from the height of the electronic component 5, and the second insulating layer 4 is polished. Thus, a thinning step is not necessary, and unnecessary stress is not applied to the electronic component 5 due to polishing, so that it is possible to eliminate a factor that causes poor connection of the electronic component 5. Furthermore, it is desirable that the metal block 27 is substantially spherical. By making it spherical, the metal lump 27 has no directivity, so that it can be handled easily and can be easily mounted on the second conductive pattern 6.

  The second insulating layer 4 is formed by applying pressure while heating a prepreg obtained by impregnating a woven fabric or a nonwoven fabric with an uncured thermosetting resin to cure the thermosetting resin. As a prepreg, a glass epoxy prepreg in which a glass cloth is impregnated with a thermosetting epoxy resin, a BT resin prepreg in which a glass cloth is impregnated with a thermosetting bismaleimide / triazine resin, and a thermosetting epoxy resin in an aramid nonwoven fabric It is possible to use an aramid prepreg impregnated with, but various materials can be used as long as the structure is obtained by impregnating a thermosetting resin into a woven fabric or a non-woven fabric. In addition to the prepreg obtained by impregnating a woven or non-woven fabric with a thermosetting resin, it is also possible to use a mixture of an inorganic filler such as silicon dioxide or alumina and a thermosetting resin.

  A third conductive pattern 7 is disposed on the second insulating layer 4. The 3rd conductive pattern 7 consists of a substance which has electrical conductivity, for example, consists of Cu foil and a conductive resin composition. In the present invention, Cu foil is used.

  The third conductive pattern 7 and the metal block 27 are electrically connected by the second plating film 9 in the blind via hole 8 that penetrates the third conductive pattern 7 and the second insulating layer 4 and is connected to the metal block 27. It is connected to the. The shallow via hole 8 can be formed by the presence of the metal block 27, and thus the stable second plating film 9 can be formed in the via hole 8.

  The second plating film 9 is constituted by electroless Cu plating or electrolytic Cu plating with Pd as a nucleus. The second plating film 9 is not limited to Cu plating, and may be made of other materials such as Zn, Ni, Ti, Cr, Sn, Ag, and Au. However, it is important to select a plating material that can sufficiently react with the third conductive pattern 7 and the metal block 27. In the first embodiment, Cu is used for the second plating film 9.

  The blind via hole 8 in which the second plating film 9 is formed may remain concave as shown in FIG. 1, but may have a structure in which the concave portion is filled with a thermosetting resin. However, when the recess is filled with a thermosetting resin, it is desirable to cover the upper surface of the blind via hole 8 with a plating film such as Cu plating. The thermosetting resin filled in the recesses can be either a conductive material or an insulating material, but the conductive material is preferable in view of reliability with electrical conduction. .

  Next, an embodiment of a method for manufacturing an electronic component built-in substrate according to the present invention will be described with reference to the drawings.

  FIG. 2 is a manufacturing process sectional view of the electronic component built-in substrate according to the first embodiment of the present invention.

  As shown in FIG. 2A, the first conductive pattern of the multilayer wiring board including the first conductive pattern 2 disposed on the upper surface of the first insulating layer 1, the second conductive pattern 6 and the inner via 13. A first plating film 3 made of Au plating is formed on the second and second conductive patterns 6. Thereafter, the electronic component 5 made of a semiconductor bare chip IC having bumps 10 formed on the electrodes is flip-chip mounted on the first conductive pattern 2.

  Next, as shown in FIG. 2B, a mounting material 26 is formed on the second conductive pattern 6 by a method such as thick film printing by screen printing, material application by a dispenser, or material transfer by a stamper. A metal mass 27 is mounted on the material 26. Solder or conductive adhesive can be used for the mounting material 26. When solder is used, the metal block 27 is fixed on the second conductive pattern 6 by a reflow process after the metal block 27 is mounted. When a conductive adhesive is used, the conductive adhesive is cured using an oven or the like, and the metal block 27 is fixed on the second conductive pattern 6. When solder is used for the mounting material 26, it is important to sufficiently perform flux cleaning after mounting.

  Next, as shown in FIG. 2C, the electronic component 5 and the metal block 27 are mounted on the surface of the first insulating layer 1 on which the electronic component 5 and the metal block 27 have been mounted. The prepregs 4a and 4b and the metal foil 17 are overlapped at a desired position so as to cover the mass 27.

  The first insulating layer 1 and the prepregs 4a and 4b are preferably made of the same composition material in order to prevent warping or deformation of the substrate. However, when different materials are used, the difference in linear expansion coefficient is different. It is important to select a small material.

  In addition, a space 14 and a space 29 are formed in the prepreg 4 a so as not to contact the electronic component 5 and the metal block 27. Even when a plurality of electronic components 5 are mounted (not shown), the space 14 is a single space that surrounds the entire mounting area. The space 29 may be a space corresponding to each of the metal blocks 27 or may include a plurality of metal blocks 27 in one space 29, but when the prepreg 4a is overlaid, It is important to form the space 14 and the space 29 so as not to contact the electronic component 5 and the metal block 27. Further, the prepreg 4a is formed to be thicker than the height from the first insulating layer 1 after the electronic component 5 is mounted so that the electronic component 5 is not pressurized by contacting the electronic component 5 after the hot pressing. There is a need.

  On the other hand, to make the prepreg 4a thick in order to avoid contact with the electronic component 5, it is difficult to avoid high cost because it is a custom-made product and is not suitable for mass production. It is. Accordingly, the prepreg 4a has a desired thickness by using a plurality of prepregs having a general thickness (for example, 100 μm) that are normally used when manufacturing a wiring board.

  The prepregs 4a and 4b are a mixed sheet of a woven or non-woven fabric and an uncured thermosetting resin, or a mixture of an inorganic filler and a thermosetting resin. The prepregs 4a and 4b are heated and heated. By pressing, the thermosetting resin softened from the prepregs 4a and 4b flows out, and is always thinner than the initial thickness after the completion of heating and pressurization. For this reason, if the thickness reduction is designed in advance, it is possible to prevent the prepreg 4b from coming into contact with the electronic component 5 even after lamination. Furthermore, by using a plurality of prepregs 4a, it is possible to sufficiently secure the amount of thermosetting resin flowing out from the prepreg 4a during heating and pressurization, and thus when there are a plurality of electronic components 5 ( Even in a large space 14 that can be formed (not shown), the gap can be reliably filled with the thermosetting resin.

  In FIG. 2C, the prepreg 4b in which the spaces 14 and 29 are not formed is arranged on the prepreg 4a in which the spaces 14 and 29 are formed. It is also possible.

  Due to the characteristics of the prepregs 4a and 4b described above, as shown in FIG. 2 (d), the prepregs 4a and 4b are formed by pressing the laminated constituent materials while heating them with a press machine (not shown). The second insulating layer 4 can be formed by curing.

Next, as shown in FIG. 2 (e), the hole 18 is processed at a desired position of the metal foil 17 and the second insulating layer 4 to expose the metal block 27. As a processing method of the metal foil 17, a processing method such as a subtractive method by etching, a laser processing by a CO ₂ laser or a YAG laser, and a drill processing can be used. Further, the processing method of the second insulating layer 4, it is possible to use a processing method by laser machining, or drilling by CO ₂ laser or YAG laser. In addition, after exposing the metal block 27 by various processing methods, it is important to perform cleaning (desmear treatment) of the 18-hole portion.

  After completion of the desmear process, the second plating film 9 is formed so as to electrically connect the metal foil 17 and the metal lump 27 through the holes 18 as shown in FIG. For example, after nucleating Pd, the second plating film 9 forms an electroless Cu plating film, and further forms an electrolytic Cu plating film thereon to form a stable Cu plating film. The Cu plating film usually needs to have a thickness of about 20 to 30 μm in order to ensure connection reliability.

  The second plating film 9 is not limited to the above-described method, and various plating films such as Zn, Ni, Ti, Cr, Sn, Ag, and Au may be used as long as the second plating film 9 is a plating material that can react with the metal block 27. Is possible.

  Next, as shown in FIG. 2 (g), the metal foil 17 is patterned into a desired shape to form a third conductive pattern 7. If necessary, as shown in FIG. A solder resist 12 is formed on the back surface to form an electronic component built-in substrate. In FIG. 2H, the solder resist 12 is formed on both the front and back surfaces, but there are cases where only one side is formed or the solder resist 12 is not formed on both sides. The structure can be selected depending on the required substrate shape.

  Hereinafter, the characteristics of the electronic component built-in substrate and the manufacturing method thereof shown in the first embodiment will be described.

  In the electronic component built-in substrate of the present invention, the electronic component 5 made of a semiconductor bare chip IC is mounted on the first conductive pattern 2 on the first insulating layer 1, and the metal block 27 is mounted on the second conductive pattern 6. After that, the structure is built in the second insulating layer 4 and is electrically connected by the blind via hole 8. The electronic component 5 is mounted using a flip-chip mounting method in which the functional element surface is mounted on the first conductive pattern 2 so as to stabilize the electrical continuity. Instead of mounting the electronic component 5 directly on the first conductive pattern 2, the first plating film 3 made of Au plating whose surface is not easily oxidized is formed on the first conductive pattern 2. Due to the presence of the first plating film 3 made of the Au plating film, the electronic component 5 can be mounted on the first conductive pattern 2 while ensuring electrical continuity. Then, by mounting the metal block 27 lower than the height after mounting the electronic component 5 on the second conductive pattern 6, the second insulating layer 4 has a thickness caused by the height of the electronic component 5. This eliminates the need for a step of polishing and thinning the second insulating layer 4 and does not apply unnecessary stress to the electronic component 5 due to the polishing. Can be eliminated. Further, due to the presence of the metal block 27, the depth of the via hole 8 that electrically connects the third conductive pattern 7 and the second conductive pattern 6 is reduced to a shallow structure from the third conductive pattern 7 to the metal block 27. Therefore, the stable second plating film 9 can be formed in the via hole 8.

  As described above, according to the first embodiment, since the metal block 27 lower than the height after the electronic component 5 is mounted is formed on the second conductive pattern 6, the thickness of the second insulating layer 4 is increased. Since the via hole 8 connecting the second conductive pattern 6 and the third conductive pattern 7 can be made shallow without increasing the thickness, a stable second plating film 9 can be formed in the via hole 8. It can be done.

(Embodiment 2)
Hereinafter, Embodiment 2 according to the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view of an electronic component built-in substrate according to Embodiment 2 of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  The main difference between the second embodiment and the first embodiment is that a resist film 19 is formed around the second conductive pattern 6 as shown in FIG. By forming the resist film 19 around the second conductive pattern 6, the mounting material 26 formed when the metal block 27 is mounted on the second conductive pattern 6 spreads outside the second conductive pattern 6. Can be prevented. Therefore, it is possible to prevent a short circuit failure between the adjacent second conductive patterns 6 due to the mounting material 26. At this time, the resist film 19 has a structure in which an outer wall is formed on the outer periphery of the second conductive pattern 6, and the resist film 19 preferably has a width of about 100 to 500 μm. This is because, in the case of a design in which the width of the resist film 19 is 100 μm or less, the formation yield of the resist film 19 is extremely deteriorated. If the width of the resist film 19 becomes too wide, the resist film 19 in contact with the second insulating layer 4 becomes large. However, since the resist film 19 is generally a water-repellent material, Almost no adhesion and easy peeling. Therefore, it is important to reduce the width of the resist film 19 as much as possible to reduce the number of contacts with the second insulating layer 4. Therefore, the resist film 19 is set to a width of about 100 to 500 μm.

  As in the first embodiment, the mounting material 26 can be solder or a conductive adhesive.

(Embodiment 3)
Hereinafter, Embodiment 2 according to the present invention will be described with reference to the drawings. FIG. 4 is a cross-sectional view of an electronic component built-in substrate according to Embodiment 3 of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  As shown in FIG. 4, the main difference between the third embodiment and the first embodiment is that an electronic component 5 made of a semiconductor bare chip IC is used in a mounting auxiliary material 11 as an ACF (Anisotropic Conductive Film). A pressure contact connection method using Au bumps using an anisotropic conductive film) or NCF (Non Conductive Film) or a method of filling an underfill between the electronic component 5 and the first insulating layer 1 after mounting the electronic component 5 Used. Note that the present invention is not limited to the above-described method, and any method can be used as long as it is a flip-chip mounting method in which the semiconductor bare chip IC is mounted face-down using the mounting auxiliary material 11.

  When the electronic component 5 adopting the mounting method using the mounting auxiliary material 11 is built in the second insulating layer 4, a space 14 larger than the electronic component 5 is provided in the prepreg 4a as in the first embodiment as shown in FIG. However, the mounting auxiliary material 11 protrudes around the electronic component 5, and a space 14 larger than the mounting auxiliary material 11 is formed so as to surround the protruding mounting auxiliary material 11. is important. Due to the presence of the space 14 larger than the mounting auxiliary material 11, it is possible to prevent pressure from being applied to the electronic component 5 when the prepreg 4 a contacts the electronic component 5.

  Note that the third embodiment may have a structure in which the resist film 19 is formed on the outer periphery of the second conductive pattern 6 as in the second embodiment.

(Embodiment 4)
Embodiment 4 according to the present invention will be described below with reference to the drawings. FIG. 5 is a cross-sectional view of a manufacturing process of an electronic component built-in substrate according to Embodiment 4 of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  The main difference between the third embodiment and the first embodiment is that, as shown in FIG. 5 (c), the prepreg 4a forms a single space 30 that can enclose all of the electronic component 5 and the metal block 27. is doing. Thus, by making one space 30, the processing of the space 30 can be easily performed, the distance between the electronic component 5 and the inner wall of the space 30 is increased, and the distance between the electronic component 5 and the inner wall of the space 30 is increased. Since the metal lump 27 exists between them, it is possible to prevent the pressure from the prepreg 4a from being applied directly to the electronic component 5 at the time of hot pressing, and the connection reliability of the electronic component 5 can be stabilized.

(Embodiment 5)
Embodiment 5 according to the present invention will be described below with reference to the drawings. FIG. 6 is a cross-sectional view of a manufacturing process of an electronic component built-in substrate according to Embodiment 5 of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  The main difference between the fifth embodiment and the first embodiment is that the metal foil 17 is not used on the prepreg 4b as shown in FIG. 6C, and only the prepregs 4a and 4b are formed on the first insulating layer 1. They are stacked and integrated by a heating press (not shown). Thereafter, as shown in FIG. 6E, a desired position of the second insulating layer 4 is processed to expose the metal block 27. About the processing method, it can process by the method similar to Embodiment 1. FIG. After the completion of processing, the second plating film 9 is formed in the processed hole 18 and the metal block 27 while forming the second plating film 9 on the upper surface of the second insulating layer 4.

  In the fifth embodiment, since the metal foil 17 is not used as compared with the first embodiment, the processing of the metal foil 17 is not required when forming the hole 18, so that the processing process is simplified and the processing time is shortened. Is possible. Further, even when the third conductive pattern 7 is formed by patterning after the second plating film 9 is formed, there is no film thickness (for example, 18 μm) related to the metal foil 17, so the film thickness of the second plating film 9 (for example, 20 μm). Since the third conductive pattern 7 can be processed by only etching), the processing time can be shortened.

(Embodiment 6)
Embodiment 6 according to the present invention will be described below with reference to the drawings. FIG. 7 is a cross-sectional view of a receiving device or electronic apparatus using the electronic component built-in substrate of the present invention. Unless otherwise described, the same structure as that of the first embodiment is given the same number and the description thereof is omitted.

  In the sixth embodiment, as shown in FIG. 7, the electronic component built-in substrate manufactured in the first embodiment is used, and the electronic component 24 is mounted on the surface using the solder 23. I am making equipment. By using the electronic component built-in substrate, it is possible to reduce the size of the receiving device or the electronic device as compared with the case where the electronic component built-in substrate is not used.

  The electronic component built-in substrate according to the present invention, the electronic device using the same, and the method for manufacturing the same can produce the electronic component built-in substrate in which the semiconductor bare chip IC is built in the substrate in a simple process. Since the connection reliability of electronic components can be improved, it can be used, for example, in the manufacture of an ultra-small three-dimensional mounting module.

Sectional drawing of the electronic component built-in substrate in Embodiment 1 of this invention (A) to (h) are cross-sectional views of the manufacturing process of the electronic component built-in substrate according to the first embodiment of the present invention. Sectional drawing of the electronic component built-in substrate in Embodiment 2 of this invention Sectional drawing of the electronic component built-in substrate in Embodiment 3 of this invention (A) to (h) are cross-sectional views of the manufacturing process of the electronic component built-in substrate according to Embodiment 4 of the present invention. (A) to (h) are cross-sectional views of the manufacturing process of the electronic component built-in substrate according to the fifth embodiment of the present invention. Sectional drawing of the receiver or electronic device in Embodiment 6 of this invention Sectional view of the electronic component built-in substrate manufactured by the conventional manufacturing method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st insulating layer 2 1st electroconductive pattern 3 1st plating film 4 2nd insulating layer 5 Electronic component 6 2nd electroconductive pattern 7 3rd electroconductive pattern 8 Via hole 9 2nd plating film 10 Bump 11 Mounting auxiliary material 12 Solder resist 13 Inner via 19 Resist film 26 Mounting material 27 Metal lump

Claims (32)

A first insulating layer;
A first conductive pattern and a second conductive pattern made of a first metal provided on the upper surface of the first insulating layer;
A first plating film made of a second metal formed on upper surfaces of the first conductive pattern and the second conductive pattern;
A metal block provided so as to be electrically connected to the second conductive pattern via the first plating film on the second conductive pattern;
An electronic component connected to the first conductive pattern via the first plating film and the bump;
A second insulating layer provided on the first insulating layer so as to cover the metal block and the electronic component;
A third conductive pattern made of the first metal provided on an upper surface of the second insulating layer;
An electronic component built-in substrate comprising a via hole penetrating the second insulating layer and electrically connecting the metal block and the third conductive pattern by a second plating film. The electronic component built-in substrate according to claim 1, wherein the second plating film is made of a first metal. The electronic component built-in substrate according to claim 1, wherein the first metal is Cu, and the second metal is Au. The electronic component built-in substrate according to claim 1, wherein the second plating film is made of at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. The electronic component built-in substrate according to claim 1, wherein the bump is made of at least Au, Sn, or Ag. The electronic component built-in substrate according to claim 1, wherein the metal block includes at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. The electronic component built-in substrate according to claim 1, wherein a height of the metal block is lower than a sum of a height of the electronic component and a height of the bump. The electronic component built-in substrate according to claim 1, wherein the metal block is fixed on the second conductive pattern by solder. The electronic component built-in substrate according to claim 7, wherein the solder is Pb-free solder. The electronic component built-in substrate according to claim 1, wherein the metal block is fixed on the second conductive pattern by a conductive adhesive. The electronic component built-in substrate according to claim 1, wherein the metal block is substantially spherical. The electronic component built-in substrate according to claim 1, wherein a resist film is formed on an upper surface of the first insulating layer so as to surround an outer periphery of the second conductive pattern. A first insulating layer;
A first conductive pattern and a second conductive pattern made of a first metal provided on the upper surface of the first insulating layer;
A first plating film made of a second metal formed on upper surfaces of the first conductive pattern and the second conductive pattern;
A metal block provided so as to be electrically connected to the second conductive pattern via the first plating film on the second conductive pattern;
An electronic component connected to the first conductive pattern via the first plating film and the bump;
A second insulating layer provided on the first insulating layer so as to cover the metal block and the electronic component;
A third conductive pattern made of the first metal provided on an upper surface of the second insulating layer;
A receiver having an electronic component built-in substrate that includes a via hole that penetrates the second insulating layer and electrically connects the metal block and the third conductive pattern with a second plating film. A first insulating layer;
A first conductive pattern and a second conductive pattern made of a first metal provided on the upper surface of the first insulating layer;
A first plating film made of a second metal formed on upper surfaces of the first conductive pattern and the second conductive pattern;
A metal block provided so as to be electrically connected to the second conductive pattern via the first plating film on the second conductive pattern;
An electronic component connected to the first conductive pattern via the first plating film and the bump;
A second insulating layer provided on the first insulating layer so as to cover the metal block and the electronic component;
A third conductive pattern made of the first metal provided on an upper surface of the second insulating layer;
An electronic apparatus having an electronic component built-in substrate that includes a via hole that penetrates the second insulating layer and electrically connects the metal block and the third conductive pattern with a second plating film. A first conductive pattern and a second conductive pattern made of a first metal are formed on the upper surface, and a first plating film made of a second metal is formed on the first conductive pattern and the second conductive pattern. Mounting an electronic component via a bump on the first plating film on the top surface of the first conductive pattern of one insulating layer;
Mounting a metal block on the first plating film on the upper surface of the second conductive pattern;
Laminating a second insulating layer on the first insulating layer so as to cover the electronic component and the metal block;
Laminating a metal foil made of the first metal on the second insulating layer;
A step of pressurizing and integrating the laminated first insulating layer, the second insulating layer, and the metal foil;
A step of drilling a predetermined position of the metal foil to expose the second insulating layer;
Processing the second insulating layer to expose the metal mass;
Electrically connecting the metal mass and the metal foil by a second plating film;
And a step of forming the third conductive pattern by processing the metal foil. A first conductive pattern and a second conductive pattern made of a first metal are formed on the upper surface, and a first plating film made of a second metal is formed on the first conductive pattern and the second conductive pattern. Mounting an electronic component via a bump on the first plating film on the top surface of the first conductive pattern of one insulating layer;
Mounting a metal block on the first plating film on the upper surface of the second conductive pattern;
Laminating a second insulating layer on the first insulating layer so as to cover the electronic component and the metal block;
A step of pressing and integrating the laminated first insulating layer and second insulating layer while heating;
Processing the second insulating layer to expose the metal mass;
A method of manufacturing an electronic component built-in substrate, comprising: forming a third conductive pattern on the upper surface of the second insulating layer by a second plating film; and electrically connecting the metal block to the metal block. The method for manufacturing an electronic component built-in substrate according to claim 15, wherein the second plating film is made of a first metal. The method of manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the first metal is Cu, and the second metal is Au. The method of manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the second plating film is made of at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. The method of manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the bump is made of at least Au, Sn, or Ag. The method for manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the second insulating layer is made of a prepreg in which at least one woven fabric or nonwoven fabric is impregnated with a thermosetting resin. A gap larger than the electronic component and a gap approximately equal to or larger than the metal block are formed in the second insulating layer before the stacking, and the gap corresponding to the electronic component and the metal block is stacked when the second insulating layer is stacked. The method for manufacturing an electronic component-embedded substrate according to claim 15, wherein the electronic component-embedded substrate is disposed inside. One gap is formed in the second insulating layer before the stacking so as to surround the electronic component and the metal block, and all the electronic component and the metal block are stacked before the second insulating layer is stacked. The method for manufacturing an electronic component built-in substrate according to claim 15, wherein the electronic component-embedded substrate is disposed in the gap. The method of manufacturing an electronic component built-in substrate according to claim 15 or 16, wherein the step of exposing the metal block is performed by laser processing or drilling. The method of manufacturing a substrate with built-in electronic component according to claim 15 or 16, wherein the metal block includes at least one of Cu, Pd, Zn, Ni, Ti, Cr, Sn, Ag, and Au. 17. The method for manufacturing an electronic component built-in substrate according to claim 15, wherein a height of the metal block is lower than a sum of a height of the electronic component and a height of the bump. The method for manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the metal block is fixed on the second conductive pattern by solder. The method of manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the solder is Pb-free solder. The method for manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the metal block is fixed on the second conductive pattern by a conductive adhesive. The method for manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein the metal block is substantially spherical. The method for manufacturing a substrate with built-in electronic components according to claim 15 or 16, wherein a resist film is formed on an upper surface of the first insulating layer so as to surround an outer periphery of the second conductive pattern. The method of manufacturing a substrate with built-in electronic component according to claim 16, wherein the third conductive pattern is patterned into a desired shape after forming the second plating film on substantially the entire upper surface of the second insulating layer.

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