JP2008182281A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the space of an isolation region at the boundary part of an SOI region and a bulk region. <P>SOLUTION: The semiconductor device comprises a substrate 11 having first and second regions, a first insulating film 12 provided on the substrate in the first region, a first epitaxial layer 17 provided on the substrate in the second region and having an upper surface higher than that of the first insulating film, and a first semiconductor layer 13 provided on the first insulating film with a gap 15 between the first epitaxial layer, having an upper surface substantially flush with that of the first epitaxial layer, and having a tapered face 62 facing the side surface of the first epitaxial layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a hybrid wafer having an SOI (Silicon On Insulator) region and a bulk region.

  In recent years, a thin-film SOI (Silicon On Insulator) wafer is used in place of a conventional silicon wafer, and elements are formed on the SOI wafer, thereby reducing parasitic capacitance and reducing the power consumption and speed of logic circuits. Attempts have been actively made, and the commercialization of microprocessors using SOI wafers has also begun. In the future, the need for a system LSI chip with such SOI logic as the core is expected to increase.

  However, in the MOSFET on the SOI wafer, since the potential of the body region where the channel is formed is in a floating state, a leak current is generated and a threshold value is changed due to a circuit operation due to a so-called substrate floating effect. For this reason, the SOI wafer is unsuitable for application to a circuit having strict specifications on the leakage current level or matching characteristics, such as a DRAM cell transistor, a sense amplifier circuit, and an analog circuit pair transistor.

  In order to solve this problem, there is a proposal to prepare a hybrid wafer in which a bulk region is formed on an SOI wafer and to form a circuit that is not suitable for an SOI wafer such as a DRAM in the bulk region. Specifically, for example, there are the following methods.

  First, there is a method in which an SOI region is selectively formed on a bulk wafer by a SIMOX (Separation by IMplantation of Oxygen) method using a mask pattern (see Patent Document 1 and Non-Patent Document 1).

  Second, there is a method in which another wafer is bonded onto a bulk wafer patterned with an insulating film (see Patent Document 2).

  Thirdly, there is a method in which the SOI layer and the buried insulating film on the SOI wafer are partially removed by etching (see Patent Document 3, Patent Document 4, and Patent Document 5).

  Fourth, in order to eliminate the step generated between the SOI region and the bulk region in the third method, silicon or the like is selectively epitaxially grown on the support substrate in the bulk region, or further planarized by polishing. There are methods (see Patent Document 6 and Non-Patent Document 2).

  In various methods using such a hybrid wafer, the fourth method is excellent in device productivity because there is no step between the device surface in the SOI region and the device surface in the bulk region. Further, since the manufacturing is performed based on a ready-made SOI wafer, it is a technique that can flexibly cope with changes in the film thickness configuration of the SOI layer and the buried insulating film, and the material of the SOI layer such as a silicon layer and a SiGe layer.

  However, the conventional fourth method has the following problems. In describing this problem, the fourth method will be specifically described below.

  First, as shown in FIG. 41, an SOI wafer having a support substrate 111, a buried insulating film 112, and an SOI layer 113 is prepared.

  Next, as shown in FIG. 42, a first mask material (for example, SiN film) 114 for protection is deposited on the SOI layer 113. Next, the first mask material 114, the SOI layer 113, and the buried insulating film 112 in the bulk region are selectively etched away in order. At this time, the thin buried insulating film 112 ′ is left on the support substrate 111.

  Next, as shown in FIG. 43, a second mask material (for example, SiN film) 116 for protecting the sidewall of the SOI layer 113 is deposited on the entire surface. Thereafter, a spacer made of the second mask material 116 is formed on the side surface of the SOI layer 113 by anisotropic dry etching. At this time, a thin buried insulating film 112 ″ on the support substrate 111 is left as in the step of FIG.

  Next, as shown in FIG. 44, the embedded insulating films 112 and 112 ″ are removed using an HF solution or the like so as not to damage the support substrate 111. The mask material on the upper and side surfaces of the SOI layer 113 is removed. Since 114 and 116 are different types of insulating films from the buried insulating film 112, the mask materials 114 and 115 can be left even if the buried insulating films 112 and 112 ″ are removed.

  Next, as shown in FIG. 45, an epitaxial layer 117 is formed on the exposed support substrate 111 by an epitaxial growth technique as an element formation film such as single crystal silicon. In this epitaxial growth, the heights of both layers are aligned so that the upper surface of the epitaxial layer 117 substantially coincides with the upper surface of the SOI layer 113. A facet 161 is generated at the upper end of the epitaxial layer 117 on the SOI region side.

  Next, as shown in FIG. 46, the first mask material 114 is removed. At this time, since the second mask material 116 formed on the side surface of the SOI layer 113 is formed of the same material as the first mask material 114, the second mask material 116 is also removed together with the first mask material 114. As a result, a depression 160 is formed at the boundary between the SOI region and the bulk region.

  Next, as shown in FIG. 47, gate insulating films 120 and 121, gate electrodes 122, 123 and 131, and element isolation regions 118, 119 and 130 having an STI (Shallow Trench Isolation) structure are formed.

In the conventional fourth method as described above, the facet 161 and the depression 160 at the boundary between the SOI region and the bulk region are generated. Therefore, in order to eliminate the facets 161 and the depressions 160, the space of the element isolation region 130 at the boundary between the SOI region and the bulk region has been increased.
Japanese Patent Laid-Open No. 10-303385 JP-A-8-316431 JP-A-7-106434 Japanese Patent Laid-Open No. 11-238860 JP 2000-91534 A Japanese Unexamined Patent Publication No. 2000-243944 Robert Hannon, et al., 2000 Symposium on VLSI Technology of Technical Papers, pp. 66-67 T. Yamada, et al., 2002 Symposium on VLSI Technology of Technical Papers, pp.112-113

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing the space of the element isolation region at the boundary between the SOI region and the bulk region. There is.

  In order to achieve the above object, the present invention uses the following means.

  A semiconductor device according to an aspect of the present invention includes a substrate having first and second regions, a first insulating film provided on the substrate in the first region, and the substrate in the second region. A first epitaxial layer having a top surface higher than the top surface of the first insulating film, and provided on the first insulating film with a gap from the first epitaxial layer; And a first semiconductor layer having a top surface substantially equal to the top surface of the first epitaxial layer and having a tapered surface facing a side surface of the first epitaxial layer.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce the space of the element isolation region in the boundary part of SOI region and a bulk region, and its manufacturing method can be provided.

  The embodiment of the present invention uses a hybrid wafer having an SOI (Silicon On Insulator) region and a bulk region. Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

1. First Embodiment In the first embodiment, at the boundary between the SOI region and the bulk region, the side surface of the SOI layer is retreated in the lateral direction (horizontal direction with respect to the substrate) from the side surface of the buried insulating film to form a gap. Thereafter, a mask material for epitaxial growth is formed in the gap, and the mask material is left as it is to be used as an element isolation region.

  The first to fourth examples according to the first embodiment will be described below.

[1-1] First Example The first example according to the first embodiment is the basic structure of the first embodiment, and a gap is formed between the SOI layer and the epitaxial layer. The provided mask material at the time of epitaxial growth is used as an element isolation region.

  FIG. 1 is a sectional view of a semiconductor device of a first example according to the first embodiment of the present invention. As shown in FIG. 1, in the first example according to the first embodiment, in the SOI region, a buried insulating film 12 is provided on a support substrate 11, and an SOI layer 13 is provided on the buried insulating film 12. ing. On the other hand, in the bulk region, an epitaxial layer 17 is provided on the support substrate 11, and the upper surface of the epitaxial layer 17 is substantially equal to the upper surface of the SOI layer 13.

  Here, since the side surface of the SOI layer 13 on the epitaxial layer 17 side is recessed from the side surface of the buried insulating film 12 on the epitaxial layer 17 side, there is a gap 15 between the SOI layer 13 and the epitaxial layer 17. An element isolation region 16 a is provided on the buried insulating film 12 so as to fill the gap 15. The upper surface of the element isolation insulating film 16 a is substantially equal to the upper surface of the SOI layer 13 and the upper surface of the epitaxial layer 17.

  Thus, the SOI layer 13 in the SOI region and the epitaxial layer 17 in the bulk region are electrically separated by the element isolation region 16a. In other words, the epitaxial layer 17 is in contact with the buried insulating film 12 and the element isolation region 16 a but not in contact with the SOI layer 13.

The element isolation region 16a is preferably formed of the same material (for example, SiO ₂ film) as that of the buried insulating film 12.

  2 to 8 are sectional views showing the manufacturing steps of the semiconductor device of the first example according to the first embodiment of the present invention. The manufacturing method of the first example according to the first embodiment will be described below.

First, as shown in FIG. 2, an SOI wafer having a support substrate 11, a buried insulating film 12, and an SOI layer 13 is prepared. Here, a p-type silicon substrate having a specific resistance of about 10Ω is used as the support substrate 11, a SiO ₂ film having a thickness of about 150 nm is used as the buried insulating film 12, and a single crystal silicon having a thickness of about 50 nm is used as the SOI layer 13. Although a film | membrane is used, it is not limited to these.

Next, as shown in FIG. 3, a first mask material 14 for protection is deposited on the SOI layer 13. The first mask material 14 may be, for example, a SiN film, or may be a material film (for example, a SiO ₂ film) that is the same as the buried insulating film 12 or a second mask material 16 described later. Next, the first mask material 14, the SOI layer 13, and the buried insulating film 12 in the bulk region are sequentially removed by photolithography and anisotropic dry etching (for example, RIE (Reactive Ion Etching)). At this time, it is preferable to leave a thin buried insulating film 12 ′ on the support substrate 11 so as not to give the anisotropic dry etching damage to the support substrate 11 in the bulk region.

  Next, as shown in FIG. 4, the SOI layer 13 is removed by isotropic etching (for example, CDE (Chemical Dry Etching)) so that the exposed side surface of the SOI layer 13 recedes. Thereby, the gap 15 is formed.

Next, as shown in FIG. 5, a second mask material (for example, SiO ₂ film) 16 for protecting the sidewall of the SOI layer 13 is deposited on the entire surface. Here, by setting the film thickness Y of the second mask material 16 to ½ or more of the film thickness Z of the SOI layer 13, the length of the side surface of the SOI layer 13 receded from the side surface of the buried insulating film 12. The gap portion 15 can be easily embedded with the second mask material 16 without depending on the width X of the gap portion 15 corresponding to the thickness.

Next, as shown in FIG. 6, the second mask material 16 and the buried insulating film 12 ′ are removed by isotropic etching. As this isotropic etching, wet etching using HF solution, NH ₄ F solution or the like can be used. In this way, the element isolation region 16a made of the second mask material 16 is formed in the gap portion 15, and the upper surface of the support substrate 11 in the bulk region is exposed. It should be noted that the length X to be retracted and the film thickness Y of the second mask material 16 are set in consideration of the etching amount in this step so that the mask material 16 to be the element isolation region 16a remains in the gap 15. .

  Next, as shown in FIG. 7, an epitaxial layer 17 is formed on the exposed support substrate 11 as an element formation film such as single crystal silicon by an epitaxial growth technique. In this epitaxial growth, the height of the epitaxial layer 17 is adjusted so that the upper surface of the epitaxial layer 17 substantially coincides with the upper surface of the SOI layer 13.

  In this epitaxial growth, the entire surface may be grown and the epitaxial layer 17 may be planarized to the height of the mask material 14 by CMP (Chemical Mechanical Polish). However, in this case, a difference in height between the SOI layer 13 and the epitaxial layer 17 is caused by the thickness of the mask material 14, and the flatness and crystallinity of the epitaxial layer 17 may be deteriorated by dishing or scratching. Moreover, it is not very preferable in terms of cost.

  Next, as shown in FIG. 8, after the epitaxial growth, the first mask material 14 is removed.

  Next, as shown in FIG. 1, gate insulating films 20 and 21, gate electrodes 22 and 23, and element isolation regions 18 and 19 having an STI (Shallow Trench Isolation) structure are formed.

  According to the first example of the first embodiment, the following effects can be obtained.

  (1) By retreating the side surface of the SOI layer 13 from the side surface of the buried insulating film 12 and providing a gap portion 15 between the SOI layer 13 and the epitaxial layer 17, the SOI layer 13 formed in the gap portion 15 The mask material 16 can be used as it is as the element isolation region 16a. For this reason, since it is not necessary to remove the mask material 116 as in the above-described conventional fourth method, the depression 160 generated when the mask material 116 is removed does not occur. Accordingly, since it is not necessary to form a large space element isolation region for eliminating the depression 160, the space of the element isolation region 16a at the boundary between the SOI region and the bulk region can be reduced. Furthermore, the depth of the element isolation region 16a at the boundary can be reduced to the equivalent of the film thickness of the SOI layer 13.

  (2) In the fourth conventional method, after the depression 160 is generated, the material of the electrode 131 is embedded in the depression 160, and the element isolation region 130 is formed so as to eliminate the depression 160. . For this reason, if the electrode material is deeply embedded in the recess 160, the electrode material may remain as a residue in the recess 160 even after the element isolation region 130 is processed, and the gate electrode crosses the same boundary between the SOI region and the bulk region. There was a risk that a short-circuit failure would occur across a plurality of crossings.

  On the other hand, according to the first example according to the first embodiment, as described above, since the conventional depression 160 does not occur, the above-described problem of short circuit failure can be avoided.

  (3) In the above-described conventional fourth method, in the step of removing the buried insulating film 112 ″ (step of FIG. 44), the side surface of the SOI layer 113 is different from the buried insulating film 112 on the side surface so that the side surface is not etched. The second mask material 116 made of a material is provided, and therefore, when an etching condition is set such that only the buried insulating film 112 is removed, the second mask material 116 is not etched, so that only the buried insulating film 112 is formed. There was a case where an overhang was generated in which the side surface of the buried insulating film 112 was recessed rather than the side surface of the second mask material 116. Then, when the epitaxial layer 117 was formed in a state where this overhang occurred, Cavities and crystal defects occur in the overhanged part.

On the other hand, according to the first example of the first embodiment, the element isolation region 16a can be formed of the same material (for example, SiO ₂ film) as the buried insulating film 12. Accordingly, in the step of removing the buried insulating film 12 ′ (step of FIG. 6), the buried insulating film 12 ′ and the mask material 16 can be removed simultaneously while preventing the side surface of the SOI layer 13 from being etched. The conventional overhang problem does not occur. As a result, there is no possibility that cavities or crystal defects are generated in the epitaxial layer 17 due to overhang.

[1-2] Second Example A second example according to the first embodiment is a part that electrically connects the SOI layer and the epitaxial layer in a region between the SOI region and the bulk region. Are provided respectively.

  FIG. 9 is a cross-sectional view of the semiconductor device in a portion where the SOI layer and the epitaxial layer are electrically connected to the portion that is electrically insulated in the second example according to the first embodiment of the present invention.

  In FIG. 9, a region on the left side of the drawing (hereinafter referred to as an insulating region) indicates a portion where the SOI layer 13-A and the epitaxial layer 17-A are electrically insulated. Since this insulating region has the same structure as that of the first example according to the first embodiment, description thereof will be omitted.

  On the other hand, in FIG. 9, a region on the right side of the drawing (hereinafter referred to as a conduction region) indicates a portion where the SOI layer 13-B and the epitaxial layer 17-B are electrically connected. That is, the SOI layer 13-B and the epitaxial layer 17-B are in direct contact with each other. Other structures are the same as those of the insulating region.

  10 to 15 are cross-sectional views showing a manufacturing process of the semiconductor device of the second example according to the first embodiment of the present invention. The manufacturing method of the second example according to the first embodiment will be described below. Here, the description of the insulating region having the same structure as that of the first example is simplified.

  First, as shown in FIG. 10, in the conductive region, as in the first example, after the thin buried insulating film 12′-B is left, the resist 25 is formed, and the side surface of the SOI layer 13-B is Covered. Next, the gap 15 is formed in the insulating region. At this time, in the conduction region, the side surface of the SOI layer 13 -B is covered with the resist 25, so the gap portion 15 is not formed.

  Next, as shown in FIG. 11, the resist 25 in the conduction region is removed.

Next, as shown in FIG. 12, a second mask material (for example, SiO ₂ film) 16 is deposited on the entire surface. In the insulating region, the second mask material 16 is formed in the gap 15.

Next, as shown in FIG. 13, the second mask material 16 and the buried insulating films 12′-A and 12′-B are removed by wet etching using an HF solution, an NH ₄ F solution, or the like. Thereby, the upper surfaces of the support substrates 11-A and 11-B in the bulk region are exposed. In the insulating region, an element isolation region 16 a made of the second mask material 16 is formed in the gap portion 15.

  Next, as shown in FIG. 14, epitaxial layers 17-A and 17-B are formed on the exposed support substrates 11-A and 11-B as an element formation film such as single crystal silicon by an epitaxial growth technique. The In this epitaxial growth, the heights of the epitaxial layers 17-A and 17-B are adjusted so that the upper surfaces thereof substantially coincide with the upper surfaces of the SOI layers 13-A and 13-B. In the conductive region, the SOI layer 13-B and the epitaxial layer 17-B are in direct contact with each other. However, in the insulating region, the element isolation region 16a exists, and thus the SOI layer 13-A and the epitaxial layer 17-A are not in direct contact with each other. .

  Next, as shown in FIG. 15, the first mask materials 14-A and 14-B are removed.

  Next, as shown in FIG. 9, the gate insulating films 20-A, 20-B, 21-A, 21-B, the gate electrodes 22-A, 22-B, 23-A, 23-B, and the STI structure. Element isolation regions 18-A, 18-B, 19-A, and 19-B are formed, respectively.

  According to the second example according to the first embodiment, the same effect as that of the first example according to the first embodiment can be obtained in the insulating region. Further, since the SOI layer 13-B and the epitaxial layer 17-B are in direct contact with each other in the conductive region, it is effective when it is desired to electrically connect both.

[1-3] Third Example In the third example according to the first embodiment, when facets are generated by epitaxial growth, the facets are removed without using the mask material in the first example as an element isolation region as it is. Thus, the element isolation region is newly formed.

  FIG. 16 is a sectional view of a third example semiconductor device according to the first embodiment of the present invention. As shown in FIG. 16, in the third example according to the first embodiment, the part different from the first example is that an element isolation region 30 that is not a mask material is formed in order to remove the facet of the epitaxial layer 17. It is being formed again. The element isolation region 30 is formed from the SOI layer 13 to the epitaxial layer 17. The element isolation region 30 may be formed to penetrate the buried insulating film 12 and into the substrate 11. However, the SOI layer 13 and the epitaxial layer 17 may be electrically insulated from each other. 11 does not need to be formed.

  17 and 18 are cross-sectional views showing a manufacturing process of the semiconductor device of the third example according to the first embodiment of the present invention. The manufacturing method of the third example according to the first embodiment will be described below. Here, only a region having a structure different from that of the first example will be described.

  First, as shown in FIG. 17, an epitaxial layer 17 is formed on the exposed support substrate 11 by an epitaxial growth technique as an element formation film such as single crystal silicon. In this epitaxial growth, the height of the epitaxial layer 17 is adjusted so that the upper surface of the epitaxial layer 17 substantially coincides with the upper surface of the SOI layer 13, but a facet 26 may be formed at the upper end of the epitaxial layer 17 on the SOI region side.

  Next, as shown in FIG. 18, the first mask material 14 is removed.

  Next, as shown in FIG. 16, after the gate insulating films 20 and 21 are formed, an element isolation region 30 having an STI structure is formed so as to eliminate facets, and at the same time, element isolation in the SOI region and the bulk region is performed. Regions 18 and 19 are also formed. Thereafter, gate electrodes 22, 23, and 31 are formed, respectively.

  According to the third example of the first embodiment, since the element isolation region 30 is formed so that the facet is eliminated at the boundary between the SOI region and the bulk region, the facet is generated after the epitaxial growth in the first example. It is effective in the case.

  The element isolation region 30 of the third example has a larger space than the element isolation region 16a of the first example. However, the element isolation region 30 is not formed so as to eliminate the deep depression 160 as in the prior art. Needless to say, the space of the element isolation region can be sufficiently reduced.

[1-4] Fourth Example The element isolation region at the boundary between the SOI region and the bulk region is formed only between the SOI layer and the epitaxial layer in the first example according to the first embodiment. In the fourth example according to the first embodiment, it is formed between the buried insulating film and the epitaxial layer in addition to between the SOI layer and the epitaxial layer.

  FIG. 19 is a sectional view of a fourth example semiconductor device according to the first embodiment of the present invention. As shown in FIG. 19, in the fourth example according to the first embodiment, the position where the element isolation region 16a is formed is different from that in the first example. That is, the element isolation region 16 a is formed between the buried insulating film 12 and the epitaxial layer 17 in addition to between the SOI layer 13 and the epitaxial layer 17.

  Here, the side surface of the buried insulating film 12 on the epitaxial layer 17 side is recessed from the side surface of the SOI layer 13 on the epitaxial layer 17 side, and the buried insulation is larger than the width of the gap 15 between the SOI layer 13 and the epitaxial layer 17. The width of the gap 35 between the film 12 and the epitaxial layer 17 is larger. In other words, the side surface of the SOI layer 13 on the epitaxial layer 17 side protrudes from the side surface of the buried insulating film 12 on the epitaxial layer 17 side.

  If the contact surface between the element isolation region 16a and the epitaxial layer 17 is large as in the fourth example, the element isolation region 16a is formed of a SiN film in order to suppress facet during epitaxial growth. preferable.

  20 to 25 are sectional views showing steps in manufacturing the semiconductor device of the fourth example according to the first embodiment of the present invention. The manufacturing method of the fourth example according to the first embodiment will be described below. Here, only a region having a structure different from that of the first example will be described.

First, as shown in FIG. 20, a first mask material 14 for protection is deposited on an SOI wafer having a support substrate 11, a buried insulating film 12, and an SOI layer 13. The first mask material 14 may be formed of, for example, a SiN film or a SiO ₂ film, but is preferably formed of a film made of a material different from that of the buried insulating film 12. Next, the first mask material 14, the SOI layer 13, and the buried insulating film 12 in the bulk region are sequentially etched away by anisotropic etching (for example, RIE). At this time, it is preferable to leave a thin buried insulating film 12 ′ on the support substrate 11 so as not to give the anisotropic dry etching damage to the support substrate 11 in the bulk region. Then, the side surface of the SOI layer 13 is made to recede from the side surface of the buried insulating film 12 to form a gap portion 15.

  Next, as shown in FIG. 21, the buried insulating film 12 is etched by isotropic etching so that the side surface of the buried insulating film 12 recedes from the side surface of the first mask material 14, and the gap 35 is formed. It is formed.

  Next, as shown in FIG. 22, a second mask material (for example, SiN film) 16 for protecting the sidewall of the SOI layer 13 is deposited on the entire surface.

  Next, as shown in FIG. 23, the second mask material 16 and the buried insulating film 12 'are removed by isotropic etching. In this manner, the element isolation region 16a made of the second mask material 16 is formed in the gaps 15 and 35, and the upper surface of the support substrate 11 in the bulk region is exposed.

  Next, as shown in FIG. 24, an epitaxial layer 17 is formed on the exposed support substrate 11 as an element formation film such as single crystal silicon by an epitaxial growth technique. In this epitaxial growth, the height of the epitaxial layer 17 is adjusted so that the upper surface of the epitaxial layer 17 substantially coincides with the upper surface of the SOI layer 13.

  Next, as shown in FIG. 25, after the epitaxial growth, the first mask material 14 is removed.

  Next, as shown in FIG. 19, gate insulating films 20 and 21, gate electrodes 22, 23 and 31, and element isolation regions 18 and 19 having an STI structure are formed.

  According to the fourth example of the first embodiment, as in the first example, the mask material 16 of the SOI layer 13 during epitaxial growth can be used as it is as the element isolation region 16a. The space of the separation region can be reduced.

  Although the element isolation region 16a of the fourth example has a larger space than the element isolation region 16a of the first example, it is not formed to eliminate the deep recess 160 as in the prior art, so that However, it goes without saying that the space of the element isolation region (particularly the lateral width of the element isolation region) can be sufficiently reduced.

The element isolation region 16a is formed of a SiN film that is a different material from the buried insulating film 12. Here, in selective epitaxial growth, the facet can be reduced (or facet can be eliminated) when the epitaxial layer 17 forms the boundary surface with the SiN film rather than when the boundary surface is formed with the SiO ₂ film. It is known. Therefore, the facet at the boundary between the element isolation region 16a and the epitaxial layer 17 can be suppressed by providing the element isolation region 16a made of the SiN film.

  Although the case where the side surface of the buried insulating film 12 recedes from the side surface of the SOI layer 13 is shown here, the side surfaces of the both sides are receded from the side surface of the first mask material 14 to form the gap portions 15 and 35. It is only important to do so and is not limited to the structure of FIG. For example, as shown in FIG. 26, the side surface of the SOI layer 13 may recede from the side surface of the buried insulating film 12. Therefore, the width of the gap 15 may be smaller than the width of the gap 35 (FIG. 19), or the width of the gap 35 may be smaller than the width of the gap 15 (FIG. 26).

2. Second Embodiment The second embodiment is an example in which the space of the element isolation region at the boundary between the SOI region and the bulk region is reduced by not performing epitaxial growth.

  Below, the 1st and 2nd example which concerns on 2nd Embodiment is demonstrated.

[2-1] First Example In the first example according to the second embodiment, gate electrodes having a two-layer structure are formed in the SOI region and the bulk region, respectively, and the heights of the lower surfaces of both gate electrodes are as follows. Although different, the heights of the upper surfaces of both gate electrodes are made substantially the same.

  FIG. 27 is a sectional view of a first example semiconductor device according to the second embodiment of the present invention. As shown in FIG. 27, in the SOI region, a gate insulating film 20 is provided on the SOI layer 13, and a gate electrode 45 is provided on the gate insulating film 20. The gate electrode 45 has a two-layer structure including a lower electrode layer 43a and an upper electrode layer 44a.

  In the bulk region, the gate insulating film 21 is provided on the support substrate 11, and the gate electrode 46 is provided on the gate insulating film 21. The gate electrode 46 has a two-layer structure including a lower electrode layer 43b and an upper electrode layer 44b.

  The gate electrode 45 in the SOI region and the gate electrode 46 in the bulk region are different in height of the substrate under the gate electrode, but the height of the upper surface of the gate electrode is substantially equal. That is, the electrode layer 43b of the gate electrode 46 in the bulk region is thicker than the electrode layer 43a of the gate electrode 45 in the SOI region so as to fill the difference in height between the SOI region and the substrate under the gate electrode in the bulk region. Yes.

  An element isolation region 41 having an STI structure is formed at the boundary between the SOI region and the bulk region. Thereby, the SOI layer 13 and the substrate 11 in the bulk region are electrically separated. Further, element isolation regions 40 and 42 are formed in the SOI region and the bulk region, respectively. Here, the element isolation region 41 is preferably formed of a foreign material and the buried insulating film 12.

  28 to 32 are cross-sectional views showing the manufacturing steps of the semiconductor device of the first example according to the second embodiment of the present invention. The manufacturing method of the first example according to the second embodiment will be described below.

  First, as shown in FIG. 28, an SOI wafer having a support substrate 11, a buried insulating film 12, and an SOI layer 13 is prepared. Next, element isolation regions 40, 41, and 42 penetrating from the surface of the SOI layer 13 to the support substrate 11 are formed. Here, the upper portions of the element isolation regions 40, 41, and 42 protrude from the upper surface of the SOI layer 13 so that the recesses 48 are formed.

  Next, as shown in FIG. 29, the SOI layer 13 and the buried insulating film 12 are respectively removed in the bulk region. Accordingly, the recess 48 remains formed in the SOI region, and the recess 49 deeper than the recess 48 is formed in the bulk region.

  Here, when removing the buried insulating film 12, it is preferable to use wet etching at least in the final step so as not to damage the underlying support substrate 11.

  At this time, in order to prevent the element isolation regions 41 and 42 in the bulk region from being similarly damaged, a SiN liner (thin film SiN film) is laid or buried in the groove for the element isolation region. It is desirable to embed a material different from that of the insulating film 12.

  Next, as shown in FIG. 30, the gate insulating film 20 is formed on the SOI layer 13, and the gate insulating film 21 is formed on the support substrate 11. Next, a first electrode material 43 is formed on the gate insulating films 20, 21 and the element isolation regions 40, 41, 42.

  Next, as shown in FIG. 31, the upper surface of the first electrode material 43 is planarized by CMP until the upper surfaces of the element isolation regions 40, 41, and 42 are exposed. As a result, the lower electrode layer 43a of the gate electrode in the SOI region is formed in the recess 48, and the lower electrode layer 43b of the gate electrode in the bulk region is formed in the recess 49. As a result, the upper surface of the lower electrode layer 43a in the SOI region and the upper surface of the lower electrode layer 43b in the bulk region can be made equal in height, and the step between the SOI region and the bulk region is eliminated.

  Next, as shown in FIG. 32, the second electrode material 44 is formed on the lower electrode layers 43 a and 43 b and the element isolation regions 40, 41 and 42.

  Next, as shown in FIG. 27, the lower electrode layers 43a and 43b and the second electrode material 44 are collectively processed. As a result, the gate electrode 45 composed of the lower electrode layer 43a and the upper electrode layer 44a is formed in the SOI region, and the gate electrode 46 composed of the lower electrode layer 43b and the upper electrode layer 44b is formed in the bulk region. The

  According to the first example of the second embodiment, the following effects can be obtained.

  (1) In the first example according to the second embodiment, since selective epitaxial growth is not performed in the bulk region, it is not necessary to provide a mask material on the side surface of the SOI layer 13 during epitaxial growth. Accordingly, the depression 160 due to the removal of the mask material does not occur, and it is not necessary to form a large element isolation region for eliminating the depression 160. Therefore, the space of the element isolation region 41 at the boundary between the SOI region and the bulk region can be reduced.

  (2) In the prior art, a step between the SOI layer 13 and the epitaxial layer 17 may occur during epitaxial growth due to variations in the thickness of the selective growth. If the gate electrode is formed with this step remaining, the SOI region And a gate electrode having the same height cannot be formed in the bulk region.

  On the other hand, in the first example according to the second embodiment, since selective epitaxial growth is not performed in the bulk region, a step is generated between the SOI region and the bulk region. However, the lower electrode layers 43a and 43b of the gate electrode Steps can be eliminated. Therefore, gate electrodes 45 and 46 having the same height can be formed in the SOI region and the bulk region.

[2-2] Second Example The second example according to the second embodiment is a modification of the second example, and is an example in which an EEPROM is formed in the bulk region.

  FIG. 33 is a sectional view of a second example semiconductor device according to the second embodiment of the present invention. Here, the description will focus on a structure different from the first example.

  As shown in FIG. 33, in the second example according to the second embodiment, an insulating film 47 such as an ONO (Oxide Nitride Oxide) film is provided between the upper electrode layer 44b and the lower electrode layer 43b in the bulk region. Is provided. That is, in the bulk region, an EEPROM cell is formed in which the lower electrode layer 43b is a floating gate and the upper electrode layer 44b is a control gate.

  In the second example, the structure for eliminating the step between the SOI region and the bulk region is different from that in the first example. That is, the lower electrode layer 43b is formed with a thickness substantially equal to that of the lower electrode layer 43a, and the upper electrode layer 44b and the insulating film 47 eliminate the step between the SOI region and the bulk region.

  In the bulk region, the lower electrode layer 43 b is formed along the side surface portion formed along the side surface of the recess 49 (side surfaces of the element isolation regions 41 and 42) and the bottom surface of the recess 49 (on the gate insulating film 21). And a formed bottom surface portion. The insulating film 47 includes a side surface portion formed along the side surface portion of the lower electrode layer 43b, a bottom surface portion formed along the bottom surface portion of the lower electrode layer 43b, the element isolation regions 41 and 42, and the lower electrode. And an upper surface portion formed along the upper surface of the layer 43b. That is, the lower electrode layer 43 b and the insulating film 47 in the bulk region have a concave structure along the shape of the concave portion 49. Furthermore, since the upper electrode layer 44b is formed so as to fill a recess having a concave structure composed of the lower electrode layer 43b and the insulating film 47, the central portion of the upper electrode layer 44b is thicker than the end portion.

  According to the second example of the second embodiment, the same effect as that of the first example according to the second embodiment can be obtained.

  Furthermore, in the second example, the lower electrode layer 43b and the insulating film 47 in the bulk region are formed in a concave shape by using a step between the SOI region and the bulk region. As a result, a coupling ratio between the upper electrode layer 44b and the lower electrode layer 43b can be ensured, and there is an advantage that it contributes to stable operation of the cell.

3. Third Embodiment The third embodiment is an example in which the buried insulating film and the SOI layer in the SOI region are used as the gate insulating film and the gate electrode in the bulk region.

  The first and second examples according to the third embodiment will be described below.

[3-1] First Example A first example according to the third embodiment is a basic structure in which the buried insulating film and the SOI layer in the SOI region are used as the gate insulating film and the gate electrode in the bulk region.

  FIG. 34 is a cross-sectional view of the first example semiconductor device according to the third embodiment of the present invention. As shown in FIG. 34, in the semiconductor device of the first example according to the third embodiment, the insulation used as the buried insulating film 12a is formed by forming the buried insulating film 12a in the SOI region relatively thin. The film is used as the gate insulating film 12b in the bulk region. Further, the layer used as the SOI layer 13a in the SOI region is used as the lower electrode layer 13b of the gate electrode 54 in the bulk region. The electrode layer used as the gate electrode in the SOI region is used as the upper electrode 53b of the gate electrode 54 in the bulk region.

  The gate electrode 53a in the SOI region and the gate electrode 54 in the bulk region are different in height of the substrate under the gate electrodes 53a and 54, but the heights of the upper surfaces of the gate electrodes 53a and 54 are substantially equal. That is, the gate electrode 54 in the bulk region has a two-layer structure, thereby filling the difference in the height of the substrate under the gate electrode in the SOI region and the bulk region.

  Here, when the SOI layer 13a is formed of, for example, a single crystal silicon layer, a part of the gate electrode 54 (lower electrode layer 13b) in the bulk region is formed of a single crystal silicon layer.

  FIG. 35 to FIG. 36 are sectional views showing steps in manufacturing the semiconductor device of the first example according to the third embodiment of the present invention. The manufacturing method of the first example according to the third embodiment will be described below.

  First, as shown in FIG. 35, an SOI wafer having a support substrate 11, a buried insulating film 12, and an SOI layer 13 is prepared. Next, element isolation regions 50, 51, 52 penetrating from the surface of the SOI layer 13 to the support substrate 11 are formed. Thereby, the buried insulating film 12a and the SOI layer 13a are formed in the SOI region. In the bulk region, a gate insulating film 12b made of a buried insulating film 12 is formed, and a lower electrode layer 13b for a gate electrode made of an SOI layer 13 is formed.

  Next, as shown in FIG. 36, the gate insulating film 20 is formed on the SOI layer 13a in the SOI region. Thereafter, an electrode material 53 is formed on the entire surface.

  Next, as shown in FIG. 34, the electrode material 53 and the lower electrode layer 13b are collectively processed. Thereby, a gate electrode 53a made of the electrode material 53 is formed in the SOI region, and a gate electrode 54 having a two-layer structure made up of the lower electrode layer 13b and the upper electrode layer 53b made of the electrode material 53 is formed in the bulk region. It is formed.

  According to the first example of the third embodiment, the following effects can be obtained.

  (1) In the first example according to the third embodiment, since selective epitaxial growth is not performed in the bulk region, it is not necessary to provide a mask material on the side surface of the SOI layer 13 during epitaxial growth. Accordingly, the depression 160 due to the removal of the mask material does not occur, and it is not necessary to form a large element isolation region for eliminating the depression 160. Therefore, the space of the element isolation region 51 at the boundary between the SOI region and the bulk region can be reduced.

  (2) In the prior art, a step between the SOI layer 13 and the epitaxial layer 17 may occur during epitaxial growth due to variations in the thickness of the selective growth. If the gate electrode is formed with this step remaining, the SOI region And a gate electrode having the same height cannot be formed in the bulk region.

  In contrast, in the first example according to the third embodiment, since selective epitaxial growth is not performed in the bulk region, a step is generated between the SOI region and the bulk region, but the gate electrode 54 in the bulk region has a two-layer structure. By doing so, this step can be eliminated. Therefore, the gate electrodes 53a and 54 having the same height can be formed in the SOI region and the bulk region.

  (3) In the first example according to the third embodiment, the material layers used as the buried insulating film 12a, the SOI layer 13a, and the gate electrode 53a in the SOI region, and the gate insulating film 12b, the gate electrode in the bulk region 54 are used as material layers of the lower electrode layer 13b and the upper electrode layer 53b, respectively. Therefore, it is not necessary to provide a new process when forming an element in the bulk region, so that the process becomes easy.

  (4) In the first example according to the third embodiment, the buried insulating film 12a in the SOI region is used as the gate insulating film 12b in the bulk region, and the SOI layer 13a in the SOI region is used as the gate electrode (lower electrode) in the bulk region. Used as layer 13b). Here, when the SOI layer 13 in the present embodiment is formed of single crystal silicon, there is no grain in the case of being formed of conventional polycrystalline silicon. Therefore, in the present embodiment, it is possible to avoid defects related to the grain. . For example, it becomes possible to form a gate insulating film having a uniform thickness, and there is no deterioration in microscopic breakdown voltage, and a thinner film can be achieved. In addition, the gate electrode made of single crystal silicon can achieve lower resistance in wiring than the gate electrode made of polycrystalline silicon.

[3-2] Second Example A second example according to the third embodiment is obtained by adding an EEPROM to the bulk area in the first example.

  FIG. 37 is a sectional view of the semiconductor device of the second example according to the third embodiment of the present invention. As shown in FIG. 37, in the semiconductor device of the second example according to the third embodiment, a gate electrode 53a having a single layer structure is formed in the SOI region, and a gate electrode 54 having a two layer structure is formed in the bulk region. The gate electrode 56 of the EEPROM is formed.

  Here, in the EEPROM in the bulk region, the gate insulating film 12c is formed of the same film 12 as the buried insulating film 12a and the gate insulating film 12b, and the lower electrode layer 13c functioning as a floating gate is formed of the SOI layer 13a and the lower electrode layer 13b. The insulating film 20b is formed of the same film 20 as the gate insulating film 20a, and the upper electrode layer 53c functioning as a control gate is formed of the same layer 53 as the gate electrode 53a and the upper electrode layer 53b. .

  The gate electrode 53a in the SOI region and the gate electrodes 54 and 56 in the bulk region have different heights of the substrate under the gate electrode 53a and the gate electrodes 54 and 56, but the height of the upper surface of the gate electrodes 53a, 54, and 56 is different. The length is almost equal. In other words, the gate electrodes 54 and 56 in the bulk region have a two-layer structure, thereby filling the difference in the height of the substrate under the gate electrode in the SOI region and the bulk region.

  According to the second example of the third embodiment, the same effect as that of the first example of the third embodiment can be obtained.

  Further, when an EEPROM is formed in the bulk region, the gate insulating film 12c, the lower electrode layer 13c, the insulating film 20b, and the upper electrode layer 53c are the same as the buried insulating film 12a, the SOI layer 13a, the gate insulating film 20a, and the gate electrode 53a. Each is formed using layers. For this reason, it is not necessary to provide a new process for forming the EEPROM in the bulk region, and the process becomes easy.

  In addition, the present invention is not limited to the above-described embodiments, and can be variously modified as follows, for example, without departing from the scope of the invention in the implementation stage.

  (1) The final removal method of the buried insulating film 12 in the bulk region is not limited to wet etching. For example, after removing the buried insulating film 12 by RIE, a damaged layer generated on the support substrate 11 may be further removed.

  (2) The gap 15 formed by retreating the SOI layer 13 is filled with the second mask material 16, but the step of filling with the second mask material 16 can be omitted.

  In this case, when the epitaxial layer 17 is formed, there is a possibility that epitaxial growth may also be performed from the receding side surface of the SOI layer 13, but by increasing the receding amount of the side surface of the SOI layer 13 (width of the gap 15), It is also possible to control so that the SOI layer 13 and the epitaxial layer 17 are not connected.

  Further, regions having different retraction amounts are formed by using a resist process, and an insulating region and a conductive region as described in the second example of the first embodiment are separately formed only by the magnitude of the retraction amount. Is also possible.

  Further, since the gap portion 15 is not buried, a step corresponding to the film thickness of the SOI layer 13 exists on the buried insulating film 12 near the boundary of the insulating region. If it is a thin film, there is no problem.

  (3) The gap 15 can also be formed as follows. First, as shown in FIG. 38, the first mask material 14 is patterned by RIE. Next, the SOI layer 13 is removed using isotropic etching, and the gap 15 is formed. At this time, as isotropic etching, for example, dry etching by CDE, wet etching by KOH solution, or the like is used. Therefore, in this case, since the forward tapered surface 62 is formed on the side surface of the SOI layer 13, there is no further concern that the device formation will be hindered such as film residue. After the gap 15 is formed, the buried insulating film 12 in the bulk region is etched by RIE and wet etching. Thereafter, when the process of not filling the gap 15 as described above is performed, the structure as shown in FIG. 39 or 40 is completed.

  Here, FIG. 39 shows a structure when facets are not generated in the epitaxial layer 17, and FIG. 40 shows a structure when facets 26 are generated in the epitaxial layer 17.

  When the forward tapered surface 62 is formed on the side surface of the SOI layer 13 as described above, the gap portion 15 may be embedded with the second mask material 16.

  (4) The element isolation region 16a is formed after removing the SOI layer 13 and the buried insulating film 12 in the bulk region, but is not limited thereto. For example, after the element isolation region 16a is formed at least at the boundary between the SOI region and the bulk region, the SOI layer 13 and the buried insulating film 12 in the bulk region may be removed, and then epitaxial growth may be performed.

  (5) With respect to the material and crystallinity of the SOI layer 13, the buried insulating film 12, the support substrate 11, the mask materials 14 and 16, and the epitaxial layer 17, it is possible to apply various materials applied to device formation.

  (6) The upper surface of the element isolation region 16a is not limited to the same height as the upper surfaces of the SOI layer 13 and the epitaxial layer 17, and is slightly higher or lower than the upper surfaces of the SOI layer 13 and the epitaxial layer 17. It may become. For example, when the element isolation region 16a is an oxide film, the upper surface of the element isolation region 16a may be lower than the upper surfaces of the SOI layer 13 and the epitaxial layer 17 due to the removal process of the oxide film. Further, when the element isolation region 16a is a nitride film, the height of the upper surface of the element isolation region 16a is not changed by the oxidation or oxide film removal process, but the SOI layer 13 and the epitaxial layer 17 are removed by the oxidation or oxide film removal process. Since the upper surface is lowered, as a result, the upper surface of the element isolation region 16 a may be higher than the upper surfaces of the SOI layer 13 and the epitaxial layer 17.

  Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

Sectional drawing which shows the semiconductor device of the 1st example concerning the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st example concerning the 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the first embodiment of the present invention following FIG. 2. FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the first embodiment of the invention following FIG. 3. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the first embodiment of the present invention, following FIG. 4. FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the first embodiment of the present invention, following FIG. 5. Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st example concerning the 1st Embodiment of this invention following FIG. FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the first embodiment of the invention following FIG. 7. Sectional drawing which shows the semiconductor device of the 2nd example concerning the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 2nd example concerning the 1st Embodiment of this invention. FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second example according to the first embodiment of the invention following FIG. 10; FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second example according to the first embodiment of the invention following FIG. 11. FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second example according to the first embodiment of the invention following FIG. 12; FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second example according to the first embodiment of the invention following FIG. 13; FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second example according to the first embodiment of the invention following FIG. 14. Sectional drawing which shows the semiconductor device of the 3rd example concerning the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 3rd example concerning the 1st Embodiment of this invention. FIG. 18 is a cross-sectional view showing the manufacturing process of the third example of the semiconductor device according to the first embodiment of the present invention, following FIG. 17; Sectional drawing which shows the semiconductor device of the 4th example concerning the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 4th example concerning the 1st Embodiment of this invention. FIG. 21 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the fourth example according to the first embodiment of the invention following FIG. 20; FIG. 22 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the fourth example according to the first embodiment of the invention following FIG. 21; FIG. 23 is a cross-sectional view showing the manufacturing process of the fourth example of the semiconductor device according to the first embodiment of the present invention, following FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the fourth example of the semiconductor device according to the first embodiment of the present invention, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the fourth example of the semiconductor device according to the first embodiment of the present invention, following FIG. 24; Sectional drawing which shows the other semiconductor device of the 4th example concerning the 1st Embodiment of this invention. Sectional drawing which shows the semiconductor device of the 1st example concerning the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st example concerning the 2nd Embodiment of this invention. FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the second embodiment of the invention following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first example according to the second embodiment of the invention following FIG. 29; FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first example according to the second embodiment of the invention following FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the second embodiment of the invention following FIG. 31; Sectional drawing which shows the semiconductor device of the 2nd example concerning the 2nd Embodiment of this invention. Sectional drawing which shows the semiconductor device of the 1st example concerning the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st example concerning the 3rd Embodiment of this invention. FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first example according to the third embodiment of the invention following FIG. 35; Sectional drawing which shows the semiconductor device of the 2nd example concerning the 3rd Embodiment of this invention. Sectional drawing which shows the semiconductor device in which the forward taper concerning each embodiment of this invention was formed. Sectional drawing which shows the semiconductor device in which the forward taper concerning each embodiment of this invention was formed. Sectional drawing which shows the semiconductor device in which the forward taper and facet concerning each embodiment of this invention were formed. Sectional drawing which shows the manufacturing process of the semiconductor device by a prior art. FIG. 42 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. 41; FIG. 43 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. FIG. 44 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. 43; FIG. 45 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. 44; FIG. 46 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. FIG. 47 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the conventional technique following FIG. 46;

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Support substrate, 12, 12 ', 12a ... Embedded insulating film, 13, 13a ... SOI layer, 14 ... 1st mask material, 15, 35 ... Gap part, 16 ... 2nd mask material, 16a, 18, 19, 30, 40, 41, 42, 50, 51, 52, 55 ... element isolation region, 17 ... epitaxial layer, 12b, 12c, 20, 21 ... gate insulating film, 22, 23, 31, 45, 46, 53a , 54, 56 ... gate electrode, 25 ... resist, 26 ... facet, 43, 44, 53 ... electrode material, 13b, 13c, 43a, 43b ... lower electrode layer, 44a, 44b, 53b, 53c ... upper electrode layer, 20b , 47 ... insulating film, 48, 49 ... concave portion, 62 ... forward tapered surface.

Claims (6)

A substrate having first and second regions;
A first insulating film provided on the substrate in the first region;
A first epitaxial layer provided on the substrate in the second region and having a top surface higher than a top surface of the first insulating film;
The first epitaxial layer is provided on the first insulating film with a gap, and has an upper surface having a height substantially equal to the upper surface of the first epitaxial layer, And a first semiconductor layer having a tapered surface facing the side surface.   The semiconductor device according to claim 1, wherein the side surface of the first epitaxial layer has a facet. A first gate insulating film formed on the upper surface and the tapered surface of the first semiconductor layer;
The semiconductor device according to claim 1, further comprising: a second gate insulating film formed on the upper surface and the side surface of the first epitaxial layer. And a first element isolation insulating film provided in the gap and having a top surface having a height substantially equal to the top surface of the first epitaxial layer and the top surface of the first semiconductor layer. The semiconductor device according to claim 1. The first element isolation insulating film is formed on an upper surface of the first insulating film;
The semiconductor device according to claim 4, wherein the first epitaxial layer is in direct contact with the first element isolation insulating film and the first insulating film. A bottom surface provided in the first region, penetrating the first semiconductor layer and the first insulating film, and positioned below the bottom surface of the first element isolation insulating film; The semiconductor device according to claim 4, further comprising: a second element isolation insulating film that is not in direct contact with the epitaxial layer.

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