JP2008016832A - Field-effect transistor, tft drive circuit, panel, and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the structure of a novel field-effect transistor that uses a semiconductor nanowire to have fine transistor characteristics. <P>SOLUTION: The field-effect transistor includes a board 40, gate electrode 41, a gate insulating film 42, which are arranged in increasing order, and the semiconductor nanowire 45 and a source electrode 43/drain electrode 44 that are formed on the gate insulating film 42. In a contact area between the semiconductor nanowire 45 and the source electrode 43/drain electrode 44, the surface of the semiconductor nanowire 45 is covered with the constituent material of the source electrode 43/drain electrode 44. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor, a TFT drive circuit, a panel and a display, and more particularly to a field effect transistor using a semiconductor nanowire as a channel and a TFT drive circuit, panel and display using the same.

  Conventional active liquid crystal display devices and organic electroluminescence (EL) display elements are formed on a glass substrate, and pixels arranged in a matrix on the substrate are controlled by transistor elements arranged in the vicinity thereof. Since current technology cannot form a transistor of a crystalline semiconductor on a glass substrate, a field effect transistor (TFT) made of amorphous silicon or a polysilicon thin film is used for pixel control.

  In recent years, a technique for forming a thin film transistor on a flexible substrate using an organic material or a semiconductor nanowire as a channel material has been developed (see Patent Document 1 and Non-Patent Document 1).

In Patent Document 1 and Non-Patent Document 1, silicon nanowires formed on a substrate different from the substrate on which a device is formed are peeled from the substrate, dispersed in a solution, and the nanowires dispersed in the solution are disposed on a (flexible) substrate. Thus, a method of forming a high mobility channel has been proposed. In this method, since the channel region of the transistor is formed of single crystal silicon, the transistor having a mobility exceeding 100 cm ² V ⁻¹ s ⁻¹ has been successfully formed.
Special table 2004-507104 gazette “High Performance thin film transistors using semiconductor nanowires and nanoribbons”, Nature, vol.425, 2003, pp.274. “Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems”, NANO LETTERS, vol.3, No.9 2003, pp.1255-1259. “Directed Assemly of One-Dimensional Nonostructures into Functional Networks”, SCIENCE, vol.291, 2001, pp.630.

  However, in the methods disclosed in Patent Document 1 and Non-Patent Document 1, consciousness is concentrated on the method of manufacturing semiconductor nanowires and arranging semiconductor nanowires on a substrate, and the basic performance of semiconductors required in practice is sufficient. There is no study to make it possible to demonstrate. In particular, no study has been made on the connection between the semiconductor nanowire and the source and drain electrodes and the function as a channel.

  Under such circumstances, it is an object of the present invention to provide a novel field effect transistor structure using semiconductor nanowires and having good transistor characteristics. Another object of the present invention is to provide an electronic device using the field effect transistor.

  In order to solve the above-described problems, in a field effect transistor using semiconductor nanowires as a channel layer, the charge injection barrier from the electrode to the channel layer is reduced.

  Specifically, a first field effect transistor of the present invention includes a substrate, a gate electrode provided on the substrate, a gate insulating film provided on the gate electrode, and a gate insulating film provided on the gate insulating film. A semiconductor nanowire that is electrically connected to both the source electrode and the drain electrode and is disposed on the gate insulating film and functions as a channel. A portion of the surface from the bottom of the semiconductor nanowire located closest to the gate electrode to at least 5 nm upward is covered with the source electrode and the drain electrode. Above the gate insulating film in which the semiconductor nanowire is disposed includes both the case where the semiconductor nanowire is in contact with the gate insulating film and the case where the semiconductor nanowire is not in contact with the gate insulating film. In the above configuration, the substrate, the gate electrode, the gate insulating film, the source and the drain electrode are stacked in this order from bottom to top. The semiconductor nanowire is electrically connected to the source electrode and the drain electrode by covering at least 5 nm of the surface of the semiconductor nanowire with the source electrode and the drain electrode from the bottom to the upper side.

  In a preferred embodiment, the surface of the semiconductor nanowire covered with the source electrode and the drain electrode is chemically bonded to the source electrode and the drain electrode. Here, that the semiconductor nanowire and the source electrode and the drain electrode are chemically bonded means, for example, that the substance constituting the semiconductor nanowire and the substance constituting the electrode are alloyed.

In a preferred embodiment, portions of the surface of the semiconductor nanowire other than those covered with the source electrode and the drain electrode are covered with an insulating film. It is preferable that the surface layer and the core part of the semiconductor nanowire are made of different materials except for the part covered by the source electrode and the drain electrode in the semiconductor nanowire. It is preferable that the core part other than the part covered with the source electrode and the drain electrode in the semiconductor nanowire is made of Si. It is preferable that the surface layer of the semiconductor nanowire other than the portion covered with the source electrode and the drain electrode is made of SiO ₂ .

  The substrate is preferably made of a polymer material or a composite of a polymer material and an inorganic material.

  The TFT element of the present invention is composed of the above-described field effect transistor.

  The panel of the present invention includes the TFT element described above.

  The display of the present invention includes the panel described above.

  In the field effect transistor of the present invention, since the electrode is formed adjacent to the channel layer of the semiconductor nanowire, the charge injection barrier to the channel layer is small. Therefore, a field effect transistor with good transistor characteristics can be realized on the flexible substrate.

  In addition, since a substrate made of a polymer material or a composite of a polymer material and an inorganic material can be used, a flexible field effect transistor can be realized.

  Before describing the embodiment of the present invention, the process leading to the present application will be described with reference to FIGS.

  First, the operation principle of the field effect transistor will be briefly described. When a voltage is applied to the gate electrode, a channel layer is formed near the interface between the gate insulating film and the semiconductor by electrostatic induction. At this time, when a voltage is applied between the source electrode and the drain electrode, electric charge is injected from the source electrode to the channel, passes through the channel layer, and flows out to the drain electrode. This is how the current flows in the field effect transistor.

  1 (a) and 2 (a) show that semiconductor nanowires 15 and 25 are formed by applying a conventionally disclosed method described in Patent Document 1, Non-Patent Document 1 and the like to the manufacture of a field effect transistor. It is typical sectional drawing of the field effect transistor structure produced using it for a channel, FIG.1 (b) is a partially expanded view of the AA line cross section of Fig.1 (a), FIG.2 (b) is FIG. It is a partially expanded view of the AA line cross section of (a).

  As shown in FIG. 1A, a field effect transistor using the semiconductor nanowire 15 is formed in the order of a gate electrode 11, a gate insulating film 12, a source electrode 13 and a drain electrode 14, and on the source / drain electrodes 13 and 14. In the bottom contact type in which the semiconductor nanowire 15 is formed (the bottom of the semiconductor nanowire 15 is in contact with the source / drain electrodes 13 and 14), the gate electrode 21 and the gate insulating film 22 as shown in FIG. The semiconductor nanowire 25 is formed in this order, and a top contact type in which the source electrode 23 and the drain electrode 24 are formed on the nanowire 25 (the upper portion of the semiconductor nanowire 25 is in contact with the source / drain electrodes 23 and 24) can be considered. . Here, the current flowing between the source electrodes 13, 23 and the drain electrodes 14, 24 facilitates the movement of charges between the source and drain electrodes 13, 23, 14, 24 and the semiconductor nanowires 15, 25. Depends on being. The ease of movement of this charge is affected by the contact resistance and energy level between the semiconductor nanowires 15 and 25 and the source electrodes 13 and 23 and the drain electrodes 14 and 24.

  In the bottom contact type field effect transistor shown in FIG. 1A, a cross-sectional view in a region where the source electrode 13 and the semiconductor nanowire 15 are in contact is shown in FIG. A source electrode 13 is formed on the gate insulating film 12, and a semiconductor nanowire 15 is disposed thereon. The channel layer 16 is formed below the semiconductor nanowire 15. As described above, the ease of charge transfer from the source electrode 13 to the semiconductor nanowire 15 is affected by the contact resistance between the two. However, the larger the contact area between the source electrode 13 and the semiconductor nanowire 15, the better the charge transfer. Done. However, in the bottom contact type field effect transistor shown in FIG. 1B, the contact area between the source electrode 13 and the semiconductor nanowire 15 is a line contact (point contact in the cross section), so the contact area is very small. Is difficult to move and has low transistor characteristics.

  In the top contact type field effect transistor shown in FIG. 2A, a cross-sectional view in a region where the source electrode 23 and the semiconductor nanowire 25 are in contact is shown in FIG. A semiconductor nanowire 25 is disposed on the gate insulating film 22, and a source electrode 23 is formed thereon. When the electrode is formed by the vapor deposition system device after the semiconductor nanowire 25 is arranged, the electrode is formed on the semiconductor nanowire 25 so as to cover the surface of the semiconductor nanowire 25. However, under the semiconductor nanowire 25, the semiconductor nanowire 25 itself serves as a mask, and the electrode material cannot wrap around, so that voids 27 are formed between the electrode and the semiconductor nanowire 25 as shown in FIG. In the top contact type field effect transistor shown in FIG. 2, the contact area between the source electrode 23 and the semiconductor nanowire 25 is larger than that of the bottom contact type, and charge transfer is easily performed. However, the channel layer 26, which is a path for charges in the semiconductor nanowire 25, is formed in the vicinity of the gate insulating film 22, and the electrode and the semiconductor nanowire 25 are not in contact with each other due to the voids 27 and 27. Therefore, charges are injected into the semiconductor nanowire 25 from the contact portion between the semiconductor nanowire 25 and the electrode, and move to the channel layer 26 via the semiconductor portion.

  The semiconductor portion other than the channel layer 26 has a low carrier density and a high resistance. Therefore, in the top contact type field effect transistor, although the contact area between the source electrode 23 and the semiconductor nanowire 25 increases, the charge moves to the channel layer 26 via the high-resistance semiconductor region, so that the transistor characteristics are low. In order to solve such a problem, the inventors of the present application have made various studies to arrive at the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity.

(Embodiment 1)
Referring to FIG. 4, the field effect transistor according to the first embodiment having a structure in which the surface of the semiconductor nanowire 45 is covered with the electrodes 43 and 44 in the contact region between the semiconductor nanowire 45 and the source electrode 43 and the drain electrode 44. explain.

  In the field effect transistor of this embodiment, a gate electrode 41 is formed on a substrate 40, and a gate insulating film 42 is further formed thereon. A semiconductor nanowire 45 functioning as a channel is disposed on the gate insulating film 42, and a source electrode 43 and a drain electrode 44 are formed on the gate insulating film 42 so as to cover both ends of the semiconductor nanowire.

  As the substrate 40, an inorganic material such as silicon or glass or an organic material such as polyimide or aromatic polyester can be used. Here, a plastic substrate which is an organic material is used. In addition, as materials for the gate electrode 41, the source electrode 43, and the drain electrode 44, inorganic materials such as Ti, Au, Al, Ni, Ag, Cu, Pt, Pd, and alloys thereof, sulfonic acid, and carboxyl An organic material such as polyaniline or polythiophene using an acid or the like as a counter ion can be used, but a metal such as Al or Ni is used here.

  The source electrode 43 and the drain electrode 44 are in electrical contact with the semiconductor nanowire 45, respectively, but the surface of the semiconductor nanowire 45 is only covered with the metal that is a constituent material of the source electrode 43 and the drain electrode 44. In this embodiment, there is no chemical bond between them. When a bias is applied to the gate electrode 41, the conductivity of the channel layer 46 is controlled through the gate insulating film 42 in the vicinity of the interface between the semiconductor nanowire 45 and the gate insulating film 42.

  As the semiconductor nanowire 45, for example, a group IV semiconductor such as Si, Ge, or SiGe, a group III-V semiconductor such as GaAs, InP, or InAs, or a semiconductor made of a group II-VI semiconductor such as ZnS, ZnSe, or CdS is used. In this embodiment, Si is used. Alternatively, the semiconductor nanowire 45 may be doped to form a P-type semiconductor nanowire or an N-type semiconductor nanowire. Further, both N-type and P-type may be formed in one semiconductor nanowire like a PNP-type semiconductor nanowire.

  The length of the semiconductor nanowire 45 is, for example, about 1 μm to 100 μm. The diameter is, for example, about 5 nm to 1 μm. The shape of these semiconductor nanowires 45 changes according to device specifications. The cross-sectional shape of the semiconductor nanowire 45 is not limited to a circle, and may be a polygon such as a quadrangle or a hexagon, or a shape such as an ellipse.

  In the field effect transistor of the present embodiment, in order to reduce the charge barrier between the source electrode 43 and the drain electrode 44 and the channel layer 46 formed in the semiconductor nanowire 45, the surface of the semiconductor nanowire 45 is closest to the gate electrode 41. The source electrode 43 and the drain electrode 44 are formed so as to cover the surface of the semiconductor nanowire 45 at least 5 nm upward from the bottom X of the semiconductor nanowire. Here, the semiconductor nanowire bottom X located closest to the gate electrode 41 is the X point or X plane in FIG. Further, the surface of the semiconductor nanowire 45 from the bottom X of the semiconductor nanowire to the position 5 nm upward is the Y plane in FIG. 4B, and the Z plane at a position higher than the Y plane (upper position). May be covered with the electrode even a little. Note that 5 nm upward from the bottom X of the semiconductor nanowire is 5 nm from the height direction (direction substantially perpendicular to the surface of the gate insulating film 42 and away from the surface of the gate insulating film 42). It is not the length of the Y-plane arc.

  In general, the thickness of the channel layer 46 depends on the gate voltage, but is about 2 to 8 nm upward from the portion closest to the gate electrode 41. Therefore, if the surface of the channel layer 46 is covered with the constituent materials of the source electrode 43 and the drain electrode 44 and is electrically connected as much as possible, the charge injection barrier is lowered, and the channel from the source electrode 43 to the channel layer 46 is reduced. Charge injection is easily performed, and charges easily flow from the channel layer 46 to the drain electrode 44. Then, the current flowing through the channel layer 46 increases, and high transistor characteristics can be obtained. Here, if the surface of the semiconductor nanowire 45 from the bottom X of the semiconductor nanowire to 5 nm above it is covered with the constituent material of the source electrode 43 and the drain electrode 44, all or most of the surface of the channel layer 46 is covered. Is covered with the constituent material of the source electrode 43 and the drain electrode 44, so that the current flowing through the channel layer 46 is sufficiently increased, and a field effect transistor having excellent transistor characteristics is obtained.

  That is, unlike the field effect transistor structure shown in FIGS. 1 and 2, the field effect transistor of the present embodiment does not have a small contact area between the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45, and the source electrode 43 A path from the drain electrode 44 to the channel layer 46 in the semiconductor nanowire 45 is not long, and has a bottom gate type field effect transistor structure with a small charge barrier from the source electrode 43 and the drain electrode 44 to the channel layer 46 Yes. This is because, in the field effect transistor of this embodiment, the contact area between the source electrode 43 and the drain electrode 44 in the semiconductor nanowire 45 and the portion that becomes the channel layer 46 is large.

  As a manufacturing method of the semiconductor nanowire 45, first, metal fine particles serving as a catalyst are arranged on an arbitrary substrate. For example, cobalt, nickel, gold, or platinum may be used as the catalyst metal. As a method of arranging the catalyst metal fine particles on the substrate, for example, a method of forming a metal fine particle by depositing a catalyst metal thin film of about 1 to 10 nm by a sputtering method or a vapor deposition method and performing a heat treatment in an arbitrary atmosphere. Alternatively, a method of applying a metal fine particle colloid on the substrate may be used.

  Then, semiconductor nanowires 45 are grown on this substrate using the CVD method. As a method for growing a semiconductor nanowire made of silicon, for example, there can be mentioned a method in which silane or disilane is used as a source gas and the substrate temperature is grown at about 400 to 600 ° C. Silicon wire grows from fine particles of catalytic metal.

  The semiconductor nanowire 45 thus produced is peeled off from the substrate with a solvent and dispersed in the solvent. As a method of peeling the semiconductor nanowire 45, for example, a method of performing ultrasonic treatment on the substrate and mechanically peeling, or a method of performing light etching on the surface of the substrate on which the semiconductor nanowire 45 has been grown is preferably used. Here, examples of the solvent used for the dispersion include an aqueous solution, an organic solvent, or a mixture of water and an organic solvent. Examples of the organic solvent include alcohols such as ethanol, propanol, pentanol, hexanol and ethylene glycol, esters such as ethylene glycol monomethyl ether, ketones such as methyl ethyl ketone, alkanes such as hexane and octane, solvents such as tetrahydrofuran and chloroform. Should be used. As a mixed liquid of water and an organic solvent, a mixed liquid of water and alcohol, a mixed liquid of water and tetrahydrofuran, or the like can be used.

  A method for manufacturing the bottom gate field effect transistor of the present embodiment using the semiconductor nanowire 45 manufactured as described above will be described below.

  First, a resist is formed by patterning on the plastic substrate 40 in a region other than the region where the gate electrode 41 is formed by using a lithography method.

Next, the plastic substrate is etched using the above resist as a mask to dent the region where the gate electrode 41 is to be formed. Etching is performed, for example, by reactive ion etching using CF ₄ or oxygen gas, and is etched to a depth of about 100 to 300 nm.

  Next, a gate metal to be the gate electrode 41 is deposited on the etched portion. The gate electrode 41 is formed, for example, by depositing about 100 to 300 nm of Al by sputtering.

  Next, the resist and the gate metal deposited on the resist are removed, leaving the gate metal only in the gate electrode 41 portion. For these removals, the resist is dissolved using an organic resist removing solution, and the gate metal deposited on the resist is removed. Thus, the gate electrode 41 is formed.

Next, an insulating layer is deposited to form the gate insulating film 42. As a method for forming the gate insulating film 42, for example, a method of depositing SiO ₂ by about 50 to 300 nm by a CVD method can be cited.

  Next, the semiconductor nanowire 45 prepared as described above is disposed on the gate insulating film 42 and above the gate electrode 41. As an arrangement method, for example, the semiconductor nanowire 45 is arranged by dropping and drying an ink in which the semiconductor nanowire 45 is dispersed in a solvent by an inkjet method on a desired region where the semiconductor nanowire 45 is arranged. Further, the semiconductor nanowire 45 may be arranged by using a spin coating method, a transfer method, a dip coating method, a doctor blade method, or the like.

  Since the semiconductor nanowire 45 connects the source electrode 43 and the drain electrode 44 to be formed later, the direction connecting the electrodes 43 and 44 is preferably the wire axis direction. Thus, the orientation of the semiconductor nanowire 45 is aligned in a predetermined direction, that is, the orientation is performed by applying a flow to the ink when the ink in which the semiconductor nanowire 45 is dispersed in the solvent is applied or after the application. it can. For example, after immersing the substrate in semiconductor nanowire ink, the substrate is lifted to create a flow in the ink to orient the semiconductor nanowire 45, or after placing the semiconductor nanowire ink on the substrate and pushing the ink onto the substrate with a doctor blade A method of orienting the semiconductor nanowire 45 by creating a flow in the ink by spreading can be mentioned. The semiconductor nanowires 45 may be arranged using the methods described in Non-Patent Documents 2 and 3.

  Thereafter, the source electrode 43 and the drain electrode 44 are formed. As this formation method, the following method may be used.

  A resist is formed by patterning in a region other than the region where the source electrode 43 and the drain electrode 44 are formed by lithography. Thereafter, the gate insulating film 42 is etched to a depth of about 10 to 100 nm so that regions where the source electrode 43 and the drain electrode 44 are formed are recessed.

  Thereafter, nickel as a source / drain electrode material is deposited by sputtering, and then the resist and nickel deposited on the resist are lifted off and removed. When the source / drain electrode material is deposited by sputtering, the substrate material is tilted and rotated to change the angle of incidence of the electrode material on the substrate so that the electrode material wraps around to the bottom X of the semiconductor nanowire. Allow to deposit. Alternatively, a liquid electrode material may be applied by an inkjet method or the like instead of the sputtering method, and the electrode material may wrap around to the bottom X of the semiconductor nanowire. Further, a part of the source electrode 43 / drain electrode 44 is formed on the gate insulating film 42 before the semiconductor nanowire 45 is deposited, and after the semiconductor nanowire 45 is disposed, the source / drain electrode is used by using the above-described means. Material may be deposited and applied. Thus, the field effect transistor shown in FIG. 4 is completed.

  According to the manufacturing method of the bottom gate type field effect transistor of this embodiment, a high-quality electrical connection with a large area is formed between the source electrode 43 and the drain electrode 44 and the channel layer 46 of the semiconductor nanowire 45. Therefore, when the substrate is a plastic substrate, it is possible to form a field effect transistor with good transistor characteristics on the plastic substrate. Therefore, a highly reliable high performance transistor can be manufactured over a plastic substrate.

  In the field effect transistor shown in FIG. 4A, the semiconductor nanowires 45 are aligned in one line from the source electrode 43 to the drain electrode 44 in parallel to the gate insulating film 42. However, the semiconductor nanowires 45 are plural in number. Or the source electrode 43 and the drain electrode 44 may be arranged obliquely instead of being parallel to the direction connecting the two electrodes.

(Embodiment 2)
The bottom-gate field effect transistor of Embodiment 2 has a sealing film 47 that is an insulating film on the semiconductor nanowire 45 as shown in FIG. Since other components and manufacturing methods of the field effect transistor are the same as those of the first embodiment, only the sealing film 47 will be described below.

As the sealing film 47, an insulating material composed of an inorganic material such as SiN or SiO ₂ or an organic material such as polyimide or aromatic polyester is used.

In the case where an inorganic material such as SiN or SiO _{2 is} used as the sealing film 47 material, after forming the gate electrode 41, the gate insulating film 42, the semiconductor nanowire 45, the source electrode 43 and the drain electrode 44 on the substrate 40, the SiN Alternatively, the sealing film 47 may be formed by depositing about 50 to 300 nm of SiO ₂ by the CVD method. Depending on the sealing film material used, such as polyimide, a spin coating method, an ink jet method, or the like may be used. Further, for example, after forming the semiconductor nanowire 45 on the gate insulating film 42, the sealing film 47 may be formed, and then the source electrode 43 and the drain electrode 44 may be formed. When an organic material such as polyimide is used as the sealing film 47, the semiconductor nanowire 45 is mixed in a polyimide solution, a precursor solution, and the like and applied onto the gate insulating film 42 to dispose the semiconductor nanowire 45 and the sealing film 47. The formation may be performed simultaneously.

  According to the bottom gate type field effect transistor of the present embodiment, in addition to the effects of the first embodiment in which good electrical connection is obtained between the source electrode 43 and the drain electrode 44 and the channel layer 46 and high transistor characteristics are obtained. In addition, since the semiconductor nanowire 45 is covered with the sealing film 47 and is not easily affected by moisture and oxygen in the atmosphere, the transistor characteristics are almost the same even when there is a change in the environment while having a good electrical connection on the plastic substrate. A transistor that does not change can be formed. Therefore, a highly reliable high performance transistor can be manufactured over a plastic substrate.

(Embodiment 3)
As shown in FIG. 3, the bottom-gate field effect transistor of the third embodiment has a so-called core-shell type semiconductor nanowire 35 in which a surface layer 33 that is a shell covers a core portion 32 that is a core in a cross section. have. Here, the surface layer 33 and the core portion 32 are made of different materials. The semiconductor nanowire 35 does not have a core-shell structure in a region connected to the source electrode 43 and the drain electrode 44, and only the core portion 32 exists in this region.

  The field effect transistor of Embodiment 3 has the cross-sectional shape shown in FIG. 6A, and the cross section taken along the line AA in FIG. 6A is FIG. 6B. The semiconductor nanowire 35 is almost the same as the structure and manufacturing method of the transistor of the second embodiment provided with the sealing film 47 except that the semiconductor nanowire 35 has a core / shell structure. This will be described below.

  First, a method for manufacturing the core-shell type semiconductor nanowire 35 will be described.

  First, as described in Embodiment 1, nanowires made of silicon are formed.

Next, by thermally oxidizing the silicon nanowire together with the substrate on which the silicon nanowire has grown, the core-shell type semiconductor nanowire 35 shown in FIG. 3 in which the surface layer 33 is made of SiO ₂ and the core portion 32 is made of Si can be formed. . Here, the film thickness and quality of the silicon oxide film on the surface layer 33 depend on the oxidation time of thermal oxidation, the oxidation temperature, and the oxidizing atmosphere, so that the silicon oxide film can be designed according to the device specifications. As an oxidizing condition of this embodiment, for example, an oxygen atmosphere can be preferably mentioned at 1100 ° C., and it is preferable to form a silicon oxide film that becomes the surface layer 33 by rapid thermal processing.

  The method of manufacturing the bottom gate type field effect transistor of the third embodiment is the same as that of the second embodiment except that the core / shell type semiconductor nanowire 35 is used. However, when forming the source electrode 43 and the drain electrode 44 on the core-shell type semiconductor nanowire 35, it is necessary to remove the surface layer 33 of the semiconductor nanowire 35 in the region electrically connected to the source electrode 43 and the drain electrode 44. If the surface layer 33 is removed, it is not necessary to etch the gate insulating film 42 before forming the source electrode 43 and the drain electrode 44. Therefore, parts related to these in the manufacturing method will be described.

  First, the core / shell type semiconductor nanowire 35 is disposed on the gate insulating film 42.

  Next, a resist is formed by patterning in a region other than the region where the source electrode 43 and the drain electrode 44 are formed using photolithography.

  Then, the surface layer 33 of the core / shell type semiconductor nanowire 35 is removed using the resist as a mask so that the source electrode 43 / drain electrode 44 and the core / shell type semiconductor nanowire 35 are electrically connected. As a method for removing the surface layer 33, for example, dry etching or wet etching is used. As a result, in the region where the source electrode 43 and the drain electrode 44 are formed, the core-shell type semiconductor nanowire 35 is removed from the surface layer 33 so that only the core portion 32 is formed, and the gate insulation in the region where the source electrode 43 and the drain electrode 44 are formed. A gap is formed between the film 42 and the core / shell type semiconductor nanowire 35 by the removed surface layer 33. Therefore, in this embodiment, it is not necessary to etch the gate insulating film 42 for providing a gap between the semiconductor nanowire 45 and the gate insulating film 42 as in the first and second embodiments, and the gate insulating film 42 is etched. In this embodiment, it is possible to suppress a gate insulating film defect that may occur.

  Next, the constituent materials of the source electrode 43 and the drain electrode 44 are deposited on the gate insulating film 42. The method for depositing the constituent materials of the source electrode 43 and the drain electrode 44 is the same as in the second embodiment. When using a coating process such as an ink jet method, the constituent material of the source electrode 43 and the drain electrode 44 can enter the gap provided between the gate insulating film 42 and the core-shell type semiconductor nanowire 35 from the gap. It is preferable to use an electrode material having a small particle diameter.

In this embodiment, since the core portion 32 that is a semiconductor is protected by the surface layer 33 by using the semiconductor nanowire 35 having a core / shell structure, the channel region is less susceptible to moisture and oxygen in the atmosphere, and the transistor The operation is stable regardless of the usage environment. Here, since the core portion 32 of the semiconductor nanowire 35 is made of Si and the surface layer 33 is made of SiO ₂ , it is possible to apply the devices and theories used in the conventional semiconductor field to design and manufacture the channel layer. Costs and development costs can be reduced, and transistor characteristics that are less susceptible to oxygen and moisture due to the presence of the surface layer 33 can be obtained. Further, by simply removing the surface layer 33 of the semiconductor nanowire 35 in the region where the source electrode 43 and the drain electrode 44 are connected, a gap can be easily formed between the semiconductor nanowire 35 and the gate insulating film 42, and the semiconductor nanowire 35. Can be easily manufactured.

  As described above, in the present embodiment, it is possible to form a high-quality electrical connection between the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 35 without etching the gate insulating film 42, and the moisture and oxygen in the atmosphere. Therefore, a transistor having an electrical connection between the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 35 can be formed over a plastic substrate.

(Embodiment 4)
The present embodiment is different from the first embodiment in that the surface of the semiconductor nanowire covered with the source electrode and the drain electrode is chemically bonded to the source electrode / drain electrode, and the other points are the first embodiment. Since these are the same, the differences will be described below.

  FIG. 7A is a cross-sectional view of the field effect transistor according to the present embodiment, and FIG. 7B is a cross-sectional view taken along line AA of FIG. The material and shape of the semiconductor nanowire 45 are the same as those of the first field effect transistor of the present invention. As the source electrode 43 and the drain electrode 44, for example, a metal such as Ni, Au, or Ag, which is alloyed (chemically bonded) with Si that is a material of the semiconductor nanowire 45, is appropriately selected and used. Moreover, when manufacturing cost is considered, the lower the temperature for alloying, the better.

  In the present embodiment, the portion where the semiconductor nanowire 45 and the source electrode 43 / drain electrode 44 are chemically bonded is the alloy portion 48 of the source electrode 43 / drain electrode 44 and the semiconductor nanowire 45.

  In the present embodiment, the source electrode 43 and the drain electrode 44 are formed so as to cover the surface of the semiconductor nanowire 45, and the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45 are chemically bonded. 43. An intermediate level is formed between the energy level of the drain electrode 44 and the semiconductor nanowire 45. Therefore, the charge barrier between the source electrode 43 / drain electrode 44 and the channel layer 46 is smaller than that of the transistor according to the first embodiment, and the transistor characteristics are improved as compared with the transistor according to the first embodiment. The other effects are the same as those of the first embodiment.

  Hereinafter, the process of chemically bonding the semiconductor nanowire 45 and the source electrode 43 / drain electrode 44, which are different from the first embodiment, in the method of manufacturing the field effect transistor of the present embodiment will be described.

  After forming the source electrode 43 and the drain electrode 44 by the manufacturing method described in the first embodiment, the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45 are chemically bonded. As this bonding method, a method in which the entire substrate is put in an electric furnace and heat treatment is performed in an inert atmosphere is preferable. The heat treatment temperature and atmosphere may be appropriately selected according to the source / drain electrode material to be used. Alternatively, bonding may be performed by laser annealing. Moreover, when forming the source electrode 43 and the drain electrode 44 by the apply | coating method, in order to reduce heat processing temperature, it is preferable to use what has a small particle size (1-10 nm) as a source / drain electrode material.

  According to the manufacturing method of the bottom gate type field effect transistor of this embodiment, a high-quality electrical connection with a large area is formed between the source electrode 43 and the drain electrode 44 and the channel layer 46 of the semiconductor nanowire 45. Therefore, when the substrate is a plastic substrate, it is possible to form a field effect transistor with good transistor characteristics on the plastic substrate. Therefore, a highly reliable high performance transistor can be manufactured over a plastic substrate.

(Embodiment 5)
In the bottom gate type field effect transistor of this embodiment, the surface of the semiconductor nanowire 45 covered with the source electrode 43 and the drain electrode 44 is chemically bonded to the source electrode 43 and the drain electrode 44 as shown in FIG. In addition, a sealing film 47 that is an insulating film is provided on the semiconductor nanowire 45 other than the portion covered with the source electrode 43 and the drain electrode 44. The components and manufacturing method of the field effect transistor other than the sealing film 47 are the same as those in the fourth embodiment. The sealing film 47 is the same as that in the second embodiment. Therefore, the structure and manufacturing method of the field effect transistor of this embodiment will be described with reference to Embodiments 2 and 4, and description thereof will be omitted.

  In the manufacturing method, either the sealing film 47 or the chemical bond may be formed first. For example, after the semiconductor nanowire 45 is disposed on the gate insulating film 42, the sealing film 47 is formed, and then the source electrode 43 and the drain electrode 44 are formed, and the chemistry between the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45 is performed. May be performed. Further, before the sealing film 47 is formed, the semiconductor nanowire 45 and the source electrode 43 / drain electrode 44 may be chemically bonded. When an organic material such as polyimide is used as the protective film 47, the semiconductor nanowire 45 is mixed with a polyimide solution, a precursor solution, etc. and applied onto the gate insulating film 42, and the semiconductor nanowire 45 is disposed and the sealing film 47 is formed. May be performed simultaneously.

  In the present embodiment, in addition to the effects of the fourth embodiment, the sealing film 47 has the effects described in the second embodiment.

(Embodiment 6)
In the bottom gate type field effect transistor of this embodiment, the surface of the core-shell type semiconductor nanowire 35 covered with the source electrode 43 and the drain electrode 44 is chemically coupled to the source electrode 43 and the drain electrode 44 as shown in FIG. And a sealing film 47 which is an insulating film is provided on the semiconductor nanowire 35. The components and the manufacturing method of the field effect transistor other than the core-shell type semiconductor nanowire 35 are the same as those in the fifth embodiment. The core / shell type semiconductor nanowire 35 is the same as that of the third embodiment. Therefore, the structure and manufacturing method of the field effect transistor of this embodiment will be described with reference to Embodiments 3 and 5, and description thereof will be omitted.

  In this embodiment, in addition to the effects of the fifth embodiment, the core-shell type semiconductor nanowire 35 has the effects described in the third embodiment.

(Embodiment 7)
In Embodiment 7, a display using an organic electroluminescence element (organic EL element) will be described as an example of the display.

  FIG. 10A is a partially exploded perspective view schematically showing the configuration of the display of this embodiment. The display shown in FIG. 10A includes a drive circuit 51 arranged in an array on a plastic substrate 50. The drive circuit 51 includes the field effect transistor according to any of the first to sixth embodiments, and is connected to the pixel electrode. On the drive circuit 51, the organic EL layer 52, the transparent electrode 53, and the protective film 54 are arrange | positioned. The organic EL layer 52 has a structure in which a plurality of layers such as an electron transport layer, a light emitting layer, and a hole transport layer are stacked. The X scan electrode 56 and the Y scan electrode 55 connected to the electrodes of each transistor are connected to a control circuit including an X driver and a Y driver, respectively.

  FIG. 10B is a circuit diagram in the vicinity of the pixel 59. The pixel 59 is controlled by a switching transistor 57 and a driver transistor 58. A voltage is applied from the Y driver to the source electrode of the switching transistor 57 via the Y scanning electrode 55. The drain electrode of the switch transistor 57 and the gate electrode of the driver transistor 58 are electrically connected. The drain electrode of the driver transistor 58 is electrically connected to a pixel electrode (not shown) disposed below the pixel 59. A voltage for causing the pixel 59 to emit light is applied to the source electrode of the driver transistor 58.

  On the other hand, an image signal voltage is applied from the X driver to the gate electrode of the switching transistor 57 via the X scanning electrode 56. A voltage is applied to the gate electrode of the driver transistor 58 from the switching transistor 57 to which the voltage of the image signal is applied. As a result, a voltage is applied from the driver transistor 58 to the pixel electrode. When a voltage is applied between the pixel electrode and the transparent electrode, the pixel 59 portion emits light.

  Since the display of this embodiment uses any of the field effect transistors of Embodiments 1 to 6 in the drive circuit, a highly reliable and high performance transistor can be formed on the plastic substrate, and the reliability High driving can be performed.

(Other embodiments)
The above embodiments are examples of the present invention, and the present invention is not limited to these examples. For example, the chemical bond between the semiconductor nanowire and the material constituting the source electrode 43 and the drain electrode 44 is not limited to an alloy, but may be a covalent bond or an ionic bond. The display using the field effect transistor may be a liquid crystal or the like.

<Example 1>
Example 1 is an illustration of Embodiment 1. In addition, this Example is an example of Embodiment 1, and this invention is not limited to this Example.

  The field effect transistor of the present embodiment will be described with reference to FIG. As the substrate 40, a PET film having a thickness of 0.5 mm was used. Further, Ag was used as the material of the gate electrode 41, the source electrode 43, and the drain electrode 44. Further, as the semiconductor nanowire 45, a wire made of silicon was used.

  A method for manufacturing the bottom-gate field effect transistor of this example will be described below.

  First, a method for manufacturing the semiconductor nanowire 45 will be described.

  First, a gold fine particle colloid as a catalyst was applied on a Si substrate. Next, the substrate was put into a CVD apparatus, silane or disilane was used as a source gas, and the semiconductor nanowire 45 was formed by the CVD method at a substrate temperature of 400 ° C. The semiconductor nanowire 45 formed at this time was made of Si and had a diameter of 50 nm and a length of 10 to 15 μm.

  Next, the semiconductor nanowire 45 was dispersed in a solvent. As this method, a method was used in which the substrate on which the semiconductor nanowire 45 was grown was immersed in ethanol, and the semiconductor nanowire 45 was peeled off from the substrate by ultrasonic treatment, thereby producing an ink in which the semiconductor nanowire 45 was dispersed.

  Next, using a lithography method, patterning was performed on the PET substrate 40 so that a resist was placed in a region other than the region where the gate electrode 41 was to be formed, and the plastic substrate was etched using the resist as a mask to form a recess having a depth of 300 nm. .

  Then, Ag, which is a gate metal material, was deposited on the etched surface of the substrate 40 by 300 nm using an EB vapor deposition apparatus, and then the resist was removed to form the gate electrode 41.

  Next, 200 nm of SiN was deposited as a gate insulating film 42 on the surface of the substrate 40 on which the gate electrode 41 was formed by a CVD apparatus.

  Furthermore, the above-described ink in which the semiconductor nanowire 45 was dispersed was applied on the gate insulating film 42 by a spin coating method, and the semiconductor nanowire 45 was disposed on the gate insulating film 42.

  Next, patterning was performed on the gate insulating film 42 using a lithography method so that a resist was placed in a region other than the region where the source electrode 43 and the drain electrode 44 were to be formed. At this time, the size of the region for forming the source electrode 43 and the drain electrode 44 was 100 μm × 100 μm, and the distance between the source electrode 43 and the drain electrode 44 was 30 μm. Then, the gate insulating film 42 was etched by 50 nm by dry etching using the resist as a mask. By this etching, a gap of 50 nm was formed between the semiconductor nanowire 45 and the gate insulating film 42 in the region where the source electrode 43 and the drain electrode 44 were formed.

  Thereafter, Ag particles were applied to a region where the source electrode 43 and the drain electrode 44 were formed by an inkjet method, and Ag was deposited to a thickness of 300 nm to form the source electrode 43 and the drain electrode 44. At this time, the average particle diameter of Ag particles used in the ink was 3 nm. Moreover, the solvent of the ink was toluene, and the viscosity of the ink was 5 mPa · s. The applied ink was baked at 180 ° C. for 2 hours. Thus, the semiconductor nanowire 45 was covered with the source electrode 43 and the drain electrode 44 from the bottom X up to 50 nm upward. That is, in the region where the source electrode 43 and the drain electrode 44 are formed, the entire surface of the semiconductor nanowire 45 is covered with the source electrode 43 and the drain electrode 44.

  Finally, the bottom gate type field effect transistor of this example was manufactured by removing the resist.

  FIG. 11 shows current-voltage characteristics which are one of the transistor characteristics in nitrogen of the bottom-gate type field effect transistor of this example. Further, as Comparative Example 1, the constituent material is the same as that of the transistor of this example, and the characteristics of the field effect transistor having the structure shown in FIG. 2 are also shown in FIG. From this figure, it can be seen that the current of the field effect transistor of this example increases over a wider voltage range than the field effect transistor of Comparative Example 1, and the current flowing through the channel layer increases. In other words, in this embodiment, since the semiconductor nanowire 45 is covered by the source electrode 43 and the drain electrode 44 from the bottom X upward by 5 nm or more (specifically, up to 50 nm), the semiconductor nanowire 45 appears to be in nitrogen on the plastic substrate. In such an inert atmosphere, a highly reliable high-performance transistor could be manufactured.

<Example 2>
Example 2 is an illustration of Embodiment 2. In addition, this Example is an example of Embodiment 2, and this invention is not limited to this Example.

  The field effect transistor of the present embodiment will be described with reference to FIG. As the substrate 40, a PET film having a thickness of 0.5 mm was used. Further, Ag is used as the material of the gate electrode 41, the source electrode 43, and the drain electrode 44. Further, as the semiconductor nanowire 45, a wire made of silicon was used. In addition, polyimide was used as the sealing film 47 material.

  Since the basic configuration and manufacturing method of the bottom gate type field effect transistor in this example are the same as those in Example 1 except for the sealing film 47, only the sealing film 47 will be described. A polyimide solution is applied by spin coating on the substrate 40 formed in the order of the gate electrode 41, the gate insulating film 42, the semiconductor nanowire 45, the source electrode 43, and the drain electrode 44, and dried to provide a thickness of 500 nm. A stop film 47 was formed.

  FIG. 12 shows current-voltage characteristics which are one of the transistor characteristics in the atmosphere of the bottom gate field effect transistor of this example. Further, as Comparative Example 2, the characteristics of the field effect transistor shown in Example 1 in which the semiconductor nanowire 45 and the source / drain electrodes are formed in this order on the gate insulating film 42 and the sealing film is not provided are also shown in FIG. FIG. 12 shows atmospheric data unlike the nitrogen data of FIG. From this figure, in Comparative Example 2, current flows even if the absolute value of Vgs is small, and the ratio of on-current to off-current (on-off ratio) is small, whereas in this embodiment, the absolute value of Vgs is It can be seen that when it is large, the flowing current is large, and when the absolute value of Vgs is small, the flowing current is small and the on / off ratio can be increased. Therefore, it can be seen that by providing the sealing film 47 on the semiconductor nanowire 45, transistor characteristics that are hardly affected by moisture and oxygen in the atmosphere are obtained.

<Example 3>
Example 3 is an illustration of Embodiment 3. This example is an example of Embodiment 3, and the present invention is not limited to this example.

The field effect transistor of Example 3 will be described with reference to FIG. As the substrate 40, a PET film having a thickness of 0.5 mm was used. Further, Ag is used as the material of the gate electrode 41, the source electrode 43, and the drain electrode 44. As the semiconductor nanowire 35, a core-shell type semiconductor nanowire 35 in which the surface layer 33 is made of SiO ₂ and the core portion 32 is made of Si is used. In addition, polyimide was used as the sealing film 47 material.

  Since the basic configuration and manufacturing method of the bottom gate type field effect transistor in the present embodiment are substantially the same as those in the second embodiment except for the structure of the semiconductor nanowire 35, the differences from the second embodiment will be described. In addition, in Example 2, the same part as Example 1 refers to the description of Example 1.

  The core-shell type semiconductor nanowire 35 was produced as follows.

  First, a gold fine particle colloid as a catalyst was applied on a Si substrate. Next, the substrate was put in a CVD apparatus, silane or disilane was used as a source gas, a substrate temperature was set to 400 ° C., and semiconductor nanowires made of Si were formed by a CVD method. At this point, the semiconductor nanowire is not a core-shell structure.

  Next, the substrate on which the semiconductor nanowires were grown was placed in a reactor and thermally oxidized at 1100 ° C. by rapid thermal processing in an oxygen atmosphere to form core / shell type semiconductor nanowires 45. The core-shell type semiconductor nanowire 35 formed by this thermal oxidation had a length of 10 to 15 μm, a diameter of 80 nm, a diameter of the core portion 32 of 50 nm, and a thickness of the surface layer 33 of 15 nm.

  Next, the core-shell type semiconductor nanowire 35 was dispersed in a solvent. As this method, an ink in which the semiconductor nanowires 35 are dispersed was prepared by immersing the substrate on which the semiconductor nanowires 35 were grown in ethanol and peeling the core-shell type semiconductor nanowires 35 from the substrate by ultrasonic treatment.

  Then, the above-described semiconductor nanowire ink was applied to the gate insulating film 42 manufactured according to the manufacturing method described in Example 1 by a spin coating method, and the core-shell type semiconductor nanowire 35 was disposed on the gate insulating film 42. At this time, the gate insulating film 42 was only formed by the CVD method and was not etched.

  Next, patterning was performed on the semiconductor nanowire 35 using a lithography method so that a resist was placed in a region other than the region where the source electrode 43 and the drain electrode 44 were to be formed. Then, the surface layer 33 of the core-shell type semiconductor nanowire 35 in the source / drain electrode region was removed with hydrofluoric acid using the resist as a mask.

  Thereafter, the source electrode 43 and the drain electrode 44 were formed in the same manner as in Example 1. Finally, the resist was removed, and polyimide was applied to form a sealing film 47 in the same manner as in Example 2 to produce a bottom gate type field effect transistor of this example.

  FIG. 13 shows a current-voltage characteristic which is one of the transistor characteristics in nitrogen of the bottom gate field effect transistor of this example. For comparison, the characteristics of the field effect transistor of Example 1 are also shown in FIG. From this figure, by using the core-shell type semiconductor nanowire 35 as a channel, it is less susceptible to the influence of moisture and oxygen in the atmosphere, and the transistor is better than that of the first embodiment without etching the gate insulating film 42. It can be seen that the characteristics were obtained.

<Example 4>
Example 4 is an illustration of the fourth embodiment. In addition, this Example is an example of Embodiment 4, and this invention is not limited to this Example.

  The field effect transistor of this example will be described with reference to FIG. As the substrate 40, 0.7 mm thick glass was used. Further, Al was used as the material of the gate electrode 41, and Ni was used as the material of the source electrode 43 and the drain electrode 44. Further, as the semiconductor nanowire 45, a wire made of silicon was used. This embodiment is different from the first embodiment in that a part of the surface of the semiconductor nanowire 45 is chemically bonded to the constituent material of the source electrode 43 and the drain electrode 44. Therefore, the description will focus on the differences from the first embodiment.

  In the present embodiment, as in the first embodiment, the source electrode 43 and the drain electrode 44 are formed so as to cover the surface of the semiconductor nanowire 45 from the bottom to the top. Further, the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45 are chemically bonded to form an alloy part 48 made of silicide, and the energy levels of the source electrode 43 and the drain electrode 44 and the semiconductor nanowire 45 are An intermediate level is formed between the energy levels. Therefore, the contact area where the source electrode 43 / drain electrode 47 and the channel layer 46 are in electrical contact with each other is increased, and the alloy portion 48 is present, so that the source electrode 43, the drain electrode 44 and the semiconductor are present. The charge barrier between the nanowire 45 and the nanowire 45 is small, and the transistor characteristics are improved as compared with the first embodiment.

  Hereinafter, a manufacturing method of the bottom gate type field effect transistor of this example will be described.

  The manufacturing method of the semiconductor nanowire 45 and the semiconductor nanowire ink is the same as that in the first embodiment. First, using a lithography method, patterning was performed on the glass substrate 40 so that a resist was placed in a region other than the region where the gate electrode 41 was to be formed.

  Then, Al, which is a gate metal material, was deposited on the patterning surface of the glass substrate 40 with a thickness of 300 nm by an EB vapor deposition apparatus, and then the resist was removed to form the gate electrode 41.

  Next, in the same manner as in Example 1, the gate insulating film 42 was formed, etched, and the semiconductor nanowires 45 were arranged.

  Then, using a lithography method, patterning was performed on the substrate 40 on which the semiconductor nanowire 45 was placed so that a resist was placed in a region other than the region where the source electrode 43 and the drain electrode 44 were formed. At this time, the size of the region for forming the source electrode 43 and the drain electrode 44 was 100 μm × 100 μm, and the distance between the source electrode 43 and the drain electrode 44 was 30 μm. Thereafter, Ni was deposited to a thickness of 300 nm by an EB vapor deposition apparatus in a region where the source electrode 43 and the drain electrode 44 were to be formed, and then the resist was removed, thereby forming the source electrode 43 and the drain electrode 44. At this time, by changing the angle of the substrate 40 with respect to the electrode material evaporation source with the bisector of the surface of the substrate 40 extending in the direction in which the semiconductor nanowire 45 extends as the rotation axis, the Ni electrode is also applied to the bottom X of the semiconductor nanowire 45. Was formed to wrap around.

  FIG. 17 shows the positional relationship between the substrate 40 and the electrode material evaporation source 80 during vapor deposition. In order to deposit Ni, the substrate 40 is first fixed to the substrate stage 70. At this time, the substrate 40 is arranged such that the direction in which the semiconductor nanowire 45 extends and the rotation axis 72 of the substrate stage 70 are parallel, that is, the bisector of the substrate surface and the rotation axis 72 of the substrate stage 70 are parallel. To fix. At the time of fixing, the vapor deposition surface of the substrate 40 and the line connecting the electrode material evaporation source 80 and the rotating shaft 72 are orthogonal to each other. Then, at the time of deposition of Ni, the substrate stage 70 was rotated about the rotation shaft 72 so that the Ni electrode also wraps around the bottom X of the semiconductor nanowire 45. The rotation angle of the substrate stage 70 at this time is up to 87 degrees in the counterclockwise direction (+ direction) and up to 87 degrees in the clockwise direction (− direction) when the fixed state is 0 degree (−). 87 degrees).

  Finally, the substrate 40 on which the field effect transistor is formed is heat-treated at 500 ° C. by rapid thermal processing in a nitrogen atmosphere, and the semiconductor nanowire 45 and the source electrode 43 and the drain electrode 44 are alloyed to form the bottom of this embodiment. A gate type field effect transistor was fabricated.

  FIG. 14 shows a current-voltage characteristic which is one of the transistor characteristics in nitrogen of the bottom gate field effect transistor of this example. As a comparative example 3, the constituent material is the same as that of the transistor of this example, and the characteristics of the field effect transistor having the structure shown in FIG. 2 are also shown in FIG. Note that Comparative Example 1 and Comparative Example 3 are the same.

  From this figure, it can be seen that the current of the field effect transistor of this example increased over a wider voltage range than the field effect transistor of Comparative Example 3, and the current flowing through the channel layer increased. It can be seen that the transistor has high transistor characteristics under an inert atmosphere as shown in FIG.

<Example 5>
Example 5 is an illustration of the fifth embodiment. In addition, this Example is an example of Embodiment 5, and this invention is not limited to this Example.

  The field effect transistor of this example will be described with reference to FIG. Since the present embodiment is the same as the fourth embodiment except that the sealing film 47 exists, the difference from the fourth embodiment will be mainly described.

  As a material for the sealing film 47, polyimide was used. Then, the gate electrode 41, the gate insulating film 42, the semiconductor nanowire 45, the source electrode 43 and the drain electrode 44 are formed and arranged in this order on the substrate 40, and on the field effect transistor which is heat-treated at 500 ° C. in nitrogen. Then, a polyimide solution was applied by using a spin coating method and dried to form a sealing film 47 having a thickness of 500 nm.

  FIG. 15 shows current-voltage characteristics which are one of the transistor characteristics in the atmosphere of the bottom-gate type field effect transistor of this example. For comparison, the characteristics of the field effect transistor of Example 4 in which the sealing film 47 is not provided are also shown in FIG. Note that the transistor characteristics shown in FIG. 14 of the transistor according to Example 4 are characteristics in nitrogen, which is different from the characteristics shown in FIG. 15 in the atmosphere. As described in Example 2, it can be seen from FIG. 15 that by providing the sealing film 47 on the semiconductor nanowire 45, transistor characteristics that are not easily affected by moisture or oxygen in the atmosphere are obtained.

<Example 6>
Example 6 is an illustration of the sixth embodiment. This example is an example of the sixth embodiment, and the present invention is not limited to this example.

  The field effect transistor of the present embodiment will be described with reference to FIG. Note that this example is the same as Example 5 except that the semiconductor nanowire 35 has a core-shell type structure, and therefore, differences from Example 5 will be mainly described.

  The basic configuration and manufacturing method of the bottom gate type field effect transistor in this example are substantially the same as those in Example 5. In addition, since the structure and manufacturing method of Example 5 refer to the structure and manufacturing method of Examples 1 to 4, the configuration and manufacturing method of Examples 1 to 4 are also referred to in this example. The core / shell type semiconductor nanowire 35 and the method for producing the semiconductor nanowire ink are the same as those in Example 3.

  The manufacture of the field effect transistor of this example was started by first forming the gate insulating film 42 on the substrate 40 in the same manner as in Example 4. The semiconductor nanowire ink described above was applied onto the gate insulating film 42 by spin coating, and the core / shell type semiconductor nanowire 35 was disposed on the gate insulating film 42.

  Next, patterning was performed on the semiconductor nanowire 35 using a lithography method so that a resist was placed in a region other than the region where the source electrode 43 and the drain electrode 44 were to be formed. At this time, the size of the region for forming the source electrode 43 and the drain electrode 44 was 100 μm × 100 μm, and the distance between the source electrode 43 and the drain electrode 44 was 30 μm.

  Then, using the resist as a mask, the surface layer 33 of the semiconductor nanowire 35 in the region where the source electrode 43 and the drain electrode 44 are formed was removed with hydrofluoric acid.

  Next, the source electrode 43 and the drain electrode 44 are formed in the same manner as in the fourth embodiment, and the sealing film 47 is formed in the same manner as in the fifth embodiment, whereby the bottom gate type field effect transistor of the present embodiment is obtained. Produced.

  FIG. 16 shows current-voltage characteristics, which is one of the transistor characteristics in nitrogen of the bottom-gate field effect transistor of this example. For comparison, the characteristics of the field effect transistor of Example 4 in which the sealing film 47 is not provided and the semiconductor nanowire 45 is not the core-shell type are also shown in FIG. From FIG. 16, by providing the core-shell type semiconductor nanowire 35 as a channel, it is difficult to be affected by moisture and oxygen in the atmosphere, and the gate insulating film 42 is not etched, so that good transistor characteristics can be obtained. I understand that.

  As described above, the field effect transistor according to the present invention has a low charge injection barrier between the source and drain electrodes and the channel layer, and is used for an electronic device or a microdevice using a flexible display or a flexible substrate. Useful as.

(A) is sectional drawing of an example of the field effect transistor using a semiconductor nanowire, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of another example of the field effect transistor using semiconductor nanowire, (b) is the sectional view on the AA line of (a). It is a cross-sectional view of a core-shell type semiconductor nanowire. (A) is sectional drawing of the field effect transistor which concerns on Embodiment 1, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of the field effect transistor which concerns on Embodiment 2, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of the field effect transistor which concerns on Embodiment 3, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of the field effect transistor which concerns on Embodiment 4, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of the field effect transistor which concerns on Embodiment 5, (b) is the sectional view on the AA line of (a). (A) is sectional drawing of the field effect transistor which concerns on Embodiment 6, (b) is the sectional view on the AA line of (a). (A) is a partially exploded perspective view schematically showing an organic EL display in Embodiment 7, and (b) is a circuit diagram of a pixel driving transistor. 3 is a transistor characteristic diagram of a field effect transistor in Example 1. FIG. 6 is a transistor characteristic diagram of a field effect transistor in Example 2. FIG. 6 is a transistor characteristic diagram of a field effect transistor in Example 3. FIG. 6 is a transistor characteristic diagram of a field effect transistor in Example 4. FIG. 10 is a transistor characteristic diagram of a field effect transistor in Example 5. FIG. 10 is a transistor characteristic diagram of a field effect transistor in Example 6. FIG. It is a figure which shows rotation of the substrate stage at the time of vapor deposition in Example 6. FIG.

Explanation of symbols

41 Gate electrode 42 Gate insulating film 43 Source electrode 44 Drain electrode 35, 45 Semiconductor nanowire 46 Channel layer 32 Core part 33 Surface layer 40, 50 Substrate 47 Sealing film 48 Alloy part (chemical bond part)
51 Drive Circuit 52 Organic EL Layer 53 Transparent Electrode 54 Protective Film 55 X Scan Electrode 56 Y Scan Electrode 57 Switch Transistor 58 Driver Transistor 59 Pixel

Claims (10)

A substrate,
A gate electrode provided on the substrate;
A gate insulating film provided on the gate electrode;
A source electrode and a drain electrode provided on the gate insulating film;
A semiconductor nanowire electrically connected to both the source electrode and the drain electrode and disposed on the gate insulating film and functioning as a channel;
A field effect transistor, wherein a portion of the surface of the semiconductor nanowire extending from the bottom of the semiconductor nanowire closest to the gate electrode to at least 5 nm upward is covered with the source electrode and the drain electrode.   The field effect transistor according to claim 1, wherein a surface of the semiconductor nanowire covered with the source electrode and the drain electrode is chemically bonded to the source electrode and the drain electrode.   The field effect transistor according to claim 1 or 2, wherein a portion of the surface of the semiconductor nanowire other than a portion covered with the source electrode and the drain electrode is covered with an insulating film.   The field effect transistor according to claim 3, wherein a surface layer and a core portion of the semiconductor nanowire are made of different materials except for portions of the semiconductor nanowire covered by the source electrode and the drain electrode.   The field effect transistor according to claim 4, wherein the core portion other than the portion covered with the source electrode and the drain electrode in the semiconductor nanowire is made of Si. The semiconductor surface layer other than the portion covered with the source electrode and the drain electrode of the nanowire is composed of SiO _2, the field effect transistor according to claim 4 or 5.   The field effect transistor according to any one of claims 1 to 6, wherein the substrate is made of a polymer material or a composite of a polymer material and an inorganic material.   A TFT element comprising the field effect transistor according to claim 1.   A panel comprising the TFT element according to claim 8.   A display comprising the panel according to claim 9.

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