JP2007324583A - Integrated semiconductor light-emitting device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of an integrated compound semiconductor light-emitting device suitable for large-area light emission like a surface light source, and to provide a manufacturing method thereof. <P>SOLUTION: The integrated semiconductor light-emitting device has a plurality of light-emitting units. Each of the light-emitting units has at least a thin-film crystal layer having a first conductivity-type semiconductor layer 24, an active layer structure 25 and a second conductivity-type semiconductor layer 26. A main light extracting direction is a direction of the first conductivity-type semiconductor layer 24 side. The first and second conductivity-type-side electrodes 27, 28 are formed on the opposite side. The light-emitting units 11 are electrically separated from each other by inter-light-emitting unit separating trenches 12 formed by removing a portion from the surface of the thin-film crystal growing layer to one part of the buffer layer 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated compound semiconductor light emitting device, and more particularly to a light emitting diode (LED) using a GaN-based material. Note that in this specification, the expression “light-emitting diode or LED” is used as a term including a general light-emitting element including a laser diode, a superluminescent diode, and the like.

  Conventionally, electronic devices and light-emitting devices using III-V compound semiconductors are known. In particular, as light emitting devices, red light emission by an AlGaAs-based material or AlGaInP-based material formed on a GaAs substrate, orange or yellow light emission by a GaAsP-based material formed on a GaP substrate has been realized. An infrared light emitting device using an InGaAsP material on an InP substrate is also known.

  As a form of these devices, a light emitting diode (LED) utilizing spontaneous emission light, a laser diode (laser diode: LD) having an optical feedback function for extracting stimulated emission light, and a semiconductor Lasers are known, and these have been used as display devices, communication devices, high-density optical recording light source devices, high-precision optical processing devices, and medical devices.

Since the 1990s, In _x Al _y Ga _(1-xy) N-based III-V compound semiconductors (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ ₎ containing nitrogen as a group V element The research and development of 1) has progressed, and the luminous efficiency of devices using the same has been dramatically improved, and highly efficient blue LEDs and green LEDs have been realized. Subsequent research and development have realized highly efficient LEDs even in the ultraviolet region, and now blue LDs are also commercially available.

  When an ultraviolet or blue LED is integrated as an excitation light source with a phosphor, a white LED can be realized. Since white LEDs have the potential to be used as next-generation lighting devices, the industrial significance of increasing the output and efficiency of ultraviolet or blue LEDs serving as excitation light sources is extremely large. At present, studies are being made to increase the efficiency and output of blue or ultraviolet LEDs with the illumination application in mind.

  In order to increase the output of the element, that is, to improve the total radiant flux, it is essential to increase the size of the element and to ensure resistance to a large input power. In addition, an element that is sufficiently large compared to a normal LED as a point light source exhibits light emission characteristics as a surface light source, and is particularly suitable for illumination applications.

  However, an element in which the area of a normal small LED is simply increased in a similar manner generally has a problem that the uniformity of the light emission intensity of the entire element cannot be obtained. Therefore, it is conceivable to arrange a plurality of elements on the substrate. For example, a technique for forming a plurality of LEDs on the same substrate is disclosed in JP-A-11-150303 (Patent Document 1), JP-A-2001-156331 (Patent Document 2), and JP-A-2002-26384 (Patent Document 1). Document 3) and Japanese Patent Application Laid-Open No. 2003-115611 (Patent Document 4).

  Japanese Patent Application Laid-Open No. 11-150303 (Patent Document 1) discloses an integrated light-emitting component in which a plurality of LEDs are connected in series on a substrate. In this document, in order to electrically and completely separate a part having a pair of pn junctions which are a single light emitting unit, a Ni mask is used to etch a GaN layer until the insulating substrate is exposed. (See paragraph 0027). However, the method of dry etching a GaN-based material using a metal mask such as Ni does not necessarily have a high resistance to the metal mask. There is a problem in the control, and as a result, the light emitting units have to be largely separated from each other. Therefore, each light emitting unit is merely an individual LED formed separately on the same substrate. In addition, since the resistance of the metal mask is low, a sufficiently thick buffer layer necessary for manufacturing a light-emitting element with favorable crystallinity cannot be used. That is, since the metal mask cannot etch the GaN-based material to a sufficient depth, the buffer layer becomes a thin film in order to produce the structure of Patent Document 1 with the metal mask. In the examples of the specification, as described in paragraph 19, the total 3.6 μm of the n-GaN layer 3.0 μm (nGaN buffer layer), the light emitting layer 0.1 μm, and the p-GaN layer 0.5 μm is etched on the substrate. Only. There is a problem that the crystallinity of the element structure portion formed thereon must be sacrificed.

  That is, the light-emitting device described in Patent Document 1 is not substantially different from a plurality of light-emitting elements each having a single light-emitting unit on a substrate, and is a surface light source with high emission intensity uniformity. is not. As shown in FIG. 6 of Patent Document 1, it is shown that there is no light emission in the separation groove portion separating each light emitting unit. Moreover, in such a form, when one of the light emitting units in the integrated element is deteriorated, there is a problem that the light emission intensity is extremely lowered only at that portion. Furthermore, the light emitting layer portion could not be made of good crystallinity due to restrictions on the manufacturing method.

  Japanese Patent Application Laid-Open No. 2001-156331 (Patent Document 2) also describes an integrated device in which a plurality of light emitting units are formed on the same substrate. However, also in this document, as shown in FIG. 2, the light emitting units including a pair of pn junction portions are completely separated from each other by separation grooves, and are individual LEDs on the same substrate. Only. What is formed by the conventional manufacturing method has to have a large width of the separation groove portion separating the light emitting units (the manufacturing method is not disclosed), so the distance of the non-light emitting portion is large, and the surface light source Uniformity of light emission intensity as a whole cannot be ensured. Therefore, even when one light emitting unit in the integrated element is deteriorated, the light emission intensity is extremely lowered only at that portion.

  In addition, since the mask of the conventional manufacturing method does not have a sufficient selection ratio, the GaN-based material cannot be etched to a sufficient depth, so that it is sufficient to produce a light-emitting element with good crystallinity. A thick buffer layer cannot be used. Although the specification does not disclose all the layer configurations, as described in paragraph 12, the buffer layer only discloses that the low temperature portion is about 20 nm.

Japanese Laid-Open Patent Publication No. 2002-26384 (Patent Document 3) discloses an LED integration method for the purpose of providing an integrated nitride semiconductor light emitting device having a large area and good light emission efficiency. However, as described in FIG. 2, FIG. 3 and paragraph 0038, the separation groove between the light emitting unit and the other light emitting unit portion is formed by the RIE method until reaching the sapphire substrate using SiO ₂ as a mask. It is formed by etching. In this separation groove forming process, since SiO ₂ is used as an etching mask (the resistance of the oxide mask and the nitride mask is not necessarily high), when etching the GaN-based material, the selection ratio cannot be taken. There is a problem in the shape control of etching, and the width of the separation groove portion must be increased. Therefore, the distance of the part which does not light-emit is large, and the uniformity of the emitted light intensity in the whole surface light source cannot be ensured like patent document 1,2. Therefore, when one of the light emitting units in the integrated element is deteriorated, the light emission intensity is extremely reduced only at that portion. Further, since the resistance of the SiO ₂ mask is low, it is not possible to use a sufficiently thick buffer layer necessary for manufacturing a light-emitting element with good crystallinity. That is, in the SiO ₂ mask can not be etched GaN material sufficient depth, to make the structure of Patent Document 3 in SiO ₂ mask, the buffer layer becomes a thin film. In the example of this specification, as described in paragraph 19, the n-GaN layer 1.5 μm (undoped GaN layer) is only formed as a buffer layer on the substrate, and the element structure portion formed thereon is formed. There was a problem that the crystallinity of the material had to be sacrificed.

Japanese Patent Laid-Open No. 2003-115611 (Patent Document 4) discloses a light emitting device in which LEDs are integrated for the purpose of use as a surface emitting light source or a display. This document describes two types of devices, one of which is a device in which light emitting units including a pair of pn junctions are electrically isolated from one another (claim 4). FIG. 10 (b) and the like. This separation is formed by dicing (FIG. 10). In this type, as in the above three documents, the emission intensity is greatly reduced at the separation groove portion between the light emitting units, so that uniformity over the entire surface light source cannot be ensured. In addition, when one of the light emitting units is deteriorated, there is a problem that the light emission intensity is extremely lowered only in the vicinity thereof. The second type of device described in this document is a device in which light-emitting units including a pair of pn junction portions are electrically coupled to each other (Claim 5, FIG. 10 (a), etc.) ). In this type, the n-type semiconductor layer is common to the entire light emitting device (FIG. 10A). In such a case, not only the current flows from the n-side electrode to the nearest p-side electrode, but also the current flows from one n-side electrode to every p-side electrode. Current injection efficiency is not high. In addition, since all the p-side electrodes and all the n-side electrodes are electrically coupled, the deterioration at one place becomes the deterioration of the entire apparatus. Therefore, this type of device is essentially unsuitable for increasing the area for a surface light source.
Japanese Patent Laid-Open No. 11-150303 JP 2001-156331 A JP 2002-26384 A JP 2003-115611 A

  As described above, there have been proposals for forming a plurality of light emitting units on the same substrate, but the structure is not suitable for integration for the purpose of a surface light source.

  That is, an object of the present invention is to provide a structure of an integrated compound semiconductor light emitting device suitable for large area surface light emission and a method for manufacturing the same.

  The present invention relates to the following matters.

1. An integrated compound semiconductor light emitting device having a plurality of light emitting units,
The light emitting unit includes a compound semiconductor thin film crystal layer having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer; Having at least a conductivity type side electrode, and a first conductivity type side electrode,
The main light extraction direction is the first conductivity type semiconductor layer side direction when viewed from the active layer structure, and the first conductivity type side electrode and the second conductivity type side electrode are opposite to the main light extraction direction. Formed on the side,
A buffer layer provided in common between the plurality of light emitting units on the main light extraction direction side from the first conductive type semiconductor layer;
The light emitting units are provided between adjacent light emitting units, and are formed by removing the light emitting unit separation grooves from the surface of the thin film crystal layer to the interface of the buffer layer or a part of the buffer layer. An integrated compound semiconductor light emitting device characterized in that it is electrically isolated by

  2. 2. The light emitting device according to 1 above, wherein the buffer layer is a layer formed by thin film crystal growth.

  3. 3. The light emitting device according to 1 or 2 above, wherein a specific resistance of at least a portion of the buffer layer in direct contact with the first conductivity type semiconductor layer is 0.5 (Ω · cm) or more.

  4). 4. The light emitting device according to any one of the above items 1 to 3, wherein the specific resistance of the entire buffer layer is 0.5 (Ω · cm) or more.

  5. 5. The light emitting device according to any one of 1 to 4, wherein the buffer layer has a stacked structure of a plurality of layers.

  6). 6. The light emitting device according to any one of 1 to 5, wherein a width of the light emitting unit separation groove is in a range of 2 to 300 μm.

  7). The light-emitting device is divided from an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway through the buffer layer. The light-emitting device in any one of 1-6.

  8). The light emitting device is divided from an inter-device separation groove provided between a plurality of light emitting devices, and the inter-device separation groove is formed by removing the buffer layer. 7. The light emitting device according to any one of 1 to 6 above.

  9. Of the layers exposed on the side surfaces of the light emitting device, covering the entire bottom surface and side surfaces in the light emitting unit separation groove, at least the side surfaces of the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer And an insulating layer that is in contact with a part of the first conductivity type side electrode on the main light extraction direction side and covers a part of the second conductivity type side electrode opposite to the main light extraction direction. 9. The light emitting device according to any one of 1 to 8 above.

  10. An insulating layer non-formation region where the insulating layer is not formed is present on the side surface of the light emitting device from the main light extraction direction, and the insulating layer is at least the first conductive semiconductor layer, the active layer structure 10. The light emitting device as described in 9 above, wherein the light emitting device covers the side walls of the second conductive type semiconductor layer.

  11. 11. The light emitting device according to any one of the above 1 to 10, wherein the thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V.

12 When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting device according to any one of 1 to 11 above, wherein:

  13. 11. The light emitting device as described in 9 or 10 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

14 The reflectance at which the light of the emission wavelength of the light emitting device perpendicularly incident on the buffer layer from the first conductivity type semiconductor layer side is reflected by the buffer layer is represented by R2, and the second conductivity type semiconductor layer is formed on the insulating layer. R12 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident from the side is reflected by the insulating layer, and light having the emission wavelength of the light emitting device that is perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. When the reflectance reflected by the insulating layer is represented by R11, and the reflectance by which the light having the emission wavelength of the light emitting device perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is represented by R1q. ,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
14. The light-emitting device according to any one of 9, 9, and 13, wherein the insulating layer is configured to satisfy all of the above conditions.

  15. 15. The light emitting device according to any one of 1 to 14 above, wherein a surface of the buffer layer in a main light extraction direction is not flat.

16. R3 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer is reflected by the buffer layer, and the light emission that is perpendicularly incident on the light extraction side space from the buffer layer. When the reflectance at which the light of the emission wavelength of the device is reflected at the interface with the space is represented by R4, R4 <R3
16. The light-emitting device according to any one of 1 to 15, wherein a low-reflection optical film is provided on the light extraction side of the buffer layer so as to satisfy the above.

  17. 17. The light-emitting device according to any one of 1 to 16, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  18. 18. The light emitting device according to any one of 1 to 17, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having a metal surface by metal solder.

  19. 19. The above-mentioned 18 characterized in that the first conductive type side electrode and the second conductive type side electrode and the metal surface of the support are joined by only metal solder or metal solder and metal bumps. Light-emitting device.

20. 20. The light emitting device as described in 18 or 19 above, wherein the base material of the support is selected from the group consisting of metal, AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN and CuW.

  21. 21. The light-emitting device according to any one of 18 to 20, wherein a metal layer is not formed in a separation portion between the light-emitting devices of the support.

22. A method of manufacturing an integrated compound semiconductor light emitting device having a plurality of light emitting units on a support,
Forming a buffer layer on the substrate;
Forming a thin film crystal layer having at least a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer;
Forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
A first etching step of exposing a portion of the first conductivity type semiconductor layer to the surface;
Forming a first conductivity type side electrode on the exposed surface of the first conductivity type semiconductor layer by the first etching step;
From the thin film crystal layer surface to the interface of the buffer layer, or from the thin film crystal layer surface to a part of the buffer layer, in order to form a light emitting unit separation groove for electrically separating the light emitting units from each other A second etching step to remove
A third etching step of removing at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer to form an inter-device separation groove for separating into a plurality of light emitting devices;
And a step of removing the substrate. A method of manufacturing an integrated compound semiconductor light emitting device.

  23. Before the step of removing the substrate, the first conductivity type side electrode and the second conductivity type side electrode are bonded to a metal surface on a support and mounted on the support. 23. The method according to 22 above.

  24. 24. The method according to 23, further comprising a step of separating the light emitting devices after the step of removing the substrate.

  25. The film forming step of the buffer layer is performed as a part of the film forming step of the thin film crystal layer and prior to the formation of the first conductivity type semiconductor layer. the method of.

  26. 26. The method according to any one of 22 to 25 above, wherein a specific resistance of at least a portion of the buffer layer that is in direct contact with the first conductivity type semiconductor layer is 0.5 (Ω · cm) or more.

  27. 27. The method according to any one of the items 22 to 26, wherein a specific resistance of the entire buffer layer is 0.5 (Ω · cm) or more.

  28. 28. The method according to any one of 22 to 27, wherein the buffer layer is formed as a stacked structure of a plurality of layers.

  29. The third etching step is performed simultaneously with or separately from the second etching step, and etching is performed from the surface of the thin film crystal layer to the interface of the buffer layer or until a part of the buffer layer is removed from the surface of the thin film crystal layer. 29. The method according to any one of the above 22 to 28, which is performed.

  30. 29. The method according to any one of the items 22 to 28, wherein in the third etching step, etching is performed until at least the surface of the substrate is reached.

31. The second and third etching steps are performed by dry etching using a gas species selected from the group consisting of Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations of two or more thereof. 31. The method according to any one of 22 to 30 above.

  32. 32. The method according to 31 above, wherein a patterned metal fluoride layer is used as an etching mask.

33. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and method of the above 32, wherein the selected from the group consisting of.

  34. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order, and before the step of forming the first conductivity type side electrode, 34. The method according to any one of 22 to 33, further comprising a step of forming an insulating layer.

  35. 35. The method according to 34 above, wherein the step of forming the insulating layer is performed after the first to third etching steps.

36. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, etching is performed at a depth from the surface to remove at least a part of the buffer layer to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
29. The method according to any one of 22 to 28, further comprising: removing a part of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove to form a scribe region.

37. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, etching is performed at a depth from the surface until at least a part of the buffer layer is removed or at least reaches the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
A step of removing all of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove and a part of the insulating layer formed on the side wall of the inter-device separation groove on the groove bottom surface side. 29. The method according to any one of 22 to 28 above.

  38. The second and third etching steps are performed at the same time, and etching is performed until the interface of the buffer layer or until a part of the buffer layer is removed, thereby forming the inter-device separation groove. The method described.

  39. 37. The device separation groove is formed by performing the second and third etching steps at the same time and performing etching until the interface of the buffer layer or until a part of the buffer layer is removed. The method described.

  40. The step of removing the substrate is performed by irradiating light from the substrate side with light having a wavelength that is transparent to the substrate and is absorbed by the buffer layer. The method according to any one of 22 to 39, which is performed by causing separation at an interface between the substrate and the buffer layer.

  41. 24. The method according to claim 23, wherein the first conductive type side electrode and the second conductive type side electrode and the metal surface on the support are joined with metal solder.

42. 42. The method according to 23 or 41, wherein the base material of the support is selected from the group consisting of metal, AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN, and CuW.

43. Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, A method according to any one of the above 22 to 42, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.

  ADVANTAGE OF THE INVENTION According to this invention, the integrated compound semiconductor light-emitting device which has a structure suitable for surface area light emission of a large area, and its manufacturing method can be provided.

In particular, according to the present invention, even when the area of the light emitting device exceeds several cm ² , it is possible to emit a blue or ultraviolet light with a high uniformity of light emission intensity. In addition, since the present invention is a flip chip type and can be mounted on a submount, sufficient heat dissipation and high light extraction efficiency can be ensured.

  In the present invention, since the light emitting unit separation groove is not formed by removing all layers including the buffer layer, adjacent light emitting units can be brought close to each other while being electrically separated. . Therefore, it is very advantageous for improving the integration density and emitting light as a surface light source. In addition, since deterioration at one location does not affect the entire apparatus, it is excellent in terms of reliability. Furthermore, since it is only necessary to form the isolation groove between the light emitting units up to a part of the buffer layer which is common between the light emitting units and has a sufficiently high resistance, it is sufficiently thick without considering the etching depth limitation. A buffer layer can also be used. For this reason, it is possible to improve the crystallinity of the light emitting element portion, which is desirable from the viewpoint of increasing the output of the light emitting device. Also, it is desirable from the viewpoint of shortening the etching time.

  In the present invention, since the substrate does not exist in the main light extraction direction, the following advantages can be obtained. For example, a semiconductor light emitting device formed of a material such as a GaN-based material, an InGaN-based material, an AlGaN-based material, an InAlGaN-based material, or an InAlGaBN-type material formed on a C + sapphire substrate by a general MOCVD method. If present, the sapphire substrate surface side of these materials is a nitrogen surface, and the growth direction of these materials is usually a Ga surface. Here, in general, the Ga surface is difficult to perform chemical etching and the like, and it is difficult to roughen the surface to improve the light extraction efficiency, but the nitrogen surface can be chemically etched relatively easily. Thus, roughening or the like is possible. On the other hand, when a substrate exists, chemical etching is almost impossible with a typical substrate such as sapphire. Accordingly, in the present invention, the sapphire substrate or the like is peeled off, and then the exposed nitrogen surface is chemically etched, so that it is possible to easily roughen the surface, and as a result, the light emission efficiency of the light emitting device is easily improved. be able to.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”.

Further, in the present invention, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), plasma assist MBE, PLD (Pulsed).
Laser Deposition), PED (Pulsed Electron Deposition), VPE (Vapor Phase Epitaxy), LPE (Liquid
In addition to the formation of thin film layers, amorphous layers, microcrystals, polycrystals, single crystals, or their laminated structures in crystal growth equipment such as the (Phase Epitaxy) method, carrier treatment by subsequent heat treatment, plasma treatment, etc. It is described as thin film crystal growth including activation treatment.

  FIG. 1 shows an example of an integrated compound semiconductor light emitting device (hereinafter simply referred to as a light emitting device) of the present invention. In order to explain the structure of the light emitting device of FIG. 1 in detail, the structure will be described with reference to FIG. Here, as shown in FIGS. 1 and 2, an example in which one light-emitting device 10 is configured by three light-emitting units 11 is shown. However, the number of integrations is not particularly limited, and one integrated substrate is provided. The number can be set as appropriate. For example, the number may be two or more than 500 may be accumulated. Here, the number is preferably 25 to 200, and it is also preferable that they are two-dimensionally arranged.

  In the present invention, as shown in the drawing, one light emitting unit includes at least a first conductive semiconductor layer including a first conductive cladding layer 24, a second conductive semiconductor layer including a second conductive cladding layer 26, And a compound semiconductor thin film crystal layer having an active layer structure 25 sandwiched between the first and second conductivity type semiconductor layers, a second conductivity type side electrode 27, and a first conductivity type side electrode. As shown in the drawing, the light emitting unit separation groove 12 defines the light emitting unit 11 in the integrated compound semiconductor light emitting device 10, but the buffer layer 22 is provided in common between the light emitting units.

  In this example, the second conductivity type side electrode 27 is disposed on a part of the surface of the second conductivity type cladding layer 26, and the portion where the second conductivity type cladding layer 26 and the second conductivity type side electrode 27 are in contact with each other. Is the second current injection region 35. Further, the second conductivity type cladding layer, a part of the active layer structure, and a part of the first conductivity type cladding layer are removed, and the first conductivity type cladding layer 24 exposed at the removed portion is in contact. By arranging the first conductivity type side electrode 28, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the substrate.

In the present invention, the light emitting units 11 are electrically separated from each other by the light emitting unit separating grooves 12. That is, the light emitting unit separation groove 12 divides a highly conductive layer in the thin film crystal layer and is removed at least up to the buffer layer 22, preferably halfway through the buffer layer as shown in FIG. In addition, there is no substantial electrical coupling between the light emitting units.
As will be described in detail later, at least a portion of the buffer layer that is in direct contact with the first conductive semiconductor layer (the first conductive clad layer 24 in the figure) is substantially insulative. In the present invention, there is one light emitting point (independent light emitting unit) in one light emitting unit.

  In the present invention, the width of the light emitting unit separation groove is preferably 2 to 300 μm, more preferably 5 to 50 μm, and most preferably 8 to 15 μm. In the present invention, especially in combination with the manufacturing method described later, the width of the separation groove between the light emitting units can be shortened, and integration suitable for a surface light source becomes possible.

  FIG. 2 also shows a part of another light-emitting device adjacent to the central light-emitting device 10. In the manufacturing process, the respective light emitting devices 10 are separated and formed on the same substrate 21 by the inter-device separation grooves 13 as described above. The completed light emitting device shown in FIG. 1 is obtained by replacing one light emitting device 10 in FIG. 2 on a metal surface 41 on a support 40 with a second conductivity type side electrode 27 and a first conductivity type via a metal solder 42. This corresponds to a structure in which the side electrodes 28 are connected to each other. An example of the manufacturing method will be described later.

  In the example of FIG. 2, the inter-device separation groove 13 is formed by removing the thin film crystal layer until it reaches the substrate, and is a preferred form. On the other hand, a mode in which the inter-device separation groove is formed partway through the buffer layer is also preferable. In any of these cases, the insulating layer can be easily formed on the side wall of the highly conductive layer on the active layer structure side of the buffer layer.

  In the light emitting device of the present invention, the insulating layer 30 covers most of the exposed portions including the surfaces and side walls of the thin film crystal layers 22 to 26. However, the side wall portion of the light emitting device of FIG. The shape of the insulating layer in the inter-device separation groove 13 in the state of FIG. 2 that is not separated can take several forms. In any form, it is preferable that the insulating layer does not contact the substrate, and before the light emitting device is separated, a portion where the insulating layer does not exist is present in the inter-device separation groove 13 that partitions the light emitting device. Then, it is preferable that the light emitting devices are separated from a portion where the insulating film is not present. As a result, in the preferable shape of the light emitting device of the present invention, the insulating layer covering the side wall does not reach the light extraction surface side interface of the buffer layer. Specific examples of preferred forms of the insulating layer are shown below.

  In one embodiment of the present invention, as shown in FIG. 2, the insulating layer 30 does not cover the entire surface of the inter-device separation groove 13, but the insulating layer 30 is formed on the substrate surface (ie, the groove bottom surface). There is an insulating layer non-forming portion 15 that is not formed in the groove sidewall portion adjacent to the substrate. In this structure, since there is no insulating layer 30 adhering to the substrate 21, when the substrate 21 is removed by, for example, peeling, there is no possibility that the insulating layer is peeled off. In the obtained light emitting device, as shown in part B of FIG. 1, there is an insulating layer non-forming part 15 where the insulating layer 30 does not reach the substrate surface. As a result of ensuring that the insulating layer is not peeled off in the device having this shape, the function of the light-emitting device is not impaired even if the solder wraps around and the device becomes highly reliable.

  In FIG. 1, a part of the wall surface of the buffer layer 22 is exposed, but the exposed part is preferably an undoped layer that is not doped. If the exposed material is a highly insulating material, the device is highly reliable.

  Further, when the inter-device separation groove is formed partway through the buffer layer, a light emitting device having the following shape can be obtained. For example, as shown in FIGS. 13 and 14, the buffer layer 22 exists up to the end of the light emitting device, and the buffer layer has a level difference based on the bottom surface of the inter-device separation groove. And a side wall portion (side wall of the inter-device separation groove) that enters inside from the light emitting device end. In the example of FIG. 13, the insulating layer 30 covers the separation groove bottom surface portion and the side wall portion of the separation groove from the position of the groove bottom surface away from the end of the buffer layer 22 as indicated by C portion in FIG. 13. is doing. In FIG. 2, the device separation groove is stopped in the middle of the buffer layer 22 in FIG. 2, a part of the insulating layer deposited on the groove bottom surface of the buffer layer is removed to form a scribe region, and the device is separated from the scribe region. Corresponds to the shape. Further, the example of FIG. 14 corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIGS. 1 and 2, and enters the inside from the end of the light-emitting device as shown in the D part of FIG. In the side wall portion (side wall of the inter-device separation groove), there is a portion not covered with the insulating layer on the main light extraction direction side.

  Further, the depth of the inter-device separation groove can be set at an arbitrary position in the middle of the buffer layer. FIGS. 15 and 16 show examples in which the depth of the inter-device separation groove is changed in FIGS. The shapes of the E part in FIG. 15 and the F part in FIG. 16 are the same as the C part in FIG. 13 and the D part in FIG. 14, respectively.

  As in these examples, even when the inter-device separation groove is formed partway through the buffer layer, the device in which the insulating layer covering the side wall does not reach the end of the light emitting device is insulated. By ensuring that the layer is not peeled off and the exposed layer is made of a highly insulating material, the device is as reliable as the light emitting device of the embodiment shown in FIG.

  Furthermore, in the light emitting device of the present invention, the insulating layer 30 is in contact with a part of the first conductivity type side electrode 28 on the main light extraction direction side as shown in FIG. 1, that is, the first conductivity type side electrode 28. There is a portion where an insulating layer is interposed around the contact portion between the first conductive type semiconductor layer and the first conductive type semiconductor layer (first conductive type clad layer 24 in the figure), and the main light extraction direction of the second conductive type side electrode 27 That is, there is no insulating layer between the second conductivity type side electrode 27 and the second conductivity type semiconductor layer (second conductivity type clad layer 26 in the figure). It is preferable that there is a covering portion around the second conductivity type side electrode 27. This form means that the insulating layer 30 is formed after the second conductivity type side electrode 27 is formed, and the first conductivity type side electrode 28 is formed after the insulating layer 30 is formed. Although a manufacturing method based on such an order will be described later, since the second conductive type semiconductor layer such as the second conductive type cladding layer 26 is less damaged and the first conductive type side electrode is less damaged, it is highly efficient. A light emitting device is obtained. That is, the light emitting device having such a structure means high efficiency.

  Further, the size of the second conductivity type side electrode 27 is the same as that of the second current injection region 35, but the exposed surface 37 (second conductivity type side electrode exposed portion) of the second conductivity type side electrode is The size is preferably smaller than the size of the current injection region 35. Furthermore, an opening is provided in part of the insulating layer 30 covering the surface of the first conductivity type cladding layer 24 so that the first conductivity type side electrode 28 contacts the first conductivity type cladding layer 24. One current injection region 36 is formed. The area of the first conductivity type side electrode 28 is preferably larger than that of the first current injection region.

  It is also desirable that the second conductivity type side electrode and the first conductivity type side electrode do not overlap in space.

  Below, each member and structure which comprise an apparatus are demonstrated in detail.

<Board>
In the present invention, a substrate on which a semiconductor layer can be grown is selected and a substrate that can be finally removed is used. The substrate need not be transparent, but when the substrate is peeled off by laser debonding, which will be described later, in the manufacturing process, it is preferable to transmit laser light having a specific wavelength. Further, it is preferably an electrically insulating substrate. This is because, in the manufacturing process, when the substrate is similarly peeled by the laser debonding method, it is difficult to adopt such a substrate peeling method due to absorption by free electrons or the like in the conductive substrate. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, if the doping concentration of Si is used an undoped substrate, 3 × ¹⁰ 17 ^cm Si concentration less desirable ^-3, and more preferably is 1 × ¹⁰ 17 ^{cm -3} or less It is desirable from the viewpoint of electrical resistance and crystallinity. On the other hand, ZnO that can be easily removed with hydrochloric acid or the like is desirable when chemical etching is premised when the substrate is removed.

  The substrate used in the present invention is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. it can. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture an integrated compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer described later, so that a threading transition that occurs at the interface between the thin film crystal layer and the substrate can be activated in the light emitting element or the light emitting unit described later. It is also possible not to introduce it in the vicinity of the layer.

  In one embodiment of the present invention, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication so that the crystal growth of the semiconductor light emitting device and the mechanical strength in the element fabrication process are ensured. It is normal to keep it. After the necessary semiconductor layer is grown using the substrate, the substrate is removed by, for example, polishing, etching, laser debonding, or the like.

<Buffer layer>
The buffer layer 22 mainly grows a thin film crystal on the substrate, suppresses transition, alleviates the imperfection of the substrate crystal, and reduces various mismatches between the substrate crystal and the desired thin film crystal growth layer. Formed for the purpose of thin film crystal growth. Furthermore, a thickness that can stop the separation groove between the light emitting units halfway through the buffer layer and an insulating property that enables electrical separation between the light emitting units are required.

  The buffer layer is formed by thin film crystal growth. InAlGaN-based material, InAlBGaN-based material, InGaN-based material, AlGaN-based material, GaN-based material, etc., which is a desirable form in the present invention, are grown on a different substrate on a substrate. In this case, the buffer layer is particularly important because the lattice constant matching with the substrate is not necessarily ensured. For example, when a thin film crystal growth layer is grown by metal organic vapor phase epitaxy (MOVPE method), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or a low temperature growth GaN layer formed near 500 ° C. Can also be used. Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer 22 is not necessarily a single layer, and a GaN layer grown at a temperature of about 1000 ° C. without doping is further formed on the GaN buffer layer grown at a low temperature in order to improve the crystallinity. You may make it have about several micrometers. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. In the present invention, since the buffer layer exists in common between the light emitting units in the compound semiconductor light emitting device, it is desirable not to have a doped layer. However, when the buffer layer has a layer doped from the viewpoint of crystallinity, an undoped layer is formed after the doping layer is grown, and electrical insulation between the light emitting units is completely ensured. It is essential to be able to do so. It is also possible to stack a doped layer and an undoped layer in the buffer layer.

  In a particularly preferred embodiment, a two-layer structure comprising a low-temperature buffer layer in which a thin film crystal is grown at a low temperature of about 350 ° C. to less than 650 ° C. and a high-temperature buffer layer in which a thin film crystal is grown at a high temperature of about 650 ° C. to 1050 ° C. belongs to.

  Further, the total thickness of the buffer layer is preferably 4 to 20 μm, more preferably 4.5 to 10 μm, and most preferably 5 to 8 μm, and the thick film buffer layer is the main light emitting unit formed thereon. It is preferable because the quality of the thin film crystal layer to be a layer is improved.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to the present invention. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  In the present invention, since the buffer layer exists in common to each light emitting unit, it is essential to select a material so as not to hinder electrical insulation between the light emitting units. If, for example, all the light emitting units in the light emitting device are electrically coupled, when one of the light emitting units (a pair of pn junctions) deteriorates, the effect is not limited to a decrease in luminous intensity of the deteriorated light emitting units. Instead, it appears as a change in the current injection path throughout the integrated compound semiconductor light emitting device. For this reason, the deterioration of one light-emitting unit appears greatly as a characteristic variation of the light-emitting device. In the present invention, it is extremely preferable to select a material for the buffer layer so as to ensure electrical insulation between the light emitting units. Even if the light emitting unit being driven is deteriorated by being electrically insulated, the deterioration is only one problem of the light emitting unit.

Here, the buffer layer only needs to be substantially insulative to such an extent that a change such as deterioration in one light emitting unit does not affect other units. For example, the specific resistance ρ _oc (Ω · Cm) is preferably 0.5 (Ω · cm) or more. More preferably, it is 1.0 (Ω · cm) or more, more preferably 1.5 (Ω · cm) or more, and most preferably 5 (Ω · cm) or more. The buffer layer is preferably undoped in order to have a high specific resistance. However, in the case where the buffer layer is composed of a plurality of layers, even if there is a partially doped layer, this is between the undoped layers. There is no problem as long as the light emitting units are not electrically coupled. In this case, the layer adjacent to the first conductivity type semiconductor layer (for example, the first conductivity type clad layer) may have the above specific resistance.

Furthermore, since the buffer layer removes the substrate during the manufacturing process, the surface of the buffer layer becomes the main light extraction surface in one embodiment of the present invention. As will be described later, as one method of peeling the substrate, a part of the buffer layer is optically decomposed and peeled off using light that is transparent to the substrate and absorbs the buffer layer. A method is mentioned. When such a method is adopted, a material suitable for the method is selected. For example, when the substrate is sapphire and the buffer layer is GaN, an excimer laser having an oscillation wavelength of 248 nm is irradiated from the substrate side on which no thin film crystal is grown, and the buffer layer GaN is made of metal Ga and nitrogen. It is also possible to carry out laser debonding in which the substrate is peeled off as a result.
In the present invention, since there is no substrate in the main light extraction direction, it is desirable that a so-called low reflection coating layer or low reflection optical film is formed on the surface of the buffer layer in the main light extraction direction. Reflection due to a difference in refractive index at the buffer layer-air interface can be suppressed, and higher output and higher element efficiency can be achieved. Here, the reflectance at which the light of the emission wavelength of the light emitting device that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer, which will be described later, is reflected by the buffer layer is R3, and is perpendicular to the space on the light extraction side from the buffer layer When the reflectance at which the light having the emission wavelength of the incident light emitting device is reflected at the interface with the space is represented by R4,
R4 <R3
It is desirable to have a low reflection optical film on the light extraction side of the buffer layer so as to satisfy the above. For example, when the buffer layer is GaN, it is desirable to use Al ₂ O ₃ or the like as the low reflection coating film. This is because it is desirable that the refractive index of the low-reflection coating film is close to √n _bf with respect to the refractive index n _bf of the buffer layer at the light emission wavelength of the device, so that Al ₂ O with respect to the square root of the refractive index of GaN. _{This is because} the refractive index of ₃ is close.

In the present invention, it is also preferable that the main surface of the buffer layer in the light extraction direction is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Here, when the light emission wavelength of the device is λ (nm), the roughness of the buffer layer is such that the average roughness Ra (nm) is λ / 5 (nm) <Ra (nm) <10 × λ (nm).
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

  The buffer layer may be an exposed portion of the inter-device separation groove. The exposed portion is particularly preferably an undoped portion, and insulation failure due to solder or the like during device assembly can be suppressed.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In a typical embodiment of the present invention, as shown in FIG. 1, there is a first conductivity type cladding layer 24 in contact with the buffer layer 22 and divided between the light emitting units. The first conductivity type clad layer 24 functions together with the second conductivity type clad layer 26 described later to the active layer structure 25 described later to efficiently inject carriers and suppress overflow from the active layer structure. In addition, it has a function for realizing light emission in the quantum well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The first conductivity type semiconductor layer includes a layer doped to the first conductivity type, in addition to the above-mentioned layer having a cladding function, for improving the function of the device like a contact layer or for manufacturing reasons. . In a broad sense, the entire first conductivity type semiconductor layer may be considered as the first conductivity type cladding layer, and in this case, the contact layer and the like can also be regarded as a part of the first conductivity type cladding layer.

  Generally, the first conductivity type cladding layer is made of a material having a refractive index smaller than an average refractive index of an active layer structure described later and a material larger than an average band gap of an active layer structure described later. It is preferable. Furthermore, the first conductivity type cladding layer is generally made of a material that forms a so-called type I band lineup in relation to the barrier layer in the active layer structure. Under such guidelines, the first conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure, and the like prepared for realizing a desired emission wavelength.

  For example, when C + plane sapphire is used as the substrate and a laminated structure of GaN grown at a low temperature and undoped GaN grown at a high temperature is used as the buffer layer, a GaN-based material, an AlGaN-based material as the first conductivity type cladding layer, An AlGaInN-based material, an InAlBGaN-based material, or a multilayer structure thereof can be used.

The carrier concentration of the first conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 5 × 10 ¹⁷ cm ⁻³ or more, and most preferably 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and most preferably 7 × 10 ¹⁸ cm ⁻³ or less. Here, when the first conductivity type is n-type, Si is most desirable as a dopant.

  In the example of FIG. 1, the structure of the first conductivity type cladding layer shows a first conductivity type cladding layer composed of a single layer, but the first conductivity type cladding layer is composed of two or more layers. Also good. In this case, for example, a GaN-based material and an AlGaN-based material, an InAlGaN-based material, or an InAlBGaN-based material can be used. Further, the entire first conductivity type cladding layer may be a superlattice structure as a laminated structure of different materials. Furthermore, it is also possible to change the above-mentioned carrier concentration in the first conductivity type cladding layer.

  In the portion of the first conductivity type clad layer that is in contact with the first conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  A part of the first conductivity type cladding layer is etched, and the exposed side wall, the etched part, etc. of the first conductivity type cladding layer are in contact with the first conductivity type side electrode described later. A structure in which all except one current injection region is covered with an insulating layer is desirable.

  In addition to the first conductivity type cladding layer, a different layer may exist as necessary as the first conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

<Active layer structure>
An active layer structure 25 is formed on the first conductivity type cladding layer 24. The active layer structure is a layer that emits light by recombination of electrons and holes (or holes and electrons) injected from the above-described first conductivity type cladding layer and the second conductivity type cladding layer described later. A structure including a quantum well layer and including a barrier layer disposed adjacent to the quantum well layer or disposed between the quantum well layer and the cladding layer. Here, in order to realize high output and high efficiency, which are one object of the present invention, when the number of quantum well layers in the active layer structure is W and the number of barrier layers is B, B = W + 1 is preferably satisfied. That is, the relationship between the cladding layer and the entire layer of the active layer structure is formed as “first conductivity type cladding layer, active layer structure, second conductivity type cladding layer”, and the active layer structure is defined as “barrier layer, quantum well. It is desirable for high output to be formed as “layer, barrier layer” or “barrier layer, quantum well layer, barrier layer, quantum well layer, barrier layer”. FIG. 3 schematically shows a structure in which five quantum well layers and six barrier layers are stacked.

  Here, in the quantum well layer, the layer thickness is as thin as the de Broglie wavelength in order to express the quantum size effect and increase the luminous efficiency. For this reason, in order to achieve high output, it is desirable to provide not only a single quantum well layer but also a plurality of quantum well layers and separate them into an active layer structure. At this time, a layer that is separated while controlling the coupling between the quantum well layers is a barrier layer. In addition, it is desirable that the barrier layer exists for separation of the cladding layer and the quantum well layer. For example, when the cladding layer is made of AlGaN and the quantum well layer is made of InGaN, a form in which a barrier layer made of GaN exists between them is desirable. This is also desirable from the viewpoint of thin film crystal growth because it can be easily changed when the optimum temperature for crystal growth is different. When the clad layer is made of InAlGaN having the widest band gap and the quantum well layer is made of InAlGaN having the narrowest band gap, InAlGaN having an intermediate band gap can be used for the barrier layer. Furthermore, in general, the difference in the band gap between the cladding layer and the quantum well layer is larger than the difference in the band gap between the barrier layer and the quantum well layer, and considering the efficiency of carrier injection into the quantum well layer, The quantum well layer is preferably not directly adjacent to the cladding layer.

  It is desirable that the quantum well layer is not intentionally doped. On the other hand, it is desirable to dope the barrier layer to reduce the resistance of the entire system. In particular, the barrier layer is preferably doped with an n-type dopant, particularly Si. This is because Mg, which is a p-type dopant, easily diffuses in the device, and it is important to suppress the diffusion of Mg during high output operation. Therefore, Si is effective, and it is desirable that the barrier layer is doped with Si. However, it is preferable not to perform doping at the interface between the quantum well layer and the barrier layer.

  It is preferable that the active layer structure side wall of one element is covered with an insulating layer 30 as shown in FIG. In this case, when flip-bonding the element manufactured according to the present invention, there is an advantage that a short circuit due to solder or the like on the side wall of the active layer structure does not occur.

  In the present invention, it is desirable that the light emitted from the quantum well layers in each light emitting unit has substantially the same emission spectrum. This is for realizing uniform light emission as a surface light source as a compound semiconductor light emitting device.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductivity type cladding layer 26 efficiently injects carriers into the aforementioned active layer structure 25 together with the aforementioned first conductivity type cladding layer 24 and suppresses overflow from the active layer structure. It has a function for realizing light emission in the well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The second conductivity type semiconductor layer includes a layer doped to the second conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire second conductivity type semiconductor layer may be considered as the second conductivity type cladding layer. In that case, the contact layer or the like can also be regarded as a part of the second conductivity type cladding layer.

  In general, the second conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the above-mentioned active layer structure and a material larger than the average band gap of the above-mentioned active layer structure. . Furthermore, the second conductivity type clad layer is generally made of a material that forms a so-called type I band lineup, particularly in relation to the barrier layer in the active layer structure. Under such guidelines, the second conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure and the like prepared for realizing a desired emission wavelength. For example, when C + plane sapphire is used as the substrate and GaN is used as the buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material, an AlGaBInN-based material, or the like can be used as the second conductivity type cladding layer. . Further, a laminated structure of the above materials may be used. Also, the first conductivity type cladding layer and the second conductivity type cladding layer can be made of the same material.

The carrier concentration of the second conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 4 × 10 ¹⁷ cm ⁻³ or more, and further preferably 5 × 10 ¹⁷ cm ⁻³ or more. × 10 ¹⁷ cm ⁻³ or more is most preferable. Preferably 7 × ¹⁰ 18 ^{cm -3} or less as an upper limit, more preferably 3 × ¹⁰ 18 ^{cm -3} or less, and most preferably 2 × ¹⁰ 18 ^{cm -3} or less. Here, Mg is most desirable as the dopant when the second conductivity type is p-type.

  The structure of the second conductivity type cladding layer is an example of a single layer formed in the example of FIG. 1, but the second conductivity type cladding layer may be composed of two or more layers. Good. In this case, for example, a GaN-based material and an AlGaN-based material can be used. The entire second conductivity type cladding layer may be a superlattice structure composed of a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the second conductivity type cladding layer.

  In general, in a GaN-based material, when the n-type dopant is Si and the p-type dopant is Mg, the crystallinity of p-type GaN, p-type AlGaN, and p-type AlInGaN is n-type GaN, n It does not reach each of type AlGaN and n-type AlInGaN. Therefore, in device fabrication, it is desirable to implement a p-type cladding layer with poor crystallinity after crystal growth of the active layer structure. From this viewpoint, the first conductivity type is n-type and the second conductivity type is p-type. Is desirable.

  In addition, it is desirable that the thickness of the p-type cladding layer with poor crystallinity (which corresponds to the second conductivity type cladding layer in the case of taking a desirable form) is somewhat thin. In the present invention in which flip chip bonding is performed, the substrate side is the main light extraction direction, so there is no need to consider light extraction from the second-conductivity-type-side electrode side, which will be described later. It is possible to form a membrane electrode. For this reason, it is not necessary to expect current diffusion in the lateral direction in the second conductivity type cladding layer as in face-up mounting, and it is necessary to make the second conductivity type cladding layer thin to some extent from the element structure. Is also advantageous. However, when it is extremely thin, the carrier injection efficiency is lowered, and therefore there is an optimum value. The thickness of the second conductivity type cladding layer can be selected as appropriate, but is preferably 0.05 μm to 0.3 μm, and most preferably 0.1 μm to 0.2 μm.

  In the portion of the second conductivity type clad layer that is in contact with the second conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  It is desirable that the exposed side wall of the second conductivity type cladding layer be entirely covered with an insulating layer except for a second current injection region that realizes contact with the second conductivity type side electrode described later.

  Furthermore, in addition to the second conductivity type cladding layer, a different layer may exist as necessary as the second conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in a portion in contact with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

  In addition, unless it is contrary to the summary of this invention, you may form the layer which does not enter into the above-mentioned category as needed as a thin film crystal layer.

<Second conductivity type side electrode>
The second conductivity type side electrode realizes a good ohmic contact with the second conductivity type nitride compound semiconductor, and becomes a reflection mirror in a good emission wavelength band when flip-chip mounted, When flip chip mounting is performed, good adhesion to a support or the like using a solder material or the like is realized. For this purpose, the material can be selected as appropriate, and the second conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  Further, when the second conductivity type is p-type and the second conductivity-type side electrode side of the second conductivity-type cladding layer is GaN, the constituent elements of the second conductivity-type side electrode are Ni, Pt, Pd, Mo, It is desirable to include any of Au. In particular, the first layer on the p-side cladding layer side of the second conductivity type side electrode is preferably Ni, and the surface of the second conductivity type side electrode opposite to the p-side cladding layer side is Au. desirable. This is because Ni has a large work function absolute value, which is convenient for p-type materials, and Au is preferable as the outermost surface material in consideration of resistance to process damage described later, mounting convenience, and the like.

  The second conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the second conductivity type carrier can be injected. For example, when the second conductivity type side contact layer is provided, the second conductivity type side electrode is in contact with it. Formed.

<First conductivity type side electrode>
The first-conductivity-type-side electrode achieves good ohmic contact with the first-conductivity-type nitride compound semiconductor, and when flip-chip mounted, it becomes a reflection mirror in a good emission wavelength band, When chip mounting is performed, good adhesion to a support with a solder material or the like is realized. For this purpose, a material can be selected as appropriate. The first conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  If the first conductivity type is n-type, the n-side electrode desirably includes a material selected from Ti, Al, and Mo, or all of them as constituent elements. This is because the absolute value of the work function of these metals is small. In addition, Al is usually exposed in the direction facing the main light extraction direction of the n-side electrode.

  In the present invention, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. It is desirable not to. This is because when the light emitting device is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while ensuring a sufficient area to ensure sufficient adhesion to the support or the like. It is important to secure a sufficient interval to prevent an unintended short circuit due to a solder material or the like.

  Here, the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is preferably 15 μm or more. This is because a margin is required in the process of forming the first conductivity type side electrode, which is preferably formed by a photolithography process and a lift-off method.

  The first conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the first conductivity type carrier can be injected. For example, when the first conductivity type side contact layer is provided, the first conductivity type side electrode is in contact with it. Formed.

<Insulating layer>
When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” and “anywhere between different light emitting units”. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation. For example, single layer oxides, nitrides, fluorides and the like are preferable. Specifically, SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF It is preferably selected from _{x 1} , CaF _x , SrF _x , MgF _{x and the} like. These can secure insulating properties stably over a long period of time.

On the other hand, the insulating layer 30 can be a multilayer film of an insulator. Since this is a dielectric multilayer film, by appropriately adjusting the refractive index of the dielectric in the insulating layer, so-called high reflection having a relatively high optical reflectivity with respect to the light generated in the light emitting device. The function of the coating can also be expressed. For example, when the center value of the light emission wavelength of the element is λ, SiO _x and TiO _x are laminated to have an optical thickness of λ / 4n (where n is the refractive index of each material at the wavelength λ). Thus, it is possible to realize high reflection characteristics. In this way, when the chip is flip-chip bonded, it is possible to increase the light extraction efficiency in the main extraction direction, and an unintentional short circuit caused by soldering materials, etc. It is very desirable to prevent both of them.

Specifically, the reflectance at which the light having the emission wavelength of the light emitting device perpendicularly incident on the buffer layer from the first conductivity type semiconductor layer side including the first conductivity type cladding layer is reflected by the buffer layer is represented by R2, and is insulated. The reflectance of the light emission wavelength of the light emitting device that is perpendicularly incident from the side of the second conductivity type semiconductor layer including the second conductivity type cladding layer in the layer is reflected by the insulating layer as R12, and the first conductivity type cladding as the insulating layer The light having the emission wavelength of the light emitting device that is perpendicularly incident from the side of the first conductive semiconductor layer including the layer is reflected by the insulating layer as R11, and is perpendicularly incident from the active layer structure side including the quantum well layer in the insulating layer. When the reflectance at which the light emission wavelength of the light emitting device is reflected by the insulating layer is represented by R1q,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
It is preferable that the insulating layer is configured so as to satisfy at least one of the conditions, in particular, all of the expressions 1 to 3.

These are desirable ranges for an insulating layer formed of a dielectric multilayer film to function efficiently as an optical reflecting mirror. Further, considering the stability of the material and the range of refractive index, it is desirable that the dielectric film contains fluoride, and specifically, AlF _x , BaF _x , CaF _x , SrF _x , MgF It is desirable that any of _x is included.

<Support>
Although it is essential that the support 40 can serve as a support for the thin film crystal layer when the substrate is peeled off, the support 40 can also have functions of current introduction and heat dissipation after device completion. Highly desirable. In this respect, the base material of the support is preferably selected from the group consisting of metal, AlN, SiC, diamond, BN, and CuW. These materials are preferable in that they are excellent in heat dissipation and can efficiently suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as a support. In addition, when a portion of the thin film crystal layer is decomposed into metal Ga and nitrogen by laser irradiation when removing the substrate, which will be described later, it is desirable to perform wet etching when removing the metal Ga. The body is preferably made of a material that is not etched. Furthermore, it is possible to wet-etch the substrate itself, and it is desirable that the support is made of a material that is not etched. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. In addition, SiN _x , SiO ₂ or the like formed by various CVD methods is desirable for covering with a dielectric or the like.

  From the viewpoint that the support further has functions of current introduction and heat dissipation after completion of the element, it is desirable that the support has electrode wiring for current introduction on the base material, and the device is mounted on this electrode wiring. It is desirable that the mounting portion has an adhesive layer for joining the light emitting device and the support as appropriate. Here, although it is possible to use a paste containing Ag, a metal bump, or the like as the adhesive layer, it is very desirable from the viewpoint of heat dissipation that it is made of metal solder. The metal solder can realize a flip chip mount that is overwhelmingly excellent in heat dissipation compared with a paste material containing Ag, a metal bump, and the like. Here, examples of the metal solder include In, InAg, InSn, SnAg, PbSn, AuSn, AuGe, and AuSi. In particular, a high melting point solder such as AuSn, AuSi, or AuGe is more desirable. This is because when a large current is injected to operate the light emitting element at an ultrahigh output, the temperature in the vicinity of the element rises to about 200 ° C. The melting point of the solder material is higher than the element temperature during driving. The metal solder which has is more preferable. In some cases, it is also desirable to use bumps in order to cancel out the level difference of the elements at the time of flip chip mounting, and further to join the metal solder material while filling the periphery thereof.

  Further, the integrated compound semiconductor light emitting device of the present invention can freely change the metal wiring on the support so that each light emitting unit in one light emitting device can be connected in parallel, in series, or It is also possible to mix them.

〔Production method〕
Next, a method for manufacturing the integrated compound semiconductor light emitting device of the present invention will be described.

  In one example of the manufacturing method of the present invention, as shown in FIG. 4, first, a substrate 21 is prepared, and a buffer layer 22, a first conductivity type cladding layer 24, an active layer structure 25, and a second conductivity type cladding layer are formed on the surface thereof. 26 are sequentially formed by thin film crystal growth. The MOCVD method is desirably used for forming these thin film crystal layers. However, the MBE method, the PLD method, and the like can also be used for forming all thin film crystal layers or some thin film crystal layers. These layer configurations can be appropriately changed according to the purpose of the element. In addition, various processes may be performed after the formation of the thin film crystal layer. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  In order to realize the shape shown in FIGS. 1 and 2 in the present invention after the thin film crystal layer growth, it is preferable to form the second conductivity type side electrode 27 as shown in FIG. That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. When the p-type electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface when the second conductivity type is p-type as a desirable form, this is compared with GaN-based materials. This is because the hole concentration in the p-GaN clad layer with a low effective activation rate is lowered by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. For this reason, in the present invention, after the thin film crystal growth, the formation of the second conductivity type side electrode is another process step (for example, a first etching step, a second etching step, a third etching step, or an insulating layer forming step, which will be described later) It is desirable that the second conductivity type side electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, etc.) be performed prior to this.

  In the present invention, when the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. Is a relatively stable metal such as Au, it is unlikely to be damaged by the process even after the subsequent process. Also from this viewpoint, in the present invention, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  In the present invention, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced similarly. it can.

  Various film formation techniques such as sputtering and vacuum deposition can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique, a metal mask, etc. Site-selective vapor deposition using can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 5, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask, which will be described in detail in a second etching process and a third etching process described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

  Next, as shown in FIG. 6, the separation grooves 12 between the light emitting units are formed by the second etching process. In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. Generally, the total sum of the layers etched by the first etching step is usually about 0.5 μm. However, in the second etching step, all of the first conductivity type cladding layer 24 and a part of the buffer layer 22 are reached. Is often 1 μm or more, for example, in the range of 1 to 5 μm, or in the range of 3 μm or more, for example, 3 to 7 μm. In some cases, it may be in the range of 3 to 10 μm, and more than 10 μm. However, there is an advantage that the etching depth can be shortened as compared with the case of etching until reaching the substrate. Therefore, the width of the light emitting unit separation groove 12 can be made short as described above.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that needs to etch the system material, a relatively thick SiNx film is required. For example, when etching a 4 μm GaN-based material in the second dry etching step, a SiN _x mask exceeding 0.8 μm is required. But when it comes to SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the light emitting unit separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first, second, and third etching steps, while being easy to etch for patterning (preferably wet etching). What is required is one that can be etched and that has a good patterning shape, in particular, good linearity of the side wall portion. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in control of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, as will be described later, when a mask such as SrF ₂ is exposed to plasma of chlorine or the like during dry etching of the semiconductor layer, the etching rate at the subsequent removal of the mask layer is reduced before exposure to plasma of chlorine or the like. It has a tendency to decrease in comparison. For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _17, SiN x, SiO ₂ or the like mask 51, a metal fluoride Even if it does not exist in the entire lower portion of the chemical mask layer 52, it is sufficient if it is formed on a material that is at least susceptible to acid.

  By such a second etching step, as shown in FIG. 6, a separation groove between light emitting units is formed.

  Next, as shown in FIG. 7, an inter-device separation groove 13 is formed by a third etching process. In the third etching step, the thickness of the GaN-based material to be etched needs to etch all of the buffer layer, so that it may be extremely deep, 5 to 10 μm, compared with the second etching step. Also, it may exceed 10 μm. Therefore, as described in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The preferable conditions and the like (including the laminated mask) are as described for the second etching step.

  The inter-device separation groove needs to be formed by dividing at least the first conductivity type cladding layer. In one preferred embodiment of the present invention, the inter-device separation groove 13 is formed so as to reach the substrate 21 as shown in FIG. In this case, the apparatus can be easily separated. Alternatively, the inter-device separation groove may be formed by etching part of the substrate.

  On the other hand, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. For example, if the inter-device isolation groove is formed up to the middle of the buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, and insulation against wraparound of solder or the like can be maintained. (See FIGS. 13 to 16 for the form after the light emitting device is completed). In this case, the layer exposed from the side wall without being covered with the insulating layer preferably has high insulating properties. In the embodiment in which the inter-device separation groove is formed up to the middle of the buffer layer, the second etching step and the third etching step can be performed at the same time, so that there is an advantage that the steps can be simplified.

Note that the first etching step, the second etching step, and the third etching step may be performed first or later. In order to simplify the process, it is also preferable that the first etching step is performed first, and the second etching and / or the third etching step is performed without removing the etching mask at that time. As shown in FIG. 17, first, a first etching mask 51 is formed of an acid-resistant material such as SiN _x and SiO ₂ (preferably SiN _x ), and etching is performed so that the first conductivity type cladding layer 24 appears. Without removing 51, a second and / or third etch mask 52 with a metal fluoride layer is formed. And after implementing a 2nd and / or 3rd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that. Even when the second etching step and the third etching step are performed separately, the first etching mask 51 may be present until both etchings are completed.

If the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element isolation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the element manufacturing process and further for securing the scribe region.

  After the third etching step, an insulating layer 30 is formed as shown in FIG. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

Next, as shown in FIG. 9, a predetermined portion of the insulating layer 30 is removed, and the second conductivity type side electrode exposed portion 37 from which the insulating layer is removed on the second conductivity type side electrode 27, the first conductivity type cladding. The first current injection region 36 from which the insulating layer has been removed is formed on the layer, and the insulating layer non-formed portion 15 from which the insulating layer has been removed from the substrate surface and the side wall in the inter-device isolation trench 13 is formed. The insulating layer 30 on the second conductivity type side electrode 27 is desirably removed so that the peripheral portion of the second conductivity type side electrode is covered with the insulating layer. That is, the surface area of the exposed portion of the second conductivity type side electrode is preferably smaller than the area of the second current injection region. Here, in order to prevent the occurrence of an unintentional short-circuit due to a margin of a photolithography process, particularly a photolithography process, or a solder material, the width of the width covered with the insulating layer from the periphery of the second conductivity type side electrode Among them, when the width of the narrowest portion is L _2W , L _2W is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material. L _2w is usually 2000 μm or less, preferably 750 μm or less.

For the removal of the insulating layer, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer is a single layer of SiN _x , dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

  The second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed by etching at the same time.

  The simultaneous removal of a part of the insulating layer on the side wall of the groove when the insulating layer non-forming portion 15 is provided can be formed by the following process, for example. When a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation groove 13 is formed by photolithography, and then wet etching is performed using an etchant capable of etching the insulating layer, the inside of the inter-device separation groove is obtained. The removal of the insulating layer on the substrate surface proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer covering the substrate side of the groove sidewall is removed with a wet etchant. As shown in FIG. 9, the insulating layer is formed on the substrate side of the inter-device separation groove. A non-existing shape is obtained. When the insulating layer is removed as described above, the side wall of the thin film crystal layer where the insulating layer is not present is preferably the side wall of the undoped layer. This is because an unintended electrical short circuit does not occur even when solder for joining to the support or the like adheres to the side wall when flip chip mounting is performed. Such a removed shape of the insulating layer is a desirable shape, particularly when the substrate is removed during the manufacturing process of the light emitting device, because unintended problems such as peeling of the insulating layer are not accompanied. Even when the inter-device separation groove is formed up to the middle of the buffer layer, an insulating layer is formed on the main light extraction direction side of the side wall portion (side wall of the inter-device separation groove) that enters from the end of the light emitting device. In the form in which there is an uncovered portion (for example, in the case of manufacturing the structure of FIGS. 14 and 16), when the insulating film is deposited by the above-described process, it is different that it is deposited not on the substrate surface but on the groove bottom surface. However, the same process can be employed. Further, in the form in which the insulating layer covers a part of the bottom surface of the separation groove and the side wall portion of the separation groove (for example, in the case of manufacturing the structure of FIGS. 13 and 15), it is suitable for the planned shape in the above process. An appropriate etching mask shape may be prepared by photolithography, and a part of the insulating layer deposited on the bottom surface of the groove may be removed to form a scribe region without performing side etching.

  Next, as shown in FIG. 10, the first conductivity type side electrode 28 is formed. As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from Ti, Al, and Mo, or all of them. In addition, Al is usually exposed in the direction facing the main light extraction direction of the n-side electrode.

Various film formation techniques such as sputtering and vacuum deposition can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique or a place selection using a metal mask, etc. An appropriate vapor deposition or the like can be used as appropriate. Here, in order to allow a margin in the formation process to some extent, if the width of the narrowest portion among the portions where the first conductivity type side electrode is in contact with the insulating layer is L _1w , L _1w is 7 μm or more. Particularly, 9 μm or more is preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  In this example, the first conductivity type side electrode is formed so as to be in contact with a part of the first conductivity type cladding layer. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact with the first conductivity type side electrode. Can do.

  In the manufacturing method of the present invention, the first conductivity type side electrode is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is preferably formed with Al on the surface of the electrode material. In this case, if the n-side electrode is formed before the formation of the insulating layer like the second conductivity type side electrode, the surface of the n-side electrode, that is, the Al metal, will history the etching process of the insulating layer. . As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching an insulating layer, but Al has low resistance to various etchants including hydrofluoric acid, and such a process is effectively performed. Then, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the present invention, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer is effective in reducing damage to the electrode.

  Thus, after the structure of FIG. 10 (FIG. 2) is formed, preparations for removing the substrate are made. In general, the entire structure of the wafer shown in FIG. 10 or a part thereof is first bonded to the support 40. This is because the thickness of the thin film crystal layer as a whole is at most about 15 μm, and if the substrate is peeled off, the mechanical strength becomes insufficient, and it becomes difficult to stand alone and undergo subsequent processes. It is. The material of the support is as described above, and is mounted on the metal surface 41 (electrode wiring or the like) on the support with, for example, metal solder 42.

  At this time, in the light emitting device of the present invention, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged so as not to spatially overlap each other, and the first conductivity type side electrode is the first conductivity type side electrode. Since it is larger than one current injection region and has a sufficient area, it is desirable to prevent both unintentional short-circuiting and ensure high heat dissipation. Further, the sidewalls of other thin film crystal layers are also protected by the insulating layer except for a part of the buffer layer, particularly the undoped portion. There is no short circuit.

  Next, after bonding the element to the support, the substrate is peeled off. Any method such as polishing, etching, or laser debonding can be used for peeling the substrate. When polishing a sapphire substrate, it is possible to remove the substrate using an abrasive such as diamond. It is also possible to remove the substrate by dry etching. Furthermore, for example, when a sapphire is a substrate and a thin film crystal growth portion is formed of an InAlGaN-based material, the sapphire substrate transmits from the sapphire substrate side, and is absorbed by GaN used for the buffer layer, for example, 248 nm. It is also possible to perform laser debonding using an excimer laser having an oscillation wavelength of 1 to decompose a part of GaN in the buffer layer into metal Ga and nitrogen and peel off the substrate.

When using ZnO, ScAlMgO ₄ or the like as a substrate, the substrate can be removed by wet etching using an etchant such as HCl.

  Here, in the preferred embodiment of the present invention, since there is no portion where the insulating layer is in contact with the substrate, when the substrate is peeled off, the insulating layer is not peeled off secondarily.

  Thereafter, the light emitting device is separated together with the support in the separation region corresponding to the location where the inter-device separation groove is present to obtain a single light emitting device. Here, it is desirable that no metal wiring exists in the separation region of the support. This is because separation between devices is difficult if metal wiring exists here. The integrated compound semiconductor light-emitting device of the present invention can freely change the metal wiring on the support so that each light-emitting unit in one light-emitting device can be connected in parallel or in series. It is also possible to make it.

  For the cutting of the separation region portion of the support, an appropriate process such as dicing, scribing and braking can be selected depending on the base material. In addition, when the inter-device separation groove is formed partway through the buffer layer (for example, when the groove is formed halfway through the buffer layer at the same depth as the light-emitting unit separation groove), the device Separation between the light emitting devices in the thin-film crystal growth layer portion can be easily realized by using the inter-separation grooves to perform damage by diamond scribe, ablation of a part of the buffer layer by laser scribe, and the like. Thereafter, the support can be separated into each light emitting device by dicing. In some cases, separation between the light emitting devices can be performed by dicing the thin film crystal growth layer and the support at the same time.

  In this way, the light emitting device shown in FIG. 1 is completed.

  In the manufacturing method of the present invention, in addition to being able to effectively manufacture a structure advantageous for light emission as a surface light source, as described, formation of a thin film crystal layer, formation of a second conductivity type side electrode, etching process (first etching process) , Second etching step, third etching step), formation of insulating layer, removal of insulating layer (formation of exposed portion of second conductivity type side electrode and first current injection region and removal of insulating layer in the vicinity of inter-device separation groove) The formation of the first conductivity type side electrode is preferably carried out in this order. By this process order, the thin film crystal layer directly under the second conductivity type side electrode is not damaged, and the first conductivity type side electrode is also formed. A light emitting device without damage can be obtained. The device shape reflects the process flow. That is, the light emitting device has a structure in which the second conductivity type side electrode, the insulating layer, and the first conductivity type side electrode are laminated in this order. In other words, the second conductivity type side electrode is in contact with the second conductivity type clad layer (or other second conductivity type thin film crystal layer) without an insulating layer interposed, There is a portion covered with an insulating layer, and an insulating layer is interposed between the first conductivity type side electrode and the first conductivity type cladding layer (or other first conductivity type thin film crystal layer) around the electrode. There is a part.

  The features of the present invention will be described more specifically with reference to the following examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

Example 1
The semiconductor light emitting device shown in FIG. 15 was fabricated by the following procedure. 4 to 10 will be referred to as related process diagrams.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 10 nm is first formed thereon as the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 4 μm was formed at 1040 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 3 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and the first conductivity type (n-type) first cladding layer 24 a is Si-doped (Si concentration 1.5 × A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps so far generally corresponds to FIG. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiNx mask, and a SiNx etching mask was produced. At this time, etching of the unnecessary portion of the SiNx film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step described later, and a mask is left. A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps so far generally corresponds to FIG.

Next, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method in order to perform a second etching process for forming the light emitting unit separating grooves 12 in each light emitting device. Next, the SrF ₂ film in the region for forming the separation groove between the light emitting units was removed, and a mask for forming the separation groove between the light emitting units of the thin film crystal layer, that is, the SrF ₂ mask for the second etching process was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN corresponding to the light emitting unit separation trenches. An active layer structure 25 made of a barrier layer, an n-AlGaN first clad layer 24a, an n-GaN contact layer 24c, an n-GaN second clad layer 24b, and a thin film crystal layer up to a part of the undoped GaN buffer layer 22, ICP etching using _two gases was performed. During this second etching step, the SrF ₂ mask was hardly etched. The width of the separation groove 12 between the light emitting units could be 10 μm as the width of the mask.

After forming the light emitting unit separating groove 12 by the second etching step, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, in order to carry out the third etching step for forming the inter-device separation grooves 13 between the respective compound semiconductor light emitting devices, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region where the inter-device separation groove was to be formed was removed, and an inter-device separation groove forming mask for the thin film crystal layer, ie, a third etching step SrF ₂ mask was formed.

Next, as a third etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier at portions corresponding to the device isolation trenches. All of the active layer structure 25 composed of layers, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, the undoped GaN buffer layer 22 (22a, 22b), and the thin film crystal layer ICP etching using Cl ₂ gas was performed. During the third etching step, the SrF ₂ mask was hardly etched. By this process, an inter-device separation groove having a width of 50 μm was formed.

After forming the inter-device separation groove 13 by the third etching step, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode 27, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIG.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. At this time, SiN _x and SiO _x are formed one layer at a time so that the optical wavelength is 1/4 with respect to the light emission wavelength of the device, and have a relatively high reflectance with respect to the light emission wavelength. I made it. The structure completed through the steps up to here generally corresponds to FIG.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer remaining on a part of the side wall of the substrate, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) on which the resist mask was not formed with a hydrofluoric acid-based etchant was removed. Further, due to the side etching effect using hydrofluoric acid, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer was also removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

  Subsequently, in order to form the n-side electrode 28, a resist pattern was formed by preparing for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti 20 nm / Al 300 nm as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another production example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this example was obtained. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIG.

  Next, as a preparation for carrying out substrate peeling, an Si substrate having a Ni / Pt / Au laminated metal wiring (metal layer 41) formed on the surface was prepared as a support 40. The entire wafer (the thin film crystal growth layer, the electrode, the insulating layer, etc. on the substrate 21) on which the light emitting device was built was bonded to this support using AuSn solder. At the time of bonding, the wafer on which the support 40 and the light emitting device are formed is heated to 300 ° C. so that the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. I made it. At this time, an unintended short circuit or the like of the element did not occur.

  Next, in order to perform substrate peeling, an excimer laser (248 nm) was irradiated from the surface of the substrate 21 on which thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Next, a low-reflection optical film 45 made of alumina was formed by sputtering on the buffer layer side of the ultrathin light-emitting element fused to the support 40 with metal solder 42. At this time, the alumina was formed with a quarter of the emission wavelength as the optical film thickness so that the alumina had a low reflection coating with respect to the emission wavelength of the device.

  Finally, in order to divide each light emitting device one by one, the element isolation region portion in the support was cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the integrated compound semiconductor light emitting device shown in FIG. 11 was completed.

(Example 2)
In Example 1, Example 1 was repeated except that the thin film crystal layer was formed as follows after the buffer layer 22 was formed. That is, in Example 1, after forming 4 μm-thick undoped GaN as the second buffer layer 22b at 1040 ° C., the first conductivity type (n-type) second cladding layer 24b was further doped with Si (Si concentration 5 × A 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm, and a Si-doped (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm as the first conductivity type (n-type) contact layer 24c. Further, a Si-doped (Si concentration 5.0 × 10 ¹⁸ cm ⁻³ ) Al _0.10 Ga _0.90 N layer having a thickness of 0.1 μm is formed as the first conductivity type (n-type) first cladding layer 24a. Formed. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, in the same manner as in Example 1, the light emitting device shown in FIG. 11 was completed. At this time, an unintended short circuit of the element did not occur.

In the processes of Examples 1 and 2, the SiN _x mask was removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask. It is also preferable to remove after the step.

  Furthermore, by stopping the etching in the third etching step in the middle of the buffer layer, the light emitting device shown in FIGS. 14 and 16 can be manufactured (however, the insulating film is a multilayer dielectric film). At this time, if an appropriate etching mask shape is prepared by photolithography suitable for the planned shape and side etching is not performed, the light emitting device shown in FIGS. 13 and 15 is obtained.

(Example 3)
The semiconductor light emitting device shown in FIG. 12 was produced by the following procedure.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 10 nm is first formed thereon as the first buffer layer 22a using the MOCVD method. An undoped GaN layer having a thickness of 3.5 μm was formed at 1040 ° C. as the buffer layer 22b.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 3 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to simultaneously perform the second etching step for forming the light emitting unit separation grooves and the third etching step for forming the device separation grooves, an SrF ₂ mask was formed on the entire surface of the wafer by vacuum evaporation. . Next, the SrF ₂ film in the light emitting unit separation groove forming region and the device separation groove forming region is removed, and the thin film crystal layer separation etching mask, that is, the second etching step and the third etching step are simultaneously performed. An etching mask was formed.

Next, as the second and third etching steps to be performed simultaneously, the p-GaN contact layer 26c, the p-GaN second cladding layer 26b, and the p-AlGaN second layer in the portions corresponding to the light emitting unit separation grooves and the device separation grooves. One cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, an n-AlGaN first cladding layer 24a, an n-GaN contact layer 24c, an n-GaN second cladding layer 24b, an undoped GaN buffer layer 22 The thin film crystal layer up to a part of was subjected to ICP etching using Cl ₂ gas. During the second and third simultaneous etching steps, the SrF ₂ mask was hardly etched. Further, the light emitting unit separation groove 12 was formed with a thickness of 6 μm according to the width of the mask.

The second and third etching steps were performed at the same time, and after forming the light emitting unit separation groove and the device separation groove, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as preparation before forming the first conductivity type side electrode, an etching mask was formed. Here, SrF ₂ was formed on the entire surface of the wafer by vacuum evaporation. Next, a photolithography process was performed again to pattern the SrF ₂ mask, and a first etching mask was produced.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the ICP plasma etching was completed, the entire SrF ₂ mask was removed. Again, since Au was exposed on the surface of the p-side electrode, it was not altered at all by these processes.

Next, SiN _x having a thickness of 125 nm was formed as an insulating layer 30 on the entire surface of the wafer by p-CVD. Next, a p-side electrode exposed portion is formed on the p-side electrode 27 made of Pd—Au, an n-side current injection region is formed on the n-side contact layer, and an insulating layer present in the inter-device isolation trench In order to simultaneously remove a portion of the resist mask, a resist mask is formed using a photolithography technique, and then a portion where the resist mask is not formed using RIE plasma of SF ₆ gas, ie, p-side electrode exposure The formation of the portion, the formation of the n-side current injection region on the n-side contact layer 24c, and the removal of a part of the insulating layer existing in the inter-device isolation trench were performed. Here, the periphery of the p-side electrode was covered with a SiN _x insulating layer. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region. Further, for example, as described in the first and second embodiments, an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape, and the shape of FIG. 12 shows this shape.) Alternatively, an appropriate etching mask shape is prepared by photolithography suitable for the planned shape, and the side etching of the insulating layer is not advanced, so that FIG. Shape is also possible.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, p was not altered at all.

  Subsequently, in order to form the n-side electrode 28, a resist pattern was formed by preparing for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (the thin film crystal growth layer, the electrode, the insulating layer, etc. on the substrate 21) on which the light emitting device was built was bonded to this support using AuSn solder. At the time of bonding, the wafer on which the support 40 and the light emitting device are formed is heated to 300 ° C. so that the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. I made it. At this time, an unintended short circuit or the like of the element did not occur at this time.

  Next, in order to perform substrate peeling, an excimer laser (248 nm) was irradiated from the surface of the substrate 21 on which thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting device one by one, the element isolation region portion in the support was cut together with the buffer layer at the bottom of the inter-device isolation groove using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the integrated compound semiconductor light emitting device shown in FIG. 11 was completed.

It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows the structure before completion of one example of the light-emitting device of this invention. It is a figure which shows an active layer structure typically. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention. 1 is a view showing a light emitting device manufactured in Example 1. FIG. 6 is a view showing a light emitting device manufactured in Example 2. FIG. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is a figure which shows one example of the light-emitting device of this invention. It is process sectional drawing explaining one Embodiment of the manufacturing method of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light-emitting device 11 Light-emitting unit 12 Inter-light-emitting unit separation groove 13 Inter-device separation groove 15 Insulating layer non-formation portion 21 Substrate 22 Buffer layer 22a First buffer layer 22b Second buffer layer 24 First conductivity type cladding layer 24a First Conductive type first cladding layer 24b First conductive type second cladding layer 24c First conductive type (n-type) contact layer 25 Active layer structure 26 Second conductive type cladding layer 26a Second conductive type first cladding layer 26b Second conductive type Type second cladding layer 26c second conductivity type (p-type) contact layer 27 second conductivity type side electrode 28 first conductivity type side electrode 30 insulating layer 35 second current injection region 36 first current injection region 37 second conductivity type Side electrode exposed portion 40 Support 41 Metal surface 42 Metal solder 45 Low reflection optical film 51 First etching mask (SiN _x, etc.)
52 Second and / or third etching mask (metal fluoride mask)

Claims (43)

An integrated compound semiconductor light emitting device having a plurality of light emitting units,
The light emitting unit includes a compound semiconductor thin film crystal layer having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer; Having at least a conductivity type side electrode, and a first conductivity type side electrode,
The main light extraction direction is the first conductivity type semiconductor layer side direction when viewed from the active layer structure, and the first conductivity type side electrode and the second conductivity type side electrode are opposite to the main light extraction direction. Formed on the side,
A buffer layer provided in common between the plurality of light emitting units on the main light extraction direction side from the first conductive type semiconductor layer;
The light emitting units are provided between adjacent light emitting units, and are formed by removing the light emitting unit separation grooves from the surface of the thin film crystal layer to the interface of the buffer layer or a part of the buffer layer. An integrated compound semiconductor light emitting device characterized in that it is electrically isolated by   2. The light emitting device according to claim 1, wherein the buffer layer is a layer formed by thin film crystal growth.   3. The light emitting device according to claim 1, wherein a specific resistance of at least a portion of the buffer layer in direct contact with the first conductivity type semiconductor layer is 0.5 (Ω · cm) or more.   The light emitting device according to claim 1, wherein a specific resistance of the entire buffer layer is 0.5 (Ω · cm) or more.   The light emitting device according to claim 1, wherein the buffer layer has a stacked structure of a plurality of layers.   The light emitting device according to any one of claims 1 to 5, wherein a width of the light emitting unit separation groove is in a range of 2 to 300 µm.   The light-emitting device is divided from an inter-device separation groove provided between a plurality of light-emitting devices, and the inter-device separation groove is formed partway through the buffer layer. Item 7. The light emitting device according to any one of Items 1 to 6.   The light emitting device is divided from an inter-device separation groove provided between a plurality of light emitting devices, and the inter-device separation groove is formed by removing the buffer layer. The light emitting device according to claim 1.   Of the layers exposed on the side surfaces of the light emitting device, covering the entire bottom surface and side surfaces in the light emitting unit separation groove, at least the side surfaces of the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer And an insulating layer that is in contact with a part of the first conductivity type side electrode on the main light extraction direction side and covers a part of the second conductivity type side electrode opposite to the main light extraction direction. The light-emitting device according to claim 1.   An insulating layer non-formation region where the insulating layer is not formed is present on the side surface of the light emitting device from the main light extraction direction, and the insulating layer is at least the first conductive semiconductor layer, the active layer structure The light emitting device according to claim 9, wherein the light emitting device covers a side wall of the second conductivity type semiconductor layer.   The light-emitting device according to claim 1, wherein the thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a V group. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting device according to claim 1, wherein:   11. The light emitting device according to claim 9, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers. The reflectance at which the light of the emission wavelength of the light emitting device perpendicularly incident on the buffer layer from the first conductivity type semiconductor layer side is reflected by the buffer layer is represented by R2, and the second conductivity type semiconductor layer is formed on the insulating layer. R12 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident from the side is reflected by the insulating layer, and light having the emission wavelength of the light emitting device that is perpendicularly incident on the insulating layer from the first conductive semiconductor layer side is R12. When the reflectance reflected by the insulating layer is represented by R11, and the reflectance by which the light having the emission wavelength of the light emitting device perpendicularly incident on the insulating layer from the active layer structure side is reflected by the insulating layer is represented by R1q. ,
(Formula 1) R2 <R12
(Formula 2) R2 <R11
(Formula 3) R2 <R1q
The light emitting device according to claim 9, wherein the insulating layer is configured to satisfy all of the conditions.   The light emitting device according to claim 1, wherein a surface of the buffer layer in a main light extraction direction is not flat. R3 is a reflectance at which the light having the emission wavelength of the light emitting device that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer is reflected by the buffer layer, and the light emission that is perpendicularly incident on the light extraction side space from the buffer layer. When the reflectance at which the light of the emission wavelength of the device is reflected at the interface with the space is represented by R4, R4 <R3
The light emitting device according to claim 1, further comprising a low reflection optical film on the light extraction side of the buffer layer so as to satisfy the above.   The light emitting device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The light emitting device according to claim 1, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having a metal surface by metal solder.   19. The bonding between the first conductivity type side electrode and the second conductivity type side electrode and the metal surface of the support is made of only metal solder, or metal solder and metal bumps. The light-emitting device of description. The light emitting device according to claim 18 or 19, wherein the base material of the support is selected from the group consisting of metal, AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN, and CuW.   21. The light emitting device according to claim 18, wherein a metal layer is not formed at a separation portion between the light emitting devices of the support. A method of manufacturing an integrated compound semiconductor light emitting device having a plurality of light emitting units on a support,
Forming a buffer layer on the substrate;
Forming a thin film crystal layer having at least a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer;
Forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
A first etching step of exposing a portion of the first conductivity type semiconductor layer to the surface;
Forming a first conductivity type side electrode on the exposed surface of the first conductivity type semiconductor layer by the first etching step;
From the thin film crystal layer surface to the interface of the buffer layer, or from the thin film crystal layer surface to a part of the buffer layer, in order to form a light emitting unit separation groove for electrically separating the light emitting units from each other A second etching step to remove
A third etching step of removing at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer to form an inter-device separation groove for separating into a plurality of light emitting devices;
And a step of removing the substrate. A method of manufacturing an integrated compound semiconductor light emitting device.   Before the step of removing the substrate, the first conductivity type side electrode and the second conductivity type side electrode are bonded to a metal surface on a support and mounted on the support. The method of claim 22.   24. The method according to claim 23, further comprising the step of separating the plurality of light emitting devices after the step of removing the substrate.   The film formation step of the buffer layer is performed as a part of the film formation step of the thin film crystal layer and prior to the formation of the first conductivity type semiconductor layer. The method described.   The method according to any one of claims 22 to 25, wherein a specific resistance of at least a portion of the buffer layer in direct contact with the first conductivity type semiconductor layer is 0.5 (Ω · cm) or more.   The method according to any one of claims 22 to 26, wherein the specific resistance of the entire buffer layer is 0.5 (Ω · cm) or more.   The method according to any one of claims 22 to 27, wherein the buffer layer is formed as a stacked structure of a plurality of layers.   The third etching step is performed simultaneously with or separately from the second etching step, and etching is performed from the surface of the thin film crystal layer to the interface of the buffer layer or until a part of the buffer layer is removed from the surface of the thin film crystal layer. The method according to any one of claims 22 to 28, wherein the method is performed.   The method according to any one of claims 22 to 28, wherein in the third etching step, etching is performed until at least the surface of the substrate is reached. The second and third etching steps are performed by dry etching using a gas species selected from the group consisting of Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations of two or more thereof. 31. A method according to any one of claims 22-30.   32. The method of claim 31, wherein a patterned metal fluoride layer is used as an etching mask. Wherein the metal fluoride _{layer, SrF 2, AlF 3, MgF} 2, BaF 2, CaF 2 and 33. The method of claim 32 wherein the selected from the group consisting of.   The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order, and before the step of forming the first conductivity type side electrode, The method according to claim 22, further comprising a step of forming an insulating layer.   The method according to claim 34, wherein the step of forming the insulating layer is performed after the first to third etching steps. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, etching is performed at a depth from the surface to remove at least a part of the buffer layer to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
The method according to claim 22, further comprising: removing a part of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove to form a scribe region. The step of forming the second conductivity type side electrode, the first etching step and the step of forming the first conductivity type side electrode are performed in this order,
In the third etching step, etching is performed at a depth from the surface until at least a part of the buffer layer is removed or at least reaches the substrate to form the inter-device separation groove,
Furthermore, after the first to third etching steps, before the step of forming the first conductivity type side electrode, a step of further forming an insulating layer,
A step of removing all of the insulating layer deposited on the bottom surface of the groove in the inter-device separation groove and a part of the insulating layer formed on the side wall of the inter-device separation groove on the groove bottom surface side. A method according to any one of claims 22 to 28.   The device separation groove is formed by performing the second and third etching steps simultaneously and performing etching until the interface of the buffer layer or until a part of the buffer layer is removed. 36. The method according to 36.   The device separation groove is formed by performing the second and third etching steps simultaneously and performing etching until the interface of the buffer layer or until a part of the buffer layer is removed. 37. The method according to 37.   The step of removing the substrate is performed by irradiating light from the substrate side with light having a wavelength that is transparent to the substrate and is absorbed by the buffer layer. The method according to claim 22, wherein the peeling is performed at the interface between the substrate and the buffer layer.   The method according to claim 23, wherein the bonding of the first conductivity type side electrode and the second conductivity type side electrode to the metal surface on the support is performed by metal solder. The base material of the support, a _{metal, AlN, Al 2 O 3,} Si, glass, SiC, diamond, claim 23 or 41 method wherein a is selected from the group consisting of BN and CuW. Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, A method according to any one of claims 22 to 42, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.

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