JP2007189131A - Solid photographing element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid photographing element wherein the signal outputs of respective colors are increased as crosstalks are reduced, with respect to the photographing element wherein there is so provided on a first conductive semiconductor a first conductive well having a lower concentration than the first conductive semiconductor as to dispose photoelectric converters in this first conductive well. <P>SOLUTION: The photographing element has: a first conductive first semiconductor layer; a second semiconductor layer wherein it is disposed on the first semiconductor layer and its concentration relative to the first conductive impurity is lower than the concentration of the first semiconductor layer; and a second conductive barrier layer disposed in the inside of the second semiconductor layer. The barrier layer is disposed below the photoelectric converters other than the photoelectric converter wherein a color filter is disposed corresponding to the color of the longest wavelength. Moreover, the barrier layer disposed below an active region is disposed nearer on the side of the first semiconductor layer than the barrier layer disposed below a separating region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having a color filter.

  In recent years, video cameras and electronic cameras have been widely used. For these cameras, CCD-type, CMOS-type, etc. solid-state image sensors are used. In the solid-state imaging device, a plurality of pixels each having a photoelectric conversion unit are arranged in a matrix, and a signal charge is generated by the photoelectric conversion unit of each pixel. Each photoelectric conversion unit is electrically separated by a separation region. A CMOS type solid-state imaging device has a pixel amplifier in each pixel, and generates and outputs an electrical signal corresponding to a signal charge.

  The generated and accumulated signal charge is transferred from the charge storage unit to the CCD or pixel amplifier in accordance with the operation of the transfer unit arranged adjacent to the photoelectric conversion unit. A signal charge or an electric signal corresponding to the signal charge is output to the outside via a CCD or signal line.

  In a CMOS type solid-state imaging device, in order to form a CMOS, a P-type well is provided on an N-type silicon substrate, and a pixel region is disposed in the P-type well. However, the configuration in which the P-type well is provided on the N-type silicon substrate as described above tends to be insufficient in sensitivity (that is, the amount of charge generated with respect to the incident amount).

  This is because the charge generated in the P-type well is taken into the N-type silicon substrate, and a component that does not contribute as signal charge is generated. For this reason, a configuration has been proposed in which a P-type well having a lower concentration is disposed on a P-type silicon substrate (for example, Patent Document 1).

  A solid-state image sensor that obtains a color signal has a predetermined color filter above the photoelectric conversion unit of the pixel. As for the color filter, one of red (R), green (G), and blue (B) is arranged corresponding to the photoelectric conversion unit in the RGB system, and one of cyan, magenta, and yellow is arranged in the complementary color system. The In addition, a color filter of four or more colors may be used.

  By the way, it is known that a solid-state imaging device that obtains a color signal in this way has low sensitivity to light with a long wavelength (R in the case of RGB). This is because light having a longer wavelength penetrates from the surface of the semiconductor to a deeper position and performs photoelectric conversion. When photoelectric conversion is performed at a deep position, the distance that the charge drifts becomes long, so that the probability of reaching a desired photoelectric conversion unit is low.

  For this reason, the sensitivity of light having a long wavelength decreases. Further, when such charges reach the photoelectric conversion units of adjacent pixels, crosstalk occurs. In recent years, it has been desired to improve the resolution by reducing the pixel size. However, when the pixel size is reduced, the distance between adjacent photoelectric conversion units is also reduced, the crosstalk component generated by light having a long wavelength is increased, and the SN ratio is deteriorated.

Therefore, in Patent Document 2, a photoelectric conversion unit other than a photoelectric conversion unit in which an R color filter is disposed (hereinafter referred to as an R pixel, an R photoelectric conversion unit, or simply R. The same applies to B and G). It has been proposed to improve the S / N ratio by disposing a barrier region at the lower portion of the light source and blocking charges that enter the adjacent photoelectric conversion unit from the R color filter and become crosstalk.
JP 2002-170945 A JP 2004-152819 A

If a low-concentration P-type well is provided on a P-type semiconductor substrate according to Patent Document 1 and a barrier region is disposed according to Patent Document 2, a solid-state imaging device with improved light output and reduced crosstalk should be obtained.
However, in reality, although the sensitivity of R is improved and crosstalk is reduced, there is a new problem that the output value of the optical signal other than R becomes small.

  The present invention has been made in view of such problems, and provides a solid-state imaging device in which the signal output of each color is increased while crosstalk is reduced.

As a result of further research, the present inventor has found that the barrier region is provided on the photoelectric conversion unit side from the lowermost part of the separation region in the configuration disclosed in the above patent document, and this is the cause of the above problem. And came to invent. That is, in the above configuration, the photoelectric conversion portions other than R are not sufficiently wide from the surface, and the area for photoelectric conversion is reduced. Therefore, in the conventional configuration, incident light is not efficiently photoelectrically converted.
Accordingly, the solid-state imaging device according to the first aspect of the present invention includes a first conductive type first semiconductor layer and an upper surface of the first semiconductor layer, and the first conductive type impurity concentration is higher than that of the first semiconductor layer. A second semiconductor layer having a low concentration, and a second conductivity type barrier region layer disposed inside the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer, depending on the amount of incident light An active region having at least a photoelectric conversion unit that generates and accumulates electric charge and a color filter that is disposed corresponding to the photoelectric conversion unit and transmits incident light having a wavelength corresponding to a predetermined color are electrically connected between the active region. A plurality of pixels including a separation region to be separated are two-dimensionally arranged on the surface of the second semiconductor layer, and the barrier region layer is a portion other than a photoelectric conversion unit in which the color filter corresponding to the longest wavelength color is disposed. Photoelectric converter Provided below, the barrier region layer disposed under the active area and being disposed on the first semiconductor layer side than the barrier region layer disposed below the isolation region.
With this configuration, the width in the thickness direction in which photoelectric conversion is performed can be increased while crosstalk is reduced, and incident light can be efficiently photoelectrically converted. For this reason, the output of an optical signal increases.

  The solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the photoelectric conversion unit has a second conductivity type charge storage layer, and the active region has a charge stored in the charge storage layer. A transfer gate portion that transfers the charge, and a floating diffusion portion that is electrically connected to the charge storage layer by the operation of the transfer gate portion and charges stored in the charge storage layer are transferred, and a charge transferred to the floating diffusion portion A pixel amplifier section that outputs a signal corresponding to the above, a reset transistor that resets the floating diffusion section to a constant potential, and a selection transistor that selects a pixel, and a silicon oxide film by selective oxidation is disposed in the isolation region It is characterized by that.

  If charges generated by light incident from a certain pixel enter the photoelectric conversion unit of an adjacent pixel, such charge becomes crosstalk. However, such charges may adversely affect pixels within the same area. That is, an active element other than the photoelectric conversion unit is disposed in the pixel, and if unnecessary charges enter such an active element, an adverse effect such as a malfunction is caused, and the active element is made unstable. In the configuration having a plurality of active elements in the pixel as in this aspect, not only crosstalk is reduced, but the charge that becomes noise is prevented from entering the active elements other than the photoelectric conversion unit in the pixel. It becomes possible to hold the active element in a more stable state. In addition, when a so-called LOCOS oxide film is used for the isolation region, it is easy to form a barrier region layer having a step.

The solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the second aspect, wherein the active region includes a first active region where at least the photoelectric conversion unit is disposed, the pixel amplifier unit, and the selection transistor. At least a second active region, wherein the first active region and the second active region are electrically separated by the silicon oxide film formed by the selective oxidation. .
In this aspect, a photoelectric conversion unit having a charge storage unit is arranged in the first active region, and an active element that dislikes noise is arranged in the second active region. With this configuration, it is more difficult for the noise to enter the pixel amplifier and the selection transistor, and a more stable operation is maintained.

  A solid-state imaging device according to a fourth aspect of the present invention, in any one of the first to third aspects, has a crosstalk of the first conductivity type between the barrier region layer and the surface of the second semiconductor layer. A prevention layer is arranged. With this configuration, crosstalk is further reduced.

In the solid-state imaging device according to the fifth aspect of the present invention, in any one of the first to fourth aspects, a circuit for outputting a signal from the pixel is further disposed, and the circuit includes the second semiconductor layer. The MOS transistor disposed in the second semiconductor layer is provided with a second conductivity type well region on the surface of the second semiconductor layer, and the MOS transistor disposed in the second conductivity type well region is electrically connected to the second semiconductor layer. A well region of the first conductivity type to be separated is provided, and a MOS transistor is disposed in the well region of the first conductivity type.
In the solid-state imaging device according to the sixth aspect of the present invention, in any one of the first to fifth aspects, the impurity concentration of the first semiconductor layer is 1E18 cm 3 or more, and the impurity concentration of the second semiconductor layer is The impurity concentration of the first semiconductor layer is 1/10 or less.

  A solid-state imaging device according to a seventh aspect of the present invention includes a first conductive type first semiconductor layer, and an impurity concentration of the first conductive type lower than that of the first semiconductor layer disposed on the first semiconductor layer. A second semiconductor layer, a photoelectric conversion unit that generates and accumulates electric charge according to the amount of incident light, and a color filter that is arranged corresponding to the photoelectric conversion unit and transmits incident light having a wavelength corresponding to a predetermined color. A plurality of pixels having at least two-dimensionally arranged on the surface of the second semiconductor layer, and other color filters are arranged under the photoelectric conversion unit in which the color filter corresponding to the longest wavelength color is arranged. The second semiconductor layer having a thickness greater than that below the photoelectric conversion portion is disposed.

Even in such a configuration, the width in the thickness direction in which photoelectric conversion is performed can be increased and photoelectric conversion of incident light can be performed efficiently while crosstalk is reduced as in the first embodiment. For this reason, the output of an optical signal increases.
In the seventh aspect, a first conductivity type crosstalk preventing layer may be disposed at least partially between the surface of the second semiconductor layer and the first semiconductor layer.

According to the present invention, it is possible to increase the width in the thickness direction for performing photoelectric conversion, efficiently perform photoelectric conversion of incident light, and reduce crosstalk. For this reason, the output of an optical signal increases.

Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic plan view of 2 × 2 pixels of the solid-state imaging device according to the first embodiment of the present invention. Each wiring electrode is abbreviated. In addition, as described above, “R” is a pixel (or photoelectric conversion unit, hereinafter the same) having an R color filter, “G” is a pixel having a G color filter, and “B” is a pixel having a B color filter. Is shown. Here, the color filters are arranged in a Bayer array. However, the present invention is not limited to this, and a stripe arrangement may be used.

  Each pixel 2 includes a photoelectric conversion unit 3, a transfer transistor 4, a pixel amplifier 5, a row selection transistor 6, and a reset transistor 7. Here, the transfer transistor 4, the pixel amplifier 5, the row selection transistor 6, and the reset transistor 7 are all NMOS transistors.

  Reference numerals 31, 32, 38, 39, and 40 are N-type impurity diffusion regions that are part of each transistor. Reference numerals 33, 34, 35, and 36 are polysilicon gates (electrodes) of the transistors. is there. Reference numeral 38 denotes a power supply diffusion unit to which the power supply voltage VDD is applied, and reference numerals 31 and 32 denote floating diffusion units as will be described later.

  The photoelectric conversion unit 3 is a buried photodiode including a charge storage layer 44 and a depletion prevention layer 43 (see FIG. 2). One of R, G, and B color filters is arranged corresponding to the photoelectric conversion unit 3. Although the RGB color filter is used here, the present invention is not limited to this, and a complementary color filter may be used. Further, a photodiode without a depletion prevention layer may be used instead of the embedded photodiode.

  The photoelectric conversion unit 3 photoelectrically converts light incident through the color filter and stores the generated charge in the charge storage layer 44. The charges accumulated in the charge accumulation layer 44 of the photoelectric conversion unit 3 are transferred to the floating diffusion units 31 and 32 when the transfer transistor 4 is turned on.

  The transfer transistor 4 is a MOS transistor having the charge storage layer 44 of the photoelectric conversion unit 3 as a drain and one floating diffusion unit 31 as a source. The transfer transistor 4 is driven by a drive signal applied to its gate 33 (hereinafter referred to as a transfer gate).

  The floating diffusion portions 31 and 32 include a first floating diffusion portion 31 disposed adjacent to the transfer gate 33 and a second floating diffusion portion 32 separated by a separation region 46 from the first floating diffusion portion 31. And are electrically connected by the wiring electrode 37. The floating diffusion portions 31 and 32 are electrically connected to the gate 35 of the pixel amplifier 5 by the wiring electrode 37.

  The pixel amplifier 5 is a MOS transistor having the power source diffusion portion 38 as a drain and the diffusion region 39 as a source. As described above, the gate 35 of the pixel amplifier 5 is connected to the floating diffusion portions 31 and 32 (the source of the transfer transistor 4). The pixel amplifier 5 outputs an electric signal corresponding to the voltage of the gate. Accordingly, the pixel amplifier 5 outputs an electrical signal corresponding to the amount of charge generated by the photoelectric conversion unit 3.

  The row selection transistor 6 is a MOS transistor having the diffusion region 39 as a drain and the diffusion region 40 as a source. The row selection transistor 6 outputs the output of the pixel amplifier 5 to the vertical signal line 22 by being turned on. That is, the pixel amplifier 5 and the row selection transistor 6 can be read by the source follower.

The reset transistor 7 is a MOS transistor having the power source diffusion portion 38 as a drain and the second floating diffusion portion 32 as a source. The reset transistor 7 resets charges accumulated in the floating diffusion portions 31 and 32 by being turned on.
FIG. 2 is a cross-sectional view taken along the line BB ′ of FIG. Note that the configuration above the silicon oxide film is omitted. Actually, a wiring electrode, a protective film, a color filter, and the like are disposed above the silicon oxide films 45 and 48.

  In the present solid-state imaging device, a P-type epitaxial layer 42 having a lower concentration is disposed on a P-type silicon substrate 41 having a high impurity concentration. That is, the first conductive type first semiconductor layer and the first conductive type second semiconductor layer form one substrate. The thickness of the P-type epitaxial layer 42 is 6 micrometers (calculated in FIG. 3 to be described later, including a region having an excessive concentration). However, it is not limited to this, and may be in the range of 5-12 micrometers.

  The impurity concentration of the P-type silicon substrate 41 is 1E18 / cm 3 (10 to the 18th power per cubic centimeter; the same applies hereinafter), and the impurity concentration of the P-type epitaxial layer 42 (hereinafter simply referred to as concentration) is 1E15 / cm 3. It is. However, the concentration is not limited to these. The concentration of the P-type silicon substrate 41 may be in the range of 1E16 to 5E20 / cm 3, and the concentration of the P-type epitaxial layer 42 may be lower than that.

  As described above, in the solid-state imaging device 1, the concentration of the P-type silicon substrate 41 is higher than that of the P-type epitaxial layer 42 disposed on the P-type silicon substrate 41. On the other hand, the charge generated by photoelectric conversion and serving as a signal is an electron here, and moves to a higher potential. The P-type silicon substrate 41 containing a high concentration of P-type impurities has a lower potential than the P-type epitaxial layer 42. For this reason, even if the charge (electrons) generated in the P-type epitaxial layer 42 drifts, it is guided not to the substrate side but to the surface side of the P-type epitaxial layer 42. The photoelectric conversion unit 3 is disposed on the surface side of the P-type epitaxial layer 42. Therefore, with the above configuration, less charge is absorbed on the substrate side, and a high light output is obtained.

  If the concentration of the P-type epitaxial layer 42 is lower than that of the P-type silicon substrate 41, the above effect can be obtained. However, if the concentration of the P-type silicon substrate 41 is 1E18 / cm 3 or more and the concentration of the P-type epitaxial layer 42 is 1/10 or less of the concentration of the P-type silicon substrate 41, the potential generated by the two concentration differences. The absolute value of the difference is sufficiently large and more preferable.

  The photoelectric conversion units 3R and 3G are buried photodiodes each having an N-type charge storage layer 44 and a P-type depletion prevention layer 43 on the upper surface thereof. A photoelectric conversion unit having an R color filter is referred to as a photoelectric conversion unit 3R, a photoelectric conversion unit having a G color filter is referred to as a photoelectric conversion unit 3G, and a photoelectric conversion unit having a B color filter is referred to as a photoelectric conversion unit 3B. The charge storage layer 44 has a thickness of 0.3 micrometers and a concentration in the range of 5E16 to 5E17 / cm3. The depletion prevention layer 43 has a thickness of 0.2 micrometers and a concentration in the range of 1E18 to 1E19 / cm3.

  A thin silicon oxide film 45 is disposed on the upper surface of the depletion prevention layer 43. Here, the film thickness is 0.05 micrometers. Each pixel is electrically separated by a separation region 46. In the isolation region 46, a thick LOCOS silicon oxide film (hereinafter referred to as a LOCOS oxide film) 48 and an isolation diffusion 49 made of P-type impurities having a thickness of about 0.5 micrometers are disposed below the isolation region 46. The thickness of the LOCOS oxide film 48 is 0.8 micrometers. However, it is not limited to this. Further, if the LOCOS oxide film is sufficiently separated, the separation diffusion 49 is not necessarily arranged.

  As described above, here, the silicon oxide film 48 by selective oxidation (LOCOS) and the isolation diffusion 49 below the isolation region 46 are used. However, trench isolation may be used.

  FIG. 3A is a net impurity concentration distribution diagram of E-E ′ portion in FIG. 2, and FIG. 3B is a net impurity concentration distribution diagram of F-F ′ portion in FIG. 2. In each case, the vertical axis indicates the concentration, and the horizontal axis indicates the depth from the substrate surface (the surface of the depletion prevention layer). The vertical axis is normalized by logarithmic display. As is clear from this figure, a barrier region layer 47 having a thickness of about 1 micrometer is disposed under the photoelectric conversion unit 3G (and the photoelectric conversion unit 3B not shown in FIG. 2).

  As understood from FIG. 3A, the barrier region layer 47 is not disposed under the photoelectric conversion unit 3R. As can be understood from FIG. 3B, the barrier region layer 47 is disposed at a depth of about 4 micrometers from the surface (that is, d1 in FIG. 2 is 4 micrometers). Further, there is a PN junction between the charge storage layer 44 and the P-type well layer 42 at a depth of about 0.5 micrometers from the surface.

  The barrier region layer 47 has the same P-type conductivity as the P-type epitaxial layer 42 and has a higher concentration than this. Here, the peak concentration is 3E17 / cm 3. However, the peak concentration of the barrier region layer 47 may be higher than that of the P-type epitaxial layer 42. However, 10 times or more the concentration of the P-type epitaxial layer 42 is preferable.

  As described above, the electric charge that is photoelectrically converted into a signal is an electron here, and is difficult to be guided to a region where a P-type impurity having a low potential is high in concentration. Therefore, since the barrier region layer 47 exists, it becomes difficult for the electric charges 76 generated by the light 72 incident from the photoelectric conversion unit 3R to drift toward the adjacent photoelectric conversion unit 3G. This will be described below.

  Since the light 51 incident from the photoelectric conversion unit 3R has a long wavelength, electric charges (electrons) 52 are generated in the deep portion of the P-type epitaxial layer. The charge 52 drifts in the P-type epitaxial layer 42 so as to move away from the P-type silicon substrate 41 because the P-type silicon substrate 41 has a high concentration.

  The barrier region layer 47 is not disposed under the photoelectric conversion unit 3R, and a large amount of charge is guided to the charge storage layer 44 of the photoelectric conversion unit 3R and becomes an R signal. Among the remaining charges 52, the charges 52 drifting toward the adjacent photoelectric conversion unit 3G are directed to the barrier region layer 47 having a low potential (high concentration). For this reason, the barrier region layer 47 becomes a barrier and blocks the drift of the charge 52. That is, even if the charge 52 temporarily drifts toward 3G, it drifts toward the charge accumulation unit 44 of the photoelectric conversion unit 3R having a higher potential. Therefore, crosstalk is reduced.

  Furthermore, not only is the crosstalk reduced, but it is also possible to prevent noise charges from entering each transistor in the same pixel. Therefore, each transistor in the same pixel can be held in a more stable state.

The barrier region layer 47 is disposed inside the P-type well layer 42 and separated from the separation diffusion 49 and the charge storage layer 44. As is apparent from FIG. 3 (b), this distance is approximately 2 micrometers. As described above, the P-type epitaxial layer 42 having a sufficient thickness is disposed under the photoelectric conversion units 3G and 3B. Therefore, a sufficient depletion layer in which incident light is photoelectrically converted can be obtained. For this reason, the amount of generated charges increases, and the light output value increases accordingly.
Furthermore, the barrier region layer 47 disposed under the photoelectric conversion units 3G and 3B is disposed closer to the P-type silicon substrate 41 than the barrier region layer 47 disposed under the isolation region 46. That is, the barrier region layer 47 is different in the depth d1 disposed under the charge storage layer 44 and the depth d2 disposed under the isolation region 46. Thereby, a step is generated in the separation region 46. The step value (d1-d2) is about 0.4 micrometers, which is ½ of the LOCOS oxide film 48.

  Since such a step is generated, crosstalk is further reduced. That is, in order for the electric charge 52 generated under the photoelectric conversion unit 3R to drift toward the photoelectric conversion unit 3G adjacent to the G and become crosstalk, the charge 52 must pass under the separation region 46. However, the passage has a slight width d3 between the separation diffusion layer 49 and the barrier region layer 47. In addition, the isolation diffusion layer 49 and the barrier region layer 47 have a high P-type impurity concentration (and therefore a low potential), making it difficult for electrons to pass through. For this reason, the P-type epitaxial layer 42 having a sufficient thickness is disposed under the photoelectric conversion units 3G and 3B to increase the light output value and to reduce the crosstalk due to the step.

  As described above, this step is approximately 0.4 micrometers here. However, this step is effective even at 0.3 micrometers, and the larger the step, the greater the effect. In this embodiment, since the thickness of the LOCOS oxide film 48 is 0.8 micrometers and the thickness of the separation diffusion layer 49 is 0.5 micrometers, d3 is 1.1 micrometers. However, the width of d3 may be made narrower by changing the thickness of the LOCOS oxide film 48 and the thickness of the isolation diffusion layer 49. The width of d3 is preferably 1.5 micrometers or less.

  The step is formed using the LOCOS oxide film 48. For this reason, the stepped barrier region layer 47 can be easily formed by one ion implantation. As will be described later, the barrier region layer 47 is formed by ion implantation. In ion implantation, the thicker the silicon oxide film, the smaller the distance from which ions are implanted from the silicon surface. A LOCOS oxide film 48 is disposed in the isolation region 46, and the silicon oxide film is thicker in the isolation region 46 than in other regions. Therefore, the separation region 46 reduces the depth at which the ions reach more than other regions. For this reason, a step is generated in the depth of the barrier region layer 47 between the isolation region 46 and other regions.

  Here, in the manufacturing process for forming the barrier region layer 47, the oxide film (LOCOS oxide film 48) in the isolation region 46 is set to 0.8 micrometers, and the silicon oxide film on the photoelectric conversion unit 3 is set to 0.05 as a protective film. The micrometer is arranged. Therefore, ions implanted under the thin silicon oxide film are implanted approximately 0.4 micrometers deeper than ions implanted under the thick LOCOS oxide film 48. As described above, by ion-implanting the pixel region having a difference in silicon oxide film thickness, the stepped barrier region layer 47 can be easily formed by a single ion implantation process.

  The thicker the LOCOS oxide film 48 is, the larger the step is, and the effect is increased. However, if the silicon oxide film exceeds about 1.6 micrometers in the manufacturing process, it becomes difficult to manufacture.

  Further, the LOCOS oxide film 48 is left as it is after forming the barrier region layer 47 and used as an isolation region. Therefore, the step portion of the barrier region layer 47 and the charge storage layer 44 are aligned in a self-aligning manner. Therefore, it is more preferable that the shallow barrier region layer 47 protrudes under the photoelectric conversion units 3G and 3B and the width for photoelectric conversion is not reduced. However, the present invention is not limited thereto, and a resist may be used as a mask for forming the barrier region layer 47, or the LOCOS oxide film 48 may be used as a mask and then removed to form a silicon oxide film again. .

  By the way, the value of d3 shown in FIG. 2 is that d2 is 2.5 micrometers, the total thickness of the LOCOS oxide film 48 and the depth of the isolation diffusion 49 is 1.6 micrometers, and the thickness of the barrier region layer 47. If the thickness is 1 micrometer, it is 0.4 micrometers. Thus, the width d3 through which charges in the separation region 46 can pass is small. In order to generate crosstalk, the charge must pass through this narrow width d3. Therefore, crosstalk is further reduced.

  Here, the crosstalk value was calculated. This crosstalk value assumes that the size of the pixel is 8 micrometers square and light is incident on the pixel vertically, and the number of charges that drift to an adjacent pixel and become crosstalk is applied to the pixel on which light is incident. The value is divided by the number of trapped charges.

  The crosstalk value that is incident from the R photoelectric conversion unit and contributes to the output value of the adjacent G pixel is 0.35%, and the crosstalk value that is incident from the G photoelectric conversion unit and contributes to the output value of the adjacent R pixel Was 0.14%. This value is significantly lower than 1%, which is remarkably recognized as image disturbance.

  FIG. 4 is a graph showing the spectral sensitivity characteristics of the solid-state imaging device 1 according to the present embodiment. As a comparative example, a spectral sensitivity characteristic of a conventional solid-state imaging device in which a P-type semiconductor layer is disposed on an N-type silicon substrate and a photoelectric conversion unit is provided on the P-type semiconductor layer is also shown. The vertical axis is a linear display of the value obtained by standardizing the photocurrent. This value corresponds to an electric signal generated by the photoelectric charge output from each pixel. The horizontal axis is the wavelength.

  At a wavelength of about 0.45 micrometers, which is the B (blue) wavelength region, the photocurrent of the solid-state image sensor 1 is not different from that of the comparative solid-state image sensor. However, the photocurrent of the solid-state imaging device 1 is clearly larger than that of the solid-state imaging device of the comparative example on the longer wavelength side than the wavelength in the vicinity of 0.5 micrometers, which is the G (green) wavelength region. The photocurrent value is improved by 17% at a wavelength of 0.53 micrometers, which is the wavelength of G, and by 60.7% at a wavelength of 0.6 micrometers, which is the wavelength of R, as compared with the comparative example.

  FIG. 5 is a cross-sectional view taken along line C-C ′ of FIG. FIG. 6 is a cross-sectional view taken along the line D-D ′ in FIG. 1. In all cases, the structure above the silicon oxide film is omitted except for the gate electrode made of polysilicon.

  In regions other than the isolation region 46, a diffusion region is formed on the silicon surface, or a gate electrode is disposed to become an active region. The solid-state imaging device 1 of this embodiment has a plurality of active regions 55 and 56 in each pixel. One is a first active region 55 having at least the photoelectric conversion unit 3, and the other is a second active region 56 having at least the pixel amplifier 5 and the row selection transistor 6. As described above, the photoelectric conversion unit 3, the pixel amplifier 5 and the row selection transistor 6, which are active elements for performing source follower readout, are arranged in different active regions 55 and 56.

  In the first active region 55, the transfer gate 33, the floating diffusion portion 31, and the like are arranged as other active elements. Further, in the second active region 56, an N type diffusion region 32 and a gate electrode 34 constituting a reset transistor which is another active element are arranged.

  Among these active elements, the pixel amplifier 5 and the row selection transistor 6 preferably reduce noise in order to perform source follower readout. The charge generated by light becomes noise charge unless light enters from the photoelectric conversion unit and is captured by the predetermined charge storage unit 44. For example, when noise charges enter the N-type diffusion regions 39 and 40, the output value changes accordingly, and the operation is not stable.

  However, as can be understood from FIGS. 5 and 6, the second active region 56 in which the pixel amplifier 5 and the row selection transistor 6 are arranged is surrounded by a step in the barrier region layer 47. . Due to the level difference of the barrier region layer 47, the noise charge entry width d3 is narrowed as described above, which becomes a noise charge barrier. Therefore, it becomes difficult for the above-mentioned noise to enter the pixel amplifier 5 and the row selection transistor 6, and the source follower readout is executed more stably.

  FIG. 7 is a cross-sectional view in each manufacturing process of the solid-state imaging device 1 according to the present embodiment, and corresponds to a D-D ′ portion in FIG. 1. Hereinafter, the manufacturing process of the solid-state imaging device 1 will be described with reference to the drawings. First, a P-type epitaxial layer 42 is formed in a predetermined region of the P-type silicon substrate 41 according to a known technique.

Next, a step of forming an isolation region by the LOCOS oxide film 48 is performed. That is, first, a silicon nitride film (not shown) is formed by a CVD method and patterned so as to leave a portion that becomes an active region. A thick LOCOS oxide film will be formed later in the opening, but an isolation diffusion 49 is provided in advance in the opening. The separation diffusion 49 finally has a depth of 0.8 micrometers and a concentration of 1E17 to 1E18 / cm 3. Next, a LOCOS oxide film having a thickness of 0.8 micrometers is selectively formed in the isolation region in this opening by a thermal oxidation method.
After removing the silicon nitride film, a thin silicon oxide film 45 is formed in the active region by a thermal oxidation method for the purpose of a protection film for ion implantation. FIG. 7A shows this state.

  Next, a step of forming the barrier region layer 47 is performed. That is, a resist mask having a film thickness of 3 to 5 micrometers is provided in the photoelectric conversion portion 3R and the peripheral circuit region, ion implantation is performed, and a predetermined heat treatment is performed, so that the barrier region layer 47 having a peak concentration of 3E17 / cm 3 is formed. Form. At this time, ions are implanted deeply in the thin silicon oxide film 45 and shallow in the thick LOCOS oxide film 48, so that a barrier region layer 47 having a step is easily formed to a predetermined depth. Further, the barrier region layer 47 is not formed under the photoelectric conversion unit 3R and the peripheral circuit. FIG. 7B shows this state.

  In order to simplify the description, it is assumed that the thin silicon oxide film 45 is held until the solid-state imaging device 1 is completed. However, the thin silicon oxide film 45 used here is removed after the end of this step, and the oxide film in each part may be formed again by changing the film thickness depending on the purpose, such as a protective film on the depletion prevention layer 43 or a gate oxide film. Good.

  Next, a step of providing a predetermined diffusion portion is performed. That is, a known photolithographic etching method and impurity diffusion method are repeated to form active elements in the pixel and active elements in the peripheral circuit. The diffusion part (for example, reference numeral 40) of the MOS transistor is formed by a LOCOS oxide film and self-alignment using polysilicon. The diffusion portions (charge storage portion 44 and depletion prevention layer 43) disposed in the photoelectric conversion portion are preferably formed after each gate electrode made of polysilicon is provided in order to suppress variation in charge transfer. FIG. 7C shows this state. Then, the present solid-state imaging device 1 is completed by forming wirings, color filters, microlenses, protective films and the like.

Here, the step of the barrier region layer 47 is formed using the cross-sectional shape of the LOCOS oxide film and the thin oxide film 45. However, as described above, a resist may be used.
FIG. 8 is a circuit diagram of the solid-state imaging device 1 according to the first embodiment of the present invention. Here, the configuration has pixels 3 in 3 rows and 3 columns, but the number of pixels is not limited to this.

  The solid-state imaging device 1 includes a pixel region in which the pixels 2 are arranged, a reading unit (vertical signal line, horizontal signal line, etc.) that guides signals output from the pixels 2 to the outside, and a reading circuit that operates the pixels 2 and the reading unit. (Vertical scanning circuit 10, horizontal scanning circuit 20, etc.). Note that here, the reading circuit is sometimes referred to as a peripheral circuit.

  Each pixel 2 includes a photoelectric conversion unit 3, a transfer transistor 4, a pixel amplifier 5, a row selection transistor 6, and a reset transistor 7. Here, the transfer transistor 4, the pixel amplifier 5, the row selection transistor 6, and the reset transistor 7 are all NMOS transistors.

  The transfer transistors 4 have gates commonly connected in the row direction by the drive wiring 11 and operate in accordance with the drive signal φTG (n, n + 1) of the vertical scanning circuit 10. The row selection transistors 6 have gates commonly connected in the row direction by the drive wiring 12 and operate according to the drive signal φL (n, n + 1) of the vertical scanning circuit 10. The reset transistors 7 have gates commonly connected in the row direction by the drive wiring 13 and operate according to the drive signal φRS (n, n + 1) of the vertical scanning circuit 10. The drain of the pixel amplifier 5 and the drain of the reset transistor 7 are commonly connected to all the pixels, and are connected to the power supply voltage VDD via the wiring 14. The source of the pixel amplifier 5 is connected to the drain of the row selection transistor 6, and the source of the row selection transistor 6 is connected to the vertical signal line 22 in the column direction.

  A constant current source 23 and a vertical signal line reset transistor 24 for resetting the vertical signal line 22 are arranged at one end of each vertical signal line 22. A constant voltage VCS is applied to the constant current source 23, and a constant voltage VRV is applied to the vertical signal line reset transistor 10. Here, both VCS and VRV are set to the ground potential. A drive signal φRV is applied to the gate of the vertical signal line reset transistor 24, and the vertical signal line 22 is reset in accordance with the drive signal φRV.

  The other end of each vertical signal line 22 is connected to the horizontal signal line 21 via a column amplifier 25, a sample hold circuit 26, and a horizontal switch transistor 27. An output amplifier 28 and a horizontal reset transistor 29 are connected to the horizontal signal line 21. The gate of the horizontal switch transistor 27 is connected to the drive wiring 15. The horizontal switch transistor 27 is operated by a drive signal from the horizontal scanning circuit 20. The horizontal reset transistor 29 operates in response to the drive signal φRH, and resets the horizontal signal line 21 to the constant potential VRH.

The sample hold circuit 26 is a circuit that performs correlated double sampling. The electrical signal output from the pixel amplifier 6 includes a dark level corresponding to fixed pattern noise, reset noise, and the like (hereinafter simply referred to as noise). The dark level changes every time the gate potential of the pixel amplifier 6 is reset. Therefore, first, an electric signal (dark level) corresponding to noise immediately after reset is output from the pixel and temporarily accumulated in the sample hold circuit 26. Next, the photoelectric charge accumulated in the photoelectric conversion unit 3 is transferred to the gate of the pixel amplifier 6, and an electrical signal corresponding to the photoelectric charge superimposed on the noise is output from the pixel to the sample hold circuit 26. Is output to the horizontal signal line 28.
Here, the sample hold circuit 26 includes a clamp capacitor 16 that temporarily accumulates a dark level for each column, and a clamp transistor 17 that sets one electrode of the clamp capacitor 16 to a constant potential VRH. The sample-and-hold circuit and the correlated double sampling method are well-known techniques and will not be described in detail here.

  FIG. 9 is a drive timing chart of the solid-state imaging device 1 according to the present embodiment. The operation of the solid-state imaging device 1 will be described with reference to this figure. Note that transistors included in each pixel are NMOS transistors, and are turned on in response to a high-level drive signal. In addition, it is assumed that an exposure period (a period in which charges due to incident light are accumulated in the charge accumulation portion) has started before reaching the period T1.

  First, in a period T1, φL (n) is set to a high level. As a result, the row selection transistor 6 in the n-th row is turned on, and the source follower reading is started. Other rows are in a non-selected state.

  At the same time that φL (n) is set to the high level, φRS (n) is set to the high level, and the reset transistor 7 in the n-th row is turned on during the period T2. As a result, the floating diffusion portion and the gate of the pixel amplifier 5 are reset to the power supply voltage VDD. Further, by this reset operation, the floating diffusion portion becomes a dark level corresponding to the reset voltage. At the end of T2, the reset transistor 7 returns to the off state, but the floating diffusion portion and the gate of the pixel amplifier hold the dark level.

  In parallel with this operation, φSH is set to the high level during the period T3 and the clamp transistor 17 is turned on. As a result, source follower reading is performed, and the dark level corresponding to the reset voltage is output to the vertical signal line 22 from the pixel amplifier 5 via the row selection transistor 6 in the nth row. When the clamp transistor 17 is turned off at the end of the period T 3, the output side electrode of the clamp capacitor 16 is in a floating state while the dark level is held in the clamp capacitor 16, and the sample hold circuit 26 performs darkness. Level holding operation is performed.

  In the period T4, φTG (n) is set to the high level, and the transfer transistor 4 is turned on. As a result, the charge due to the incident light accumulated in the charge accumulation unit is transferred to the floating diffusion unit. Since the row selection transistor 6 in this row is in the on state, an electric signal corresponding to the voltage on which the charge due to the dark level and incident light is superimposed is output to the vertical signal line 22. At the end of the period T4, the transfer transistor T4 is turned off. The output electric signal is held on the vertical signal line 22 in the previous stage of the sample hold circuit 26 until the start of the horizontal scanning period.

  The period T6 is a horizontal scanning period. φH1 is set to the high level, and the horizontal switch transistor 27 is turned on. As a result, the dark level is subtracted by the sample and hold circuit 26 and a true electrical signal corresponding to the photocharge is output from the vertical signal line 22 in the first column to the horizontal signal line 21. Then, electrical signals are output in the same manner from the second and third rows.

  After the electrical signals are read from all the columns, the next row, n + 1 row, is selected in period T7, and the electrical signals are similarly read. In this way, electrical signals are read from the sequentially selected rows to obtain one image. Here, the exposure period is from the end of T4 to the start of T4. However, a known electronic shutter operation may be performed, and a mechanical shutter may be used in combination.

By the way, a CMOS circuit is used as the peripheral circuit of the solid-state imaging device. The CMOS circuit is composed of a PMOS transistor and an NMOS transistor. As is well known, the PMOS transistor is disposed in the N-type well, and the NMOS transistor is disposed in the P-type well.
Of these, NMOS transistors may be required to be arranged at a plurality of different P-type well potentials depending on the purpose of use. In such a case, a plurality of electrically isolated P-type wells are provided, and a plurality of types of NMOS transistors are arranged in P-type wells to which different potentials are applied.

  If a plurality of electrically isolated P-type wells are arranged in an N-type silicon substrate, a plurality of P-type wells are provided on the N-type silicon substrate and a reverse bias is applied between them. Is electrically separated. However, such a separation is not possible with a configuration in which a P-type epitaxial layer is arranged on a P-type silicon substrate as in the present solid-state imaging device. Therefore, the peripheral circuit of the solid-state imaging device has a configuration as shown in FIG. FIG. 10 is a partial cross-sectional view of the peripheral circuit of the solid-state imaging device according to the present embodiment.

The PMOS transistor is disposed in an N-type well 61 provided on the surface of the P-type epitaxial layer 42. The PMOS transistors may have the same N-type well potential. However, if different potentials are required, a plurality of such N-type wells 61 may be arranged so that each N-type well 61 and the P-type epitaxial layer 42 are reverse-biased.
The PMOS transistor is composed of source / drains 64 and 65 which are P-type diffusion regions, and a gate electrode 66 disposed through a thin silicon oxide film 45 therebetween. The N-type well 61 is provided with a diffusion region 63 for applying a potential, and a predetermined voltage is guided to the diffusion region 63 by wiring. Although not shown, a plurality of PMOS transistors are arranged in the N-type well 61, and each is separated by a thick LOCOS oxide film 48 and an N-type isolation diffusion 62 disposed therebelow.

  The NMOS transistors are disposed in a first P-type well 67 and a second P-type well 73 that are electrically separated from each other. For convenience sake, two different P-type wells 67 and 73 are illustrated here, but the present invention is not limited to this, and three or more may be arranged. If three or more are arranged, their P-type wells are electrically isolated.

The first P-type well 67 uses a part of the P-type epitaxial layer 42, and the first NMOS transistor is disposed here. The first NMOS transistor includes source / drains 70 and 71 which are N-type diffusion regions, and a gate electrode 72 which is disposed through a thin silicon oxide film 45 therebetween. The P-type well 67 is provided with a diffusion region 69 for applying a potential, and a predetermined voltage is guided to the diffusion region 69 by wiring. Although not shown, a plurality of NMOS transistors are arranged in the P-type well 67, and each is separated by a thick LOCOS oxide film 48 and an N-type isolation diffusion 68 disposed therebelow.
On the other hand, the second P-type well 73 is surrounded by an N-type region 79. For this reason, the second P-type well 73 is electrically isolated from the first P-type well 67 (that is, the P-type epitaxial layer 42). N-type region 79 is formed in this region by diffusion of N-type impurities by ion implantation. However, the formation of the N-type region 79 is not limited to this. First, an N-type diffusion region is formed in a portion that becomes a P-type well 73 and a portion that becomes an N-type region 79, and then P-type diffusion is performed in a region that becomes a P-type well 73, and a P-type well is formed inside. 73 and an N-type region 79 may be formed therearound.
The concentration of the P-type well 73 is 1E14 to 5E16 / cm 3. When a desired potential is applied, a depletion layer is generated at the interface between the N-type region 79 and the P-type epitaxial layer 42 and at the interface between the N-type region 79 and the second P-type well 73. When these two depletion layers are connected, punch-through occurs, and the second P-type well 73 and the P-type epitaxial layer 42 are electrically connected. Accordingly, the second P-type well 73 and the first P-type well 73 are electrically connected to the first P-type well 73. The P-type well 67 is also electrically connected. That is, the first P-type well 67 and the second P-type well 73 do not function as separate wells. For this reason, it is preferable that the N-type region 79 is 1E18 / cm 3 or more, or the thickness is increased.
If the impurity of the P-type silicon substrate is boron and the concentration is 1E19 / cm 3 or more, heavy metal ions such as iron can be gettered. That is, the substrate becomes a gettering site. For this reason, gettering sites are arranged over the entire surface of the solid-state imaging device 1, and a remarkable effect as gettering occurs. Along with this, the dark current of the solid-state imaging device becomes very small.
[Second Embodiment]
FIG. 11 is a cross-sectional view of the solid-state imaging device 80 according to the second embodiment, and corresponds to a cross-sectional view taken along the line BB ′ in FIG. Here, the configuration above the silicon oxide film is also omitted. Actually, a wiring electrode, a protective film, a color filter, and the like are disposed above the silicon oxide films 45 and 48.

  As in the first embodiment, the solid-state imaging device 80 has a P-type epitaxial layer 82 having a lower concentration on a P-type silicon substrate 81 having a high impurity concentration. That is, the first conductive type first semiconductor layer and the first conductive type second semiconductor layer form one substrate. In addition, the pixel having the photoelectric conversion unit 3 having the depletion prevention layer 43 and the charge storage layer 44 is the same as in the first embodiment.

  Therefore, in the solid-state imaging device 80, the concentration of the P-type silicon substrate 81 is higher than that of the P-type epitaxial layer 82 disposed thereon. Therefore, even if the charge (electrons) generated in the P-type epitaxial layer 82 drifts, it is guided not to the substrate side but to the surface side of the P-type epitaxial layer 82. The photoelectric conversion unit 3 is disposed on the surface side of the P-type epitaxial layer 82. Therefore, with the above configuration, less charge is absorbed on the substrate side, and a high light output is obtained.

If the concentration of the P-type epitaxial layer 82 is lower than that of the P-type silicon substrate 81, the above effect can be obtained. However, if the concentration of the P-type silicon substrate 41 is 1E18 / cm 3 or more and the concentration of the P-type epitaxial layer 82 is 1/10 or less of the concentration of the P-type silicon substrate 81, the potential difference caused by the two concentration differences. The absolute value of is sufficiently large and more preferable.
Here, the concentration of the P-type silicon substrate 81 is 1E18 / cm 3, and the concentration of the P-type epitaxial layer 82 is 1E15 / cm 3. However, the concentration is not limited to these, and the concentration of the P-type silicon substrate 81 may be in the range of 1E16 to 5E20 / cm 3, and the concentration of the P-type epitaxial layer 82 may be lower than that.

  In the solid-state imaging device 80, the thickness of the epitaxial layer disposed under the R photoelectric conversion unit 3R is different from the thickness of the epitaxial layer disposed under the G and B photoelectric conversion units 3G and 3B. . That is, under the photoelectric conversion unit 3R where the color filter corresponding to the longest wavelength color is arranged, the P-type epitaxial layer is thicker than under the photoelectric conversion units 3G and 3B where other color filters are arranged. Layers are placed. For this reason, it becomes difficult for the electric charge 84 generated by the light 83 incident from the photoelectric conversion unit 3R to drift toward the adjacent photoelectric conversion unit 3G. This will be described below.

  Since the light 83 incident from the photoelectric conversion unit 3R has a long wavelength, electric charges (electrons) 84 are generated in the deep portion of the P-type epitaxial layer 82. The charge 84 drifts in the P-type epitaxial layer 82 so as to move away from the P-type silicon substrate 81 because the P-type silicon substrate 81 has a high concentration.

  Among the charges generated by the incident light 83, the charge 84 drifting toward the adjacent photoelectric conversion unit 3G is directed to the step portion of the P-type silicon substrate 81 having a low potential (high concentration). This stepped portion becomes a barrier and blocks the drift of the electric charge 84. For this reason, even if the charge 84 drifts temporarily toward 3G, it drifts toward the charge storage part 44 of the photoelectric conversion part 3R having a higher potential. Therefore, crosstalk is reduced.

  Furthermore, not only is the crosstalk reduced, but it is also possible to prevent noise charges from entering each transistor in the same pixel. Therefore, each transistor in the same pixel can be held in a more stable state.

  The thickness of the P-type epitaxial layer 82 is 6 micrometers under the photoelectric conversion unit 3R (d4). However, it is not limited to this, and may be in the range of 5-12 micrometers. The thickness of the P-type epitaxial layer 82 under the other photoelectric conversion units 3G and 3B (d5) is 4 micrometers. However, it is not limited to this, and it is effective if it is thinner than d4. The difference between d4 and d5 is preferably 1 micrometer or more.

  The value of d5 is 4 micrometers as described above. For this reason, a P-type epitaxial layer 82 having a sufficient thickness is disposed under the photoelectric conversion units 3G and 3B. Therefore, a sufficient depletion layer in which incident light is photoelectrically converted can be obtained. Therefore, the amount of generated charge increases, and the light output value increases accordingly.

  Including such a step of the P-type epitaxial layer 82, the present solid-state imaging device is formed as follows. FIG. 12 is a cross-sectional view in each manufacturing process of the solid-state imaging device 80 according to the present embodiment, and corresponds to FIG. However, the alignment area | region arrange | positioned in the area | region different from the photoelectric conversion part 3 and another active area | region is also shown. FIG. 13 is a cross-sectional view in each subsequent manufacturing process. Hereinafter, the manufacturing process of the solid-state imaging device 80 will be described with reference to this drawing.

  First, a P-type silicon substrate 81 is prepared, a mask material is patterned so that the region 85 is opened, and the P-type silicon substrate 81 in the region 81 is dry-etched. This etching is carried out from the surface deeper than the etching of the region 86 described later. Here, the process is performed up to 6 micrometers from the surface. This area 85 is an area that will later become an alignment mark. The mask material may be anything as long as it is durable to silicon etching. Here, a resist is used. Further, wet etching may be used instead of dry etching.

  Next, the mask material is similarly patterned so that the region 86 is opened, and the P-type silicon substrate 81 is dry-etched. Here, etching is performed to a depth of 5 micrometers from the surface. FIG. 12A shows this state. Next, a P-type epitaxial layer 82 is formed using a known epitaxial technique. Here, the P-type epitaxial layer 82 is grown by 6 micrometers. This state is shown in FIG. Thus, a step is generated on the surface. The step of d6 is about 5 micrometers, and the step of d7 is about 6 micrometers.

  Next, according to a well-known CMP technique, the surface of the P-type epitaxial layer 82 having a step is polished and planarized. At this time, the polishing is stopped in a state where the level difference d6 is eliminated and the level difference d7 remains. This control can be performed by polishing time or optical end point detection. This state is shown in FIG.

Next, a step of forming an isolation region by the LOCOS oxide film 48 is performed. That is, first, a silicon nitride film (not shown) is formed by a CVD method and patterned so as to leave a portion that becomes an active region. At this time, the stepped portion 88 is aligned as an alignment mark so that the stepped portion 88 of the P-type epitaxial layer 82 is disposed below the predetermined isolation region 89. In this way, a thick P-type epitaxial layer is disposed under the photoelectric conversion unit 3R to be formed later, and a thin P-type epitaxial layer is disposed under the photoelectric conversion units 3G and 3B.
A thick LOCOS oxide film will be formed later in the opening, but an isolation diffusion 49 is provided in advance in the opening. The separation diffusion 49 finally has a depth of 0.8 micrometers and a concentration of 1E17 to 1E18 / cm 3. Next, a LOCOS oxide film having a thickness of 0.8 μm is formed in this opening by a thermal oxidation method.

Next, as in the first embodiment, a photoelectric conversion unit, other elements in the pixel, peripheral circuits, and the like are formed, and the solid-state imaging element 80 is completed.
Note that the circuit diagram, driving method, and the like of the solid-state image sensor 80 are the same as those of the solid-state image sensor 1 according to the first embodiment, and a description thereof will be omitted.

[Third Embodiment]
FIG. 14 is a cross-sectional view of a solid-state imaging device according to the third embodiment. The solid-state image sensor 90 of (a) is based on the solid-state image sensor 1 according to the first embodiment, and the solid-state image sensor 91 of (b) is based on the solid-state image sensor 80 according to the second embodiment. I have to. Also here, the configuration above the silicon oxide film is omitted.

First, the present embodiment will be described with reference to FIG. The solid-state imaging device 90 according to the present embodiment is different from the solid-state imaging device 1 according to the first embodiment in that a crosstalk prevention layer 92 is disposed. Since other configurations are the same as those of the first embodiment, description thereof is omitted.
The crosstalk prevention layer 92 is a diffusion layer made of P-type impurities, and the peak concentration and thickness of the crosstalk prevention layer 92 are the same as those of the barrier region layer 47. The crosstalk preventing layer 92 is disposed between the barrier region layer 47 and the surface of the P-type epitaxial layer 42. More specifically, the crosstalk prevention layer 92 is disposed below the isolation region 46 and between the barrier region layer 47. In the figure, the crosstalk prevention layer 92 is disposed in close contact with the barrier region layer 47. However, it is not always necessary to make it adhere. However, it is more preferable to arrange in this way, and it is more preferable to contact with the separation diffusion 49.

  By providing this crosstalk prevention layer 92, it is further reduced that charges generated by being incident from the photoelectric conversion unit 3R are captured by the adjacent photoelectric conversion units 3G and 3B and become crosstalk.

  Further, the solid-state imaging device 91 (FIG. 14B) according to the present embodiment is different from the solid-state imaging device 80 according to the second embodiment in that a crosstalk preventing layer 93 is disposed. In this case, the crosstalk preventing layer 93 is disposed between the surface of the P-type silicon substrate 81 and the P-type epitaxial layer 42. More specifically, the crosstalk prevention layer 92 is disposed below the isolation region 46 and between a portion protruding from the surface of the P-type silicon substrate 81. In the figure, the crosstalk prevention layer 92 is disposed in close contact with the P-type silicon substrate 81. However, it is not always necessary to make it adhere. However, it is more preferable to arrange in this way, and it is more preferable to contact with the separation diffusion 49.

  By providing this crosstalk prevention layer 93, it is further reduced that charges generated by being incident from the photoelectric conversion unit 3R are captured by the adjacent photoelectric conversion units 3G and 3B and become crosstalk.

  The solid-state imaging device of the present invention can be used in an electronic camera that captures still images and a digital video camera that captures moving images.

2 is a schematic plan view of 2 × 2 pixels of the solid-state imaging device according to the first embodiment of the present invention. FIG. It is sectional drawing in the B-B 'part of FIG.

3 is a drive timing chart of the solid-state imaging device according to the first embodiment.
(A) is a net impurity concentration distribution diagram of the EE ′ portion in FIG. 2, and (b) is a net impurity concentration distribution diagram of the FF ′ portion in FIG. 2. It is a graph which shows the spectral sensitivity characteristic of the solid-state image sensing device concerning a 1st embodiment. It is sectional drawing in the CC 'part of FIG. It is sectional drawing in the DD 'part of FIG. It is sectional drawing in each manufacturing process of the solid-state image sensor concerning 1st Embodiment. It is a circuit diagram of the solid-state image sensor concerning a 1st embodiment. 3 is a drive timing chart of the solid-state imaging device according to the first embodiment. It is a peripheral circuit fragmentary sectional view of the solid-state image sensing device concerning a 1st embodiment. It is sectional drawing of the solid-state image sensor which concerns on the 2nd Embodiment of this invention. It is sectional drawing in each manufacturing process of the solid-state image sensor concerning 2nd Embodiment. It is sectional drawing in each manufacturing process of the solid-state image sensor which concerns on 2nd Embodiment following FIG. It is sectional drawing of the solid-state image sensor which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 80, 90, 91 Solid-state image sensor 2 Pixel 3 Photoelectric conversion part 4 Transfer transistor 5 Pixel amplifier 6 Row selection transistor 7 Reset transistor 31, 32 Floating diffusion part 33 Transfer gate 41, 81 P-type silicon substrate 42, 82, P Type epitaxial layer 44 Charge storage portion 45 Thin silicon oxide film 46, 89 Isolation region 47 Barrier region layer 48 LOCOS oxide film 49 Separation diffusion 55, 56 Active region 61 N-type well 67 First P-type well 73 Second P-type Well 92, 93 Crosstalk prevention layer 64, 74, 84, 94 Upper barrier region layer

Claims (8)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer disposed on an upper surface of the first semiconductor layer and having a lower impurity concentration of the first conductivity type than the first semiconductor layer;
A barrier region layer of a second conductivity type disposed inside the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
An active region having at least a photoelectric conversion unit that generates and accumulates electric charge according to the amount of incident light, a color filter that is arranged corresponding to the photoelectric conversion unit and transmits incident light having a wavelength corresponding to a predetermined color, and the active A plurality of pixels including a separation region that electrically separates the regions are arranged in a two-dimensional manner on the surface of the second semiconductor layer,
The barrier region layer is provided under a photoelectric conversion unit other than the photoelectric conversion unit in which the color filter corresponding to the longest wavelength color is disposed,
The solid-state imaging device, wherein the barrier region layer disposed under the active region is disposed closer to the first semiconductor layer than the barrier region layer disposed under the isolation region. The photoelectric conversion unit has a charge storage layer of a second conductivity type,
The active region has a transfer gate portion that transfers charges accumulated in the charge accumulation layer, and is electrically connected to the charge accumulation layer by the operation of the transfer gate portion, and charges accumulated in the charge accumulation layer are transferred. A floating diffusion unit, a pixel amplifier unit that outputs a signal corresponding to the charge transferred to the floating diffusion unit, a reset transistor that resets the floating diffusion unit to a constant potential, and a selection transistor that selects a pixel. In addition,
The solid-state imaging device according to claim 1, wherein a silicon oxide film by selective oxidation is disposed in the isolation region. The active region includes a first active region where at least the photoelectric conversion unit is disposed;
A second active region in which the pixel amplifier unit and the selection transistor are disposed at least;
The solid-state imaging device according to claim 2, wherein the first active region and the second active region are electrically separated by a silicon oxide film formed by the selective oxidation. 4. The solid-state imaging according to claim 1, wherein the first conductivity type crosstalk prevention layer is disposed between the barrier region layer and the surface of the second semiconductor layer. 5. element. A circuit for outputting a signal from the pixel is further arranged, and the circuit includes:
A MOS transistor disposed in the second semiconductor layer;
A second conductivity type well region on the surface of the second semiconductor layer, and a MOS transistor disposed in the second conductivity type well region;
A first conductivity type well region electrically isolated from the second semiconductor layer, and a MOS transistor disposed in the first conductivity type well region;
5. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. The impurity concentration of the first semiconductor layer is 1E18 cm 3 or more, and the impurity concentration of the second semiconductor layer is 1/10 or less compared to the impurity concentration of the first semiconductor layer. The solid-state imaging device according to claim 5. A first semiconductor layer of a first conductivity type;
A second semiconductor layer disposed on the first semiconductor layer, wherein the impurity concentration of the first conductivity type is lower than that of the first semiconductor layer;
A pixel having at least a photoelectric conversion unit that generates and accumulates electric charge according to the amount of incident light, and a color filter that is arranged corresponding to the photoelectric conversion unit and transmits incident light having a wavelength corresponding to a predetermined color. Two or more two-dimensionally arranged on the surface of the semiconductor layer,
The second semiconductor layer having a thickness greater than that under the photoelectric conversion unit in which the other color filters are disposed is disposed under the photoelectric conversion unit in which the color filter corresponding to the longest wavelength is disposed. A solid-state imaging device. 8. The solid-state imaging device according to claim 7, wherein a first conductivity type crosstalk prevention layer is disposed at least partially between the surface of the second semiconductor layer and the first semiconductor layer.