JP2007188096A - Display drive control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display drive control device which is most suitable for display drive including display with a small amount of change and display with a large amount of change and can realize saving of chip area and reduction of power consumption and cost. <P>SOLUTION: In the display drive control device, memory capacity of an internal display memory (20) is set smaller than the amount of data of one display picture of a display panel (140) as the drive object, and the display data can be transferred with the system in which externally inputted display data is once stored in the display memory (20) and is then sent to a drive circuit (37) to output a drive signal and with the system in which the display data is sent directly to the drive circuit by way of no display memory (20) to output a drive signal. Moreover, both transfer methods can be executed on the time division basis. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique that is useful when applied to a display drive control device that drives a display device such as a liquid crystal panel, and is particularly useful when used for a display drive control device of a display panel of a small information terminal such as a mobile phone. Regarding technology.

  In recent years, as display devices for portable electronic devices such as mobile phones and PDAs (Personal Digital Assistances), a dot matrix type liquid crystal panel in which a plurality of display pixels are two-dimensionally arranged in a matrix is generally used. Inside the device, there is a liquid crystal display control device (liquid crystal controller) integrated into a semiconductor integrated circuit for controlling the display of the liquid crystal panel, a driver for driving the liquid crystal panel, or a liquid crystal display drive control device (liquid crystal controller driver IC) incorporating the driver. It is installed.

  A liquid crystal controller driver IC for displaying and driving a liquid crystal panel provided in such a portable electronic device is required to have a small chip area and low power consumption due to the nature of being mounted on a portable terminal. Conventionally, a liquid crystal controller driver used in a system having a small liquid crystal panel such as a cellular phone generally has a built-in display memory having a capacity larger than the amount of display data for one screen of the display panel, and the display data is temporarily displayed. After being stored in the memory, it is read out every horizontal line, converted into a gradation voltage and output to the display panel.

As an invention relating to a liquid crystal controller driver having a built-in display memory, there is an invention disclosed in Patent Document 1, for example.
Japanese Patent Laid-Open No. 9-281933

  By the way, in recent years, the display size of the display panel, the number of display colors, and the like are increasing more and more in the mobile phone. Therefore, if the liquid crystal controller driver is adapted to the liquid crystal panel with the same structure as before, the capacity of the built-in display memory becomes enormous, so the chip area and power consumption of the liquid crystal controller driver increase remarkably. Costs will also rise.

  Conventionally, a liquid crystal panel provided in a portable information terminal such as a PDA (Personal Digital Assistance) has a larger screen size than a liquid crystal panel of a cellular phone. It has been difficult to incorporate a large-capacity display memory that can be stored. For this reason, it is common to store image data in an external memory called an external frame buffer, and the microprocessor reads the image data from the frame buffer each time and transfers it to the liquid crystal controller driver.

  An object of the present invention is to provide a display drive control apparatus capable of appropriately driving a display panel having a relatively large display size and number of colors, and capable of reducing chip area, power consumption, and cost. There is to do.

  Another object of the present invention is to provide a display drive control device suitable for miniaturization of electronic equipment having a relatively large display panel such as a PDA.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, the capacity of the internal display memory is configured to be smaller than the data amount of one screen of the display panel to be driven, and the display data input from the outside is temporarily stored in the display memory and then output as the display data sending method. It is possible to both send the drive signal to the driver and output the drive signal, and send the drive signal directly to the output driver without going through the display memory. It is possible to do.

  According to such means, for example, a display memory is used when displaying an image with little change, and display data is transferred without going through the display memory when displaying an image with many changes such as a moving image. The display memory suitable for the display contents can be used properly. As a result, it is not necessary to increase the capacity of the display memory more than necessary, and the chip size of the liquid crystal controller driver IC incorporating the display memory can be reduced.

  In addition, the present invention configures a gradation voltage generation circuit so that display driving according to the number of bits can be performed even when the number of bits of data of one pixel is different, and a bit conversion circuit for display data is provided. Is. As a result, although the number of colors that can be displayed decreases as the number of bits of data of one pixel decreases, the display data for one screen is stored in the internal display memory that cannot store the display data for one screen in full color display. It becomes possible. At this time, the operation of the amplifier for unnecessary voltage among the buffer amplifiers constituting the gradation voltage generation circuit is stopped. Thereby, power consumption can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, even if the display size and the number of colors of the display panel are increased, the capacity of the display memory can be reduced as appropriate, thereby reducing the chip size and cost and the power consumption. There is an effect. This effect is particularly useful when employed in small portable electronic devices.

  In addition, when performing a display in which both a display with little change and a display that changes frequently such as a moving image are mixed, a display data transfer method through a display memory and a transfer method without a display memory are used. Since different types of methods can be used according to the display contents, there is an effect that wasteful transfer processing can be omitted and power consumption can be reduced. In addition, there is an effect that it is possible to realize transmissive display accompanying the above effect.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal controller driver which is an embodiment of a display drive control apparatus of the present invention.
The liquid crystal controller driver 100 of this embodiment is not particularly limited, but is formed on one semiconductor chip such as single crystal silicon by a known semiconductor manufacturing technique.

  In FIG. 1, reference numeral 10 denotes an input interface that is connected to devices such as a baseband processor 115 and an application processor 116 outside the chip and transmits / receives signals, and 20 is a display RAM such as an SRAM that stores display data.

  The input interface 10 includes a write data latch circuit 11 that latches display data input from the baseband processor 115 and the application processor 116, a command register 12 in which codes indicating various commands and display data destinations are set, and a display RAM 20 And an allocation register 13 in which a display position on the screen based on the display data is set.

  15 is a selector as a selection means for selecting a display data write destination, 21 is an X address counter for generating a horizontal data write address of the display RAM 20 in which the display data is stored, and 22 is for decoding the generated X address. X address decoder, 23 is a Y address counter for generating a data write address in the vertical direction of the display RAM 20, 24 is a display access control circuit for controlling the data read timing of the display RAM 20 based on the set value of the allocation register 13, and 25 is this display An address control circuit 26 that shifts or thins out the address value from the Y address counter 23 under the control of the access control circuit, and a Y address decoder that decodes the Y address. The display access control circuit 24 and the address control circuit 25 constitute display position control means.

  Further, 30 is a timing control circuit for synchronizing the display data input timing from the baseband processor 115 and the display data output timing from the display RAM 20, and 31 is the display data read from the display RAM 20 or directly from the input interface 10. A data selector for selecting any one of the display data sent, 32 is a latch address selector for selecting which address of the latch circuit 33 the data selected by the data selector 31 is latched, and 33 and 34 are liquid crystal panels 140 is a first latch circuit and a second latch circuit that hold display data for one horizontal line, 36 is a gradation voltage generation circuit that generates a gradation voltage selected according to the display data, and 35 is latched Gradation to select gradation voltage corresponding to display data択回 path, 37 is a driving circuit as an output driver for driving the vertical electrodes of the liquid crystal panel 140 (in the case of TFT liquid crystal panel called the source line or the data line). Among these, the data selector 31 and the latch address selector 32 constitute data supply means.

  The liquid crystal controller driver 100 of this embodiment sequentially generates and outputs data line drive signals for the liquid crystal panel 140 for each horizontal line based on display data input from the outside or display data read from the display RAM 20. In synchronism with this, a common driver (not shown) (also called a gate driver in the case of a TFT liquid crystal panel) repeatedly selects the common lines (gate lines) of the liquid crystal panel 140, for example, from the upper end toward the lower end. Thus, the image is displayed. The common driver may be formed on the same chip as the liquid crystal controller driver 100, or may be configured as a separate semiconductor integrated circuit.

  In the liquid crystal controller driver 100 of this embodiment, the display data used to drive the liquid crystal panel 140 is sent from the baseband processor 115. The display data is temporarily stored in the display RAM 20 and then stored in the latch circuit 33. The read operation and the transfer operation directly from the input interface 10 to the latch circuit 33 without using the display RAM 20 are possible.

  Whether the display data is written to the display RAM 20 or supplied to the latch circuit 33 is selected by switching the selector 15 based on the setting value of the command register 12. The command register 12 can be set by the baseband processor 115. Writing of display data such as a still image to the display RAM 20 is performed by the baseband processor 115, and transfer of display data such as a moving image requiring high-speed data transfer to the latch circuit 33 is performed by the application processor 116. can do.

FIG. 2 is a diagram for explaining the relationship between the capacity of the display memory of the liquid crystal controller driver of the embodiment and the display area of the liquid crystal panel.
The display RAM 20 has a data capacity that is smaller than the display data amount of one screen of the liquid crystal panel 140, that is, (total number of pixels × number of bits per pixel), for example, a capacity capable of storing ½ data of one screen. It is comprised so that it may have. Therefore, the display area associated with each address in the display RAM 20 is a partial area (hereinafter referred to as a fixed display area) 142 of the display area of the liquid crystal panel 140, as shown in FIG.

  However, the display area 142 associated with the display RAM 20 is not fixed, and various arrangements can be made according to the set value of the allocation register 13. The shape of the display area that can be associated can be variously modified as shown in FIG. 2B, such as a rectangular area, a horizontally long rectangle, and a vertically long rectangular area. Further, by making it possible to set a plurality of addresses in the allocation register 13, various settings can be made such as a single area or an area divided into a plurality of areas.

  Such association is based on the setting value of the allocation register 13, and the control in the Y address direction, such as reading of the Y address data of the display RAM 20 in accordance with the read timing of the display data of the horizontal line of the liquid crystal panel 140, At that time, this is realized by the control in the X address direction such as in which position of the latch circuit 33 the display data read from the display RAM 20 is stored. The former control is performed by the display access control circuit 24 and the address control circuit 25, and the latter control is performed by the display access control circuit 24, the latch address selector 32, and the data selector 31.

  In the present embodiment, the display based on the display data of the display RAM 20 (hereinafter referred to as fixed display) and the direct writing display not via the display RAM 20 can be mixedly operated. By utilizing this function, the image data transferred by direct writing can be displayed in the area around the fixed display area 142 of FIG.

  Next, the operation when the fixed display and the direct writing display are mixed will be described with reference to FIGS. In the present specification, the fixed display means not a display that is always fixed but a display based on display data in the display RAM 20 to the last.

  4A to 4D are explanatory diagrams of a display operation when a direct writing display is present in a part of the fixed display area 142. FIG. The fixed display area 142 that performs display based on the display data of the display RAM 20 can be enlarged to the entire liquid crystal panel 140 when the number of bits indicating one pixel is reduced as will be described later. FIG. 4 shows a case where the fixed display area 142 is the entire screen of the liquid crystal panel 140. The number of bits in a pixel is determined by providing a bit number designation field in the control register 12 or an empty field of an existing register, and the baseband processor 115 or the like sets the register in advance. It can be configured so that it can be specified by setting.

  4A and 4B show how still image data from the baseband processor 115 is written to the display RAM 20 in the driver, and the data is read from the display RAM 20 and displayed on the liquid crystal panel 140. FIG. Yes. 4C and 4D, either the direct write data (moving image data) transferred from the application processor 116 or the image data already written in the display RAM 20 is selected by the selector 31 and the liquid crystal panel. 140 shows a state of being displayed.

  When such a display is performed, an enable signal EN (H) indicating a display effective period in the horizontal direction (line direction) and an enable signal EN (V) indicating a display effective period in the vertical direction from the application processor 116 to the timing control circuit 30. And the timing control circuit 30 switches the data selector 31 to the selector 15 side via the display access control circuit 24 only while these enable signals indicate a valid level (high level), and the latch circuit 33 On the other hand, a control signal permitting data capture is output to the latch address selector circuit 32, and the latch circuit 33 is controlled to latch the direct display data from the application processor 116 only during the permitted period. Display data read from the RAM 20 is It is controlled to switch.

  On the other hand, FIG. 5 and FIG. 6 show the display data transfer timing when the direct writing display exists outside the fixed display area 142 as shown in FIG. Among these, FIG. 5 is a time chart showing the latch operation of display data to the latch circuits 33 and 34 when only direct writing is displayed as in the range of FIG. 3A, and FIG. ) Is a time chart showing a display data latching operation to the latch circuits 33 and 34 when the fixed display and the direct write display are mixed as in the range of). 5 and 6, latch clock φ1 is a clock signal synchronized with a dot clock DOTCLK supplied from the outside, and latch clock φ2 is a clock signal synchronized with a horizontal synchronization signal HSYNC supplied from the outside.

  As shown in FIG. 5, when only direct writing is displayed, display data for one line of the display panel is sequentially taken into the first latch circuit 33 in synchronization with the latch clock φ1 during one horizontal period. The display data for one horizontal line stored in the latch circuit 33 is moved to the second latch circuit 34 at a time in synchronization with one latch clock φ2 every horizontal period. Then, the display data latched by the second latch circuit 34 is transferred to the drive circuit 37, and a segment drive signal is generated and output. The latch clocks φ 1 and φ 2 are supplied from the timing control circuit 30.

  When only direct writing is displayed in FIG. 5, the selector 15 transmits display data from the outside to the selector 31 side based on the set value of the control register 12, and the data selector 31 displays from the outside. Switching to the data selection side is performed, and the display data is sequentially written into the latch circuit 33 via the selectors 15 and 31.

  On the other hand, as shown in FIG. 6, in the period in which the direct writing display and the fixed display are mixed, first, display data is transferred from the outside in synchronism with the display timing as in the case of FIG. As the data is written and the fixed display position on one horizontal line set in the allocation register 13 is reached, the selection path of the data selector 31 is switched under the control of the display access control circuit 24 and the display of the internal RAM 20 is performed. Data is latched at an address corresponding to the fixed display position of the latch circuit 33.

  The display data can be written into the internal RAM 20 during a period when the direct writing display is not performed, or even during a period when the direct writing display is performed during the vertical blanking period.

  As described above, according to the liquid crystal controller driver 100 of this embodiment, it is possible to perform display driving in which both fixed display using display data of the display RAM 20 and direct writing display not via the display RAM 20 are mixed. Therefore, even if the screen size of the liquid crystal panel 140, that is, the amount of display data for one screen increases, the capacity of the display RAM 20 can be appropriately reduced.

FIG. 8 shows another example of the correspondence between the display data in the display RAM 20 and the display screen of the liquid crystal panel in the liquid crystal controller driver 100 of the embodiment.
The method of associating the display RAM 20 with the screen is not only the method of associating a part of the screen as shown in FIG. 2, but also by reducing the number of gradations of one pixel of the liquid crystal panel 140. It is also possible to associate the display data of the RAM 20 with all the pixels of the liquid crystal panel. For example, as shown in FIG. 7, the liquid crystal panel 140 can display 16 (4 bits) gradation per pixel. When the 16 gradation display is set to the standard mode, 4 (2 bits per pixel) is displayed. ) By providing a low gradation mode for displaying in gradation, even when the capacity of the display RAM 20 is half of the display data amount for one screen in the standard mode, the display RAM 20 is stored by switching to the low gradation mode. The displayed data can be associated with all the pixels of the liquid crystal panel 140.

  However, when such a low gradation mode is provided, when writing the display data read from the display RAM 20 to the latch circuit 33, the 4-bit read data is divided into upper 2 bits and lower 2 bits. For example, a configuration is required in which the bits are written to the upper 2 bits of two adjacent 4-bit latches each masked with the lower 2 bits to switch from writing 4-bit data to writing 2-bit data.

  FIG. 7 shows a case where one pixel is a standard of 4 bits. Similarly, the embodiment capable of driving a liquid crystal panel capable of gradation display based on display data in which one pixel is composed of 18 bits. In the liquid crystal controller driver of the example, the display area of the display panel 140 and the display in the display RAM 20 are displayed as shown in (1) to (5) of FIG. You can change the relationship with the data.

  8 (1) is a standard mode in which one pixel is represented by 18 bits, FIG. 8 (2) is a quasi-high gradation mode in which one pixel is represented by 16 bits, and FIG. 8 (3) is one pixel is 12 bits. 8 (4) shows an intermediate gradation mode in which one pixel is represented by 8 bits, and FIG. 8 (5) shows a low gradation mode in which one pixel is represented by 3 bits. By selecting the low gradation mode of FIG. 8 (5), the image data for two screens can be stored in the display RAM 20, as shown in FIG. 8 (6). From FIG. 8, it can be seen that the corresponding display area expands as the number of colors per pixel decreases.

  FIG. 9 shows a configuration of the display RAM 20 having a capacity capable of storing half of the display data of one screen of the liquid crystal panel when full color display is performed, and the latch circuit 130 (in FIG. 1, in the display RAM 20). And a method for reading data to the latch circuit 130 when the number of bits of image data per pixel is switched.

  In FIG. 9, the RAM configuration in accordance with the vertical period is, for example, 320 pixels in the vertical direction and 240 dots in the horizontal direction, and 16 bits per pixel, that is, about 65,000 colors can be displayed. This means that the number of memory rows of the display RAM 20 for storing data to be displayed on a liquid crystal panel is 320 in accordance with the number of pixels in the vertical direction of the liquid crystal panel. Similarly, the RAM configuration in accordance with the horizontal period means that the number of memory columns of the display RAM 20 for storing data to be displayed on the liquid crystal panel of 320 × 240 dots in the same manner is 240 in accordance with the number of pixels in the horizontal direction of the liquid crystal panel. Means that

  On the other hand, the latch circuit 130 that holds the data read from the display RAM 20 is assumed to be 240 × 16 bits that can hold the image data of all the pixels in the horizontal direction of the liquid crystal panel in any case. In this case, in the RAM configuration adapted to the vertical period, the display data read from the display RAM 20 stores 120 pixels of odd rows in one half of the latch circuit 130 as shown in FIG. 120 pixels may be stored in the other half of the latch circuit, and output to the data selector 31 when 240 pixels are aligned.

  Further, in the RAM configuration adapted to the horizontal period, the display data read from the display RAM 20 is stored in the latch circuit 130 for each row (240 pixels) as shown in FIG. 9B and is output to the data selector 31. What should I do?

  Using the liquid crystal controller driver capable of driving a liquid crystal panel capable of displaying 65,000 colors with vertical and horizontal 320 x 240 dots as described above, color display of 256 colors (8-bit gradation) with vertical and horizontal 320 x 240 dots In the case of driving a liquid crystal panel capable of display, in a RAM configuration adapted to the vertical period, each row of the display RAM 20 displays 240 pixels × 8 bits for one line of the liquid crystal panel (however, external write data is in units of 16 bits) Data is stored. Therefore, in this case, as shown in FIG. 9C, display data for one row may be read from the display RAM 20 and held in the latch circuit at a time before being output to the data selector 31.

  Further, in the RAM configuration adapted to the horizontal period, display data of 480 pixels × 8 bits for two lines of the liquid crystal panel is stored in each row of the display RAM 20. Therefore, in this case, as shown in FIG. 9D, half of the display data (240 pixels) for one row read from the display RAM 20 is stored in the first latch circuit, and then transferred to the second latch. Then, the remaining half of the data may be read out to the first latch circuit and then output to the data selector 31 sequentially.

  As described above, by determining the configuration of the display RAM 20 and the bit length of the latch circuit in accordance with the size of the liquid crystal panel and the number of bits per pixel necessary for gradation display, the optimum so as to minimize the chip cost. Different layouts can be selected.

Next, a configuration example of the gradation voltage generation circuit 36 in the liquid crystal controller driver of the above embodiment will be described with reference to FIG.
The gradation voltage generation circuit 36 of this embodiment performs impedance conversion on a ladder resistor 361 connected between the power supply voltage terminals Vcc and Vss and an arbitrary voltage divided by the ladder resistor 361 as shown in FIG. The plurality of buffer amplifiers BFF0 to BFF63 are configured to output and output gradation voltages V63 to V0 having a maximum of 64 levels. The ladder resistor 361 has a resistance ratio set so as to generate gradation voltages V63 to V0 that correct the γ characteristics of the liquid crystal panel to be used, or a gradation voltage necessary to correct the γ characteristics. The nodes to which the input terminals of the buffer amplifiers BFF0 to BFF63 are connected are determined so that they can be taken out.

  Further, the gradation voltage generation circuit 36 of this embodiment is provided with a decoder 362 for decoding the number of pixel bits set in the bit number designation register in the control register 12, and each of the buffer amplifiers BFF0 to BFF63. Power switches SW0 to SW63 are provided, and the output of the decoder 362 is configured to be able to switch one of the buffer amplifiers BFF0 to BFF63 that is activated according to the number of designated pixel bits. That is, for example, when the designated pixel bit number is 6 bits, all amplifiers are activated, and when the designated pixel bit number is changed from 6 bits to 5 bits, 32 of the 64 buffer amplifiers BFF0 to BFF63 are half. When the number of designated pixel bits is 4 bits, 3/4 of the 64 buffer amplifiers BFF0 to BFF63 can be turned off. Thereby, the power consumption of the gradation voltage generation circuit 36 can be significantly reduced.

  Further, the gradation voltage generation circuit 36 enables every other buffer amplifier BFF0 to BFF63 when the number of pixel bits is reduced to 5 bits, for example, and three buffer amplifiers when the number of pixel bits is 4 bits. The output voltage is thinned out by enabling every other, and the maximum gradation voltage V63 and the minimum gradation voltage V0 are output even when the number of pixel bits is reduced. By outputting V63 and V0 in this way, there is no possibility that the contrast is lowered when either white or black is used as the background color. However, in this case, the thinning interval is slightly wider than the others at approximately the middle between the maximum gradation voltage V63 and the minimum gradation voltage V0.

  On the other hand, the gradation selection circuit 35 selects selectors 351, 352 for selecting any one of the gradation voltages V63 to V0 from the gradation voltage generation circuit 36 based on image data having a maximum of 6 bits corresponding to RGB. 353. Further, in this embodiment, the pixel data is generated in accordance with the reduction of the gradation voltage generated as described above by exchanging the bit arrangement of the pixel data between the second latch circuit 34 and the gradation selection circuit 35. Bit conversion circuits 391, 392, and 393 are provided to prevent the missing voltage from being selected.

  The bit conversion circuits 391 to 393 transmit the data of the latch circuit 34 as they are when one pixel is composed of 6 bits for each of RGB, and each pixel has 5 bits for each of RGB (for example, B5, B4, B3, B2). , B1), the most significant bit B5 is inserted into the least significant bit B0 which is invalid and converted to data B5, B4, B3, B2, B1, B5.

  As a result, the maximum voltage V63 and the minimum voltage V0 can be output and the output of the buffer amplifier that has been turned off can be prevented from being selected. In this embodiment, by outputting the maximum gradation voltage V63 and the minimum gradation voltage V0, the thinning interval is slightly wider between V63 and V0 than the others, but the intermediate gradation between V63 and V0. The bit conversion circuit 39 may be configured such that the regulated voltage is not thinned out and this voltage is selected.

  In this embodiment, the bit replacement method in the case where one pixel is composed of 5 bits for each of RGB has been described. However, the same idea can be applied to the case where one pixel is composed of 4 bits or 3 bits for each of RGB. Thus, it is preferable to select a voltage at a predetermined interval from the gradation voltages V63 to V0 and to replace the RGB code bits so that the maximum gradation voltage V63 and the minimum gradation voltage V0 are output.

  Further, a selector for selecting a voltage obtained by dividing the ladder resistor 361 between the ladder resistor 361 and the buffer amplifiers BFF0 to BFF63, and a register for setting the γ characteristic of the liquid crystal panel are provided in the control register 12. By switching each selector according to the set value of the register and outputting a voltage at a desired level, it is possible to output a gradation voltage that corrects the γ characteristic according to the liquid crystal panel to be used. May be.

  Furthermore, in the embodiment, the gradation voltage generation circuit 36 generates 64 gradation voltages V63 to V0, but instead of generating 64 gradation voltages, 32 gradation voltages V31 to V0 are generated. Using the generated 32 levels of gradation voltages V31 to V0, in the gradation selection circuit 35, any two adjacent voltages (for example, V21 and V22) are V21 and V21 in the first frame of two frames, for example. By alternately displaying V22 in the frame, an intermediate voltage (V21 + V22) / 2 is effectively applied to the liquid crystal, so that it is possible to perform gradation display in 64 stages.

Next, a system to which the liquid crystal controller driver of the above embodiment is applied will be described. FIG. 10 shows an example of a circuit configuration of a mobile phone system that employs the liquid crystal controller driver of the above embodiment.
In the figure, 100 is the above-described liquid crystal controller driver, 110 is a high-frequency RF unit that performs transmission / reception of radio signals and conversion between radio signals and baseband signals, and 115 is a signal processing and overall system related to audio signals and transmission / reception signals. A baseband processor as a system control device for controlling the image, etc. 116 is an application processor having a multimedia processing function such as moving image processing according to the MPEG system, a resolution adjustment function, a Java high-speed processing function, etc. 117 is a ring tone output And a voice processing unit for signal processing of received voice, 118 is a non-volatile memory for storing user setting data such as address book data, and 119 is used as a frame buffer for storing still image data for one screen of the liquid crystal panel. Display data buffer memory during video playback In SRAM, which is used to (Static Random Access Memory), these circuits are mounted on the system board 150 made of a printed wiring board.

  The baseband processor 115 is a DSP (Digital Signal Processor) 121 that identifies received data addressed to itself and extracts audio data, or converts transmission data into a format for wireless transmission, system control based on user operation details, It includes an MCU (microcontroller unit) 120 that performs data processing and display control of transmission / reception data. The application processor 116 is an LSI that may be installed in accordance with the performance of the entire system. The application processor 116 includes a codec circuit 123 that performs encoding / decoding processing of MPEG (Moving Picture Experts Group) data, a Java language processing circuit, and the like. Become. A system in which this is omitted is also possible. Reference numeral 140 denotes a color liquid crystal panel driven by the liquid crystal controller driver 100. In a system using the liquid crystal controller driver of the above embodiment as the liquid crystal controller driver 100, the display data amount of one screen as the liquid crystal panel 140 is built in the liquid crystal controller driver. A display having a size larger than the capacity of the display RAM 20 can be used for full screen display.

  The liquid crystal controller driver 100, the high frequency RF unit 110, the baseband processor 115, the application processor 116, the memory 118, and the SRAM 119 are connected to each other via a system bus S-BUS formed on the board so that data can be transferred. In the system using the liquid crystal controller driver of the above-described embodiment, the baseband processor 115 writes image data into the display RAM 20 in the liquid crystal controller driver 100 for the image whose display does not change so much, so that the memory is always stored as before. It is possible to display the image data without reading the image data from 119 and transferring it to the liquid crystal controller driver 100, thereby reducing the burden on the baseband processor 115.

  In addition, in this cellular phone system using the liquid crystal controller driver of the above embodiment, the received video data is decoded by the decoder circuit 123 in addition to the fixed display of the telephone number and name of the other party on the liquid crystal panel 140, and the SRAM 119 is temporarily used. Then, the baseband processor 115 sends the decoded data to the liquid crystal controller driver 100 in accordance with the display timing, so that the moving image can be reproduced by direct writing display without using the built-in display RAM 20.

FIG. 11 shows an example of an image displayed on the liquid crystal panel 140 in the mobile phone system of FIG.
According to the mobile phone system, as shown in FIG. 11A, the moving image display V1 based on the direct writing display and the fixed displays V2 and V3 based on the display data of the display RAM 20 can be mixed and displayed. I can do it. Further, the positions of the fixed displays V2 and V3 can be changed to appropriate positions as shown in FIG. 11B by the set value of the allocation register 13 by the baseband processor 115.

  As described above, the fixed display method based on the display data of the display RAM 20 is used for a display with little change such as the display of the power mark, the antenna mark, and the date and time information. As a result, it is possible to omit the process of repeatedly transferring the same display data to the liquid crystal controller driver for display data with little change, and to avoid the detour to the display RAM 20 for display data that changes frequently. Appropriate processing methods can be selectively used, and power consumption can be reduced by processing suitable for the display contents.

  As described above, the method of selecting and displaying the data in the built-in RAM and the direct data from the outside has been described. FIG. 12 shows a transparent display method as an application example using this method. The transparent display function refers to a function for displaying a specified color on a panel or preventing it from being displayed. As a configuration, a register (transmission register 165) that holds color information, a latch circuit (write data latch 11) that holds data input from the outside, and a circuit that compares the output of the register and the output of the latch circuit ( Compare circuit 166). The output of the compare circuit 166 controls the type of color displayed on the panel. The color information is divided into red R, green G, and blue B components and held as several bits of data.

  FIG. 12A shows a state in which the data of the write data latch 11 is directly output to the data selector 31 without passing through the compare circuit 166. FIG. 12B shows a mode in which the data of the write data latch 11 passes through the compare circuit 166 and is not output (transmitted) by the transmission control circuit 167 by comparison with the register 165 holding the color information. Indicates the state. The modes shown in FIGS. 12A and 12B may be switched by a control signal from outside the chip, or may be switched by the value of the color information register.

  In FIG. 12A (in a mode in which transparent display is not performed), the output of the write data latch 11 is directly output to the data selector 31 without passing through the compare circuit 166, and is overlapped with the output data of the internal RAM 20. The output timing of the data selector 31 displayed on the panel 140 is controlled by the access control circuit 24. In FIG. 12B, an arbitrary display color (white) that is not output is set in the transmission register 165. The output of the transmission register 165 and the output of the write data latch 11 are input to the compare circuit 166.

  The input output value is compared by the compare circuit 166, and a match / mismatch result is output to the transmission control circuit 167. The transmission control circuit 167 generates a signal indicating that a specified color (for example, white) is transmitted (not output), and sends the result to the access control circuit 24. The output timing of the data selector 31 displayed on the panel 140 is controlled by the access control circuit 24 and is superposed on the data read from the internal RAM 20 by the data selector 31. As a result, the color information input to the register 165 is transmitted on the panel, and the background blue data appears on the panel. Instead of the transmissive register 165, information on the color that is not desired to be transmitted may be set in the non-transparent register, and only a color that matches the output of the write data latch 11 may be output. A configuration in which the number of objects to be compared is reduced is advantageous.

  By the above method, a specific figure (circle in the figure) in the rectangular area can be cut out and displayed on the panel 140 with the directly written data as shown in FIG.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
For example, in the embodiment, the display RAM (display memory) 20 has been described as storing display data with little change such as mark display and date / time display. However, for example, display data of a portion in which the display memory is filled with the same color as the background color ( It is also possible to store only the color data), display the background using the data in the display memory, and display the other parts by direct writing without using the display memory.

  Further, the selector 15 is exemplified as means for selecting whether the display data is sent from the input interface to the display memory or to the output driver without passing through the display memory. For example, the write command on / off of the display RAM 20 and the data selector are selected. The configuration can be variously modified such that the function as the selection means can be realized by switching 31. Alternatively, two input ports for display data may be provided in the input interface, one connected to the display memory side and the other connected to the output driver side without going through the display memory.

  In the above description, the liquid crystal controller driver of the cellular phone system, which is a field of use based on the invention made by the present inventor, has been described, but the present invention is not limited to this, and a small portable electronic device. It can be widely used in a display drive control device for driving the display panel.

It is a block diagram which shows schematic structure of the liquid crystal controller driver of the Example of this invention. It is a figure explaining the relationship between the capacity | capacitance of the display memory of the liquid crystal controller driver of an Example, and the display area of a liquid crystal panel. It is a figure which shows the example of a display mixed with the fixed display based on the data of a display memory, and the direct writing display which does not go through via a display memory. It is a figure which shows the display operation when the fixed display based on the data of the display memory and the direct writing display not via the display memory are mixed. 4 is a time chart for explaining a display data transfer operation in the horizontal period (A) of FIG. 3. 4 is a time chart for explaining a display data transfer operation in the horizontal period (B) of FIG. 3. It is a figure explaining the other usage example of a display memory. It is a figure which shows the specific usage example of the display memory at the time of changing the gradation number of 1 pixel. It is a figure explaining each example at the time of changing the array structure of a display memory, and the gradation number of a pixel about the transfer method of the display data from a display memory to a 1st latch circuit. It is a block diagram which shows the structural example of the mobile telephone system which employ | adopted the liquid crystal controller driver of the Example. It is an image figure which shows the example of a display in the mobile telephone system of FIG. It is a figure explaining the main structure of the liquid crystal controller driver which enables permeation | transmission control, and its operation example. It is a block diagram which shows the structural example of a gradation voltage generation circuit.

Explanation of symbols

10 Input Interface 13 Allocation Register 15 Selector 20 Display RAM (Display Memory)
23 Y address counter 24 Display access control circuit 25 Address control circuit 26 Y address decoder 30 Timing control circuit 31 Data selector 32 Latch address selector 33 First latch circuit 34 Second latch circuit 35 Gradation voltage selection circuit 36 Gradation voltage generation circuit 37 Drive circuit 110 RF unit for high frequency 115 BBP (baseband processor)
116 APP (Application Processor)
117 Audio processing unit 120 MCU (micro controller unit)
140 LCD panel BFF0 to BFF63 Buffer amplifier

Claims (4)

A display drive control device comprising a display memory for storing display image data, sequentially reading display image data from the display memory to generate and output a drive signal for the display device,
In the subsequent stage of the display memory, data selection means capable of selecting and transmitting either image data read from the display memory or image data input from the outside,
A grayscale voltage generation circuit for generating a plurality of grayscale voltages necessary for generating a display drive signal, comprising a resistance voltage divider circuit and a plurality of buffer amplifiers that impedance-convert and output the voltage divided by the resistance voltage divider circuit When,
A register for setting the number of pixel bits of the image data,
The display drive control device according to claim 1, wherein the gradation voltage generation circuit is configured to be able to transition some of the plurality of buffer amplifiers to an inactive state according to the number of bits of the image data.   2. The display drive control device according to claim 1, wherein the gradation voltage generation circuit deactivates a predetermined one of the plurality of buffer amplifiers in accordance with a set value of the register.   The gradation voltage generation circuit outputs at least the maximum and minimum of the plurality of gradation voltages when the predetermined one of the plurality of buffer amplifiers is inactivated according to the set value of the register. The display drive control device according to claim 2, wherein: A gradation selection circuit for selecting a voltage according to the image data selected by the data selection means from among the voltages generated by the gradation voltage generation circuit;
A bit conversion circuit for converting the bit of the image data and supplying the converted bit to the gradation selection circuit corresponding to the buffer amplifier to be deactivated in the gradation voltage generation circuit. The display drive control device according to claim 1.

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