JP2007123851A - Floating body germanium photo transistor with photo absorption threshold bias region - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve floating body effect of a germanium photo transistor. <P>SOLUTION: This manufacturing method for a floating body germanium photo transistor with a photo absorption threshold bias region includes: a step of forming an epitaxial Ge layer on an insulator layer, selectively formed on a first surface of a P-type silicon substrate; a step of forming a channel region in the Ge layer; a step for forming a gate dielectric, a gate electrode and a gate spacer; a step of forming source/drain (S/D) regions in the Ge layer; and a step of forming a photo absorption threshold bias region adjacent the channel region in the Ge layer. In one embodiment, a second S/D region is separated from the channel by an offset region, and the photo absorption threshold bias region is the offset region in the Ge layer, after light P-doping. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

Detailed Description of the Invention

[Related patent applications]
The present invention is based on the pending US patent application no. This is a partial continuation application (CIP application) of 11 / 174,035 (filed July 1, 2005).

  The present invention claims priority under the above parent application under 35 USC 35, 120, and explicitly incorporates the parent application as a reference.

[Background Technology]
(1. Technical field)
The present invention relates generally to integrated circuit (IC) fabrication, and more particularly to a floating body germanium (Ge) phototransistor having a photo absorption threshold bias region. phototransistor) and related manufacturing methods.

(2. Explanation of related technology)
FIG. 1 is a cross-sectional image of an interface between Ge and Si ₃ N ₄ by a transmission electron microscope (XTEM). The Ge film is regrown by liquid phase epitaxy. US patent application Ser. No. 1993, filed concurrently with the invention by Lee et al. (Title of Invention; Epitaxial Growth Method of Germanium Photodetector for CMOS Image Processing). 11 / 069,424 (filed on Feb. 28, 2005) discloses a method for growing a single crystal Ge film by liquid layer epitaxy as well as a method for manufacturing a PIN photodetector for detecting infrared photons. However, it is noted that the interface between the single crystal Ge and the bottom dielectric layer (Si ₃ N ₄ ) is not perfect as the TEM image shows. This interface can cause current leakage in the diode. Also, this interface is likely to occur in a GePIN diode using a complete Ge film, and the bottom interface degrades electrical performance.

  Thicker germanium films are suitable for use in transistor fabrication. This is because the drain depletion region does not contact the high defect region of germanium that contacts the insulator interface. To address the floating body problem, the source electrode can be extended through the entire thickness of the germanium thin film to the silicon substrate. The source can further extend through the dense defect germanium and to the interface of the insulator. However, with this structure, current leakage at the source junction is relatively high. As a result, the floating substrate effect of the transistor is reduced.

[Disclosure of the Invention]
The present invention provides an improvement in the floating body effect of a Ge phototransistor and, in one form, provides an offset drain that increases the efficiency of the phototransistor. The germanium thin film in the contact region between germanium and silicon nitride is moderately doped, and the shallow source junction is used to minimize current leakage at the source junction. In another form, the drain diffusion region is offset from the gate to provide additional germanium capacitance for light absorption. In devices with very short channels, the offset drain is important because the effective total light absorption area is very small.

  Accordingly, a method of manufacturing a floating body Ge phototransistor having a light absorption threshold bias region is provided. The method includes a step of preparing a P-type silicon (Si) substrate, a step of selectively forming an insulator layer on the first surface of the silicon substrate, and a step of forming an epitaxial Ge layer on the insulator layer. Forming a channel region in the Ge layer; forming a gate dielectric, a gate electrode and a gate spacer on the channel region; and forming a source / drain (S / D) region in the Ge layer. And a step of forming a light absorption threshold bias region adjacent to the channel region in the Ge layer.

  In one aspect, the step of selectively forming the insulator layer on the first surface of the Si substrate includes depositing a silicon nitride having an upper surface on the Si substrate, and after forming the epitaxial Ge layer. Exposing the second surface of the Si substrate by selectively etching the material that seals the Ge layer, the Ge layer, and silicon nitride. The method further includes depositing silicon oxide on the second surface of the Si substrate and chemically and mechanically polishing (CMP) the silicon oxide to the level of the material that seals the Ge layer. And a step of removing a material for sealing the Ge layer by etching.

  In another form, the method further includes performing boron (boron) ion implantation and forming a P-type region in the Ge layer directly over the top surface of the silicon nitride.

  The first S / D region is generally formed on the second surface of the Si substrate and has a first length. The second S / D region has a second length that is longer than the first length. The light absorption threshold bias region is below the second S / D region. In other words, the second S / D region is separated from the channel by being offset. The light absorption threshold bias region is formed by a P-type offset region in the Ge layer.

  A detailed description of the above-described method and a floating body Ge transistor having a light absorption threshold bias region is given below.

[Detailed explanation]
FIG. 2 is a partial cross-sectional view of a floating body germanium (Ge) phototransistor having a light absorption threshold bias region. The phototransistor 200 includes a P-type silicon (Si) substrate 202 and an insulator layer 204 on a first surface 206 of the Si substrate 202. Epitaxial Ge layer 208 is on insulator layer 204. Since the phototransistor 200 does not require an LDD region, the LDD region is not shown in the drawing. In other embodiments, the phototransistor 200 may be fabricated with any LDD region (not shown). For example, if the peripheral circuit configuration transistor (not shown) has a structure including an LDD region, the phototransistor 200 may include the LDD region.

  The channel region 210 is formed in the Ge layer 208. Gate dielectric 212, gate electrode 214, and gate spacer 216 are on channel region 210. A first source / drain (S / D) region 218 and a second S / D region 220 are also formed in the Ge layer 208. A light absorbing threshold bias region 222 is also shown near the channel region 210 in the Ge layer 208.

  In one embodiment, the insulator layer 204 is a silicon nitride layer having a top surface 226. The Si substrate 202 includes a second surface 228 that is adjacent to the first surface 206. The silicon oxide 230 is on the second surface 228 of the silicon substrate. A P-type region 232 is also shown immediately above the silicon nitride top surface 226 in the Ge layer 208.

  The first S / D region 218 is substantially on the second surface 228 of the silicon substrate and has a first length 234. More specifically, the second surface 228 of the substrate is below the region of silicon oxide adjacent to the “outer” edge of the first S / D region 218. The “outer” end is the end of the S / D region that is farthest from the channel region 210. The second S / D region 220 has a second length 236 that is longer than the first length 234. The light absorption threshold bias region 222 in the Ge layer 208 is below the second S / D region 220. A metal interlayer interconnect 238 is also shown. In other words, the second S / D region 220 has an extended region 237 (between the dotted line and the channel). The extended area 237 makes the second S / D area 220 longer than the first S / D area 218. In this embodiment, the light absorption threshold bias region 222 is below the extended region 237.

  FIG. 3 is a partial cross-sectional view of a floating body Ge phototransistor having a light absorption threshold bias region and an offset S / D region. Similar to FIG. 2, the first S / D region 218 is substantially on the second surface 228 of the Si substrate. More specifically, the second surface 228 of the substrate is below the region of silicon oxide adjacent to the “outer” edge of the first S / D region 218. The “outer end” is the end of the S / D region that is farthest from the channel region 210.

  Further, as shown in FIG. 3, the end portion 300 on the channel side of the second S / D region 220 or the end portion 300 closest to the channel is not in direct contact with the channel region 210 as in the prior art. . More precisely, the channel side end 300 is offset from the channel region 210 by a distance 302. The light absorption threshold bias region 222 in the Ge layer 208 includes a P-type offset region 222 that separates the second S / D region 220 from the channel region 210. More specifically, the P-type offset region 222 separates the end portion 300 of the second S / D region from the channel region 210.

  The maximum offset distance 302 is d or less calculated by the following equation.

ε is the dielectric constant of germanium, N is the channel doping concentration, and V _D and V _DSAT are the drain bias voltage and drain saturation voltage at the operating gate bias voltage, respectively. The above equation is an equation assuming that the second S / D region 220 is a drain.

  With reference to either FIG. 2 or FIG. 3, the insulator layer 204 on the Si substrate 202 has a thickness 240 in the range of approximately 10-500 nm. The epitaxial Ge layer 208 has a thickness 242 in the range of about 300 to 1000 nanometers (nm).

  In one embodiment, the gate dielectric 212 and gate spacer 216 are formed from a wide bandgap material. The use of a wide bandgap material allows light (IR) penetration into the Ge layer 206 from the “up” direction. In other words, only some of these regions are made from a wide bandgap material. In another embodiment, using a narrow bandgap material and / or a metal gate, IR light penetrates the Ge layer from the side or from below.

For example, gate dielectric _{212, SiO 2, GeO 2, Al} 2 O 3, HfO 2, ZrO 2, TiO 2, Ta 2 O 5 or a combination of these materials. The gate electrode 214 may be polycrystalline Ge, polycrystalline SiGe, or polycrystalline silicon (polysilicon). The gate spacer 216 may be SiO ₂ or Si ₃ N ₄ . However, this is not a complete list of materials. Further, as described above, a material having a wide forbidden bandwidth may not be used. As used herein, a wide bandgap material has a bandgap greater than about 1.1 eV and facilitates the penetration of light having a wavelength between 1 and 1.6 micrometers. Allow. This is the wavelength of light absorbed by Ge. 1.1 eV is the forbidden bandwidth of Si. Polycrystalline SiGe and polycrystalline Ge have a slightly narrower forbidden bandwidth than 1.1 eV, which allow at least partial penetration of IR.

〔Feature Description〕
FIG. 4 is another partial cross-sectional view of the phototransistor shown in FIG. The germanium phototransistor is formed on a P-type silicon substrate or a P-well of a silicon integrated circuit substrate. The germanium at the boundary with the nitride is appropriately added with boron. Both source and drain junctions are very shallow. This is to prevent the depletion region from reaching a high defect density at the germanium / nitride interface region. The detailed configuration and operation of this apparatus will become apparent from the description of the manufacturing process.

  The manufacturing process of the device is as follows.

  1. The preferred known silicon integration process for manufacturing silicon CMOS to assist electronic circuits is followed. For manufacturing germanium phototransistors, a P-type substrate or P-type well region is retained.

  2. A liquid phase epitaxy (LPE) germanium thin film is formed on silicon nitride formed on a silicon substrate. The film thickness of germanium is typically not less than about 300 nm. Do not remove top cover oxide.

  3. The top cover oxide and germanium are subjected to a photoresist and etching process.

  4). Deposit oxide. The oxide thickness is about 1 to 1.5 times the sum of the germanium and cover oxide thicknesses.

  FIG. 5 is a diagram showing an additional step in the manufacture of the phototransistor shown in FIG.

  5. The wafer is planarized by CMP. At this time, the cover oxide is not completely removed. Then, the remaining cover oxide is removed by wet etching.

  6). In order to adjust the threshold voltage, the germanium film is doped by boron ion implantation. Then, deep boron ion implantation is performed to dope the germanium layer in the P-type region at the boundary with the nitride.

  7). Using conventional methods, a gate oxide is deposited to form a gate electrode. Then, arsenic ions are implanted into the shallow source / drain regions. Oxide passivation and metallization steps are performed in the following steps.

  Since the depletion region at the source junction does not extend to the crystal defect region below the germanium layer near the silicon nitride, the leakage current at the source junction is reduced. Holes generated by light can be accumulated in the germanium film. The holes effectively bias the germanium film so as to reduce the threshold voltage of the germanium phototransistor. As a result, the output current increases. In the vicinity of silicon nitride, the germanium thin film is doped with a P-type impurity. This reduces the generated current and prevents the drain depletion region from reaching the boundary with the silicon nitride.

  FIG. 6 is another partial cross-sectional view of the phototransistor shown in FIG. In other embodiments, the drain junction of the phototransistor is offset from the end of the drain. For transistors with very short channels, this embodiment is useful because the active photodetection area is very small. The offset region is doped with a P-type impurity at a low concentration. In this embodiment, the transistor does not require a conventional LDD structure. The manufacture of a phototransistor having an offset drain is the same as the phototransistor shown in FIGS. 2 and 4 except that a photoresist process is required to mask the offset drain region during drain ion implantation. Can be.

  The maximum offset distance is d or less calculated by the following equation.

ε is the dielectric constant of germanium, N is the channel doping concentration, and V _D and V _DSAT are the drain bias voltage and drain saturation voltage at the operating gate bias voltage, respectively. When the transistor is selected and both the gate and drain are appropriately biased, the drain offset region (light absorption threshold bias region) is fully depleted in the presence of light. Therefore, the drain current does not decrease due to the offset region. In this selected transistor, in the absence of light, the offset region is not completely depleted. The drain current is small and therefore the ratio of drain current in the presence / absence of light is very large.

  The present invention will be described with respect to an insulator-structured Ge MOSFET device that has the advantage of a floating body effect due to improved amplification of the photodetection signal. The Ge epitaxial film is formed by liquid phase epitaxial regrowth. However, the floating body effect relating to this Ge MOS phototransistor can be applied to any device formed on a germanium-on-insulator (GeOI) wafer.

  The floating body model for an SOI device is depicted as a substrate that is capacitively coupled to the gate, drain, source, and substrate through separate capacitors. More complex models include a parasitic bipolar transistor having a bottom coupled to the substrate, and an emitter and collector coupled to the source and drain, and a parallel connected rear transistor having a gate coupled to the substrate. back transistor).

  The Ge deposition method may be chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or other suitable thin film growth methods. Next, the Ge film is patterned and etched into the desired shape. These shapes need to include a small region of Ge immediately above the top of the Si substrate. This region functions as a seed window for the Ge epitaxial process. A conformal dielectric layer (20 nm to 1000 nm) is then deposited to seal the Ge film. Instantaneous thermal annealing (RTA) is used to heat the wafer and melt the Ge film. For example, silicon oxide or silicon nitride can be used as the dielectric layer. Since the melting temperature (melting point) of the Ge crystal is 938 ° C., the RTA temperature is between 920 ° C. and 1000 ° C. During this annealing, the Ge film melts, and the dielectric insulator that seals the Ge functions as a very small pool so that liquid Ge does not flow randomly. The Si substrate below the insulator and above the dielectric remains solid. The wafer is then naturally cooled. During the cooling of liquid Ge, liquid phase epitaxy (LPE) occurs where growth begins at the Si / Ge boundary in the seeding window. And it grows from a side part by this liquid phase epitaxy. Finally, single crystal Ge is formed with crystal defects concentrated and terminated in the seed window.

  7A and 7B are flowcharts illustrating a method for manufacturing a floating body Ge phototransistor having a light absorption threshold bias region. Although this method is shown as a series of clearly numbered steps, this number does not necessarily indicate the order of these steps. Some of these steps may be omitted, performed in parallel, or performed without requiring strict maintenance of sequential order. The method begins at step 700.

  In step 702, a Si substrate to which a P-type impurity is added is prepared. Step 704 selectively forms an insulator layer on the first surface of the Si substrate. In one embodiment, the insulator layer has a layer thickness in the range of about 10-500 nm. Step 706 forms an epitaxial Ge layer over the insulator layer. Step 708 forms a channel region in the Ge layer. Step 710 forms a gate dielectric, a gate electrode, and a gate spacer over the channel region. Step 712 forms source / drain (S / D) regions in the Ge layer. Step 714 forms a light absorption threshold bias region adjacent to the channel region in the Ge layer.

  In one embodiment, forming 706 an epitaxial Ge layer on the insulator layer includes performing liquid phase epitaxy (LPE) on the deposited Ge. For example, the step 706 may include the following sub-steps (not shown). Step 706a deposits Ge to a thickness in the range of about 300-1000 nm. For example, Ge may be deposited using CVD, PVD, or MBE methods. In step 706b, the Ge is sealed with a Ge barrier material having a melting temperature higher than that of Ge. Typically, the Ge barrier material is a material that does not chemically interact with Ge. Then, in step 706c, the Ge is melted at a temperature lower than the melting temperature of the Ge barrier material. For example, in step 706c, the temperature of the Si substrate may be continuously heated to a range of about 920 to 1000 ° C. for a time in a range of about 0 to 10 seconds. A continuous heating time of “0” seconds means that the substrate can be cooled immediately when it reaches the target temperature.

  In other embodiments, the step 704 of selectively forming an insulator layer on the first surface of the Si substrate includes a sub-step. Step 704a deposits silicon nitride having an upper surface on a Si substrate. After forming the epitaxial Ge layer in step 706, step 704b is performed. Step 704b selectively etches the material that seals the Ge layer, the Ge layer, and the silicon nitride to expose the second surface of the Si substrate. Then, in step 707a, silicon oxide is deposited on the second surface of the Si substrate. In step 707b, the silicon oxide is chemically mechanically polished (CMP) to the level of the material that seals the Ge layer. Step 707c etches to remove the material that seals the Ge layer.

  In another embodiment, deep boron (B) ion implantation is performed in step 707d. Then, in step 707e, a P-type region is formed immediately above the upper surface of silicon nitride in the Ge layer (result of step 707d).

  In one embodiment, forming 712 a first S / D region in the Ge layer includes a substep. Step 712a forms a first S / D region having a first length substantially over the second surface of the Si substrate. Step 712b forms a second S / D region having a second length that is longer than the first length. Then, the step of forming the light absorption threshold bias region in the Ge layer (step 714) includes the step of forming the light absorption threshold bias region under the second S / D region.

  As an alternative to step 712b, step 712c forms a second S / D region separated from the channel by an offset region. In step 714, a P-type impurity is added to the offset region in the Ge layer.

In one embodiment, forming gate dielectric and gate spacer 710 includes forming the gate dielectric and gate spacer from a wide bandgap material. For example, the gate _{dielectric, SiO 2, GeO 2, Al} 2 O 3, HfO 2, ZrO 2, TiO 2, Ta 2 O 5 or a combination of these materials. The gate electrode may be polycrystalline Ge, polycrystalline SiGe, or polycrystalline silicon (polysilicon). The gate spacer may be SiO ₂ or Si ₃ N ₄ .

  An epitaxial Ge phototransistor having a light absorption threshold bias region and related fabrication methods have been described. Certain manufacturing steps and materials are used as examples to illustrate the invention. However, the invention is not limited to merely these examples. Those skilled in the art will find other variations and embodiments of the invention.

  The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope shown in the claims, and the present invention is also applied to an embodiment obtained by appropriately combining technical means disclosed in the embodiment. It is included in the technical scope of the invention.

According to transmission electron microscopy (XTEM), which is the interface between the cross-sectional image between the Ge and _Si 3 _{N 4.} 2 is a partial cross-sectional view of a floating body germanium (Ge) phototransistor having a light absorption threshold bias region. FIG. 6 is a partial cross-sectional view of a floating body Ge phototransistor having a light absorption threshold bias region and an offset S / D region. FIG. 3 is another partial cross-sectional view of the phototransistor shown in FIG. 2. It is a figure which shows the additional process in the manufacturing method of the phototransistor shown in FIG. FIG. 4 is another partial cross-sectional view of the phototransistor shown in FIG. 3. It is a flowchart explaining the manufacturing method of the floating body Ge phototransistor which has a light absorption threshold value bias area | region. It is a flowchart explaining a manufacturing method of a floating body Ge phototransistor having a light absorption threshold bias region.

Claims (23)

A method of manufacturing a floating body germanium (Ge) phototransistor having a light absorption threshold bias region comprising:
Preparing a silicon (Si) substrate to which a P-type impurity is added;
Selectively forming an insulator layer on the first surface of the Si substrate;
Forming an epitaxial Ge layer on the insulator layer;
Forming a channel region in the Ge layer;
Forming a gate dielectric, a gate electrode and a gate spacer on the channel region;
Forming a source / drain (S / D) region in the Ge layer;
Forming a light absorption threshold bias region adjacent to the channel region in the Ge layer.   The method of claim 1, wherein the step of forming the epitaxial Ge layer on the insulator layer includes a step of treating the deposited Ge by a liquid phase epitaxy (LPE) method.   The method of claim 2, wherein depositing Ge on the insulator layer comprises depositing Ge to a thickness in the range of about 300 to 1000 nanometers (nm). The step of treating the deposited Ge by the LPE method includes:
Sealing the Ge with a Ge barrier material having a melting temperature higher than the melting temperature of the Ge;
Melting the Ge at a temperature lower than the melting temperature of the Ge barrier material. Selectively forming the insulator layer on the first surface of the Si substrate;
Depositing silicon nitride having an upper surface on the Si substrate;
Exposing the second surface of the Si substrate by selectively etching the material sealing the Ge layer, the Ge layer, and the silicon nitride after forming the epitaxial Ge layer. ,
Depositing silicon oxide on the second surface of the Si substrate;
Chemical mechanical polishing (CMP) the silicon oxide until the height of the material sealing the Ge layer is reached;
The method according to claim 1, further comprising: removing a material for sealing the Ge layer by etching. Deep boron ion implantation,
6. The method of claim 5, further comprising: forming a P-type region in the Ge layer directly above the silicon nitride top surface. Forming the S / D region in the Ge layer;
Forming a first S / D region having a first length substantially over the second surface of the Si substrate;
Forming a second S / D region having a second length longer than the first length,
Forming the light absorption threshold bias region in the Ge layer includes forming the light absorption threshold bias region under the second S / D region; The method according to claim 5. Forming the S / D region in the Ge layer;
Forming a first S / D region substantially over the second surface of the Si substrate;
Forming a second S / D region separated from the channel by an offset region;
6. The method of claim 5, wherein forming the light absorption threshold bias region in the Ge layer includes adding a P-type impurity to the offset region in the Ge layer. .   The step of depositing Ge on the insulator layer and the second surface of the Si substrate comprises chemical vapor deposition (CVD), physical vapor deposition (PVD), and molecular beam epitaxy (MBE). 4. The method of claim 3, comprising depositing Ge by a method selected from the group.   4. The method of claim 3, wherein the step of melting Ge includes heating the Si substrate at a temperature in the range of about 920 to 1000 [deg.] C. for a time in the range of about 0 to 10 seconds. the method of.   The method of claim 1, wherein selectively forming the insulator layer on the Si substrate comprises forming an insulator layer having a layer thickness in the range of about 10 to 500 nm. .   The step of forming the gate dielectric, the gate electrode, and the gate spacer on the channel region includes forming the gate dielectric and the gate spacer from a wide bandgap material. The method of claim 1, comprising: Forming the gate dielectric, the gate electrode, and the gate spacer on the channel region;
The gate dielectric on the channel is selected from a material selected from the group consisting of SiO ₂ , GeO ₂ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O ₅ , and combinations thereof. Forming, and
Forming the gate electrode from a material selected from the group consisting of polycrystalline Ge, polycrystalline SiGe, and polycrystalline silicon (polysilicon);
Forming the gate spacer adjacent to the electrode from a material selected from the group consisting of SiO ₂ and Si ₃ N ₄ . A floating body germanium (Ge) phototransistor having a light absorption threshold bias region,
A silicon (Si) substrate doped with P-type impurities;
An insulator layer on the first surface of the Si substrate;
An epitaxial Ge layer on the insulator layer;
A channel region in the Ge layer;
A gate dielectric, a gate electrode, and a gate spacer on the channel region;
First and second source / drain (S / D) regions in the Ge layer;
A phototransistor comprising a light absorption threshold bias region adjacent to the channel region in the Ge layer.   The phototransistor of claim 14, wherein the epitaxial Ge layer has a layer thickness in the range of about 300 to 1000 nanometers (nm). The insulator layer is a silicon nitride layer having an upper surface;
The Si substrate includes a second surface adjacent to the first surface;
The phototransistor of claim 14, further comprising silicon oxide on the second surface of the Si substrate.   The phototransistor according to claim 16, further comprising a region to which a P-type impurity is added in a Ge layer immediately above the upper surface of the silicon nitride. The first S / D region is generally above the second surface of the Si substrate and has a first length;
The second S / D region has a second length longer than the first length,
The phototransistor of claim 16, wherein the light absorption threshold bias region in the Ge layer is below the second S / D region. The first S / D region is generally above the second surface of the Si substrate;
17. The light absorption threshold bias region in the Ge layer includes an offset region to which a P-type impurity is added that separates the second S / D region from the channel. The phototransistor described. The said 2nd S / D area | region has the channel side edge part offset from the said channel area | region by the distance which is not larger than d calculated by a following formula, It is characterized by the above-mentioned. Phototransistor (where ε is the dielectric constant of germanium, N is the channel doping concentration, and V _D and V _DSAT are the second S / D bias voltage and saturation voltage, respectively, at the operating gate bias voltage. is there).
  The phototransistor of claim 14, wherein the insulator layer on the Si substrate has a layer thickness in the range of about 10 to 500 nm.   15. The phototransistor of claim 14, wherein the gate dielectric and the gate spacer are made of a wide bandgap material. The gate dielectric is formed of a material selected from the group consisting of SiO ₂ , GeO ₂ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O ₅ , and combinations thereof;
The gate electrode is formed of a material selected from the group consisting of polycrystalline Ge, polycrystalline SiGe, and polycrystalline silicon (polysilicon);
Said gate spacers are phototransistor according to claim 22, characterized in that it is formed from a material selected from the group consisting of SiO ₂ and Si ₃ N _4.