JP2007094921A - Memory card and control method for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of difficulty in surely writing multivalued data. <P>SOLUTION: In a memory cell, data for a second page are written after data for a first page are written. In a holding circuit 7, the data for the first page read from the memory cell are held when the data for the second page are written. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory card including, for example, a NAND flash memory, and more particularly to a memory card capable of storing a plurality of bits of data in one memory cell and a control method thereof.

  A NAND flash memory applied to a memory card or the like includes, for example, a plurality of EEPROM cells connected in series and a selection transistor, and stores written data in a nonvolatile manner. In this NAND flash memory, data is written and read in units called “pages” in which a plurality of memory cells are aggregated, and data is erased in units called “blocks” in which a plurality of pages are aggregated. Is called. In other words, the NAND flash memory can be regarded as a collection of hierarchical structures of “memory cell” → “page” → “block”.

  The NAND flash memory can be classified into a binary memory and a multi-value memory. The binary memory can store only two values (1 bit) of logic “0” and logic “1” in one memory cell, but the multi-value memory can store three or more values (multiple bits). .

  The current multi-level memory is a memory that stores a 2-bit value in one memory cell. Usually, two different page addresses are assigned to the 2-bit value. A page assigned to the lower bits is called a lower page, and a page assigned to the upper bits is called an upper page. When writing 2-bit data in one memory cell, writing is performed twice. That is, a value corresponding to the lower page address and a value corresponding to the upper page address are written.

  According to the current multi-level memory writing rule, it is possible to write the upper page after writing the lower page, but it is prohibited to write the lower page after writing the upper page. If this rule is followed, if an abnormal situation occurs when writing the lower page and the storage state of the memory cell is destroyed, the writing of the lower page may be failed. However, if writing to the upper page fails and the storage state of the memory cell is destroyed, the data of the lower page is also destroyed. In other words, a write failure on one page destroys data on other pages. When writing fails in this way, it is necessary to rewrite and repair the corrupted data.

Conventionally, although not a multi-level memory, a flash memory has been developed that prevents the loss of data even when a power interruption occurs during data writing (for example, Patent Document 1). However, it is difficult to apply the technique of Patent Document 1 to a multilevel memory.
JP 2001-154926 A

  An object of the present invention is to provide a memory card capable of reliably writing multi-value data and a control method therefor.

  According to an aspect of the memory card of the present invention, the first page of data is written, the second page of data is written into the memory cell, and when the second page of data is written, the memory cell is read from the memory cell. And a holding circuit for holding data of the first page.

  An aspect of a memory card control method according to the present invention is a memory card control method for storing at least first page and second page data in one memory cell, wherein the second page data is written to the memory cell. In this case, the data of the first page is read from the memory cell and held.

  ADVANTAGE OF THE INVENTION According to this invention, the memory card which can write multi-value data reliably, and its control method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 2 is a block diagram showing a configuration including a host and a memory card.

  A host device (hereinafter referred to as a host) 20 includes hardware and software (system) for accessing a connected memory card.

  The memory card 1 operates upon receiving power supply when connected to the host 20, and performs processing in accordance with access from the host 20. As described above, the memory card 1 has the NAND flash memory 3 and the controller 4. The controller 4 manages the internal physical state of the NAND flash memory 3 (where the physical block address includes what logical sector address data or which block is in the erased state). .

  The NAND flash memory 3 is a non-volatile memory in which a block size (erase block size) at the time of erasure is set to, for example, 256 kBytes, and data is written / read in units of, for example, 2 kBytes. The NAND flash memory 3 is manufactured using, for example, a 0.09 μm process technology. That is, the design rule of the NAND flash memory 3 is less than 0.1 μm.

  In addition to the CPU 8 and ROM 9 described above, the controller 4 includes a memory interface unit 5, a host interface unit 6, a buffer 7, and a RAM (Random Access Memory) 10.

  The memory interface unit 5 performs interface processing between the controller 4 and the NAND flash memory 3. The host interface unit 6 performs interface processing between the controller 4 and the host 20.

  The buffer 7 temporarily stores a certain amount of data (for example, one page) when data sent from the host 20 is written to the NAND flash memory 3, or data read from the NAND flash memory 3. When a message is sent to the host 20, a certain amount of data is temporarily stored.

  The CPU 8 controls the operation of the entire memory card 1. For example, when the memory card 1 is supplied with power, the CPU 8 loads firmware (control program) stored in the ROM 9 onto the RAM 10 and executes predetermined processing. That is, the CPU 8 creates various tables on the RAM 10, receives a write command, a read command, and an erase command from the host 20, accesses the corresponding area on the NAND flash memory 3, and performs a data transfer process through the buffer 7. To control.

  The ROM 9 is a memory that stores a control program used by the CPU 8. The RAM 10 is a volatile memory that is used as a work area for the CPU 8 and stores control programs and various tables.

  The buffer 7 has a capacity for storing, for example, one page of data, and holds data read from the lower page when writing data, for example.

  FIG. 3 shows a schematic configuration of the NAND flash memory 3. The NAND flash memory 3 has a memory cell array in which a plurality of blocks are arranged. Each block is a data erasing unit, and a plurality of memory cells MC are arranged in a matrix in each block. The memory cell MC of the NAND flash memory 3 stores multi-value data, for example, 2-bit data. A set of a plurality of memory cells MC commonly connected to a word line (not shown) constitutes a plurality of pages. Specifically, among 2-bit data stored in one memory cell MC, a lower page is assigned to the lower bits and an upper page is assigned to the upper bits. In writing data, data is first written to the lower page, and then data is written to the upper page.

  Recently, it is known that the threshold voltage of a memory cell fluctuates due to the influence of the coupling capacitance between adjacent cells when data is written. For this reason, in order to reduce the influence of the coupling capacity of adjacent cells, a writing method in which the lower page address is separated from the upper page address has been developed.

  FIG. 4 shows an example. For example, the upper page “4” is set for the lower page “0”, and the upper page “5” is set for the lower page “1”. Further, an upper page “8” is set for the lower page “2”, and an upper page “9” is set for the lower page “3”. The write operation of the memory cell in which the page address is set in this way is as follows. First, the lower pages “0”, “1”, “2”, and “3” are written, and then the upper pages “4” and “5” are written. Next, the lower pages “6” and “7” are written, and then the upper pages “8” and “9” are written. This write operation is defined as follows. That is, before the upper page of a certain memory cell is written between adjacent cells, the lower page of the memory cell adjacent to this memory cell is written. Specifically, for example, the lower page “1” of the adjacent memory cell is written before the upper page “4” of the memory cell is written, and the adjacent memory cell is written before the upper page “5” of the memory cell is written. The lower page “2” is written.

  In the first embodiment, when data is written to the upper page of a certain memory cell, the data of the lower page of the memory cell is read and held, thereby preventing destruction of the lower page data. For this reason, a correspondence table of the lower page address and the upper page address assigned to the same memory cell is created in, for example, the ROM 9 inside the controller 1. That is, the write address indicating the write order for the memory cells is determined in advance in consideration of the adjacent cell capacity. A correspondence table of the predetermined lower page address and upper page address is stored in the ROM 9.

  FIG. 5 shows an example of the table TB. According to this table TB, the controller 1 reads the data of the corresponding lower page from the memory cell and stores it in the buffer 7 immediately before writing to the upper page. The data stored in the buffer 7 is held until the data writing to the upper page is completed.

  FIG. 1 shows the operation of the controller 1. As shown in FIG. 1, the controller determines whether the write address is a lower page address (S11). As a result, if it is the lower page address, the data of the lower page is written (S12). In writing the lower page, it is determined whether an error has occurred (S13). If an error has occurred, error processing is performed (S14). That is, the data of the lower page is written again. The data of the lower page is held in a data cache (not shown) provided in the NAND flash memory 3, for example. For this reason, the data of the lower page can be reliably rewritten.

  On the other hand, if it is determined in step S11 that the write address is the upper page address, referring to the table shown in FIG. 5, the write is already performed from the memory cell to be written with the lower page address corresponding to the upper page address. The lower page data is read. The read data is stored in the buffer 7 in the controller 1 (S15). In this state, the data of the upper page is written into the write target memory cell (S16). It is determined whether or not an error has occurred in writing the upper page (S17). If no write error occurs, the write is completed normally.

  On the other hand, when an error occurs in writing the upper page, the data on the lower page is also destroyed. Therefore, first, the lower page data stored in the buffer 17 is written into the memory cell (S18), and then the upper page data is written into the memory cell (S19). The data of the upper page is held in a data cache (not shown) provided in the NAND flash memory 3, for example. Therefore, it is possible to reliably rewrite the data of the upper page.

  According to the first embodiment, when the upper page data is written, first, the lower page data corresponding to the upper page is read out and backed up in the buffer 7, and then the upper page data is written. . For this reason, when upper page data is written, lower page data can be prevented from being destroyed, and multi-value data can be written reliably.

  The storage capacity of the buffer 7 is only required to store the data of the lower page of the write target memory cell. That is, even when the lower page address and the upper page address are separated from each other, the buffer 7 only needs to have a storage capacity for one page. Therefore, the area occupied by the controller 1 with respect to the chip can be suppressed.

  In the case of the first embodiment, the lower page data read time and storage time are added to the upper page write time. However, for reading lower page data, for example, by using synchronous burst read (Synchronous Burst Read) capable of reading one page of data at high speed in synchronization with a clock signal, the read time can be shortened. And the entire writing time can be shortened.

(Second Embodiment)
In the first embodiment, each time the upper page data is written, the lower page data is read and stored in the buffer 7. On the other hand, in the second embodiment, for example, after the power is turned on, the above operation is executed at the time of the first writing.

  For example, the lower page data is written, the power is turned off after the writing operation is normally completed, and then the upper page data is continuously written to the memory cell in which the lower page data is written when the power is turned on. There is. In this case, the data of the lower page and the data of the upper page written in the memory cell are almost unrelated data. In such a writing mode, when writing of the upper page fails, conventionally, it has been difficult to recover the data of the lower page.

  Therefore, in the second embodiment, the above operation is performed when data is written to the upper page immediately after the power is turned on.

  FIG. 6 shows the operation of the second embodiment. For example, when the memory card 1 is connected to the host 20 and the power is turned on, it is first determined whether or not the data is written immediately after the power is turned on (S21). This determination is performed according to flag data, for example. This flag may be set when the power is turned on, for example, and reset when the upper page is written. In the case of the first writing, it is determined whether or not the writing address is a lower page (S11). As a result, if it is the upper page address, the data of the lower page is read from the write target memory cell and stored in the buffer 7 as in the first embodiment (S15). Thereafter, upper page data is written (S16-S19).

  Further, when writing data immediately after power-on and writing lower page data, the control shifts from step S11 to S23.

  If the flag is reset and the writing is not performed immediately after the power is turned on, the control proceeds from step S21 to S22. Thereafter, the data of the lower page or the data of the upper page is written into the memory cell (S23-S28). In this case, when the upper page data is written, the lower page data is not read.

  According to the second embodiment, only when the upper page data is written to the memory cell in which the lower page is written, immediately after the power is turned on, the lower page data is first read and stored in the buffer 7. Thereafter, the upper page data is written. For this reason, the data of the lower page written before power-off can be reliably protected.

  Moreover, since the buffer 7 only needs to have a storage capacity for one page, an increase in the chip occupation area of the controller 1 can be suppressed.

  In addition, the lower page data is read only when the upper page data is written immediately after the power is turned on, and then the lower page data is not read when the upper page data is written. It is.

(Modification 1)
In the first and second embodiments, the data of the lower page read from the memory cell is stored in the buffer 7. However, the present invention is not limited to this, and may be stored in the RAM 10 via the CPU 8 shown in FIG.

(Modification 2)
Moreover, in the said 1st, 2nd embodiment, although table TB was formed in ROM9, it is not limited to this. For example, a calculation formula for calculating the lower page address and the upper page address may be stored in the ROM 9, and the lower page address and the upper page address calculated using the calculation formula may be stored in the RAM 10.

(Modification 3)
Alternatively, as shown in FIG. 2, an address conversion circuit (AC) 5-1 corresponding to a conversion formula for converting, for example, a lower page address and an upper page address is arranged in the memory interface 5, and this address conversion circuit 5- The address may be calculated by 1.

(Modification 4)
Furthermore, in the first and second embodiments, the relationship between the lower page address and the upper page address is shown in FIGS. 3 to 5, but is not limited to this.

  For example, as shown in FIG. 7, every other memory cell arranged in one row is suppressed in order to suppress the variation of the threshold voltage of the memory cell due to the coupling capacity of the memory cells adjacent in the row and column directions. A write method has been developed that selects and sets two lower page addresses and two upper page addresses in one row. In the example shown in FIG. 7, the memory cells MC00, MC02... Are set to the lower page “0” and the upper page “4”, and the memory cells MC01, MC03... Are set to the lower page “1” and the upper page “5”. Has been. A page address is set as shown below. The write operation of the memory cell in which the page address is set in this way is performed as follows. That is, before writing the upper page of a certain memory cell, the lower page of the memory cell adjacent to this memory cell is written. Specifically, for example, the lower page “2” of the adjacent memory cells MC10, MC12... Is written before the upper page “4” of the memory cells MC00, MC02. Further, before the upper page “5” of the memory cells MC01, MC03... Is written, the lower page “3” of the adjacent memory cells MC11, MC13.

  The first and second embodiments can be applied to the memory cell in which the page address is set in this way. That is, for example, when data is written to the upper page “4” of the memory cells MC00, MC02..., The data written to the lower page “0” of the memory cells MC00, MC02.

  Also by this modification, the same effects as those of the first and second embodiments can be obtained.

(Modification 5)
In the first and second embodiments, the case where 2 bits and 2 pages of data are stored in one memory cell has been described. However, the present invention is not limited to this, and data of 3 bits, 3 pages or more can be stored in one memory cell. In this case, the storage capacity of the buffer 7 may be set to the storage capacity of the number of pages−1.

(Modification 6)
Further, in the first and second embodiments, when the upper page data is written, the lower page data is read. However, the present invention is not limited to this.

  For example, in the multi-level memory, when writing of the upper page fails, data for several pages from the lower page to the upper page may be held in the buffer 7 in order to restore the information of the lower page. When writing of the upper page has failed, first, the data of the lower page corresponding to the upper page that has failed to be written stored in the buffer 7 is written, and then the data of the upper page is written. According to this method, it is not necessary to read the data of the lower page when writing the upper page.

  As shown in FIG. 4 and FIG. 7, in the write method in which the lower page address and the upper page address are discontinuous with respect to one memory cell, the storage capacity of the buffer 7 is changed from, for example, the lower page address to the upper page. A capacity for storing data corresponding to the number of lower pages included in the maximum address interval and a capacity necessary for holding data of the upper page to be written are set.

  Specifically, in the example shown in FIG. 4, the lower page address “2” and the upper page address “8” including the lower page address “2”, “3”, “6”, “7”. There are 5 pages of “8”. For this reason, the storage capacity of the buffer 7 is set to 5 pages. By setting the storage capacity of the buffer 7 in this manner, the data of the lower page address of the memory cell corresponding to the upper page address can be held in the buffer 7 until the writing corresponding to the upper page address is completed. . Therefore, it is possible to write multi-value data reliably and at high speed without significantly increasing the storage capacity of the buffer 7 and without reading the data of the lower page when writing the upper page.

(Modification 7)
The first and second embodiments and the modifications have been described for the NAND flash memory. However, the present invention is not limited to this, and the present invention can also be applied to a NOR flash memory for storing multi-value data. .

  In the first and second embodiments and the modifications, the case of four values (2 bits) has been described. However, the present invention can also be applied to a NAND flash memory that stores data of not only four values but eight values (3 bits) or more.

  Of course, various modifications can be made without departing from the scope of the present invention.

The flowchart which shows operation | movement of 1st Embodiment. The figure which shows an example of the memory card with which 1st Embodiment is applied. The figure which shows an example of the memory card with which 1st Embodiment is applied. The figure which shows the other example of the memory card to which 1st Embodiment is applied. The figure which shows an example of the table to which 1st Embodiment is applied. The flowchart which shows operation | movement of 2nd Embodiment. The figure which shows the modification of a memory card.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory card, 3 ... NAND type flash memory, 4 ... Controller, 7 ... Buffer, 8 ... CPU, TB ... Table.

Claims (5)

A memory cell to which the second page data is written after writing the first page data;
A memory card, comprising: a holding circuit that holds the data of the first page read from the memory cell when writing the data of the second page.   2. The memory card according to claim 1, wherein the holding circuit holds the data of the first page read from the memory cell when writing the data of the second page immediately after power-on. A method of controlling a memory card that stores data of at least a first page and a second page in one memory cell,
A method for controlling a memory card, comprising: reading and holding data of the first page from the memory cell when writing data of a second page to the memory cell.   4. The memory card according to claim 1, wherein the address of the first page and the address of the second page are separated from each other.   4. The memory card control method according to claim 3, wherein reading and holding the first page data from the memory cell is performed when writing the second page data immediately after power-on.

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