JP2006338789A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having high data holding characteristics and a high-speed reading operation. <P>SOLUTION: In this flash memory, an address is sequentially designated by a predetermined number of times Nmax at every supply of a power supply voltage, the retention checking of the memory cell transistor MC of each address is carried out, and a memory cell transistor MC where a threshold voltage is reduced is reprogrammed. Thus, as compared with the conventional case of performing retention checking in each reading operation, a high speed of the reading operation is achieved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a memory cell transistor that stores data according to a change in threshold voltage.

  In recent years, in a nonvolatile semiconductor memory device such as a flash memory, data retention has become very difficult with miniaturization and high integration of memory cell transistors. For example, in a flash memory, when a negative charge is injected into the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor rises to store data “0”, and when the negative charge is extracted from the floating gate, the memory cell transistor is turned off. The threshold voltage decreases and data “1” is stored. However, there is a problem that the negative charge injected into the floating gate is gradually released over time, the threshold voltage of the memory cell transistor is lowered, and the data changes from “0” to “1”. .

Therefore, during a read operation, a normal read voltage is applied to the control gate to read data, and a voltage higher than the normal read voltage is applied to the control gate to read data, and the logic of the two read data is different. In such a case, a method has been proposed in which the threshold voltage of the memory transistor is judged to be lowered and reprogramming is performed (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 62-128097

  However, in the conventional method, each time a read operation is performed, data is read twice and compared, and reprogramming is performed in accordance with the comparison result.

  Therefore, a main object of the present invention is to provide a nonvolatile semiconductor memory device having a high data retention characteristic and a fast read operation.

  A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cell transistors each assigned a unique address, a first register for storing an address for starting a retention check, and a retention check mode. A decoder that sequentially designates a predetermined number of addresses from the addresses stored in the first register, and a first voltage that is a normal read voltage is applied to the gate of the memory cell transistor at the address designated by the decoder Then, the storage data of the memory cell transistor is read, and a second voltage between the first voltage and the threshold voltage when the memory cell transistor is programmed is applied to Read circuit for reading stored data, and apply first and second voltages The logic levels of the two read storage data are compared, and if they do not match, a comparison circuit that outputs a mismatch signal, and the address next to the address last specified by the decoder as the first address to start the retention check The first write circuit for writing to the first register is provided.

  Another nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cell transistors, a decoder for sequentially designating a plurality of memory cell transistors in response to power supply voltage being applied, and a decoder When the first voltage, which is a normal read voltage, is applied to the gate of the memory cell transistor designated by the above to read the stored data of the memory cell transistor, and when the first voltage and the memory cell transistor are programmed A read circuit for reading the stored data of the memory cell transistor by applying a second voltage between the threshold voltages of the two and the logic of the two stored data read by applying the first and second voltages A comparison circuit that compares the levels and outputs a mismatch signal if they do not match is provided.

  In the nonvolatile semiconductor memory device according to the present invention, a register for storing an address for starting a retention check is provided, and in the retention check mode, a retention check of memory cell transistors having a predetermined number of addresses from the address stored in the register is provided. The next address after the retention check is completed is written to the register as an address for starting the retention check. Therefore, every time the retention check mode is set, the retention check of a predetermined number of memory cell transistors is performed collectively, so that the read operation can be speeded up compared to the conventional case where the retention check is performed for each read operation. it can. In addition, by appropriately setting the number of addresses for which the retention check is performed, it is possible to prevent the retention check time from becoming too long.

  In another nonvolatile semiconductor memory device according to the present invention, since the retention check is performed when the power is turned on, the speed of the read operation can be increased as compared with the conventional case where the retention check is performed for each read operation.

[Embodiment 1]
FIG. 1 is a block diagram showing the overall configuration of a flash memory according to Embodiment 1 of the present invention. In FIG. 1, the flash memory includes a memory cell array 1, an address decoder 2, a control circuit 3, a sense voltage application circuit 4, a sense circuit 5, a comparison circuit 6, and a register 7.

  Memory cell array 1 includes a plurality of memory cell transistors arranged in a plurality of rows and columns. A unique address signal is assigned to each memory cell transistor. The memory cell transistor has a well-known two-layer gate structure, and has a floating gate and a control gate. As shown in FIG. 2, when a negative charge is injected into the floating gate, the threshold voltage of the memory cell transistor rises from VTH1 to VTH0 to store data “0”, and when the negative charge is extracted from the floating gate, the memory cell transistor Is reduced from VTH0 to VTH1, and data "1" is stored.

  Returning to FIG. 1, the address decoder 2 is connected to any one of a plurality of memory cell transistors included in the memory cell array 1 in accordance with an address signal ADD given from the outside or an address signal ADD given from the control circuit 3. Specifies the cell transistor.

  The control circuit 3 controls the entire flash memory according to a control signal CNT and a write data signal DI given from the outside. During the erase operation, a negative high voltage is applied between the control gate and the source of the memory cell transistor designated by the address decoder 2 to pull out the negative charge of the floating gate. During the program operation, a positive high voltage is applied between the control gate and the source of the memory cell transistor designated by the address decoder 2 and the write data signal DI is “0” to inject negative charges into the floating gate. In the read operation, sense voltage application circuit 4 and sense circuit 5 are controlled to read the data stored in the memory cell transistor designated by address decoder 2.

  FIG. 3 is a circuit block diagram showing portions related to the read operation. In FIG. 3, the control gate of the memory cell transistor MC designated by the address decoder 2 among the plurality of memory cell transistors MC of the memory cell array 1 is connected to the output node of the sense voltage application circuit 4, and the source thereof is the ground potential GND. The drain is connected to the line of the power supply potential VCC via the resistance element 8 and to the input node of the sense circuit 5.

  The sense voltage application circuit 4 applies a predetermined potential V1 (see FIG. 2) between the VTH1 and VTH0 to the control gate of the memory cell transistor MC designated by the address decoder 2 during the read operation. When the threshold voltage of the memory cell transistor MC is VTH1, a current larger than the threshold current ITH flows, the drain of the memory cell transistor MC becomes “L” level, and the sense circuit 5 sets the read data signal DO to “ Set to “H” level (“1”). When the threshold voltage of the memory cell transistor MC is VTH0, a current smaller than the threshold current ITH flows, the drain of the memory cell transistor MC becomes “H” level, and the sense circuit 5 sets the read data signal DO to “ Set to “L” level (“0”).

  The negative charge injected into the floating gate of the memory cell transistor MC is gradually released over time, and the threshold voltage of the memory cell transistor MC decreases and the data changes from “0” to “1”. . Therefore, in this flash memory, the retention check mode is executed every time the power supply voltage is turned on.

  Returning to FIG. 1, the register 7 stores a signal ADDS indicating an address at which a retention check is started and the number Nmax of addresses to be checked in one retention check mode. In the retention check mode, the control circuit 3 sequentially increments the address signal ADDS to provide Nmax address signals ADD to the address decoder 2, and then adds a signal ADDS indicating an address for starting the next retention check to the register 7. Store. The register 7 may be constituted by a part of the memory cell array 1 or may be constituted by another nonvolatile memory.

  Address decoder 2 designates memory cell transistor MC in accordance with address signal ADD supplied from control circuit 3. Sense voltage application circuit 4 provides normal read potential V1 to the control gate of memory cell transistor MC designated by address decoder 2, and then applies read potential V2 between V1 and VTH0. Sense circuit 5 supplies read data signals DO1, DO2 corresponding to V1, V2 to comparison circuit 6 for each memory cell transistor MC. If the threshold voltage of programmed memory cell transistor MC falls from VTH0 and is between V1 and V2, read data signals DO1 and DO2 are at "L" level and "H" level, respectively.

  Comparison circuit 6 includes N channel MOS transistors 11 and 12 and an EX-OR gate 13 as shown in FIG. N-channel MOS transistor 11 is connected between input node N10 and one input node N11 of EX-OR gate 13, and its gate receives signal RC1. N-channel MOS transistor 12 is connected between input node N10 and the other input node N12 of EX-OR gate 13, and its gate receives signal RC2.

  During a period when read data signal DO1 is applied to input node N10, signal RC1 is set to "H" level for a predetermined time, and read data signal DO1 is latched at node N11. Further, the signal RC2 is set to the “H” level for a predetermined time during the period when the read data signal DO2 is applied to the input node N10, and the read data signal DO2 is latched at the node N12. The EX-OR gate 13 sets the signal PR to the “L” level when the logic levels of the data signals DO1 and DO2 match, and sets the signal PR to “L” when the logic levels of the data signals DO1 and DO2 do not match. Set to “H” level.

  The control circuit 3 gives the next address signal ADD to the address decoder 2 when the signal PR is at “L” level, and after reprogramming the memory cell transistor MC when the signal PR is at “H” level. The next address signal ADD is supplied to the address decoder 2.

  FIG. 5 is a flowchart showing the retention check operation of the flash memory. When the power supply voltage is turned on in FIG. 5, the control circuit 3 stands by in step S1 until the flash memory can be read. In step S2, the control circuit 3 reads the signal ADDS indicating the address at which the retention check is started and the maximum number Nmax of the retention check from the register 7, sets the address signal ADD to ADDS, and sets the number N of the retention check to 1. To do.

  Nmax is set so that the retention check time is within the setup time of the flash memory when the power supply voltage is turned on, and the retention check of all the memory cell transistors MC is completed when the power is turned on a plurality of times. Further, when the memory cell array 1 is divided into a plurality of memory blocks, a retention check of one memory block may be performed every time the power supply voltage is turned on.

  Address signal ADD generated by control circuit 3 is applied to address decoder 2. The address decoder 2 designates one of the memory cell transistors MC in the memory cell array 1 according to the address signal ADD. In step S3, V1 is applied to the control gate of the memory cell transistor MC designated by the address decoder 2, and the data signal DO1 is read and latched in the comparison circuit 6. Next, in step S4, V2 is applied to the control gate of the memory cell transistor MC, and the data signal DO2 is read and latched in the comparison circuit 6.

  In step S5, the comparison circuit 6 determines whether or not the logic levels of the data signals DO1 and DO2 match. If they do not match, the memory cell transistor MC is reprogrammed in step S6 to match. If yes, go to Step S7. By reprogramming the memory cell transistor MC, the threshold voltage which has been lower than V2 is set to VTH0 again.

  In step S7, the control circuit 3 determines whether or not the number N of retention checks is equal to the maximum number Nmax. If N = Nmax is not satisfied, the address signal ADD is incremented and the number N of retention checks is incremented in step S8. Returning to step S3, if N = Nmax, the address ADDS = ADD + 1 at which the next retention check is started is stored in the register 7 in step S9, the retention check mode is terminated, and the standby mode is entered.

  In the first embodiment, two different read potentials V1 and V2 are applied to the control gate of the memory cell transistor MC to read the data signals DO1 and DO2, and if the logic levels of the data signals DO1 and DO2 do not match, Reprogram the memory cell transistor MC. Therefore, as shown in FIG. 6, the threshold voltage of the memory cell transistor MC (the hatched portion in FIG. 6) whose threshold voltage VTH is lower than V2 can be set to VTH0 again. The data retention characteristics can be improved.

  In addition, since the retention check is performed when the power is turned on, the data retention characteristics can be improved without any external operation. Further, since the Nmax number of memory cell transistors MC are collectively checked when the power is turned on, the reading operation can be performed at higher speed than the conventional case where the retention check is performed for each reading operation. Further, since Nmax is set so that the retention check is completed within the setup time when the power is turned on, the setup time does not increase.

  In the first embodiment, the retention check mode is set when the power is turned on, but the retention check mode may be set by an external command signal.

  The flash memory may be a NAND type, a NOR type, or an AND type. Further, as long as the memory stores data by changing the threshold voltage, not only the flash memory but also any memory may be used.

  Further, although the data signals DO1 and DO2 are latched by the N channel MOS transistors 11 and 12, the latch circuit may have any configuration. Further, the latch circuit (N-channel MOS transistor 12) for the second data signal DO2 may be omitted.

[Embodiment 2]
FIG. 7 is a block diagram showing the overall configuration of the flash memory according to the second embodiment of the present invention, and is a diagram compared with FIG. Referring to FIG. 7, this flash memory is different from the flash memory of FIG. 1 in that a register 14 for storing a signal ADD indicating the address of the memory cell transistor MC that needs to be reprogrammed is added. is there. The register 14 outputs an alarm signal AL indicating that there is a memory cell transistor MC that needs to be reprogrammed at the time of status reading. Note that the register 14 may be constituted by a part of the memory cell array 1 or may be constituted by another nonvolatile memory.

  When the logical levels of the data signals VO1 and VO2 read from the memory cell transistor MC do not match, the control circuit 3 stores a signal ADD indicating the address of the memory cell transistor MC in the register 14. When the reprogramming of the memory cell transistor MC is instructed by the external control signal CNT or the like, the control circuit 3 gives the address signal ADD read from the register 14 to the address decoder 2 and the memory cell designated by the address decoder 2 Reprogram transistor MC.

  FIG. 8 is a flowchart showing the retention operation of the flash memory, which is compared with FIG. Referring to FIG. 8, instead of reprogramming memory cell transistor MC in step S6, signal ADD indicating the address of memory cell transistor MC is stored in register 14. In step S10, the alarm signal AL is output.

  In the second embodiment, when the logic levels of the data signals VO1 and VO2 read from the memory cell transistor MC do not match, the signal ADD indicating the address of the memory cell transistor MC is stored in the register 14 and the memory The reprogramming of the cell transistor MC is performed in another period. Therefore, the retention check time can be shortened.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of a flash memory according to Embodiment 1 of the present invention. FIG. FIG. 2 is a diagram showing a memory operation of a memory cell transistor included in the memory cell array shown in FIG. 1. FIG. 2 is a circuit block diagram for explaining a read operation of the flash memory shown in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a comparison circuit illustrated in FIG. 1. 2 is a flowchart showing a retention check operation of the flash memory shown in FIG. It is a figure for demonstrating the effect of the flash memory shown in FIG. It is a block diagram which shows the whole structure of the flash memory by Embodiment 2 of this invention. 8 is a flowchart showing a retention check operation of the flash memory shown in FIG.

Explanation of symbols

  1 memory cell array, 2 address decoder, 3 control circuit, 4 sense voltage application circuit, 5 sense circuit, 6 comparison circuit, 7 and 14 registers, MC memory cell transistor, 11 and 12 N channel MOS transistor, and 13 EX-OR gate.

Claims (6)

A non-volatile semiconductor memory device,
A memory cell array including a plurality of memory cell transistors each assigned a unique address;
A first register for storing an address for starting a retention check;
A decoder that sequentially designates a predetermined number of addresses from the addresses stored in the first register during the retention check mode;
The first voltage, which is a normal read voltage, is applied to the gate of the memory cell transistor at the address specified by the decoder to read the stored data of the memory cell transistor, and the first voltage and the memory cell transistor A read circuit that reads a stored data of the memory cell transistor by applying a second voltage between the threshold voltage and when the memory cell transistor is programmed,
A comparison circuit that compares the logical levels of the two stored data read by applying the first and second voltages and outputs a mismatch signal when they do not match, and the address of the address last specified by the decoder A non-volatile semiconductor memory device comprising: a first write circuit that writes a next address to the first register as an address for starting the retention check.   The nonvolatile semiconductor memory device according to claim 1, further comprising a program circuit that reprograms the memory cell transistor in response to the mismatch signal. And a second register for storing an address of the memory cell transistor to be reprogrammed, and in response to the mismatch signal, the address of the memory cell transistor as the address of the memory cell to be reprogrammed. The nonvolatile semiconductor memory device according to claim 1, further comprising a second write circuit for writing to the register.   The nonvolatile semiconductor memory device according to claim 3, further comprising a program circuit that reprograms the memory cell transistor at the address stored in the second register in response to an instruction to reprogram.   5. The nonvolatile semiconductor memory device according to claim 1, further comprising a setting circuit that sets the retention check mode in response to a power supply voltage being turned on. A non-volatile semiconductor memory device,
A memory cell array including a plurality of memory cell transistors;
A decoder for sequentially designating the plurality of memory cell transistors in response to power supply voltage being applied;
The first voltage, which is a normal read voltage, is applied to the gate of the memory cell transistor designated by the decoder to read the stored data of the memory cell transistor, and the first voltage and the memory cell transistor are programmed. A read circuit for reading the stored data of the memory cell transistor by applying a second voltage between the threshold voltage and the two voltages read by applying the first and second voltages A nonvolatile semiconductor memory device comprising a comparison circuit that compares the logical levels of stored data and outputs a mismatch signal if they do not match.

Images