JP2006325308A - Step-down switching regulator, its control circuit, and electronic apparatus employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous rectification step-down switching regulator in which deterioration in efficiency due to reversal of a current flowing through an inductor is prevented. <P>SOLUTION: A driver circuit 10 creates first and second gate voltages Vg1 and Vg2 of a switching transistor M1 and a synchronous rectification transistor M2 based on a PWM signal Vpwm output from a PWM control section 20. A comparing section 30 outputs a high level comparison signal Vcmp when a switching voltage Vsw exceeds a ground voltage. A forced off switch SW1 is provided with the gate voltage Vg2 and when the output from the comparing section 30 goes high, the output voltage Vg2' is fixed to a low level. The output voltage Vg2' from the forced off switch SW1 is inputted to the gate terminal of an auxiliary transistor M3 connected in parallel with the synchronous rectification transistor M2. A delay circuit 60 imparts a predetermined delay to the output voltage Vg2' from the forced off switch SW1 and provides an output signal to the gate terminal of the synchronous rectification transistor M2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a step-down switching regulator, and more particularly to a control technology for a synchronous rectification switching regulator.

Various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years are equipped with microcomputers that perform digital signal processing. The power supply voltage required for driving such a microcomputer has been reduced with the miniaturization of the semiconductor manufacturing process, and there is one that operates at a low voltage of 1.5 V or less.
On the other hand, a battery such as a lithium ion battery is mounted on such an electronic device as a power source. The voltage output from the lithium ion battery is about 3V to 4V. If this voltage is supplied to the microcomputer as it is, useless power consumption occurs. Therefore, a step-down switching regulator or a series regulator is used. In general, the battery voltage is stepped down to a constant voltage and supplied to a microcomputer.

  As a step-down switching regulator, there are a method using a rectifying diode (hereinafter referred to as a diode rectifying method) and a method using a rectifying transistor instead of a diode (hereinafter referred to as a synchronous rectifying method). In the former case, there is an advantage that high efficiency can be obtained when the load current flowing through the load is low. However, since a diode in addition to the inductor and the capacitor is required outside the control circuit, the circuit area becomes large. In the latter case, the efficiency when the current supplied to the load is small is inferior to that of the former, but since a transistor is used instead of a diode, it can be integrated inside the LSI, and the circuit area including peripheral components As a result, downsizing is possible. When an electronic device such as a cellular phone is required to be downsized, a switching regulator using a rectifying transistor (hereinafter referred to as a synchronous rectification switching regulator) is often used.

Here, the current consumption of the microcomputer used in the above-described electronic device varies greatly between operation and standby, and only a small amount of current flows during standby, but a certain amount of current is required during operation.
For example, Patent Documents 1 and 2 disclose switching regulators that switch between a synchronous rectification method and a diode rectification method according to a load current.

JP 2004-32875 A JP 2002-252971 A

  FIGS. 9A and 9B are diagrams showing current time waveforms of heavy and light loads of the synchronous rectification switching regulator, respectively. In the figure, IL represents the current flowing through the inductor, Io represents the load current, and the time average value of the current IL flowing through the inductor is the load current Io. As shown in FIG. 9A, at heavy load, the load current Io is large, so the current flowing through the inductor continues to take a positive value. However, as shown in FIG. 9B, when the load current Io decreases at the time of light load, the current IL flowing through the inductor becomes negative as indicated by the shaded portion, and the direction of the current IL flowing through the inductor is reversed. As a result, in the synchronous rectification method, a current flows from the inductor to the ground through the synchronous rectification transistor at light load. Since this current is not supplied to the load but supplied from the output capacitor, power is wasted.

In order to solve this problem, the current flowing through the inductor is monitored by monitoring the potential at the connection point between the synchronous rectification transistor and the inductor (hereinafter referred to as switching voltage) and comparing this switching voltage with a predetermined threshold voltage. A method for detecting the orientation of the camera is conceivable.
According to this method, the synchronous rectification transistor is forcibly turned off when the switching voltage exceeds the threshold voltage set near the ground potential during the period in which the synchronous rectification transistor is on. Current consumption can be reduced and efficiency can be improved.

As a result of studying a switching regulator that monitors the switching voltage as described above, detects that the direction of the current flowing through the inductor is reversed, and turns off the synchronous rectification transistor, the inventor recognizes the following problems. It came to.
That is, when the switching voltage is monitored and the direction of the current flowing through the inductor is detected, a comparator that compares the switching voltage with a predetermined threshold voltage is used, and the synchronous rectification transistor is turned on / off based on the output of the comparator. To control. At this time, there may be a delay from when the switching voltage reaches the threshold value and the current flowing through the inductor is inverted until the synchronous rectification transistor is turned off. In this delay period, a wasteful current flows through the synchronous rectification transistor, so there is room for further improvement in efficiency.

  The present invention has been made in view of such a problem, and the object thereof is to reduce the current flowing to the ground via the synchronous rectification transistor in a synchronous rectification step-down switching regulator and improve the efficiency. The present invention provides a step-down switching regulator and a driving circuit thereof.

  A control circuit according to an aspect of the present invention relates to a control circuit for a step-down switching regulator. The control circuit includes a switching transistor and a synchronous rectification transistor connected in series between the input terminal and the ground, and an inductor connected to the outside of the control circuit using a voltage at a connection point of the two transistors as a switching voltage. Applied to one end of the switching transistor and the gate terminal of the switching transistor and the synchronous rectification transistor based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator approaches a predetermined reference voltage The driver circuit that generates the first and second gate voltages to be compared with the switching voltage and a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the switching voltage exceeds the predetermined threshold voltage The comparison unit and the second gate voltage output from the driver circuit are input, and the comparison unit During the period when the comparison signal of a predetermined level is output, the switch that outputs the second gate voltage fixed to the low level and the output signal of the switch are input to the gate terminal and connected in parallel with the synchronous rectification transistor An auxiliary transistor, and a delay circuit that gives a predetermined delay time to the output signal of the switch and outputs the delayed signal to the gate terminal of the synchronous rectification transistor.

  According to this aspect, when the second gate voltage becomes a high level, the auxiliary transistor is first turned on, and then the synchronous rectification transistor is turned on after a predetermined delay time has elapsed. When only the auxiliary transistor is on, the switching voltage is determined by the drain-source voltage of the auxiliary transistor, that is, the product of the on-resistance and the current flowing through the inductor. The switching voltage increases as the current flowing through the inductor decreases from a negative potential. At this time, if the on-resistance of the auxiliary transistor is high, the increasing speed of the switching voltage can be increased. As a result, the time from when the switching voltage reaches a predetermined threshold voltage to when the synchronous rectification transistor is turned off can be shortened, wasteful current consumption can be reduced, and high efficiency can be achieved.

The on-resistance of the auxiliary transistor may be set higher than the on-resistance of the synchronous rectification transistor.
By setting the on-resistance of the auxiliary transistor high, the speed at which the switching voltage rises after the synchronous rectification transistor is turned on can be increased, and the time until the synchronous rectification transistor is turned off is shortened, resulting in higher efficiency. Can be achieved.

  The predetermined threshold voltage may be a ground potential. When the auxiliary transistor is turned on and the switching voltage rises from the negative voltage and reaches the ground potential, the direction of the current flowing through the inductor is reversed. Therefore, the wasteful current consumption is reduced by comparing the switching voltage and the ground potential. be able to.

The comparison unit includes a level shift circuit that level-shifts the switching voltage and the threshold voltage by a predetermined voltage in the positive direction, and a comparator that compares the switching voltage level-shifted by the level shift circuit with the threshold voltage. But you can.
By comparing the switching voltage and the threshold voltage by level shifting in the positive direction, even when the threshold voltage is the ground potential, the comparator can be used for voltage comparison.

In the level shift circuit, a switching voltage is input to a base terminal, a collector terminal is grounded, a PNP-type first bipolar transistor that outputs a voltage obtained by level shifting the switching voltage from an emitter terminal, and a base terminal and a collector terminal are grounded. And a PNP-type second bipolar transistor that outputs a voltage obtained by level shifting the ground potential from the emitter terminal.
By using the forward voltage between the base and emitter of the PNP type bipolar transistor, the switching voltage and the threshold voltage can be level shifted in the positive direction.

The control circuit is provided at the subsequent stage of the comparison unit, and becomes active when the second gate voltage output from the driver circuit is at a high level, latches the comparison signal output from the comparison unit, and outputs it as a detection signal to the switch. A latch circuit may be further provided. The switch may fix and output the second gate voltage at a low level during a period when the detection signal output from the latch circuit, not the comparison signal, is at a predetermined level.
When the synchronous rectification transistor is switched from on to off, oscillation of the switching voltage may be induced by the inductor. By providing a latch circuit at the subsequent stage of the comparison unit, the synchronous rectification transistor can be kept off even when the switching voltage oscillates across the threshold voltage, and the step-down switching regulator operates stably. be able to.

The latch circuit may reset the latched detection signal when the second gate voltage changes from a high level to a low level.
By referring to the second gate voltage and resetting the detection signal when the period for turning on the synchronous rectification transistor is completed, the above-described latch operation is performed again in the next period for turning on the synchronous rectification transistor. It can be performed.

  The latch circuit includes a D flip-flop. The D flip-flop has a second gate voltage input to the reset terminal, a high-level fixed voltage input to the data terminal, and a comparison signal output from the comparison unit to the clock terminal. May be input.

The latch circuit may further include an OR gate that outputs a logical sum of the output signal of the D flip-flop and the comparison signal output from the comparison unit, and may output the output signal of the OR gate as a detection signal.
According to this, even if the comparison signal output from the comparison unit fluctuates once the D flip-flop is latched, the output of the OR gate is fixed to the output signal of the D flip-flop. It can be performed.

The synchronous rectification transistor may be an NMOS transistor.
The control circuit may be integrated on a single semiconductor substrate.

  Another aspect of the present invention is a step-down switching regulator. This step-down switching regulator includes a capacitor having one end grounded, an inductor having one end connected to the other end of the capacitor, and the above-described control circuit that supplies a switching voltage to the other end of the inductor. The voltage at the other end is output.

  According to this aspect, since the synchronous rectification transistor can be turned off in a short period after the control circuit detects that the direction of the current flowing through the inductor is reversed, the efficiency of the step-down switching regulator can be improved. it can.

  Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery that outputs a battery voltage, a microcomputer, and the above-described step-down switching regulator that steps down the battery voltage and supplies the voltage to the microcomputer.

  According to this aspect, even when the current flowing through the microcomputer fluctuates and the load current is small and the load operation is small, the step-down operation can be performed efficiently, and the battery life can be extended.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the step-down switching regulator according to the present invention, the conversion efficiency can be improved.

FIG. 1 is a block diagram illustrating a configuration of an electronic device 300 in which a step-down switching regulator 200 according to an embodiment is mounted. The electronic device 300 is, for example, a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360.
The battery 310 is a lithium ion battery, for example, and outputs about 3 to 4 V as the battery voltage Vbat.
The analog circuit 330 includes high-frequency circuits such as a power amplifier, an antenna switch, an LNA (Low Noise Amplifier), a mixer, and a PLL (Phase Locked Loop), and includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. . The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V.
The microcomputer 350 is a block that comprehensively controls the entire electronic device 300 and operates with a power supply voltage of 1.5V.
The LED 360 includes RGB three-color LEDs (Light Emitting Diodes) and is used as a liquid crystal backlight or illumination, and a driving voltage of 4 V or more is required for driving.

The power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel. For the analog circuit 330, the digital circuit 340, the microcomputer 350, and the LED 360, Supply an appropriate power supply voltage.
The step-down switching regulator according to the present embodiment is suitably used for driving a stable voltage with respect to a load whose current consumption changes according to an operating state, such as a microcomputer 350 that operates at 1.5 V. It is done. Hereinafter, the configuration of the step-down switching regulator according to the present embodiment will be described in detail.

FIG. 2 is a circuit diagram showing a configuration of the step-down switching regulator 200 according to the embodiment. The step-down switching regulator 200 is a synchronous rectification step-down switching regulator, and includes a control circuit 100, an inductor L1, and an output capacitor C1. The control circuit 100 is an LSI chip integrated on a single semiconductor substrate, and a switching transistor M1, a synchronous rectification transistor M2, and an auxiliary transistor M3 functioning as switching elements are built in the control circuit 100.
The output capacitor C1 has one end grounded and the other end connected to the load circuit RL and the inductor L1. The inductor L1 is connected to the control circuit 100 and applied with the switching voltage Vsw.

The step-down switching regulator 200 controls the current flowing through the inductor L1 by the control circuit 100, steps down the battery voltage Vbat by charging the output capacitor C1, and supplies the voltage appearing at the output capacitor C1 to the load circuit RL. To do. In the present embodiment, the load circuit RL corresponds to the microcomputer 350 in FIG.
Hereinafter, a voltage supplied to the load circuit RL is referred to as an output voltage Vout, a current flowing through the load circuit RL is referred to as a load current Io, and a current flowing through the inductor L1 is referred to as IL. Further, the direction of the current flowing through the inductor L1 toward the load circuit RL is a positive direction.

  The control circuit 100 includes an input terminal 102, a switching terminal 104, and an output terminal 106 as input / output terminals. A battery 310 is connected to the input terminal 102, and a battery voltage Vbat is input as an input voltage. The switching terminal 104 is connected to the inductor L1 and outputs a switching voltage Vsw generated inside the control circuit 100. The output terminal 106 is a terminal to which the output voltage Vout applied to the load circuit RL is fed back.

  The control circuit 100 includes a driver circuit 10, a PWM control unit 20, a comparison unit 30, a delay circuit 60, a forced off switch SW1, a switching transistor M1, a synchronous rectification transistor M2, and an auxiliary transistor M3.

The switching transistor M1 is a P-channel MOS transistor, and has a source terminal connected to the input terminal 102 and a drain terminal connected to the switching terminal 104. The back gate terminal of the switching transistor M1 is connected to the input terminal 102, and a body diode (parasitic diode) D1 exists between the back gate terminal and the drain terminal.
The synchronous rectification transistor M2 is an N-channel MOS transistor, the source terminal is grounded, and the drain terminal is connected to the drain terminal of the switching transistor M1 and the switching terminal 104. The back gate terminal of the synchronous rectification transistor M2 is grounded. A body diode D2 exists between the back gate terminal and the drain terminal of the synchronous rectification transistor M2.

The switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the input terminal 102 to which the battery voltage Vbat is applied and the ground, and the control circuit 100 uses the voltage at the connection point of the two transistors as the switching voltage Vsw. Is applied to one end of an inductor L1 connected to the outside via a switching terminal 104.
The auxiliary transistor M3 is connected in parallel with the synchronous rectification transistor M2, and is turned on / off in synchronization with the synchronous rectification transistor M2, as will be described later. The on-resistance Ron3 of the auxiliary transistor M3 is set higher than the on-resistance Ron2 of the synchronous rectification transistor M2.

The PWM control unit 20 controls a pulse width modulation signal (hereinafter referred to as “duty ratio”) that defines the duty ratio of the ON period of the switching transistor M1 and the synchronous rectification transistor M2 so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined reference voltage. A PWM signal). The output voltage Vout of the step-down switching regulator 200 is input to the PWM control unit 20 via the output terminal 106.
The resistors R1 and R2 divide the output voltage Vout, and output the output voltage Vout ′ multiplied by R2 / (R1 + R2) to the inverting input terminal of the error amplifier 22. The reference voltage Vref is input to the non-inverting input terminal of the error amplifier 22, and an error between the output voltage Vout ′ and the reference voltage Vref is amplified and output as an error voltage Verr.

  The oscillator 26 oscillates at a predetermined frequency and outputs a periodic voltage Vosc having a triangular wave shape or a sawtooth wave shape. The first comparator 24 compares the periodic voltage Vosc and the error voltage Verr, and outputs a PWM signal Vpwm that is at a high level when Vosc> Verr and is at a low level when Vosc <Verr. This PWM signal Vpwm is a pulse width modulated signal having a constant cycle time and a period of high level and low level changing according to the output voltage Vout ′.

  Based on the PWM signal Vpwm output from the PWM controller 20, the driver circuit 10 applies a first gate voltage Vg1 to be applied to the gate terminal of the switching transistor M1 and a second terminal to be applied to the gate terminal of the synchronous rectification transistor M2. A gate voltage Vg2 is generated. The switching transistor M1 is turned on when the first gate voltage Vg1 is at a low level and turned off when the first gate voltage Vg1 is at a high level. The synchronous rectification transistor M2 is turned on when the second gate voltage Vg2 is at a high level, and turned off when the second gate voltage Vg2 is at a low level. The driver circuit 10 sets the ratio of the time during which the switching transistor M1 and the synchronous rectification transistor M2 are turned on based on the high-level and low-level duty ratios of the PWM signal Vpwm, and turns the two transistors on and off alternately. In order to prevent the switching transistor M1 and the synchronous rectification transistor M2 from being simultaneously turned on and a through current from flowing therethrough, the driver circuit 10 has a period in which the first gate voltage Vg1 is at a high level and the second gate voltage Vg2 is at a low level ( Dead time) is provided for each period.

The comparison unit 30 receives the switching voltage Vsw. The comparison unit 30 compares the switching voltage Vsw and the ground potential, and outputs a high level comparison signal Vcmp when the switching voltage Vsw exceeds the ground potential.
The comparison unit 30 receives the switching voltage Vsw. The comparison unit 30 includes a level shift circuit 32 and a second comparator 34, compares the switching voltage Vsw with the ground potential, and outputs a high level comparison signal Vcmp when the switching voltage Vsw exceeds the ground potential.

The level shift circuit 32 includes PNP-type first and second bipolar transistors Q1 and Q2, and a switching voltage Vsw and a ground potential GND are input to respective base terminals. The collector terminals of the bipolar transistors Q1 and Q2 are grounded, and the emitter terminal outputs a voltage in which the switching voltage Vsw and the ground potential are level-shifted in the forward direction by a forward voltage Vf = 0.7V. .
The non-inverting input terminal of the second comparator 34 is connected to the emitter terminal of the first bipolar transistor Q1, and the inverting input terminal is connected to the emitter terminal of the second bipolar transistor Q2. The switching voltage Vsw level-shifted by the second comparator 34 and the level shift circuit 32 is compared with the ground potential, and a high level is output when Vsw> 0V and a low level is output when Vsw <0V.

  The second gate voltage Vg2 output from the driver circuit 10 is input to the forced off switch SW1. The forced-off switch SW1 outputs either the second gate voltage Vg2 or the low level based on the comparison signal Vcmp output from the comparison unit 30. The forced off switch SW1 outputs a low level when the comparison signal Vcmp output from the comparison unit 30 is at a high level, and is input from the driver circuit 10 during other periods, that is, when the comparison signal Vcmp is at a low level. The second voltage Vg2 is output as it is. Hereinafter, the output signal output from the forced-off switch SW1 is denoted as Vg2 '.

FIG. 3 is a circuit diagram showing a configuration example of the forced-off switch SW1. The forced off switch SW1 includes an inverter 50 and a NOR gate 52. The second gate voltage Vg2 output from the driver circuit 10 is input to the input terminal of the inverter 50. The inverter 50 inverts the second gate voltage Vg <b> 2 and outputs it to the first input terminal of the NOR gate 52. The detection signal Vsens output from the latch circuit 40 is input to the second input terminal of the NOR gate 52. The forced off switch SW1 outputs the output signal of the NOR gate 52 as Vg2 ′.
According to the forced off switch SW1 configured in this way, the output voltage Vg2 ′ of the forced off switch SW1 is at a high level only when the second gate voltage Vg2 is at a high level and the comparison signal Vcmp is at a low level. During the other period, the output voltage Vg2 ′ of the forced off switch SW1 is at a low level.

The output voltage Vg2 ′ of the forced off switch SW1 is output to the gate terminal of the auxiliary transistor M3 and the delay circuit 60.
The delay circuit 60 gives a predetermined delay time to the output voltage Vg2 ′ of the forced off switch SW1 and outputs it to the gate terminal of the synchronous rectification transistor M2. The delay circuit 60 outputs a voltage Vg2 ″ which becomes high level after a predetermined delay time τ elapses from the rise of the voltage Vg2 ′ and becomes low level simultaneously with the fall of the voltage Vg2 ′. The delay time τ is set to about 1/10 of the on period of the synchronous rectification transistor M2, for example. Since such a delay circuit 60 can be easily configured using a known technique, a detailed description thereof is omitted.

Hereinafter, the operation at the time of heavy load and light load of the control circuit 100 according to the present embodiment will be described with reference to FIGS.
FIG. 4 is a time chart showing an operation state when the control circuit 100 according to the present embodiment is under heavy load. The time chart of FIG. 4 explains the operation at the time of heavy load with a large load current Io, and represents the operation when the current IL flowing through the inductor L1 is in the positive direction while the synchronous rectification transistor M2 is on. ing.
When the first gate voltage Vg1 is at a high level, the switching transistor M1 is turned off, and when the first gate voltage Vg1 is at a low level, the switching transistor M1 is turned on. That is, in the figure, Ton1 indicates a period during which the switching transistor M1 is on.

  The second gate voltage Vg <b> 2 indicates a voltage to be applied to the synchronous rectification transistor M <b> 2 generated by the driver circuit 10. In the drawing, the second gate voltage Vg2 ″ indicates the voltage actually applied to the gate terminal of the synchronous rectification transistor M2. When the second gate voltage Vg2 ″ is at a high level, the synchronous rectification transistor M2 is turned on, and when the second gate voltage Vg2 ″ is at a low level, the synchronous rectification transistor M2 is turned off. In the figure, Ton2 indicates a period during which the synchronous rectification transistor M2 is on. Further, in the figure, the second gate voltage Vg2 'indicates a voltage applied to the gate terminal of the auxiliary transistor M3, and Ton3 indicates a period during which the auxiliary transistor M3 is on.

  As described above, the second gate voltage Vg2 output from the driver circuit 10 is once input to the forced-off switch SW1, and Vg2 ′ = Vg2 while the comparison signal Vcmp output from the comparison unit 30 is at the low level. It becomes. During the period when the comparison signal Vcmp is at the high level, the output voltage Vg2 ′ of the forced off switch SW1 is at the low level (0V) regardless of the value of the gate voltage Vg2 output from the driver circuit 10, and the synchronous rectification transistor M2, The auxiliary transistor M3 is forcibly turned off.

  During the period of time T0 to T1, the switching transistor M1 is on and the synchronous rectification transistor M2 is off. At time T1, the first gate voltage Vg1 of the switching transistor M1 becomes high level, and the switching transistor M1 is turned off. Thereafter, both the switching transistor M1 and the synchronous rectification transistor M2 are turned off during the period of time T1 to T2. When the switching transistor M1 is turned off at time T1, the current that has been flowing through the inductor L1 until then is not supplied from the switching transistor M1.

  Here, since the current IL flowing through the inductor L1 must be continuous, this current is supplied via the body diodes (parasitic diodes) D2 and D3 of the synchronous rectification transistor M2 and the auxiliary transistor M3. That is, the back gate terminals of the synchronous rectification transistor M2 and the auxiliary transistor M3 are grounded, and the body diodes D2 and D3 shown in FIG. 2 exist between the back gate terminal and the drain terminal. Accordingly, during the period from when the switching transistor M1 is turned off at time T1 to when the auxiliary transistor M3 is turned on at time T2, current is supplied to the inductor L1 via the body diodes D2 and D3. During this time, a switching voltage Vsw that is lower than the ground potential 0V by about a diode forward voltage Vf = 0.7V appears at the switching terminal 104.

At time T2, the second gate voltage Vg2 changes from the low level to the high level. At this time, since the comparison voltage Vcmp is at a low level, the output voltage Vg2 ′ of the forced-off switch SW1 is at a high level, and the auxiliary transistor M3 is turned on. When the auxiliary transistor M3 is turned on, the current flowing through the inductor L1 via the synchronous rectification transistor M2 and the body diodes D2 and D3 of the auxiliary transistor M3 is supplied as the drain current of the auxiliary transistor M3.
At this time, the switching voltage Vsw is given by the product of the current IL flowing through the inductor L1 and the on-resistance Ron3 of the auxiliary transistor M3, and approaches 0 V as the current IL flowing through the inductor L1 decreases with time. To go. The slope of the increase of the switching voltage Vsw at this time depends on the on-resistance of the auxiliary transistor M3.

After the output voltage Vg2 ′ of the forced-off switch SW1 becomes high level at time T2, the output voltage Vg2 ″ of the delay circuit 60 becomes high level at time T3 after the delay time τ elapses, and the synchronous rectification transistor M2 is turned on. Turn on.
After time T3, the auxiliary transistor M3 and the synchronous rectification transistor M2 are simultaneously turned on, whereby the current IL flowing through the inductor L1 is supplied via these two transistors. As a result, the rising slope of the switching voltage Vsw is determined by the combined resistance of the on-resistances Ron2 and Ron3 of the two transistors. Therefore, when the synchronous rectification transistor M2 is turned on at time T3, the rising speed of the switching voltage Vsw is reduced. As described above, in the time chart of FIG. 4, since the current flowing through the inductor L1 is in the positive direction, the switching voltage Vsw does not become a positive voltage during the period in which the synchronous rectification transistor M2 is on. The comparison signal Vcmp is low level.

When the second gate voltage Vg2 output from the driver circuit 10 becomes low level at time T4, the voltages Vg2 ′ and Vg2 ″ output from the forced-off switch SW1 and the delay circuit 60 also become low level, and the synchronous rectification transistor M2 The auxiliary transistor M3 is turned off. Thereafter, at time T5, the first gate voltage Vg1 output from the driver circuit 10 becomes low level, and the switching transistor M1 is turned on.
100 according to the present embodiment sets the operation from time T0 to T5 as one cycle under heavy load, and by repeating this operation, the battery voltage Vbat is stepped down and the desired output voltage Vout is supplied to the load circuit RL. Supply.

Next, the operation at light load will be described with reference to FIG. FIG. 5 is a time chart showing the operating state of the control circuit 100 according to the present embodiment at light load.
The operation from time T0 to T2 is the same as that at the time of heavy load in FIG. When the second gate voltage Vg2 output from the driver circuit 10 becomes high level at time T2, only the auxiliary transistor M3 is turned on, and the switching voltage Vsw starts increasing with a large slope.

When Vsw> 0V is satisfied at time T3, the second comparator 34 performs voltage detection.
In general, the response speed of the comparator changes according to the change speed of the input voltage. 6A and 6B are diagrams for explaining the response speed of the comparator. FIG. 6A shows time waveforms of two input voltages Vi that change at different speeds. FIG. 6B shows a time waveform of the output voltage Vo corresponding to each waveform of FIG. As indicated by broken lines in FIGS. 6A and 6B, when the rate of change of the input voltage Vi with time is low (II), the output voltage Vo after the input voltage Vi exceeds the threshold voltage Vth of the comparator. The time Δt required to change becomes longer. On the other hand, as shown by the solid lines in FIGS. 6A and 6B, when the rate of time change of the input voltage Vi is high (I), the input voltage Vi exceeds the threshold voltage Vth. After that, the time Δt ′ until the output voltage Vo of the comparator changes is shortened, and the detection speed is increased.

  Returning to FIG. As described above, only the auxiliary transistor M3 is turned on before the delay time τ elapses after the second gate voltage Vg2 output from the driver circuit 10 changes from low level to high level at time T2, and the switching voltage Vsw rises with a large slope. After Vsw> 0 at time T3, the comparison signal Vcmp output from the second comparator 34 changes to high level at time T3 ′ after the detection delay time Δt by the comparator has elapsed.

  When the comparison voltage Vcmp output from the comparison unit 30 becomes high level at time T3 ', the output voltage Vg2' of the forced-off switch SW1 is forcibly fixed at low level, and the auxiliary transistor M3 is turned off. At this time, since the switching transistor M1, the synchronous rectification transistor M2, and the auxiliary transistor M3 are all turned off, the high impedance state is entered, the switching voltage Vsw fluctuates, and when the switching transistor M1 is turned on at time T5, the battery voltage Vbat is stabilized. To do.

As described above, according to the present embodiment 100, at the time of light load, the operation from time T0 to T5 is set as one cycle, and by repeating this operation, the battery voltage Vbat is stepped down and the desired output voltage Vout is loaded. Supply to the circuit RL.
According to the control circuit 100 according to the present embodiment, the switching voltage Vsw is monitored, and when the switching voltage Vsw becomes larger than 0V during the period in which the synchronous rectification transistor M2 is to be turned on, the synchronous rectification transistor M2 is forcibly set. Turn off. As a result, the direction of the current IL flowing through the inductor L1 at the time of a light load is reversed, and the current IL can be prevented from flowing toward the ground via the synchronous rectification transistor M2, and deterioration in efficiency can be suppressed.

  At this time, if the detection delay time Δt shown in FIG. 5 is long, the switching voltage Vsw becomes a positive voltage, the direction of the current IL flowing through the inductor L1 is reversed from positive to negative, and the synchronous rectification transistor M2 or the auxiliary transistor M3 It flows toward the ground via, and the efficiency deteriorates. In the control circuit 100 according to the present embodiment, after the switching transistor M1 is turned off, the switching voltage Vsw is increased with a large slope while only the auxiliary transistor M3 is turned on. The detection delay time Δt can be set shorter than when the switching voltage Vsw is increased with M2 turned on. As a result, the current IL flowing through the inductor L1 becomes negative, and the time for flowing toward the ground can be shortened, so that the efficiency can be improved.

  Further, since the on-resistance Ron3 of the auxiliary transistor M3 is set lower than the on-resistance Ron2 of the synchronous rectifying transistor M2, the transistor size of the auxiliary transistor M3 can be designed to be small. The increase in the chip size of the control circuit 100 due to the provision can be suppressed.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  FIG. 7 is a circuit diagram showing a modification of the control circuit 100 of FIG. The control circuit 100 includes a latch circuit 40 that latches the comparison signal Vcmp at the subsequent stage of the comparison unit 30 shown in FIG.

  The latch circuit 40 receives the second gate voltage Vg2 output from the driver circuit 10 and the comparison signal Vcmp output from the comparison unit 30. The latch circuit 40 is active during a period in which the synchronous rectification transistor M2 is to be turned on, that is, a period during which the second gate voltage Vg2 output from the driver circuit 10 is at a high level, and the comparison signal Vcmp output from the comparison unit 30. Are latched, and the latched signal is output as the detection signal Vsens. The latch circuit 40 resets the latched detection result when the second gate voltage Vg2 changes from the high level to the low level.

  The latch circuit 40 includes a D flip-flop 42, an OR gate 44, a NOR gate 46, and an inverter 48. The power supply voltage Vdd corresponding to the high level is input to the set terminal and the data terminal of the D flip-flop 42, and the reset terminal is connected to the output of the NOR gate 46. The NOR gate 46 receives the second gate voltage Vg2 inverted by the inverter 48 and the enable signal EN given from the outside, and outputs the negative logical sum of the two signals to the reset terminal of the D flip-flop 42. The enable signal EN is a signal that controls the step-down operation of the step-down switching regulator 200, and the step-down switching regulator 200 performs the step-down operation when the enable signal EN is at a low level and stops the step-down operation when the enable signal EN is at a high level. Low.

The comparison signal Vcmp output from the comparison unit 30 is input to the clock terminal of the D flip-flop 42. The D flip-flop 42 outputs a high-level output signal Vq from the output terminal when the comparison signal Vcmp output from the comparison unit 30 becomes high level while the second gate voltage Vg2 is high level.
The OR gate 44 receives the comparison signal Vcmp output from the comparison unit 30 and the output signal Vq of the D flip-flop 42, and outputs the logical sum of the two signals to the forced-off switch SW1 as the detection signal Vsens. Note that the output signal Vq of the D flip-flop 42 may be directly output to the forced-off switch SW1 without providing the OR gate 44.

The operation of the control circuit 100 configured as described above will be described. FIG. 8 is a time chart showing an operation state of the control circuit 100 of FIG. The operations from time T0 to time T3 ′ are the same as those in FIG.
When the comparison signal Vcmp output from the comparison unit 30 becomes high level at time T3 ′, the output voltage Vg2 ′ of the forced off switch SW1 is forcibly fixed at low level, and the auxiliary transistor M3 is turned off. At this time, since the switching transistor M1, the synchronous rectification transistor M2, and the auxiliary transistor M3 are all turned off, the high-impedance state occurs and the switching voltage Vsw varies. At this time, as shown in FIG. 8, when the switching voltage Vsw fluctuates across the ground potential 0V, the comparison signal Vcmp also switches between the high level and the low level.

  Here, as described above, the control circuit 100 in FIG. 7 controls the forced-off switch SW1 based on the logical sum of the outputs of the comparison unit 30 and the D flip-flop 42. Therefore, even if the signal level of the comparison signal Vcmp fluctuates, the output signal Vq of the D flip-flop 42 is latched at a high level, so the output of the OR gate 44, that is, the detection signal Vsens remains at a high level. As a result, the auxiliary transistor M3 and the synchronous rectification transistor M2 can be kept off regardless of the change in the switching voltage Vsw.

  At time T4, the driver circuit 10 switches the second gate voltage Vg2 to a low level. When the second gate voltage Vg2 becomes low level, the output of the NOR gate 46 becomes low level, so that the D flip-flop 42 is reset and the output signal Vq becomes low level. Thereafter, at time T5, the first gate voltage Vg1 becomes low level, and the switching transistor M1 is turned on.

The control circuit 100 according to the embodiment shown in FIG. 7 repeats this operation with time T0 to T5 as one cycle, thereby stepping down the battery voltage Vbat and supplying the desired output voltage Vout to the load circuit RL. .
According to the control circuit 100 according to the present embodiment, the following effects can be obtained in addition to the effects obtained by the control circuit 100 of FIG. That is, the control circuit 100 of FIG. 7 includes a latch circuit 40, and latches the comparison signal Vcmp that becomes high level when the switching voltage Vsw becomes higher than 0V. As a result, even when the switching voltage Vsw fluctuates over 0 V, the output of the forced off switch SW1 is not switched, and the synchronous rectification transistor M2 can continue to be kept off and perform a stable step-down operation. Can do.

  In the embodiment, the microcomputer is described as an example of the load circuit driven by the step-down switching regulator 200 including the control circuit 100. However, the present invention is not limited to this, and the load circuit is reduced, and various operations can be performed in a light load state. A driving voltage can be supplied to a simple load circuit.

  Further, in the present embodiment, the setting of high level and low level logical values is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  In the embodiment, the case where the control circuit 100 is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are provided as discrete elements or chip components outside the LSI. Or you may comprise by several LSI.

It is a block diagram which shows the structure of the electronic device carrying the pressure | voltage fall type switching regulator which concerns on embodiment. 1 is a circuit diagram showing a configuration of a step-down switching regulator according to an embodiment. It is a circuit diagram which shows the structural example of a forced off switch. It is a time chart which shows the operation state at the time of heavy load of the control circuit which concerns on this Embodiment. It is a time chart which shows the operation state at the time of light load of the control circuit which concerns on this Embodiment. 6A and 6B are diagrams for explaining the response speed of the comparator. FIG. 3 is a circuit diagram showing a modification of the control circuit of FIG. 2. It is a time chart which shows the operation state of the control circuit of FIG. FIGS. 9A and 9B are diagrams showing current time waveforms of heavy and light loads of the synchronous rectification switching regulator, respectively.

Explanation of symbols

  100 control circuit, 200 step-down switching regulator, 10 driver circuit, 30 comparison unit, 32 level shift circuit, 38 delay circuit, 40 latch circuit, 42 D flip-flop, 44 OR gate, 60 delay circuit, L1 inductor, Vg2 second Gate voltage, Vsw switching voltage, M1 switching transistor, M2 synchronous rectification transistor, M3 auxiliary transistor, 300 electronic device, 310 battery, 350 microcomputer.

Claims (13)

A step-down switching regulator control circuit,
A switching transistor connected in series between the input terminal and the ground, and a synchronous rectification transistor, and the voltage at the connection point of the two transistors is connected to one end of the inductor connected to the outside of the control circuit as a switching voltage An applied output stage;
First and second to be applied to the gate terminals of the switching transistor and the synchronous rectification transistor based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator approaches a predetermined reference voltage. A driver circuit for generating a two-gate voltage;
A comparator that compares the switching voltage with a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the switching voltage exceeds the threshold voltage;
A switch for outputting the second gate voltage fixed to a low level during a period in which the second gate voltage output from the driver circuit is input and the comparison signal of the predetermined level is output from the comparison unit;
An auxiliary transistor connected to the synchronous rectification transistor in parallel with the output signal of the switch at the gate terminal;
A delay circuit that gives a predetermined delay time to the output signal of the switch, and outputs it to the gate terminal of the synchronous rectification transistor;
A control circuit comprising:   The control circuit according to claim 1, wherein an on-resistance of the auxiliary transistor is set higher than an on-resistance of the synchronous rectification transistor.   The control circuit according to claim 1, wherein the predetermined threshold voltage is a ground potential. The comparison unit includes:
A level shift circuit for level-shifting the switching voltage and the threshold voltage by a predetermined voltage in the positive direction;
A comparator that compares the switching voltage level-shifted by the level shift circuit with the threshold voltage;
The control circuit according to claim 1, comprising: The level shift circuit includes:
A PNP-type first bipolar transistor that inputs the switching voltage to a base terminal, grounds a collector terminal, and outputs a voltage obtained by level shifting the switching voltage from an emitter terminal;
A PNP-type second bipolar transistor that has a base terminal and a collector terminal grounded, and outputs a voltage obtained by level shifting the ground potential from the emitter terminal;
The control circuit according to claim 4, comprising: The second gate voltage output from the driver circuit is active during a period when the comparator circuit is provided at the subsequent stage, latches the comparison signal output from the comparator, and outputs it as a detection signal to the switch. A latch circuit;
2. The switch outputs the second gate voltage fixed to a low level during a period when the detection signal output from the latch circuit, not the comparison signal, is at the predetermined level. Control circuit according to.   The control circuit according to claim 6, wherein the latch circuit resets the latched detection signal when the second gate voltage is changed from a high level to a low level.   The latch circuit includes a D flip-flop. The D flip-flop receives the second gate voltage as a reset terminal, receives a high-level fixed voltage as a data terminal, and outputs the clock terminal from the comparator. The control circuit according to claim 7, wherein a comparison signal is input.   The latch circuit further includes an OR gate that outputs a logical sum of the output signal of the D flip-flop and the comparison signal output from the comparison unit, and outputs the output signal of the OR gate as the detection signal. The control circuit according to claim 8, characterized in that:   The control circuit according to claim 1, wherein the synchronous rectification transistor is an NMOS transistor.   11. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate. A capacitor with one end grounded;
An inductor having one end connected to the other end of the capacitor;
The control circuit according to any one of claims 1 to 10, wherein the switching voltage is supplied to the other end of the inductor;
And a voltage at the other end of the capacitor is output. A battery that outputs battery voltage;
A microcomputer,
The step-down switching regulator according to claim 12, wherein the battery voltage is stepped down and supplied to the microcomputer.
An electronic device comprising:

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