JP2006216975A - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein it is difficult to enhance dimensional accuracy of each wiring line in the case when wiring lines of different widths are proximately formed. <P>SOLUTION: A first insulating film 2, a first conductive film 3, a third insulating film 4, second conductive films 5, 6, and a second insulating film 7 are sequentially formed on a semiconductor substrate 1. A first resist having a first width that corresponds to the width of the gate of a memory cell is formed periodically with first intervals on the second insulating film, and at least the second insulating film 7 is patterned using the first resist to form a mask pattern containing the second insulating film. A second resist 9 is selectively formed at spaces of the mask pattern in the forming regions of select gates each having a width wider than that of the gate of the memory cell, and the first conductive film is patterned using the second resist and the mask pattern. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a nonvolatile semiconductor memory device in which the structure of a wiring layer such as a nonvolatile semiconductor memory device is improved.

  For example, a NAND-type non-volatile semiconductor memory device has a select gate (SG) for connecting a memory cell unit composed of a plurality of memory cells connected in series to a bit line or a source line. The control gate of each memory cell is connected to a word line (WL), and each select gate is connected to a select gate line. The select gate is, for example, a tunnel oxide film, a floating gate polysilicon (FG Poly) film, a silicon oxide film, an ONO film in which a silicon nitride film and a silicon oxide film are stacked, and a control gate poly, like a memory cell. A silicon (CG Poly) film, a tungsten silicide (WSi) film, and a silicon nitride (SiN) film are included. After sequentially forming these films, the resist is patterned by a lithography process, and the SiN film, WSi film, CG Poly film, ONO film, and FG Poly film are processed by a dry etching process using the patterned resist as a mask. Thus, a word line and a select gate line are formed.

  Two select gates are arranged for 16 or 32 word lines constituting the memory cell unit. The select gate and select gate line are set to have a width in the channel length direction larger than that of the word line in order to improve the cut-off characteristic of the select gate. For this reason, in the lithography process when forming the select gate line and the word line, the word line adjacent to the select gate line is subjected to a complicated optical proximity effect compared to the region where the word lines are periodically arranged.

  In addition, when there is a contact such as a bit line between the select gate lines, a space is formed between the select gate lines. This further complicates the optical proximity effect on the word lines. When creating a mask that exposes a resist that is subjected to such a complicated optical proximity effect, the size of the wiring adjacent to the thick wiring is controlled by performing optical proximity correction (OPC) on the mask. The OPC of this mask is performed by simulation. However, since the OPC simulation model is currently under development, sufficient accuracy cannot be obtained. For this reason, the margin of depth of focus is lowered, and the resist may become thinner and fall down. Therefore, it has been difficult to maintain the dimensional accuracy of the word line adjacent to the thick select gate line.

  As an example for suppressing the optical proximity effect, the width of the select gate line is the same as that of the word line, and two select gates and select gate lines are provided, two on each side of one memory cell unit. Technology has been developed (see Patent Document 1).

In the above example, the optical proximity effect between the word line of the nonvolatile semiconductor memory device and the select gate line adjacent thereto is described. However, wirings with different widths are often formed adjacent to each other in a semiconductor device, and the configuration disclosed in Patent Document 1 may not be adopted depending on the circuit configuration or wiring configuration.
JP 2003-51557 A

  The present invention is intended to provide a method for manufacturing a nonvolatile semiconductor memory device capable of improving the dimensional accuracy of each wiring even when wirings having different widths are formed adjacent to each other.

  According to a first aspect of a method for manufacturing a nonvolatile semiconductor memory device of the present invention, a first insulating film and a first conductive film are sequentially formed on a semiconductor substrate, and a select gate is formed on the first conductive film. A third insulating film is formed in a region excluding the formation region, a second conductive film is formed on the first conductive film and the third insulating film, and a second conductive film is formed on the second conductive film. A first resist having a first width corresponding to the width of the gate of the memory cell is periodically formed on the second insulating film at a first interval; The resist pattern is used to pattern at least the second insulating film to form a mask pattern including the second insulating film, and the mask pattern in the formation region of the select gate wider than the gate of the memory cell is formed. Forming a second resist selectively in the space; Using resist and the mask pattern, characterized by patterning the first conductive film.

  According to a second aspect of the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a first insulating film and a first conductive film are sequentially formed on a semiconductor substrate, and a select gate is formed on the first conductive film. A third insulating film is formed in a memory cell formation region excluding the formation region of the first conductive film, a second conductive film is formed on the first conductive film and the third insulating film, and a second conductive film is formed. A plurality of first patterns having substantially the same width and interval as the gates of the memory cells on the second insulating film in the memory cell formation region; On the second insulating film in the select gate forming region adjacent to the memory cell forming region, n select gates (n is a positive integer of 2 or more) and the select gate interval n−1. Forming a first resist having a second pattern of a width of Forming a gate of the memory cell in which the second insulating film and the first conductive film are patterned using one resist, excluding a portion that becomes a space between the select gates in the select gate forming region; Forming a second resist on the second insulating film, and forming the select gate in which the second insulating film and the first conductive film are patterned using the second resist. It is characterized by.

  According to a third aspect of the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a first insulating film and a first conductive film are sequentially formed on a semiconductor substrate, and a select gate is formed on the first conductive film. A second insulating film is formed in a region excluding the formation region of the first conductive film, a second conductive film is formed on the first conductive film and the second insulating film, and the second conductive film is formed on the second conductive film. A third insulating film is formed, and a fourth insulating film having an etching rate lower than that of the third insulating film is formed at a position corresponding to a select gate forming region wider than the gate of the memory cell. And selectively forming a resist having a plurality of patterns having the same width and interval as the gate of the memory cell on the third insulating film in the gate forming region, and the resist and the fourth insulating film The third insulating film, the second conductive film, the second Patterning the insulating film and the first conductive film, wherein the gate, and forming a select gate of the memory cell.

  According to the present invention, it is possible to provide a method for manufacturing a nonvolatile semiconductor memory device capable of improving the dimensional accuracy of each wiring even when wirings having different widths are formed adjacent to each other.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 to 5 show the first embodiment, and are cross-sectional views along a direction orthogonal to a word line of a NAND type nonvolatile semiconductor memory device, that is, along a channel length direction of a memory cell and a select gate. Show.

  As shown in FIG. 1, a tunnel oxide film 2, a floating gate polysilicon (FG Poly) film 3, and an ONO film 4 are sequentially formed on a silicon substrate 1. In the ONO film 4, a region where a select gate line is to be formed later, or two adjacent select gate lines and a region corresponding to the space between these select gate lines are removed. Further, the polysilicon film 3 is patterned in a direction orthogonal to the paper surface of FIG. 1 and formed into a pattern having a predetermined width and space (not shown). Further, an element isolation region (not shown) is formed in a space portion of the pattern of the adjacent polysilicon film 3 in a self-aligning manner. Next, a control gate polysilicon (CG Poly) film 5, a WSi film 6, and a SiN film 7 are sequentially formed on the ONO film 4 and the polysilicon film 3.

  Thereafter, a resist pattern having a predetermined width and space is selectively formed on the SiN film 7. The pattern of the resist 8 formed in this way has a width and a space corresponding to, for example, a word line. Using this resist 8 as a mask, the SiN film 7 and the WSi film 6 are etched by, for example, dry etching. The resist is then removed.

  Thereafter, as shown in FIG. 2, the polysilicon film 5 and the ONO film 4 are etched by, for example, dry etching using the SiN film 7 and the WSi film 6 as a mask. In this way, a periodic mask pattern including the SiN film 7 is formed.

  Next, as shown in FIG. 3, a resist 9 is formed corresponding to the region where the select gate line is formed. In the NAND type nonvolatile semiconductor memory device applied to this embodiment, for example, memory cell units are arranged on both sides of a bit line contact, and these memory cell units are connected to the bit line contact via a select gate, respectively. . For this reason, the select gates of the two memory cell units are arranged adjacent to each other. Therefore, the resist 9 is formed corresponding to the formation region of the two select gates facing each other across the contact. In this state, the floating gate polysilicon film 3 is etched by, for example, dry etching using the resist 9 and the SiN film 7 to ONO film 4 as a mask, and then the resist 9 is removed.

  In this way, as shown in FIG. 4, the word line WL and the select gate line SGL are formed. The select gate line SGL has two convex portions having the same width as that of the word line on the upper portion and one concave portion formed between these convex portions. The width of the recess is the same as the space between the word lines. The lower portion of the select gate line SGL has a width corresponding to two word lines and one space. For this reason, the select gate line SGL has a width approximately three times that of the word line WL. Here, an example is shown in which the select gate line SGL adjacent to the bit line contact is formed with a width approximately three times as wide as the word line WL, but the select gate line on the source line side is formed in the same manner. can do.

  Thereafter, as shown in FIG. 5, an insulating film 11 covering the word line WL and the select gate line SGL, a diffusion layer 12 as a source / drain region, a bit line contact 13 and the like are formed by a known manufacturing process. A NAND type nonvolatile semiconductor memory device is formed. The contact 13 is made of, for example, tungsten (W). For example, titanium (Ti) and titanium nitride (TiN) (not shown) are formed between the contact 13 and the substrate 1.

  In the etching process shown in FIG. 2, the ONO film 4 is almost etched. However, the present invention is not limited to this, and the polysilicon film 5 for the control gate may be etched, the WSi film 6 or the SiN film 7 may be etched.

  According to the first embodiment, the width and space above the select gate line SGL are set to be the same as that of the word line. For this reason, in the lithography process, the periodicity of the pattern in the word line formation region is not broken even in the select gate line formation region. Therefore, since the optical proximity effect is periodic in these wiring formation regions, the depth of focus margin in lithography can be improved. As a result, it is advantageous in reducing the width and space of each wiring having a periodic pattern.

  In addition, the select gate line SGL can be wider than the word line WL. For this reason, even when the element is miniaturized, the cut-off characteristic of the select gate can be improved.

  FIG. 6 shows a modification of the first embodiment. In the first embodiment, the polysilicon film 3 of the select gate line SGL shown in FIG. 5 is patterned corresponding to each memory cell arranged in a direction perpendicular to the paper surface. Therefore, a contact is provided on the polysilicon film 5 of the select gate line SGL formed continuously in a direction perpendicular to the paper surface, and the potential is supplied from the polysilicon film 5 to the polysilicon film 3 to be selected. It is necessary to operate the select gate of the memory cell unit. For this reason, the ONO film 4 corresponding to the select gate line SGL is removed. However, when the polysilicon film 3 of the select gate line SGL is continuously formed in the direction perpendicular to the paper surface, the ONO film 4 is formed in a portion corresponding to the select gate line SGL as shown in FIG. It may be. In this case, by providing a contact to the polysilicon film 3 at an arbitrary position of the select gate line SGL, the select gate of the selected memory cell unit can be operated. Alternatively, the ONO film 4 can be removed at an arbitrary position of the polysilicon film 3 and the polysilicon film 5 can be connected to the polysilicon film 3. In FIG. 6, the ONO film 4 has an opening having a width substantially equal to the space between the word lines. The presence or absence of this opening depends on the etching conditions of the WSi layer 6 and the polysilicon layer 5. It is optional.

  Further, when the polysilicon film 3 of the select gate line SGL is patterned corresponding to each memory cell arranged in a direction perpendicular to the paper surface, as shown in FIG. 6, the portion corresponding to the select gate line SGL Alternatively, the ONO film 4 may be formed. In this case, an opening may be formed in the ONO film 4 of each select gate line SGL as shown in FIG. 6, and the polysilicon film 5 may be connected to the polysilicon film 3 through this opening.

(Second Embodiment)
7 to 12 show a second embodiment. In the following embodiments, the same parts as those in the first embodiment are denoted by the same reference numerals.

In the second embodiment, in FIG. 3 of the first embodiment, the resist 9 that covers the region that becomes the select gate line is formed, whereas the etching rate is lower in advance in the region that becomes the select gate line than the SiN film. An insulating film such as alumina (Al ₂ O ₃ ) is formed, and a select gate line is formed using this insulating film as a mask.

  That is, as shown in FIG. 7, first, as in the first embodiment, a tunnel oxide film 2, a floating gate polysilicon film 3, an ONO film 4, a control gate polysilicon film 5, A WSi film 6 and a SiN film 7 are sequentially formed. Thereafter, an opening 6-1 is formed in the SiN film 7 corresponding to the region to be the select gate line.

Next, as shown in FIG. 8, an insulating film 21 made of alumina (Al ₂ O ₃ ), for example, is formed on the entire surface, and the opening 6-1 is filled with the insulating film 21.
Thereafter, as shown in FIG. 9, the insulating film 21 is polished and planarized by chemical mechanical polishing (CMP) using the SiN film 7 as a stopper. In this way, the insulating film 21 is formed in the formation region of the select gate line.

  Next, as shown in FIG. 10, a resist 22 pattern is formed on the SiN film 7 and the insulating film 21. The width of the resist 22 and the space of the resist 22 are substantially the same as the width and space of the word line.

  Next, as shown in FIG. 11, the SiN film 7 is etched using the resist 22 as a mask. The insulating film 21 has a lower etching rate than the SiN film 7, but is slightly etched. For this reason, a recess is formed on the insulating film 21 that is not covered with the resist 22. Thereafter, the resist 22 is removed.

  Thereafter, as shown in FIG. 12A, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating gate polysilicon film 3 are etched using the SiN film 7 and the insulating film 21 as a mask. . In this manner, the select gate line SGL having the insulating film 21 in the uppermost layer and the word line WL having the SiN film 7 in the uppermost layer are formed. At this time, since the etching rate of the insulating film 21 is smaller than that of the SiN film 7, the film thickness of the entire laminated film in the select gate line region is larger than the film thickness of the entire laminated film in the word line region.

  The select gate line SGL formed as described above has a convex portion formed of two insulating films 21 having the same width as that of the word line, and the space between the convex portions is between the word lines. It is matched with a space. On the other hand, the lower portion of the select gate line SGL has a width substantially equivalent to two word lines and one space. For this reason, the select gate line SGL has a width approximately three times that of the word line WL. In such a select gate line SGL, the width of one of the two convex portions at the upper portion and the width of the lower portion are added with misalignment between the resist 22 and the insulating film 21 when the resist 22 is formed. It may be formed with a width.

  Thereafter, a source / drain region, a bit line, and the like are formed by a known manufacturing process, and a NAND type nonvolatile semiconductor memory device is formed.

  FIG. 12B shows a state in which contacts 27 are formed between adjacent select gate lines SGL. Here, the side walls of the word line WL and the select gate line SGL are covered with, for example, a silicon oxide film 26, and a contact 27 is formed between the adjacent select gate lines SGL. The contact 27 is made of, for example, tungsten (W). For example, titanium (Ti) and titanium nitride (TiN) (not shown) are formed between the contact 27 and the substrate 1. This contact configuration can also be applied to the following embodiments.

  In the process shown in FIG. 10, the SiN film 7 is completely removed and only the insulating film 21 is present in the region corresponding to the select gate line. However, only a part of the upper layer of the region corresponding to the select gate line may be used as the insulating film 21 and the SiN film 7 may be left under the insulating film 21.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained. In addition, according to the second embodiment, the insulating film 21 is made of a material (for example, alumina) having a low etching rate with respect to the filling material (for example, tungsten) between the select gate lines SGL. Therefore, when forming a contact between the select gate lines by self-alignment, the insulating film 21 made of alumina can be used as a mask material superior to the SiN film 7.

(Third embodiment)
13 to 16 show a third embodiment. In the second embodiment, the insulating film 21 is formed inside the SiN film 7. In contrast, in the third embodiment, the insulating film 21 is formed on the SiN film 7 so as to correspond to the formation region of the select gate line.

That is, as shown in FIG. 13, the tunnel oxide film 2, the floating gate polysilicon film 3, the ONO film 4, the control gate polysilicon film 5, the WSi film 6 and the SiN film 7 are sequentially formed on the silicon substrate 1. The Thereafter, a film having an etching rate lower than that of the SiN film 7, for example, an insulating film 21 made of Al ₂ O ₃ is formed on the SiN film 7. A resist 23 is formed on the insulating film 21 corresponding to the region where the select gate line is formed. The insulating film 21 is etched using the resist 23 as a mask, and the insulating film 21 is left only in the select gate line formation region. Thereafter, the resist 23 is removed.

  Next, as shown in FIG. 14, a patterned resist 24 is formed on the SiN film 7 and the insulating film 21. The width and space of the resist 24 are substantially the same as the width of the word line and the space between the word lines.

  Next, as shown in FIG. 15, the SiN film 7 is etched using the resist 24 and the insulating film 21 as a mask. The insulating film 21 has a lower etching rate than the SiN film 7, but is slightly etched. For this reason, a recess is formed on the insulating film 21 that is not covered with the resist 24. Thereafter, the resist 24 is removed.

  Thereafter, as shown in FIG. 16, using the insulating film 21 and the SiN film 7 as a mask material, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating gate polysilicon film 3 are etched to select gates. SGL lines and word lines WL are formed. At this time, since the insulating film 21 has an etching rate smaller than that of the SiN film 7, the insulating film 21 remains. However, even if all of them are removed, the SiN film 7 remaining above the select gate line SGL is thicker than the SiN film 7 remaining above the word line WL line. For this reason, since the SiN film 7 can be used as a mask when a contact is formed by self-alignment between adjacent select gate lines SGL, there is no need to separately form a mask film. .

  According to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

  In the first to third embodiments, the case where the present invention is applied to the memory cell array of the NAND type nonvolatile semiconductor memory device has been described. However, the present invention is not limited to the memory cell array as long as it is a circuit pattern in which wirings having different widths are formed adjacent to each other.

  17 and 18 show a modification corresponding to the first embodiment. Note that the concepts shown in FIGS. 17 and 18 are also applicable to the second and third embodiments.

  FIG. 17 shows a case where the present invention is applied to a peripheral circuit of a nonvolatile semiconductor memory device, for example, and shows a circuit pattern having a first wiring L1 and a second wiring L2. The first and second wirings L1 and L2 have the same configuration as that of the first embodiment except that neither the ONO film 4 is provided.

  The peripheral circuit having such a configuration can be formed by the same manufacturing method as in the first embodiment. That is, first, a resist pattern having a width and a space substantially coincident with the first wiring L1 is formed and etched to an arbitrary position below the SiN film 7. Thereafter, after forming a resist in the formation region of the second wiring L2, the remaining portions of the WSi film 6, the polysilicon films 5 and 3 may be etched.

  Even with such a configuration, the same effects as those of the first embodiment can be obtained.

  In the first to third embodiments, the case has been described in which the select gate line SGL has a width approximately three times that of the word line WL. However, the width relationship between adjacent wirings is not limited to this.

  In FIG. 18, the width of the third wiring L3 is set to approximately five times the width of the first wiring L1. In general, the width of the third wiring L3 only needs to be set by the width of n of the first wiring L1 and the width of n-1 inter-wiring spaces of the first wiring L1. If the first wiring L1 and the third wiring L3 have such a relationship, the first and third wirings L1 and L3 can be formed by the same method as in the first to third embodiments. The same effects as those of the first to third embodiments can be obtained.

  Furthermore, the first to third embodiments are not limited to nonvolatile semiconductor memory devices, and can be applied to the formation of circuit patterns of other semiconductor devices. In this case, the laminated structure of the tunnel oxide film 2, the floating gate polysilicon film 3, the ONO film 4, the control gate polysilicon film 5, and the WSi film 6 is not limited to this, and an arbitrary configuration is selected. can do.

(Fourth embodiment)
FIG. 19A shows an example of the arrangement of select gate lines SGL and word lines WL. In this arrangement, there is a space between the select gate lines SGL. Therefore, if a resist is formed corresponding to the select gate line SGL and the word line WL, the optical proximity effect becomes complicated, and it becomes difficult to form a resist with good dimensional accuracy.

  In order to solve this problem, in the first to third embodiments, the width and space of the resist pattern formed in the formation region of the select gate line are matched with those of the word line. On the other hand, in the fourth embodiment, the resist pattern formed in the select gate line formation region is different from the word line and the select gate line.

  That is, as shown in FIG. 19B, in the fourth embodiment, the resist pattern 31-1 corresponding to the word line, the two select gate lines SGL, and the space between these select gate lines SGL are combined. A resist pattern 31-2 corresponding to the region is formed. First, a word line formation region is processed. Thereafter, the resist pattern 31-2 is removed, a resist having an opening corresponding to the space between the two select gate lines SGL is formed, and the select gate line is formed using this resist.

  20 to 23 show a fourth embodiment.

  As shown in FIG. 20, the tunnel oxide film 2, the floating gate polysilicon film 3, the ONO film 4, the control gate polysilicon film 5, and the WSi film are formed on the silicon substrate 1 as in the first to third embodiments. 6 and SiN film 7 are formed sequentially. Thereafter, a resist 31 is selectively formed corresponding to a region where each word line is formed and a region where a space between two select gate lines and one select gate line is disposed. That is, the resist 31-1 formed in the region corresponding to the word line substantially matches the wiring width and space of the word line. The resist 31-2 formed between the resists 31-1 periodically arranged in this way is substantially equivalent to two select gate lines SGL and one space between these select gate lines SGL. It has a width.

Next, as shown in FIG. 21, the SiN film 7 is etched by, for example, dry etching using the resists 31-1 and 31-2 as a mask. Next, the resist is removed.
Thereafter, as shown in FIG. 22, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating gate polysilicon film 3 are etched by, for example, dry etching using the SiN film 7 as a mask. In this manner, word line groups having periodic wiring widths and spaces are formed in the word line formation regions constituting the memory cell units. Next, a resist 32 is formed between the word line groups thus formed, except for a portion that becomes a space between two adjacent select gate lines.

Thereafter, using the resist 32 as a mask, the SiN film 7, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating film positioned between the two select gate line formation regions between the word line groups. The gate polysilicon film 3 is etched by dry etching, for example.
In this way, as shown in FIG. 23, two adjacent select gate lines SGL are formed. The width of the select gate line SGL can be changed depending on the space when the resist 32 is formed.

  According to the fourth embodiment, a resist 31-2 having a wide width corresponding to two select gate lines SGL and a space between the select gate lines SGL adjacent to the resist 31-1 corresponding to the word line. Is forming. When the resist 31-2 is formed so as to simply form a thick wiring in this way, the optical proximity effect of the resist 31-1 adjacent to the resist 31-2 becomes simple. For this reason, mask correction by OPC is facilitated. Therefore, the accuracy of the mask and the dimensional accuracy of the resist can be improved, and a word line having a desired width can be formed.

(Fifth embodiment)
24 to 26 show a fifth embodiment. In FIG. 24, the insulating film 21 in the SiN film 7 is formed corresponding to the formation region of the select gate line. In the fifth embodiment, the steps until the insulating film 21 is formed in the SiN film 7 are the same as those in the second embodiment shown in FIGS.

  In FIG. 24, a resist 33 is formed on the SiN film 7 corresponding to the word line formation region. The width and interval of the resist 33 are substantially the same as the word line. In addition, the resist 33 is not formed in a portion corresponding to the formation region of the select gate line. That is, as shown in FIG. 19C, a space is formed between the formation regions of the word lines WL constituting the adjacent memory cell units.

  Thereafter, as shown in FIG. 25, the SiN film 7 is etched by dry etching, for example, using the resist 33 as a mask. The insulating film 21 has a lower etching rate than the SiN film 7 but is slightly etched because it is not masked by the resist 33. Next, the resist 33 is removed.

  Thereafter, as shown in FIG. 26, using the SiN film 7 and the insulating film 21 as a mask, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating gate polysilicon film 3 are etched by, for example, dry etching. . Thereby, the select gate line SGL and the word line WL are formed.

  The insulating film 21 has a function as an etching mask material for forming a select gate line. The word line WL is formed using the SiN film 7 as a mask. Therefore, the heights of the select gate line SGL and the word line WL differ depending on the difference in etching rate between the SiN film 7 and the insulating film 21.

  In FIG. 24, the select gate line is formed only in the insulating film 21, and the SiN film 7 is not left. However, the SiN film 7 may be left under the insulating film 21.

  According to the fifth embodiment, unlike the fourth embodiment, no resist is formed corresponding to the region where the select gate line is formed. Even with such a configuration, the optical proximity effect of the resist corresponding to the word line is simple. Therefore, the mask can be easily corrected by OPC, and a resist and a word line with good dimensional accuracy can be formed.

Similarly to the second embodiment, the insulating film 21 is self-aligned between the select gate lines when a material having a low etching rate is used as the insulating film 21 with respect to the filling material between the select gate lines. When forming the contact, this material can be used as a mask material superior to the SiN film 7. For example, when alumina (Al ₂ O ₃ ) is used as the insulating film 21 and tungsten is used as the filling material, the etching rate of alumina is lower than that of tungsten and SiN films. Therefore, over-etching of the contact can be prevented as compared with the SiN film, and a short circuit between the contact and the select gate line can be reliably prevented.

(Sixth embodiment)
27 to 29 show a sixth embodiment. The sixth embodiment is a modification of the third embodiment and the fifth embodiment, and the insulating film 21 is formed on the SiN film 7 corresponding to the region where the select gate line is formed.

  In FIG. 27, a resist 34 is formed on the insulating film 21 so as to correspond to the region where the select gate line is formed, and the process until the insulating film 21 is etched using the resist 34 as a mask is the same as in the third embodiment. is there. Therefore, the description is omitted. Next, the resist 34 is removed.

  Thereafter, as shown in FIG. 28, a resist 35 is formed on the SiN film 7 corresponding to the word line formation region. The resist 35 has substantially the same width and interval as the word line. Further, the resist 35 is not formed on the SiN film 7 and the insulating film 21 at a location corresponding to the select gate line formation region. That is, as shown in FIG. 19C, a space is formed between the formation regions of the word lines WL constituting the adjacent memory cell units. Next, the SiN film 7 is etched by dry etching, for example, using the resist 35 and the insulating film 21 as a mask. Thereafter, the resist 35 is removed.

  Next, as shown in FIG. 29, using the insulating film 21 and the SiN film 7 as a mask, the WSi film 6, the control gate polysilicon film 5, the ONO film 4, and the floating gate polysilicon film 3 are etched by, for example, dry etching. To do. Thereby, the select gate line SGL and the word line WL are formed. At this time, since the insulating film 21 has an etching rate smaller than that of the SiN film 7, it remains even if it is slightly etched. Alternatively, even if the insulating film 21 is removed during processing, the wiring height in the select gate line region is higher than that in the word line region.

  According to the sixth embodiment, the same effect as that of the fifth embodiment can be obtained.

  In the fourth to sixth embodiments, the case where the circuit pattern of the memory cell array of the nonvolatile semiconductor memory device is formed has been described. However, the present invention is not limited to this, and can be applied to the formation of peripheral circuit patterns of nonvolatile semiconductor memory devices and circuit patterns of other semiconductor devices as in the first to third embodiments. It is.

  Of course, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the manufacturing process of 1st Embodiment and shows the state which formed the resist on the SiN film | membrane. Sectional drawing which shows the manufacturing process following FIG. 1, and shows the state which etched to the ONO film | membrane. FIG. 3 is a cross-sectional view illustrating a manufacturing process subsequent to FIG. 2 and showing a state in which a resist is formed in a region where a select gate line is formed. FIG. 4 is a cross-sectional view showing a manufacturing process following FIG. 3 and showing a state in which select gate lines and word lines are formed. FIG. 5 is a cross-sectional view showing a manufacturing process subsequent to FIG. 4 and showing a state where bit line contacts are formed; Sectional drawing which shows the modification of 1st Embodiment. Sectional drawing which shows the manufacturing process which concerns on 2nd Embodiment, and shows the state which formed the opening in SiN film. FIG. 8 is a cross-sectional view illustrating a manufacturing process subsequent to FIG. 7 and showing an insulating film formed on the entire surface of the substrate. FIG. 9 is a cross-sectional view showing a manufacturing process subsequent to FIG. 8 and showing a state in which an opening is embedded with an insulating film. FIG. 10 is a cross-sectional view showing a manufacturing process subsequent to FIG. 9 and showing a state in which a resist is formed on the SiN film and the insulating film. FIG. 11 is a cross-sectional view showing a manufacturing process following FIG. 10 and showing a state where an SiN film is etched. FIG. 12 is a cross-sectional view showing a manufacturing process following FIG. 11 and showing a state in which select gate lines and word lines are formed. Sectional drawing which shows the manufacturing process which concerns on 3rd Embodiment, and shows the state which formed the insulating film on the SiN film. FIG. 14 is a cross-sectional view showing a manufacturing process subsequent to FIG. 13 and showing a state in which a resist is formed on the SiN film and the insulating film. FIG. 15 is a cross-sectional view showing the manufacturing process following FIG. 14 and showing a state where the SiN film is etched. FIG. 16 is a cross-sectional view showing the manufacturing process following FIG. 15 and showing a state in which select gate lines and word lines are formed. Sectional drawing which shows the modification of 1st Embodiment and shows the example which applied 1st Embodiment to the peripheral circuit of the semiconductor device. Sectional drawing which shows the modification of the wiring which has different width | variety in 1st Embodiment. FIG. 19A is a plan view showing an example of the arrangement of select gate lines SGL and word lines WL, FIG. 19B is a plan view showing the shape of the resist according to the fourth embodiment, and FIG. These are top views which show the shape of the resist which concerns on 5th, 6th embodiment. Sectional drawing which shows the manufacturing process which concerns on 4th Embodiment, and shows the state which formed the resist on the SiN film. FIG. 21 is a cross-sectional view showing the manufacturing process subsequent to FIG. 20 and showing a state where the SiN film is etched. FIG. 22 is a cross-sectional view showing a manufacturing process subsequent to FIG. 21 and showing a state in which a resist for forming a space between select gate lines is formed. FIG. 23 is a cross-sectional view showing the manufacturing process following FIG. 22 and showing a state in which a select gate line and a word line are formed. Sectional drawing which shows the manufacturing process which concerns on 5th Embodiment, and shows the state which formed the resist on the SiN film | membrane with which the insulating film was embedded. FIG. 25 is a cross-sectional view showing a manufacturing process subsequent to FIG. 24 and showing a state where the SiN film is etched. FIG. 26 is a cross-sectional view showing the manufacturing process following FIG. 25 and showing a state in which select gate lines and word lines are formed. Sectional drawing which shows the manufacturing process which concerns on 6th Embodiment, and shows the state which formed the insulating film on the SiN film. FIG. 28 is a cross-sectional view showing the manufacturing process following FIG. 27 and showing a state where the SiN film is etched. FIG. 29 is a cross-sectional view showing a manufacturing step following FIG. 28 and showing a state in which a select gate line and a word line are formed.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 3 ... Floating gate polysilicon film, 4 ... ONO film, 5 ... Control gate polysilicon film, 6 ... WSi film, 7 ... SiN film, 8, 9, 22, 23, 24, 31- 35, resist, 31-1, 31-2, resist pattern, 21, insulating film, SGL, select gate line, WL, word line.

Claims (6)

A first insulating film and a first conductive film are sequentially formed on the semiconductor substrate;
On the first conductive film, a third insulating film is formed in a region excluding a select gate formation region,
Forming a second conductive film on the first conductive film and the third insulating film;
Forming a second insulating film on the second conductive film;
A first resist having a first width corresponding to the width of the gate of the memory cell is periodically formed on the second insulating film at a first interval;
Patterning at least the second insulating film using the first resist to form a mask pattern including the second insulating film;
Forming a second resist selectively in the space of the mask pattern in the formation region of the select gate wider than the gate of the memory cell;
The method of manufacturing a nonvolatile semiconductor memory device, wherein the first conductive film is patterned using the second resist and the mask pattern. A first insulating film and a first conductive film are sequentially formed on the semiconductor substrate;
On the first conductive film, a third insulating film is formed in a memory cell formation region excluding a select gate formation region;
Forming a second conductive film on the first conductive film and the third insulating film;
Forming a second insulating film on the second conductive film;
On the second insulating film in the memory cell formation region, a plurality of first patterns having substantially the same width and interval as the gate of the memory cell and a selection gate adjacent to the memory cell formation region are provided. A first pattern having a width corresponding to n select gates (n is a positive integer greater than or equal to 2) and an interval n−1 of the select gates on the second insulating film in the formation region. Forming a resist,
Forming a gate of the memory cell in which the second insulating film and the first conductive film are patterned using the first resist;
Forming a second resist on the second insulating film, excluding a portion that becomes a space between the select gates in the select gate forming region;
The method of manufacturing a nonvolatile semiconductor memory device, wherein the select gate is formed by patterning the second insulating film and the first conductive film using the second resist. A first insulating film and a first conductive film are sequentially formed on the semiconductor substrate;
On the first conductive film, a second insulating film is formed in a region excluding a select gate formation region,
Forming a second conductive film on the first conductive film and the second insulating film;
Forming a third insulating film on the second conductive film;
Forming a fourth insulating film having an etching rate smaller than that of the third insulating film at a position corresponding to the formation region of the select gate wider than the gate of the memory cell;
Selectively forming a resist having a plurality of patterns having substantially the same width and interval as the gate of the memory cell on the third insulating film in the gate formation region of the memory cell;
The third insulating film, the second conductive film, the second insulating film, and the first conductive film are patterned using the resist and the fourth insulating film, and the memory cell gate and select A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a gate. 4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the fourth insulating film is formed inside the third insulating film. 4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the fourth insulating film is formed on the third insulating film. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the resist is also formed on the fourth insulating film.

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