JP2006173889A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid forming an unwanted current path regardless of level of different power source voltages by preventing a through current when cutting off the power source voltage. <P>SOLUTION: When a sleep signal SLP comes to be H level, a power source voltage Va is cut off, and NOR gates 45 and 46 output signals of L level. Both transistors Q7 and Q8 of a level conversion circuit 40 come to be off, to prevent a through current that flows from a power source line 36 to a ground line 37. A NAND gate 41 outputs a signal which is fixed at H level, regardless of output state of the level conversion circuit 40. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a level shift circuit for transmitting a digital signal between circuit blocks operating under different power supply voltages.

  As a means to reduce the current consumption of the circuit, it needs to be divided into a low-voltage circuit block that operates with a relatively low power supply voltage and a high-voltage circuit block that operates with a relatively high power supply voltage, and an interface circuit with external circuits and high-speed operation are required A technique is employed in which only the circuit portion to be used is a high voltage circuit block and the other circuits are low voltage circuit blocks. In this case, a level shift circuit is required for signal transmission between the low voltage circuit block and the high voltage circuit block.

  Recently, for the purpose of reducing current consumption in a system using a battery voltage, a system design for actively shutting down a power supply circuit has been made. For example, for internal circuits that require high-speed operation, a boosted constant-voltage power supply circuit is used to guarantee a power supply voltage above a certain value, and for circuits with a large tolerance for power supply voltage fluctuations, the battery voltage is May be used. In such a system, the magnitude relationship between the two power supply voltages existing across the level shift circuit may be reversed due to the shutdown of the boost type constant voltage power supply circuit or the decrease in the battery voltage.

  FIG. 6 shows a circuit configuration of the level shift circuit described in Patent Document 1. The level shift circuit 1 includes an input circuit unit 2 that operates with a low voltage power source (voltage VL) and an output circuit unit 3 that operates with a high voltage power source (voltage VH). The input circuit unit 2 and the output circuit unit 3 Are provided with switch circuits 4 and 5 that are operated by a high-voltage power source. The switch circuits 4 and 5 are constituted by transistors Q1 and Q2 and transistors Q3 and Q4, respectively.

  When the low voltage power supply is cut off, the switch circuits 4 and 5 are turned off based on the control signal Sc, and the input circuit section 2 and the output circuit section 3 are disconnected. At the same time, the transistors Q5 and Q6 are turned on, the gates of the transistors Q7 and Q8 are fixed to the ground potential, and the transistor Q11 is turned off to disconnect the high voltage power supply from the output circuit unit 3. As a result, a through current flowing through transistors Q9 and Q7 and transistors Q10 and Q8 is blocked.

FIG. 7 shows a circuit configuration of the level shift circuit described in Patent Document 2, and parts corresponding to those in FIG. In the level shift circuit 6, a transistor Q12 is connected between the transistors Q10 and Q8, and a transistor Q13 is connected between the high voltage power supply line and the output line. When the low-voltage power supply is not supplied to the circuit that transmits the input data Din, the transistor Q12 is turned off and the transistor Q13 is turned on based on the control signal Sc. As a result, the through current through the transistors Q9 and Q10 is cut off, and the output data is fixed to the L level to prevent it from becoming indefinite.
Japanese Patent Laid-Open No. 2004-128590 JP-A-10-84274

  However, in the level shift circuit 1, when the voltage VH of the high voltage power supply becomes lower than the voltage VL of the PN junction by the voltage VL of the low voltage power supply or more, the body diode (drain or source) of the P channel type transistor Q1 or Q3. Current flows through the PN junction between the substrate and the substrate. As a result, for example, when the low voltage power source is a battery, the battery life is reduced. Further, in the level shift circuit 6, since the transistor Q12 is connected, there is a problem that the minimum operable voltage increases. As a result, for example, in the case of a system that operates on battery voltage, the battery life is reduced.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a through current when a power supply voltage is cut off, and a level shift that does not cause an unnecessary current path regardless of the magnitude relationship between different power supply voltages. It is to provide a circuit.

  According to the means described in claim 1, when both the first power supply voltage and the second power supply voltage are supplied, the signal output circuit indicates the power supply state signal indicating the “supply state” of the first power supply voltage. Is output. At this time, each of the first and second CMOS NOR gates operates as an inverter, and the input digital signal becomes a pair of complementary signals (H level and L level), and the first and second FETs of the level conversion circuit. Given to the gate. The level conversion circuit converts the level of the input signal from the first power supply voltage to the second power supply voltage and outputs the converted signal. An output signal from the level conversion circuit is output through a level fixing circuit.

  On the other hand, when the first power supply voltage is cut off or falls below a predetermined value, the signal output circuit generates a power supply state signal (for example, H level) indicating the “cutoff (or reduction) state” of the first power supply voltage. Output. At this time, the first and second CMOS NOR gates output an L level signal for turning off the first and second FETs of the level conversion circuit. As a result, both the first and second FETs are turned off, and the through current flowing through the third and first FETs and the through current flowing through the fourth and second FETs can be blocked.

  In this case, the output of the level conversion circuit becomes high impedance and the output signal becomes indefinite, but the level fixing circuit fixes the signal level. In addition, since the level shift circuit does not include a semiconductor switch circuit between the first power supply voltage and the second power supply voltage, even if the second power supply voltage is cut off or lowered, An unnecessary current path through a body diode or the like does not occur between the first power source and the second power source.

  According to the means described in claim 2, the level fixing circuit is constituted by a gate circuit that receives the power supply state signal output from the signal output circuit and the signal output from the level conversion circuit. For example, when configured with a NAND gate circuit, the NAND gate circuit inverts the output signal of the level conversion circuit when a power supply state signal (eg, H level) indicating the “supply state” of the first power supply voltage is input. When a power supply state signal (for example, L level) indicating the “cutoff state” of the first power supply voltage is input, a fixed H level signal is output regardless of the output signal of the level conversion circuit. .

  According to the means described in claim 3, since the level fixing circuit is constituted by a latch circuit, even when the output signal of the level conversion circuit becomes indefinite (high impedance state), the level fixing circuit Output signal holds the signal level before the indefinite state.

  According to the means described in claim 4, the first power supply voltage on the input side of the level shift circuit is supplied from the constant voltage power supply circuit that outputs or stops (shuts down) the power supply voltage in response to the power supply state signal. Therefore, in the low power consumption operation mode such as a sleep state, the first power supply can be stopped to reduce current consumption. If the first power supply voltage is applied to a system that generates a battery that is the second power supply voltage, the life of the battery can be increased.

(First embodiment)
A first embodiment in which the present invention is applied to an in-vehicle IC will be described below with reference to FIGS.
FIG. 3 shows a schematic functional block configuration of an in-vehicle IC and a connection mode between the IC and a power source. The IC 21 is mounted on, for example, a circuit board (not shown) of a control device related to an electronic license plate device of a vehicle. The circuit board includes peripheral circuits such as an external interface circuit and a nonvolatile memory (an EEPROM as an example). (Not shown) is also installed. This device receives data transmitted wirelessly, stores the received data in an EEPROM as necessary, and reads data stored in the EEPROM when there is a wireless data read request. Then, it is sent to a transmission / reception IC (not shown).

  In the normal operation mode, the IC 21 receives supply of the voltage Vb of the battery 22 and the power supply voltage Va obtained by boosting or stepping down the battery voltage Vb with a power supply circuit 23 (corresponding to a constant voltage power supply circuit). In the sleep mode, the battery voltage Vb alone is supplied to operate. Terminals 24 and 25 of the IC 21 are supply terminals for power supply voltages Va and Vb, respectively, and a terminal 26 is a ground terminal.

  For example, if the numerical values of the voltages Va and Vb are shown for reference, the voltage Vb of the battery 22 is about 3.3 V to 3.6 V when fully charged, and the IC 21 can operate until it drops to 1.8 V. It has become. On the other hand, the power supply circuit 23 receives the battery voltage Vb and outputs a constant voltage Va of 2.5 V when the sleep signal SLP supplied from the IC 21 is at the L level, and outputs a constant voltage Va when the sleep signal SLP is at the H level. The voltage operation and voltage output are stopped.

  The IC 21 is manufactured by a CMOS process. The control circuit 27 operates under the power supply voltage Va, the control circuit 28 and the input / output interface circuit 29 operate under the power supply voltage Vb, and the control circuits 27 and 28. Level shift circuits 30 and 31 connected between the two. Among these, the control circuit 27 performs communication control related to transmission / reception of communication data, and performs sleep determination control for determining the shift to the sleep mode and outputting the sleep request signal SLPRQ.

  The control circuit 28 performs sleep control, wakeup control, and communication control. Here, sleep control is control in which when the sleep request signal SLPRQ from the control circuit 27 is received, the sleep signal SLP is set to H level to cause the IC 21 to shift from the normal operation mode to the sleep mode. When the signal that causes the wake-up is input from the external interface circuit connected via the terminal 33, the sleep signal SLP is set to L level to return the IC 21 from the sleep mode to the normal operation mode.

  Communication control refers to data input from the control circuit 27 via the level shift circuit 30, EEPROM IC and transmission / reception IC (both shown) via the input / output interface circuit 29 from the terminal (s) 34. Control that sends data read from the EEPROM via the input / output interface circuit 29 or data received by the IC for transmission / reception to the control circuit 27 via the level shift circuit 31. .

  FIG. 1 shows the configuration of the level shift circuit 30, and the same reference numerals are given to the components corresponding to those in FIGS. 6 and 7. The level shift circuit 30 receives a power supply voltage Va (corresponding to the first power supply voltage) from the power supply line 35 (corresponding to the first power supply line) and the ground line 37, and operates. Circuit block 39 (corresponding to the second power supply voltage), the power supply line 36 (corresponding to the second power supply line), and the ground line 37 to be supplied with the power supply voltage Vb (corresponding to the second power supply voltage). Are connected in cascade.

  In the circuit block 39, the N-channel type MOS transistors Q7, Q8 and the P-channel type MOS transistors Q9, Q10 constitute a level conversion circuit 40. The transistors Q7 to Q10 correspond to first to fourth FETs in the present invention, respectively. The transistors Q7 and Q8 are both source-grounded with respect to the ground line 37, and transistors Q9 and Q10 are connected between the power supply line 36 and the transistors Q7 and Q8, respectively. The gates of the transistors Q9 and Q10 are connected to the drains of the transistors Q8 and Q7, respectively, and the drains of the transistors Q8 and Q10 are the output terminals of the level conversion circuit 40.

  An output signal from the level conversion circuit 40 is output as data Dout through a NAND gate 41 (equivalent to a level fixing circuit and a gate circuit) and an inverter 42. The sleep signal SLP is provided to the circuit block 38 via inverters 43 and 44 (corresponding to a signal output circuit), and is input to the NAND gate 41 via the inverter 43, and a level fixing control signal for the NAND gate 41. Function as.

  On the other hand, in the circuit block 38, the input data Din and the sleep signal SLP from the inverter 44 are input to the NOR gate 45 (corresponding to the first CMOS NOR gate), and the NOR gate 46 (corresponding to the second CMOS NOR gate). The output signal of the NOR gate 45 (that is, the gate signal of the transistor Q8) and the sleep signal SLP are inputted. The output signals of the NOR gates 45 and 46 are applied to the gates of the transistors Q8 and Q7, respectively. The NOR gates 45 and 46 are composed of N-channel MOS transistors Q14 and Q15 and P-channel MOS transistors Q16 and Q17 as shown in FIG.

  FIG. 2 shows the configuration of the level shift circuit 31, and the components corresponding to those in FIG. The level shift circuit 31 includes a circuit block 47 that operates by receiving the supply of the power supply voltage Vb, and a circuit block 48 that operates by receiving the supply of the power supply voltage Va. In the circuit block 47, the input data Din is supplied to the gate of the transistor Q7 via the inverters 49 and 50, and is also supplied to the gate of the transistor Q8 via the inverter 49. In the circuit block 48, the output signal of the level conversion circuit 40 is output as data Dout through inverters 51 and 52 in cascade.

Next, the operation and effect of this embodiment will be described.
When the wake-up signal is input from the external interface circuit connected via the terminal 33, the control circuit 28 sets the sleep signal SLP to L level to return the IC 21 from the sleep mode to the normal operation mode. When the sleep signal SLP becomes L level, the power supply circuit 23 receives the battery voltage Vb, generates a constant power supply voltage Va, and outputs it. The IC 21 is supplied with a power supply voltage Va and a battery voltage Vb, and data is exchanged between the control circuits 27 and 28 via the level shift circuits 30 and 31.

  At this time, in the level shift circuit 30, the output signals of the inverters 43 and 44 become H level and L level, respectively, and the NAND gate 41 and the NOR gates 45 and 46 operate as inverters. When the input data Din is at the L level (0 V), the transistors Q7 and Q10 are turned off, the transistors Q8 and Q9 are turned on, and the circuit block 39 outputs the data Dout at the L level (0 V). On the other hand, when the input data Din is at the H level (voltage Va), the transistors Q7 and Q10 are turned on, the transistors Q8 and Q9 are turned off, and the circuit block 39 outputs the data Dout at the H level (voltage Vb). The operation of the level shift circuit 31 is the same.

  When detecting the end of data communication, the control circuit 27 outputs a sleep request signal SLPRQ to the control circuit 28. When the sleep request signal SLPRQ is input via the level shift circuit 30, the control circuit 28 sets the sleep signal SLP to the H level and causes the IC 21 to shift from the normal operation mode to the sleep mode. When the sleep signal SLP becomes H level, the power supply circuit 23 stops generating and outputting the power supply voltage Va.

  At this time, in the level shift circuit 30, the output signals of the inverters 43 and 44 become L level and H level, respectively. Since the NOR gates 45 and 46 of the circuit block 38 have the circuit configuration shown in FIG. 4, even if the power supply voltage Va is cut off, the transistors Q14 and Q15 are turned on and an L level signal can be output. . As a result, the transistors Q7 and Q8 of the level conversion circuit 40 are both turned off, the through current flowing from the power supply line 36 to the ground line 37 via the transistors Q9 and Q7, and the ground line 37 from the power supply line 36 via the transistors Q10 and Q8. Can be prevented from flowing through.

  At this time, the output of the level conversion circuit 40 has high impedance, and the output signal level is indefinite. However, since the NAND gate 41 outputs a signal fixed to the H level regardless of the output state of the level conversion circuit 40, the circuit block 39 can output the fixed L level (0 V) data Dout. . In the level shift circuit 31, since the power supply voltage Va of the circuit block 48 is cut off, no through current is generated in the level conversion circuit 40.

  As described above, since the IC 21 of the present embodiment includes the level shift circuits 30 and 31, the control circuit 28 and the input / output interface circuit 29 are operated by the battery voltage Vb, and the control needs to process data at high speed. The circuit 27 can be operated by the power supply voltage Va generated by the power supply circuit 23.

  The level shift circuit 30 includes a data input side circuit block 38 that operates at the power supply voltage Va that is cut off during the sleep mode, and a data output side circuit block 39 that operates at the battery voltage Vb that is always supplied. . The circuit block 38 includes NOR gates 45 and 46 that receive the sleep signal SLP provided from the inverters 43 and 44 provided in the circuit block 39. The circuit block 39 outputs signals from the NOR gates 45 and 46. The level conversion circuit 40 controlled by the above is provided.

  Therefore, while the power supply voltage Va is shut off (during the sleep mode), both the transistors Q7 and Q8 constituting the level conversion circuit 40 can be maintained in the off state, and a through current can be prevented. Further, since the NAND gate 41 using the inverted signal of the sleep signal SLP as the level fixing control signal is connected to the subsequent stage of the level conversion circuit 40, a through current flows in the inverter 42 even if the output of the level conversion circuit 40 is not determined. In this case, the level of the output data Dout can be fixed.

  Since the level shift circuit 30 does not include a semiconductor switch circuit between the circuit blocks 38 and 39, an unnecessary current path is generated between the power supply lines 35 and 36 regardless of the magnitude relationship between the power supply voltages Va and Vb. Absent. Therefore, the life of the battery 22 can be increased compared to the conventional circuit configuration. In addition, since no transistor is added to the basic structure of the level conversion circuit 40, there is no inconvenience that the minimum operable voltage increases.

(Second Embodiment)
FIG. 5 shows the configuration of the level shift circuit according to the second embodiment of the present invention, and the same parts as those in FIG. The level shift circuit 53 uses a latch circuit 55 as a level fixing circuit in a circuit block 54 that operates upon receiving the supply of the power supply voltage Vb. The latch circuit 55 includes an inverter 56 (corresponding to the first inverter) and an inverter 57 (corresponding to the second inverter) connected in antiparallel between the input and output terminals of the inverter 56.

  According to this configuration, even when the normal operation mode is shifted to the sleep mode and the output of the level conversion circuit 40 becomes high impedance, the latch circuit 55 continues to output the holding signal immediately before the shift to the sleep mode. Therefore, the output signal of the level shift circuit 53 can be fixed so as not to be indefinite.

(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
Each of the first and second power sources may be a battery or a constant voltage power source.
The signal output circuit of the present invention only needs to be provided in the second circuit block that operates by receiving the supply of the second power supply voltage, and the circuit form is not limited to the inverter.

1 is a configuration diagram of a level shift circuit showing a first embodiment of the present invention. Configuration diagram of level shift circuit The figure which shows the schematic functional block structure of vehicle-mounted IC, and the connection aspect of the said IC and power supply Configuration diagram of NOR gate FIG. 1 equivalent diagram showing a second embodiment of the present invention FIG. 1 equivalent view showing the first prior art FIG. 1 equivalent diagram showing the second prior art

Explanation of symbols

  22 is a battery, 23 is a power supply circuit (constant voltage power supply circuit), 30 and 53 are level shift circuits, 35 is a power supply line (first power supply line), 36 is a power supply line (second power supply line), and 37 is ground. 38, a circuit block (first circuit block), 39 and 54 are circuit blocks (second circuit block), 40 is a level conversion circuit, 41 is a NAND gate (level fixing circuit, gate circuit), 43, 44 is an inverter (signal output circuit), 45 is a NOR gate (first CMOS NOR gate), 46 is a NOR gate (second CMOS NOR gate), 55 is a latch circuit (level fixing circuit), and 56 is an inverter (first circuit). , 57 is an inverter (second inverter), and Q7 to Q10 are MOS transistors (first to fourth FETs).

Claims (4)

A first circuit block that operates by receiving supply of a first power supply voltage from a first power supply line and a ground line, and supply of a second power supply voltage from a second power supply line and the ground line. The second circuit block that operates is connected in cascade,
The second circuit block includes:
N-channel first and second FETs whose sources are grounded with respect to the ground line, connected between the second power supply line and the first FET, and a gate connected to the drain of the second FET. A P-channel third FET connected to the first FET, and a P-channel type connected between the second power supply line and the second FET and having a gate connected to the drain of the first FET. A level conversion circuit comprising a fourth FET;
A level fixing circuit for fixing the signal level output from the level conversion circuit;
A signal output circuit that outputs a power supply state signal indicating a power supply state of the first power supply voltage,
The first circuit block includes:
A first CMOS NOR gate that inputs an input signal and a power supply state signal output from the signal output circuit and outputs a gate signal of the second FET;
And a second CMOS NOR gate that inputs a gate signal of the second FET and a power supply state signal output from the signal output circuit and outputs a gate signal of the first FET. Level shift circuit.   2. The level fixing circuit includes a gate circuit that receives a power supply state signal output from the signal output circuit and a signal output from the level conversion circuit. Level shift circuit.   The level fixing circuit includes a first inverter having a signal output from the level conversion circuit as an input and a second inverter connected in antiparallel between the input and output terminals of the first inverter. 2. The level shift circuit according to claim 1, comprising a circuit. 2. The first power supply voltage is supplied from a constant voltage power supply circuit that stops voltage output in response to the power supply state signal, and the second power supply voltage is supplied from a battery. 4. The level shift circuit according to any one of 3 to 3.

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