JP2006165222A - Method for inspecting wiring formation process, process for fabricating semiconductor device, semiconductor substrate for evaluation, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To judge whether the conditions of a wiring formation process are appropriate or not easily and inexpensively. <P>SOLUTION: The inspection method of a wiring formation process comprises a step for forming a plurality of underlying interconnect lines 2a, 2b and 2c of different width substantially in parallel above a semiconductor substrate 1 for monitor, a step for forming an insulating film 4 on the plurality of underlying interconnect lines 2a, 2b and 2c, a step for forming a conductive film on the insulating film 4, a step for forming an evaluation wiring pattern 6 across the plurality of underlying interconnect lines 2a, 2b and 2c, a step for measuring the resistance of the evaluation wiring pattern 6, and a step for altering at least one of the forming condition of the conductive film and the patterning condition of the conductive film when the resistance does not satisfy a reference, and judges that the forming condition of the conductive film and the patterning condition of the conductive film are appropriate when the resistance satisfies the reference. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring formation process inspection method, a semiconductor device manufacturing method, an evaluation semiconductor substrate, and a semiconductor device. In particular, the present invention relates to a wiring formation process inspection method, a semiconductor device manufacturing method, an evaluation semiconductor substrate, and a semiconductor device that can easily and inexpensively determine whether or not the conditions of the wiring formation process are appropriate.

  FIG. 10A is a cross-sectional view for explaining the structure of a conventional semiconductor device. FIG. 10B is a plan view of FIG. In the semiconductor device shown in these drawings, element regions are isolated from each other by embedding an element isolation film 102 in a silicon substrate 101.

  Transistors are formed in the element region. That is, the gate oxide film 103 is formed on the surface of the silicon substrate 101, and the gate electrode 104 is formed on the gate oxide film 103. A side surface of the gate electrode 104 is covered with a sidewall 105. In the silicon substrate 101, impurity regions 107a and 107b functioning as a source and a drain, and low-concentration impurity regions (LDD regions) 106a and 106b located below the sidewall 105 are formed.

A first interlayer insulating film 108 and first Al alloy wirings 109a, 109b, and 109c are formed on the transistor. The first Al alloy wirings 109a and 109b are connected to the impurity regions 107a and 107b through connection holes (not shown), respectively, and the first Al alloy wiring 109c is connected to the gate electrode 104 through the connection holes 108a. It is connected to the.
A second interlayer insulating film 110 and a second Al alloy wiring 111 are formed on the first interlayer insulating film 108 and the first Al alloy wirings 109a, 109b, and 109c, respectively. The second Al alloy wiring 111 is routed in a direction substantially orthogonal to the first Al alloy wiring 109a, 109b, 109c (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2003-332398 (FIG. 1D)

  The wiring pattern is easily affected by the step of the base film, and disconnection or thinning (for example, a portion indicated by reference numeral 111a in FIG. 10B) is likely to occur at the portion where the step exists. Conventionally, these abnormalities are often detected by performing an appearance inspection after developing a resist pattern or forming a wiring pattern.

  The visual inspection includes a method of performing visual inspection using a microscope and a method of using an automatic visual inspection apparatus. Since the former method has a limit on the number of examinations, there was a possibility of overlooking the abnormality. In the latter case, the apparatus is expensive and the inspection takes time.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide an inspection method for a wiring formation process that can easily and inexpensively determine whether or not the conditions of the wiring formation process are appropriate. A semiconductor device manufacturing method, an evaluation semiconductor substrate, and a semiconductor device are provided.

In order to solve the above problems, an inspection method of a wiring forming process according to the present invention includes a process of forming a plurality of base wirings substantially parallel to each other and having different widths above a semiconductor substrate;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
It comprises.

According to this inspection method of the wiring formation process, a plurality of base wirings having different widths are formed below the evaluation wiring pattern. For this reason, the insulating film serving as the base of the evaluation wiring pattern is formed with unevenness due to the base wiring on the surface, like the interlayer insulating film of the semiconductor device. For this reason, the wiring pattern for evaluation is formed in a state close to the semiconductor device, and the detection sensitivity of whether or not the conditions of the wiring forming process are appropriate increases. Further, by measuring the resistance of the evaluation wiring pattern, it can be easily and inexpensively determined whether or not the evaluation wiring pattern is normal.
Thus, according to the inspection method of the present wiring formation process, it is possible to easily and accurately determine whether or not the conditions of the wiring formation process are appropriate.

After the step of forming the evaluation wiring pattern, at least one of the step of measuring the resistance of the evaluation wiring pattern and the conductive film formation condition and the conductive film patterning condition when the resistance value does not satisfy the standard. In the case where the resistance value satisfies the criteria, a step of determining that the insulating film formation conditions, the conductive film formation conditions, and the conductive film patterning conditions are appropriate may be included.
In the step of forming the evaluation wiring pattern, the evaluation wiring pattern may be formed so as to straddle a plurality of base wirings a plurality of times at a substantially right angle. In this case, the detection sensitivity of the evaluation wiring pattern is further increased.

  The width of the thinnest base wiring is approximately equal to the width of the thinnest wiring formed in the wiring forming process to be inspected, and the width of the thickest base wiring is the thickest wiring formed in the wiring forming process to be inspected. Is preferably approximately equal to the width of.

A method of manufacturing a semiconductor device according to the present invention includes forming a first wiring layer in a chip region of a semiconductor substrate and forming a plurality of base wirings substantially parallel to each other on a dicing line of the semiconductor substrate;
Forming an insulating film on the first wiring layer and the plurality of base wirings;
Forming a conductive film on the insulating film;
Forming a second wiring layer in the chip region by patterning the conductive film, and forming a wiring pattern for evaluation across the plurality of base wirings in the dicing line.
The first wiring layer is, for example, either polysilicon wiring or Al alloy wiring.

  According to this method for manufacturing a semiconductor device, it is possible to easily and inexpensively determine whether or not the conditions of the wiring formation process are appropriate by measuring the resistance of the evaluation wiring pattern formed on the dicing line. .

  The width of the thinnest base wiring is approximately equal to the width of the thinnest wiring included in the first wiring layer, and the width of the thickest base wiring is approximately equal to the width of the thickest wiring included in the first wiring layer. Preferably equal.

Another method of manufacturing a semiconductor device according to the present invention includes a step of setting a formation condition of a resist pattern for wiring formation,
Forming a conductive film on the insulating film;
Forming a resist pattern for wiring formation on the conductive film;
Forming a wiring on the insulating film by etching the conductive film using the resist pattern for wiring formation as a mask;
Comprising
The step of setting the formation conditions of the wiring formation resist pattern,
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film;
Forming a resist pattern for evaluation on the conductive film under conditions for forming the resist pattern for wiring formation;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film using the resist pattern for evaluation; and
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the formation condition of the wiring formation resist pattern is changed. When the resistance value satisfies the standard, the formation condition of the wiring formation resist pattern is appropriate. Determining.

Another method of manufacturing a semiconductor device according to the present invention includes a step of setting operating conditions of a conductive film forming device,
Forming a conductive film on an insulating film using the conductive film forming apparatus;
Forming a wiring on the insulating film by patterning the conductive film;
Comprising
The step of setting operating conditions of the conductive film forming apparatus includes:
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film using the conductive film forming apparatus;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the operating condition of the conductive film forming apparatus is changed. When the resistance value satisfies the standard, it is determined that the operating condition of the conductive film forming apparatus is appropriate. A process.

Another method of manufacturing a semiconductor device according to the present invention includes a step of setting operating conditions of an insulating film forming apparatus,
Forming an insulating film on the first wiring layer using the insulating film forming apparatus;
Forming a second wiring layer on the insulating film;
Comprising
The step of setting operating conditions of the insulating film forming apparatus includes:
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings using the insulating film forming apparatus;
Forming a conductive film on the insulating film;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the operating condition of the insulating film forming apparatus is changed. When the resistance value satisfies the standard, it is determined that the operating condition of the insulating film forming apparatus is appropriate. A process.

A semiconductor substrate for evaluation according to the present invention includes a plurality of base wirings formed substantially parallel to each other,
An insulating film formed on the plurality of base wirings;
And an evaluation wiring pattern formed on the insulating film and straddling the plurality of base wirings.

A semiconductor device according to the present invention is formed above a semiconductor substrate, a first wiring layer located in the chip region,
A plurality of underlying wirings formed above the semiconductor substrate, located on the same layer as the wiring layer and above the dicing line, and substantially parallel to each other;
An insulating film formed on the first wiring layer and the plurality of base wirings;
A second wiring layer formed on the insulating film and located in the chip region;
And an evaluation wiring pattern formed on the insulating film and straddling the plurality of base wirings.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A, FIG. 2 and FIG. 3A are cross-sectional views of a silicon substrate for monitoring for explaining an inspection method in a wiring forming process according to the first embodiment of the present invention. FIGS. 1B and 3B are plan views of the silicon substrate for monitoring in the states of FIGS. 1A and 3A, respectively. In the present embodiment, a TEG (Test Element Group) is formed on the silicon substrate 1 for monitoring, and the resistance value of the TEG is measured to thereby operate the Al alloy film forming apparatus and the exposure apparatus used in the wiring forming process. Determine whether the conditions are appropriate.

  First, as shown in FIG. 1A, a base conductive film is formed on a silicon substrate 1. The underlying conductive film is, for example, a polysilicon film, but may be an Al alloy film. The underlying conductive film is formed by a CVD method when it is a polysilicon film, and is formed by a sputtering method when it is an Al alloy film.

  Next, a photoresist film is applied on the underlying conductive film, and the photoresist film is exposed and developed, whereby a resist pattern 50 is formed on the underlying conductive film. Next, the underlying conductive film is etched using the resist pattern 50 as a mask. As a result, the base insulating film is patterned and base wirings 2a, 2b, and 2c are formed.

  As shown in FIG. 1B, the underlying wirings 2a, 2b, 2c are formed substantially parallel to each other and have different widths. The spacing between the underlying wirings 2a, 2b, 2c is, for example, substantially equal to or slightly narrower than the spacing between the wirings formed in the actual wiring forming process. Further, the width of the base wiring 2a is, for example, equal to the minimum width of the wiring formed in the actual wiring formation process, and the width of the base wiring 2c is, for example, equal to the maximum width of the wiring formed in the actual wiring formation process.

  Thereafter, as shown in FIG. 2, the resist pattern 50 is removed. Next, an interlayer insulating film 4 is formed on the silicon substrate 1 so as to cover the underlying wirings 2a, 2b, and 2c. The interlayer insulating film 4 contains silicon oxide as a main component and is formed using, for example, a CVD apparatus. The conditions for forming the interlayer insulating film 4 are the same as those in the actual wiring forming process. Concavities and convexities are formed on the surface of the interlayer insulating film 4 due to the effects of the steps of the underlying wirings 2 a, 2 b, 2 c and the silicon substrate 1.

  Next, as shown in FIG. 3A, an Al alloy film is formed over the interlayer insulating film 4 by using a sputtering apparatus. The sputtering apparatus and its operating conditions used here are the same as those in the actual wiring formation process.

  Next, a photoresist film (not shown) is applied on the Al alloy film using a coating apparatus. Next, the photoresist film is exposed using an exposure apparatus and further developed using a developing apparatus. Thereby, a resist pattern is formed on the Al alloy film. The coating device, the exposure device, the developing device, and the operating conditions used here are the same as in the actual Al alloy wiring forming process.

  Next, the Al alloy film is etched using the resist pattern as a mask. Thereby, the Al alloy film is patterned and TEG 6 is formed. The etching apparatus and etching conditions used here are the same as in the actual Al alloy wiring forming process.

  As shown in FIG. 3B, the TEG 6 is bent 180 ° outside the base wirings 2a and 2c, and extends over the base wirings 2a, 2b, and 2c a plurality of times at a substantially right angle. Pads 6 a and 6 b for connecting terminals are formed at both ends of the TEG 6. By connecting a terminal to each of the pads 6a and 6b, measuring the electrical resistance of the TEG 6, and determining whether the measured value is high, it is possible to detect the presence or absence of disconnection or thinness in the TEG 6.

When the electrical resistance of the TEG 6 is sufficiently low and satisfies the standard, the operating conditions of the sputtering apparatus for forming the Al alloy film, the apparatus for applying the photoresist film, the exposure apparatus, the developing apparatus, and the etching apparatus are appropriate. Judgment is made, the manufacture of the semiconductor device is started, and the wiring is formed.
When the electrical resistance is high and does not satisfy the standard, the TEG 6 is visually inspected with an electron microscope to identify an abnormal part, and it is determined whether a disconnection has occurred or the wiring is thin.

  FIG. 4 is a plan view showing a first example in which a disconnection occurs in the TEG 6. The disconnection 6c shown in this drawing occurs at the boundary between the base wiring (for example, 2b) and the silicon substrate 1, that is, at a portion where there is a step. The cause of the disconnection in this part is that the coverage of the Al alloy film is poor and the Al alloy film is not formed at the step part. Another reason is that since the photoresist film is thinly applied at the stepped portion, the entire resist pattern may be removed when the Al alloy film is etched.

  When the abnormality shown in FIG. 4 is detected, the sputtering apparatus for forming the Al alloy film, the apparatus for applying the photoresist film, the exposure apparatus, the developing apparatus, and the etching until the resistance value of the TEG satisfies the standard After changing at least one operating condition of the apparatus, a TEG is formed again on the silicon substrate, and the resistance is measured.

  Note that the wiring interval on the design rule may be changed. In this case, the interval after the change can be set by determining at which interval the disconnection occurs. In addition, the operating conditions of the CVD apparatus for forming the interlayer insulating film may be changed so that the surface of the interlayer insulating film is planarized.

  FIG. 5 is a plan view showing a second example in which a disconnection occurs in the TEG 6. The disconnection 6d shown in the figure is generated above the base wiring (for example, 2c). This is because the interlayer insulating film 4 is convex above the underlying wiring, so that the photoresist film is thinly applied at this portion, and the resist pattern is completely removed when the Al alloy film is etched. There is to be.

  FIG. 6 is a plan view showing an example in which a part of the TEG 6 is narrowed. The fine line portion 6e shown in the figure is generated above the base wiring (for example, 2c). This is because the interlayer insulating film 4 is convex above the underlying wiring, so that the photoresist film is thinly applied at this portion, and a part of the resist pattern is removed when the Al alloy film is etched. There is to be done.

  When the abnormality shown in FIG. 5 or FIG. 6 is detected, the operating condition of at least one of the apparatus for applying the photoresist film, the exposure apparatus, and the developing apparatus is changed until the TEG resistance value satisfies the standard. Then, TEG is again formed on the silicon substrate, and the resistance is measured. In particular, the operating conditions of the apparatus for applying the photoresist film are changed so that the photoresist film becomes thicker.

  The design rule may be changed so as to reduce the width of the base wiring. In this case, it is possible to set the width of the wiring after the change by determining which of the widths of the underlying wiring has a disconnection or thinning of the wiring. In addition, the operating conditions of the CVD apparatus for forming the interlayer insulating film may be changed so that the surface of the interlayer insulating film is planarized.

As described above, according to the first embodiment, since the plurality of base wirings 2a, 2b, and 2c having different widths are formed below the TEG 6 similarly to the semiconductor device, the TEG 6 is similar to the wiring included in the semiconductor device. It is affected by the level difference caused by the underlying wiring. Therefore, the TEG 6 can detect whether or not the conditions of the wiring forming process are appropriate with higher accuracy than in the past.
In the present embodiment, one type of TEG is illustrated, but a plurality of TEGs having different combinations of widths and intervals of the underlying wiring may be formed on the same silicon substrate 1.

  Each of FIGS. 7, 8, and 9 is a view for explaining a method for manufacturing a semiconductor device according to the second embodiment. In the present embodiment, a TEG is formed on a dicing line of a silicon substrate 1 on which a semiconductor device is formed.

  First, as shown in the cross-sectional view of FIG. 7, by forming an element isolation film 12 on the silicon substrate 10, the element regions of the chip region 1a are separated from each other. Also, the element isolation film 12 is formed on the dicing line 1b. In this figure, the element isolation film 12 is embedded in the silicon substrate 10 using the trench isolation method, but the element isolation film may be formed by the LOCOS method.

  Next, the silicon substrate 10 is thermally oxidized. Thereby, the gate oxide film 13 is formed in the element region of the chip region 1a. Next, a polysilicon film is formed on the entire surface including the gate oxide film 13 by a CVD method. Next, a photoresist film is applied on the polysilicon film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the polysilicon film.

  Next, the polysilicon film is etched using this resist pattern as a mask. Thereby, a gate electrode 14a located on the gate oxide film 13 and a polysilicon wiring (not shown) connected to the gate electrode 14a are formed in the chip region 1a, and a first dummy wiring is formed in the dicing line 1b. 14b, 14c, and 14d are formed.

The width of the first dummy wiring 14c is wider than the width of the first dummy wiring 14b and narrower than the width of the first dummy wiring 14d. The width of the first dummy wiring 14b is substantially equal to the width of the narrowest portion of the gate electrode 14a and the polysilicon wiring, and the width of the first dummy wiring 14d is the same of the gate electrode 14a and the polysilicon wiring. Is approximately equal to the width of the widest part.
Thereafter, the resist pattern is removed.

  Next, impurities are implanted into the silicon substrate 10 using the element isolation film 12 and the gate electrode 14a as a mask. Thus, low concentration impurity regions (LDD regions) 16a and 16b located in the chip region 1a are formed in the silicon substrate 10.

  Next, a silicon oxide film is formed on the entire surface including on the gate electrode 14a by, for example, a CVD method, and this silicon oxide film is etched back. Thereby, the side wall of the gate electrode 14a is covered with the side wall 15a. At this time, the side walls of the first dummy wirings 14b, 14c, and 14d are also covered with the side walls 15b, 15c, and 15d.

  Next, impurities are implanted into the silicon substrate 10 using the element isolation film 12, the gate electrode 14a, and the sidewalls 15a as masks. Thus, impurity regions 17a and 17b functioning as a source and a drain are formed in the chip region 1a of the silicon substrate 10. In this way, a transistor is formed in the chip region 1a.

  Next, a first interlayer insulating film 18 is formed on the entire surface including the chip region 1a and the dicing line 1b. The first interlayer insulating film 18 contains silicon oxide as a main component and is formed by, for example, a CVD method. Since the first interlayer insulating film 18 has the gate electrode 14a and the first dummy wirings 14b, 14c, and 14d formed on the base, irregularities are formed on the surface in each of the chip region 1a and the dicing line 1b. The

  Next, a photoresist film (not shown) is applied on the entire surface of the first interlayer insulating film 18, and the photoresist film is exposed and developed. As a result, a resist pattern is formed on the first interlayer insulating film 18. Next, the first interlayer insulating film 18 is etched using the resist pattern as a mask. As a result, a connection hole (not shown) located on the impurity regions 17a and 17b and a connection hole 18a located on the gate electrode 14a are formed in the first interlayer insulating film 18. Thereafter, the resist pattern is removed.

  Next, as shown in the plan view of FIG. 8A, the AA cross-sectional view of FIG. 8B, and the BB cross-sectional view of FIG. 8C, each of the connection holes is formed using a sputtering apparatus. An Al alloy film is formed on the entire surface of the middle and first interlayer insulating films 18. Next, a photoresist film is applied onto the Al alloy film using a coating apparatus, the photoresist film is exposed using an exposure apparatus, and the photoresist film is developed using a developing apparatus. Thereby, a resist pattern 52 is formed on the Al alloy film.

  Next, the Al alloy film is etched using an etching apparatus. At this time, the resist pattern 52 is used as a mask. Thus, the Al alloy film is patterned, Al alloy wirings 19a, 19b, 19c are formed in the chip region 1a, and TEG 19d and second dummy wirings 19e, 19f, 19g are formed in the dicing line 1b.

  Each of the Al alloy wirings 19a and 19b is connected to the impurity regions 17a and 17b by being partially embedded in the connection hole. The Al alloy wiring 19c is connected to the gate electrode 14a by being partially embedded in the connection hole 18a.

  The TEG 19d has substantially the same shape as the TEG 6 according to the first embodiment. The positional relationship between the TEG 19d and the first dummy wirings 14b, 14c, and 14d is substantially the same as the positional relationship between the TEG 6 and the underlying wirings 2a, 2b, and 2c according to the first embodiment. Therefore, by connecting terminals to pads formed on both ends of the TEG 19d and measuring the electrical resistance between these terminals, the formation conditions of the Al alloy wirings 19a and 19b are appropriate as in the first embodiment. It can be determined whether or not there was.

  If the formation conditions of the Al alloy wirings 19a and 19b are not appropriate, adjust the operating conditions of at least one of the sputtering apparatus for forming the Al alloy film, the apparatus for applying the photoresist film, the exposure apparatus, the developing apparatus, and the etching apparatus. To do.

  The second dummy wirings 19e, 19f, and 19g are parallel to each other and substantially parallel to the Al alloy wirings 19a, 19b, and 19c. The width of the second dummy wiring 19e is equal to the thinnest part of the Al alloy wirings 19a, 19b, 19c, and the width of the second dummy wiring 19g is equal to the thickest part of the Al alloy wirings 19a, 19b, 19c.

  Next, as shown in the cross-sectional view of FIG. 9A and the plan view of FIG. 9B, the Al alloy wirings 19a, 19b, 19c, TEG 19d, and the second dummy wirings 19e, 19g, 19g are included. A second interlayer insulating film 20 is formed on the entire surface. The second interlayer insulating film 20 contains silicon oxide as a main component and is formed by, for example, a CVD method. Note that the surface of the second interlayer insulating film 20 is affected by the Al alloy wirings 19a, 19b, 19c and the second dummy wirings 19e, 19f, 19g on the base, so that in the chip region 1a and the dicing line 1b, respectively. Unevenness is formed.

  Next, a photoresist film (not shown) is applied on the entire surface of the second interlayer insulating film 20, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the second interlayer insulating film 20. Next, the second interlayer insulating film 20 is etched using the resist pattern as a mask. As a result, connection holes (not shown) located on the Al alloy wirings 19a, 19b, and 19c are formed in the second interlayer insulating film 20. Thereafter, the resist pattern is removed.

  Next, an Al alloy film is formed on the entire surface of the second interlayer insulating film 20 using a sputtering apparatus. Next, a photoresist film is coated on the Al alloy film using a coating apparatus, the photoresist film is exposed using an exposure apparatus, and further developed using a developing apparatus. As a result, a resist pattern 54 is formed on the Al alloy film.

  Next, the Al alloy film is etched using an etching apparatus. At this time, the resist pattern 54 is used as a mask. Thereby, the Al alloy film is patterned, a plurality of Al alloy wirings 21a are formed in the chip region 1a, and a TEG 21b is formed in the dicing line 1b.

  The plurality of Al alloy wirings 21a are connected to any of the Al alloy wirings 19a, 19b, and 19c by being partially embedded in the connection holes. The TEG 21b has substantially the same shape as the TEG 19d. The positional relationship between the TEG 21b and the second dummy wirings 19e, 19f, and 19g is substantially the same as the positional relationship between the TEG 19d according to the first embodiment and the first dummy wirings 14b, 14c, and 14d. Therefore, it is possible to determine whether or not the formation conditions of the Al alloy wiring 21a are appropriate by connecting terminals to pads formed at both ends of the TEG 21b and measuring the electrical resistance between these terminals.

  When the formation conditions of the Al alloy wiring 21a are not appropriate, at least one operating condition of the sputtering apparatus for forming the Al alloy film, the apparatus for applying the photoresist film, the exposure apparatus, the developing apparatus, and the etching apparatus is adjusted.

  As described above, according to the second embodiment, since the dummy wiring is formed and the step is provided below the TEGs 19d and 21b of the dicing line, the TEGs 19d and 21b are connected to the Al alloy wirings 19a, 19b, and 19c in the chip region 1a. , 21a, it is affected by the step caused by the underlying wiring. Therefore, the TEGs 19d and 21b can detect whether or not the conditions of the wiring formation process are appropriate with higher accuracy than in the past.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is sectional drawing of the silicon substrate for a monitor for demonstrating the inspection method of the wiring formation process which concerns on 1st Embodiment, (B) is a top view of the silicon substrate in the state of (A). Sectional drawing for demonstrating the next process of FIG. (A) is sectional drawing for demonstrating the next process of FIG. 2, (B) is a top view of the silicon substrate in the state of (A). The top view which shows the 1st example with which disconnection has arisen in TEG6. The top view which shows the 2nd example with which disconnection has arisen in TEG6. The top view which shows the example in which a part of TEG6 is thin. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A) is a top view for demonstrating the next process of FIG. 7, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (A). (A) is sectional drawing for demonstrating the next process of FIG. 8, (B) is a top view of the silicon substrate in the state of (A). (A) is sectional drawing for demonstrating the structure of the conventional semiconductor device, (B) is a top view of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,10,101 ... Silicon substrate, 1a ... Chip area | region, 1b ... Dicing line, 2a, 2b, 2c ... Base wiring, 4 ... Interlayer insulation film, 6a, 6b ... Pad, 6c, 6d ... Disconnection, 6e ... Thin wire part , 12, 102 ... element isolation film, 13, 103 ... gate oxide film, 14a, 104 ... gate electrode, 14b, 14c, 14d ... first dummy wiring, 15a, 15b, 15c, 15d, 105 ... side wall, 16a , 16b, 106a, 106b ... low-concentration impurity region, 17a, 17b, 107a, 107b ... impurity region, 18, 108 ... first interlayer insulating film, 18a, 108a ... connection hole, 19a, 19b, 19c, 21a, 109a 109b, 109c, 111 ... Al alloy wiring, 19d, 21b ... TEG, 19e, 19f, 19g ... second dummy wiring, 20, 10 ... second interlayer insulating film, 50, 52, 54 ... resist pattern

Claims (12)

Forming a plurality of base wirings substantially parallel to each other and having different widths above the semiconductor substrate;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
A method for inspecting a wiring forming process comprising: After the step of forming the evaluation wiring pattern, measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, when at least one of the formation condition of the insulating film, the formation condition of the conductive film, and the patterning condition of the conductive film is changed, and the resistance value satisfies the standard Determining that the formation conditions of the conductive film and the patterning conditions of the conductive film are appropriate,
The inspection method of the wiring formation process according to claim 1 comprising:   The width of the thinnest base wiring is substantially equal to the width of the thinnest wiring formed in the wiring formation process to be inspected, and the thickest base wiring has the largest width formed in the wiring formation process to be inspected. The wiring forming step inspection method according to claim 1, wherein the wiring forming step is substantially equal to a width of a thick wiring.   The wiring formation process according to any one of claims 1 to 3, wherein in the step of forming the evaluation wiring pattern, the evaluation wiring pattern is formed so as to straddle the plurality of base wirings a plurality of times at a substantially right angle. Inspection method. Forming a first wiring layer in a chip region of a semiconductor substrate and forming a plurality of base wirings substantially parallel to each other on a dicing line of the semiconductor substrate;
Forming an insulating film on the first wiring layer and the plurality of base wirings;
Forming a conductive film on the insulating film;
Patterning the conductive film to form a second wiring layer in the chip region and forming an evaluation wiring pattern across the plurality of base wirings in the dicing line;
A method for manufacturing a semiconductor device comprising:   The width of the thinnest base wiring is approximately equal to the width of the thinnest wiring included in the first wiring layer, and the width of the thickest base wiring is approximately equal to the width of the thickest wiring included in the first wiring layer. The manufacturing method of the semiconductor device of Claim 5 which is equal.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the first wiring layer is one of polysilicon wiring and Al alloy wiring. A step of setting the formation conditions of the resist pattern for wiring formation;
Forming a conductive film on an insulating film formed on the first wiring layer;
Forming a resist pattern for wiring formation on the conductive film;
Forming a second wiring layer on the insulating film by etching the conductive film using the wiring formation resist pattern as a mask;
Comprising
The step of setting the formation conditions of the wiring formation resist pattern,
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film;
Forming a resist pattern for evaluation on the conductive film under conditions for forming the resist pattern for wiring formation;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film using the resist pattern for evaluation; and
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the formation condition of the wiring formation resist pattern is changed. When the resistance value satisfies the standard, the formation condition of the wiring formation resist pattern is appropriate. A process of judging;
A method for manufacturing a semiconductor device comprising: Setting the operating conditions of the conductive film forming apparatus;
Forming a conductive film on an insulating film formed on the first wiring layer using the conductive film forming apparatus;
Forming a second wiring layer on the insulating film by patterning the conductive film;
Comprising
The step of setting operating conditions of the conductive film forming apparatus includes:
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings;
Forming a conductive film on the insulating film using the conductive film forming apparatus;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the operating condition of the conductive film forming apparatus is changed. When the resistance value satisfies the standard, it is determined that the operating condition of the conductive film forming apparatus is appropriate. Process,
A method for manufacturing a semiconductor device comprising: A step of setting operating conditions of the insulating film forming apparatus;
Forming an insulating film on the first wiring layer using the insulating film forming apparatus;
Forming a second wiring layer on the insulating film;
Comprising
The step of setting operating conditions of the insulating film forming apparatus includes:
Forming a plurality of underlying wirings substantially parallel to each other above a semiconductor substrate for monitoring;
Forming an insulating film on the plurality of base wirings using the insulating film forming apparatus;
Forming a conductive film on the insulating film;
Forming a wiring pattern for evaluation across the plurality of base wiring lines by patterning the conductive film;
Measuring the resistance of the evaluation wiring pattern;
When the resistance value does not satisfy the standard, the operating condition of the insulating film forming apparatus is changed. When the resistance value satisfies the standard, it is determined that the operating condition of the insulating film forming apparatus is appropriate. Process,
A method for manufacturing a semiconductor device comprising: A plurality of underlying wirings formed substantially parallel to each other;
An insulating film formed on the plurality of base wirings;
An evaluation wiring pattern formed on the insulating film and straddling the plurality of base wirings;
An evaluation semiconductor substrate comprising: A first wiring layer formed above the semiconductor substrate and located in the chip region;
A plurality of underlying wirings formed above the semiconductor substrate, located on the same layer as the wiring layer and above the dicing line, and substantially parallel to each other;
An insulating film formed on the first wiring layer and the plurality of base wirings;
A second wiring layer formed on the insulating film and located in the chip region;
An evaluation wiring pattern formed on the insulating film and straddling the plurality of base wirings;
A semiconductor device comprising:

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